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Commit 2832271d authored by Ben Skeggs's avatar Ben Skeggs
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drm/nv50-/disp: rename class members to match nvidia channel names 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 868e34f7
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Showing with 206 additions and 206 deletions
drivers/gpu/drm/nouveau/core/engine/disp/gm107.c
View file @ 2832271d
...@@ -35,8 +35,8 @@ ...@@ -35,8 +35,8 @@
static struct nouveau_oclass static struct nouveau_oclass
gm107_disp_sclass[] = { gm107_disp_sclass[] = {
{ GM107_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base }, { GM107_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
{ GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base }, { GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
{ GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base }, { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
{ GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base }, { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
{ GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base }, { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
...@@ -44,8 +44,8 @@ gm107_disp_sclass[] = { ...@@ -44,8 +44,8 @@ gm107_disp_sclass[] = {
}; };
static struct nouveau_oclass static struct nouveau_oclass
gm107_disp_base_oclass[] = { gm107_disp_main_oclass[] = {
{ GM107_DISP, &nvd0_disp_base_ofuncs }, { GM107_DISP, &nvd0_disp_main_ofuncs },
{} {}
}; };
...@@ -72,7 +72,7 @@ gm107_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -72,7 +72,7 @@ gm107_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret) if (ret)
return ret; return ret;
nv_engine(priv)->sclass = gm107_disp_base_oclass; nv_engine(priv)->sclass = gm107_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass; nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = nvd0_disp_intr; nv_subdev(priv)->intr = nvd0_disp_intr;
INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor); INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
...@@ -99,9 +99,9 @@ gm107_disp_oclass = &(struct nv50_disp_impl) { ...@@ -99,9 +99,9 @@ gm107_disp_oclass = &(struct nv50_disp_impl) {
}, },
.base.vblank = &nvd0_disp_vblank_func, .base.vblank = &nvd0_disp_vblank_func,
.base.outp = nvd0_disp_outp_sclass, .base.outp = nvd0_disp_outp_sclass,
.mthd.core = &nve0_disp_mast_mthd_chan, .mthd.core = &nve0_disp_core_mthd_chan,
.mthd.base = &nvd0_disp_sync_mthd_chan, .mthd.base = &nvd0_disp_base_mthd_chan,
.mthd.ovly = &nve0_disp_ovly_mthd_chan, .mthd.ovly = &nve0_disp_ovly_mthd_chan,
.mthd.prev = -0x020000, .mthd.prev = -0x020000,
.head.scanoutpos = nvd0_disp_base_scanoutpos, .head.scanoutpos = nvd0_disp_main_scanoutpos,
}.base.base; }.base.base;
drivers/gpu/drm/nouveau/core/engine/disp/gm204.c
View file @ 2832271d
...@@ -35,8 +35,8 @@ ...@@ -35,8 +35,8 @@
static struct nouveau_oclass static struct nouveau_oclass
gm204_disp_sclass[] = { gm204_disp_sclass[] = {
{ GM204_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base }, { GM204_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
{ GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base }, { GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
{ GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base }, { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
{ GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base }, { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
{ GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base }, { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
...@@ -44,8 +44,8 @@ gm204_disp_sclass[] = { ...@@ -44,8 +44,8 @@ gm204_disp_sclass[] = {
}; };
static struct nouveau_oclass static struct nouveau_oclass
gm204_disp_base_oclass[] = { gm204_disp_main_oclass[] = {
{ GM204_DISP, &nvd0_disp_base_ofuncs }, { GM204_DISP, &nvd0_disp_main_ofuncs },
{} {}
}; };
...@@ -72,7 +72,7 @@ gm204_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -72,7 +72,7 @@ gm204_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret) if (ret)
return ret; return ret;
nv_engine(priv)->sclass = gm204_disp_base_oclass; nv_engine(priv)->sclass = gm204_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass; nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = nvd0_disp_intr; nv_subdev(priv)->intr = nvd0_disp_intr;
INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor); INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
...@@ -106,9 +106,9 @@ gm204_disp_oclass = &(struct nv50_disp_impl) { ...@@ -106,9 +106,9 @@ gm204_disp_oclass = &(struct nv50_disp_impl) {
}, },
.base.vblank = &nvd0_disp_vblank_func, .base.vblank = &nvd0_disp_vblank_func,
.base.outp = gm204_disp_outp_sclass, .base.outp = gm204_disp_outp_sclass,
.mthd.core = &nve0_disp_mast_mthd_chan, .mthd.core = &nve0_disp_core_mthd_chan,
.mthd.base = &nvd0_disp_sync_mthd_chan, .mthd.base = &nvd0_disp_base_mthd_chan,
.mthd.ovly = &nve0_disp_ovly_mthd_chan, .mthd.ovly = &nve0_disp_ovly_mthd_chan,
.mthd.prev = -0x020000, .mthd.prev = -0x020000,
.head.scanoutpos = nvd0_disp_base_scanoutpos, .head.scanoutpos = nvd0_disp_main_scanoutpos,
}.base.base; }.base.base;
drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
View file @ 2832271d
...@@ -374,7 +374,7 @@ nv50_disp_mthd_chan(struct nv50_disp_priv *priv, int debug, int head, ...@@ -374,7 +374,7 @@ nv50_disp_mthd_chan(struct nv50_disp_priv *priv, int debug, int head,
} }
const struct nv50_disp_mthd_list const struct nv50_disp_mthd_list
nv50_disp_mast_mthd_base = { nv50_disp_core_mthd_base = {
.mthd = 0x0000, .mthd = 0x0000,
.addr = 0x000000, .addr = 0x000000,
.data = { .data = {
...@@ -387,7 +387,7 @@ nv50_disp_mast_mthd_base = { ...@@ -387,7 +387,7 @@ nv50_disp_mast_mthd_base = {
}; };
static const struct nv50_disp_mthd_list static const struct nv50_disp_mthd_list
nv50_disp_mast_mthd_dac = { nv50_disp_core_mthd_dac = {
.mthd = 0x0080, .mthd = 0x0080,
.addr = 0x000008, .addr = 0x000008,
.data = { .data = {
...@@ -399,7 +399,7 @@ nv50_disp_mast_mthd_dac = { ...@@ -399,7 +399,7 @@ nv50_disp_mast_mthd_dac = {
}; };
const struct nv50_disp_mthd_list const struct nv50_disp_mthd_list
nv50_disp_mast_mthd_sor = { nv50_disp_core_mthd_sor = {
.mthd = 0x0040, .mthd = 0x0040,
.addr = 0x000008, .addr = 0x000008,
.data = { .data = {
...@@ -409,7 +409,7 @@ nv50_disp_mast_mthd_sor = { ...@@ -409,7 +409,7 @@ nv50_disp_mast_mthd_sor = {
}; };
const struct nv50_disp_mthd_list const struct nv50_disp_mthd_list
nv50_disp_mast_mthd_pior = { nv50_disp_core_mthd_pior = {
.mthd = 0x0040, .mthd = 0x0040,
.addr = 0x000008, .addr = 0x000008,
.data = { .data = {
...@@ -419,7 +419,7 @@ nv50_disp_mast_mthd_pior = { ...@@ -419,7 +419,7 @@ nv50_disp_mast_mthd_pior = {
}; };
static const struct nv50_disp_mthd_list static const struct nv50_disp_mthd_list
nv50_disp_mast_mthd_head = { nv50_disp_core_mthd_head = {
.mthd = 0x0400, .mthd = 0x0400,
.addr = 0x000540, .addr = 0x000540,
.data = { .data = {
...@@ -466,21 +466,21 @@ nv50_disp_mast_mthd_head = { ...@@ -466,21 +466,21 @@ nv50_disp_mast_mthd_head = {
}; };
static const struct nv50_disp_mthd_chan static const struct nv50_disp_mthd_chan
nv50_disp_mast_mthd_chan = { nv50_disp_core_mthd_chan = {
.name = "Core", .name = "Core",
.addr = 0x000000, .addr = 0x000000,
.data = { .data = {
{ "Global", 1, &nv50_disp_mast_mthd_base }, { "Global", 1, &nv50_disp_core_mthd_base },
{ "DAC", 3, &nv50_disp_mast_mthd_dac }, { "DAC", 3, &nv50_disp_core_mthd_dac },
{ "SOR", 2, &nv50_disp_mast_mthd_sor }, { "SOR", 2, &nv50_disp_core_mthd_sor },
{ "PIOR", 3, &nv50_disp_mast_mthd_pior }, { "PIOR", 3, &nv50_disp_core_mthd_pior },
{ "HEAD", 2, &nv50_disp_mast_mthd_head }, { "HEAD", 2, &nv50_disp_core_mthd_head },
{} {}
} }
}; };
int int
nv50_disp_mast_ctor(struct nouveau_object *parent, nv50_disp_core_ctor(struct nouveau_object *parent,
struct nouveau_object *engine, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject) struct nouveau_object **pobject)
...@@ -509,7 +509,7 @@ nv50_disp_mast_ctor(struct nouveau_object *parent, ...@@ -509,7 +509,7 @@ nv50_disp_mast_ctor(struct nouveau_object *parent,
} }
static int static int
nv50_disp_mast_init(struct nouveau_object *object) nv50_disp_core_init(struct nouveau_object *object)
{ {
struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_dmac *mast = (void *)object; struct nv50_disp_dmac *mast = (void *)object;
...@@ -546,7 +546,7 @@ nv50_disp_mast_init(struct nouveau_object *object) ...@@ -546,7 +546,7 @@ nv50_disp_mast_init(struct nouveau_object *object)
} }
static int static int
nv50_disp_mast_fini(struct nouveau_object *object, bool suspend) nv50_disp_core_fini(struct nouveau_object *object, bool suspend)
{ {
struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_dmac *mast = (void *)object; struct nv50_disp_dmac *mast = (void *)object;
...@@ -567,11 +567,11 @@ nv50_disp_mast_fini(struct nouveau_object *object, bool suspend) ...@@ -567,11 +567,11 @@ nv50_disp_mast_fini(struct nouveau_object *object, bool suspend)
} }
struct nv50_disp_chan_impl struct nv50_disp_chan_impl
nv50_disp_mast_ofuncs = { nv50_disp_core_ofuncs = {
.base.ctor = nv50_disp_mast_ctor, .base.ctor = nv50_disp_core_ctor,
.base.dtor = nv50_disp_dmac_dtor, .base.dtor = nv50_disp_dmac_dtor,
.base.init = nv50_disp_mast_init, .base.init = nv50_disp_core_init,
.base.fini = nv50_disp_mast_fini, .base.fini = nv50_disp_core_fini,
.base.map = nv50_disp_chan_map, .base.map = nv50_disp_chan_map,
.base.ntfy = nv50_disp_chan_ntfy, .base.ntfy = nv50_disp_chan_ntfy,
.base.rd32 = nv50_disp_chan_rd32, .base.rd32 = nv50_disp_chan_rd32,
...@@ -586,7 +586,7 @@ nv50_disp_mast_ofuncs = { ...@@ -586,7 +586,7 @@ nv50_disp_mast_ofuncs = {
******************************************************************************/ ******************************************************************************/
static const struct nv50_disp_mthd_list static const struct nv50_disp_mthd_list
nv50_disp_sync_mthd_base = { nv50_disp_base_mthd_base = {
.mthd = 0x0000, .mthd = 0x0000,
.addr = 0x000000, .addr = 0x000000,
.data = { .data = {
...@@ -611,7 +611,7 @@ nv50_disp_sync_mthd_base = { ...@@ -611,7 +611,7 @@ nv50_disp_sync_mthd_base = {
}; };
const struct nv50_disp_mthd_list const struct nv50_disp_mthd_list
nv50_disp_sync_mthd_image = { nv50_disp_base_mthd_image = {
.mthd = 0x0400, .mthd = 0x0400,
.addr = 0x000000, .addr = 0x000000,
.data = { .data = {
...@@ -625,18 +625,18 @@ nv50_disp_sync_mthd_image = { ...@@ -625,18 +625,18 @@ nv50_disp_sync_mthd_image = {
}; };
static const struct nv50_disp_mthd_chan static const struct nv50_disp_mthd_chan
nv50_disp_sync_mthd_chan = { nv50_disp_base_mthd_chan = {
.name = "Base", .name = "Base",
.addr = 0x000540, .addr = 0x000540,
.data = { .data = {
{ "Global", 1, &nv50_disp_sync_mthd_base }, { "Global", 1, &nv50_disp_base_mthd_base },
{ "Image", 2, &nv50_disp_sync_mthd_image }, { "Image", 2, &nv50_disp_base_mthd_image },
{} {}
} }
}; };
int int
nv50_disp_sync_ctor(struct nouveau_object *parent, nv50_disp_base_ctor(struct nouveau_object *parent,
struct nouveau_object *engine, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject) struct nouveau_object **pobject)
...@@ -669,8 +669,8 @@ nv50_disp_sync_ctor(struct nouveau_object *parent, ...@@ -669,8 +669,8 @@ nv50_disp_sync_ctor(struct nouveau_object *parent,
} }
struct nv50_disp_chan_impl struct nv50_disp_chan_impl
nv50_disp_sync_ofuncs = { nv50_disp_base_ofuncs = {
.base.ctor = nv50_disp_sync_ctor, .base.ctor = nv50_disp_base_ctor,
.base.dtor = nv50_disp_dmac_dtor, .base.dtor = nv50_disp_dmac_dtor,
.base.init = nv50_disp_dmac_init, .base.init = nv50_disp_dmac_init,
.base.fini = nv50_disp_dmac_fini, .base.fini = nv50_disp_dmac_fini,
...@@ -942,7 +942,7 @@ nv50_disp_curs_ofuncs = { ...@@ -942,7 +942,7 @@ nv50_disp_curs_ofuncs = {
******************************************************************************/ ******************************************************************************/
int int
nv50_disp_base_scanoutpos(NV50_DISP_MTHD_V0) nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0)
{ {
const u32 blanke = nv_rd32(priv, 0x610aec + (head * 0x540)); const u32 blanke = nv_rd32(priv, 0x610aec + (head * 0x540));
const u32 blanks = nv_rd32(priv, 0x610af4 + (head * 0x540)); const u32 blanks = nv_rd32(priv, 0x610af4 + (head * 0x540));
...@@ -974,7 +974,7 @@ nv50_disp_base_scanoutpos(NV50_DISP_MTHD_V0) ...@@ -974,7 +974,7 @@ nv50_disp_base_scanoutpos(NV50_DISP_MTHD_V0)
} }
int int
nv50_disp_base_mthd(struct nouveau_object *object, u32 mthd, nv50_disp_main_mthd(struct nouveau_object *object, u32 mthd,
void *data, u32 size) void *data, u32 size)
{ {
const struct nv50_disp_impl *impl = (void *)nv_oclass(object->engine); const struct nv50_disp_impl *impl = (void *)nv_oclass(object->engine);
...@@ -1098,7 +1098,7 @@ nv50_disp_base_mthd(struct nouveau_object *object, u32 mthd, ...@@ -1098,7 +1098,7 @@ nv50_disp_base_mthd(struct nouveau_object *object, u32 mthd,
} }
int int
nv50_disp_base_ctor(struct nouveau_object *parent, nv50_disp_main_ctor(struct nouveau_object *parent,
struct nouveau_object *engine, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject) struct nouveau_object **pobject)
...@@ -1118,7 +1118,7 @@ nv50_disp_base_ctor(struct nouveau_object *parent, ...@@ -1118,7 +1118,7 @@ nv50_disp_base_ctor(struct nouveau_object *parent,
} }
void void
nv50_disp_base_dtor(struct nouveau_object *object) nv50_disp_main_dtor(struct nouveau_object *object)
{ {
struct nv50_disp_base *base = (void *)object; struct nv50_disp_base *base = (void *)object;
nouveau_ramht_ref(NULL, &base->ramht); nouveau_ramht_ref(NULL, &base->ramht);
...@@ -1126,7 +1126,7 @@ nv50_disp_base_dtor(struct nouveau_object *object) ...@@ -1126,7 +1126,7 @@ nv50_disp_base_dtor(struct nouveau_object *object)
} }
static int static int
nv50_disp_base_init(struct nouveau_object *object) nv50_disp_main_init(struct nouveau_object *object)
{ {
struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_base *base = (void *)object; struct nv50_disp_base *base = (void *)object;
...@@ -1194,7 +1194,7 @@ nv50_disp_base_init(struct nouveau_object *object) ...@@ -1194,7 +1194,7 @@ nv50_disp_base_init(struct nouveau_object *object)
} }
static int static int
nv50_disp_base_fini(struct nouveau_object *object, bool suspend) nv50_disp_main_fini(struct nouveau_object *object, bool suspend)
{ {
struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_base *base = (void *)object; struct nv50_disp_base *base = (void *)object;
...@@ -1207,25 +1207,25 @@ nv50_disp_base_fini(struct nouveau_object *object, bool suspend) ...@@ -1207,25 +1207,25 @@ nv50_disp_base_fini(struct nouveau_object *object, bool suspend)
} }
struct nouveau_ofuncs struct nouveau_ofuncs
nv50_disp_base_ofuncs = { nv50_disp_main_ofuncs = {
.ctor = nv50_disp_base_ctor, .ctor = nv50_disp_main_ctor,
.dtor = nv50_disp_base_dtor, .dtor = nv50_disp_main_dtor,
.init = nv50_disp_base_init, .init = nv50_disp_main_init,
.fini = nv50_disp_base_fini, .fini = nv50_disp_main_fini,
.mthd = nv50_disp_base_mthd, .mthd = nv50_disp_main_mthd,
.ntfy = nouveau_disp_ntfy, .ntfy = nouveau_disp_ntfy,
}; };
static struct nouveau_oclass static struct nouveau_oclass
nv50_disp_base_oclass[] = { nv50_disp_main_oclass[] = {
{ NV50_DISP, &nv50_disp_base_ofuncs }, { NV50_DISP, &nv50_disp_main_ofuncs },
{} {}
}; };
static struct nouveau_oclass static struct nouveau_oclass
nv50_disp_sclass[] = { nv50_disp_sclass[] = {
{ NV50_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base }, { NV50_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
{ NV50_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base }, { NV50_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
{ NV50_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base }, { NV50_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
{ NV50_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base }, { NV50_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
{ NV50_DISP_CURSOR, &nv50_disp_curs_ofuncs.base }, { NV50_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
...@@ -1974,7 +1974,7 @@ nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -1974,7 +1974,7 @@ nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret) if (ret)
return ret; return ret;
nv_engine(priv)->sclass = nv50_disp_base_oclass; nv_engine(priv)->sclass = nv50_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass; nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = nv50_disp_intr; nv_subdev(priv)->intr = nv50_disp_intr;
INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
...@@ -2007,9 +2007,9 @@ nv50_disp_oclass = &(struct nv50_disp_impl) { ...@@ -2007,9 +2007,9 @@ nv50_disp_oclass = &(struct nv50_disp_impl) {
}, },
.base.vblank = &nv50_disp_vblank_func, .base.vblank = &nv50_disp_vblank_func,
.base.outp = nv50_disp_outp_sclass, .base.outp = nv50_disp_outp_sclass,
.mthd.core = &nv50_disp_mast_mthd_chan, .mthd.core = &nv50_disp_core_mthd_chan,
.mthd.base = &nv50_disp_sync_mthd_chan, .mthd.base = &nv50_disp_base_mthd_chan,
.mthd.ovly = &nv50_disp_ovly_mthd_chan, .mthd.ovly = &nv50_disp_ovly_mthd_chan,
.mthd.prev = 0x000004, .mthd.prev = 0x000004,
.head.scanoutpos = nv50_disp_base_scanoutpos, .head.scanoutpos = nv50_disp_main_scanoutpos,
}.base.base; }.base.base;
drivers/gpu/drm/nouveau/core/engine/disp/nv50.h
View file @ 2832271d
...@@ -64,10 +64,10 @@ struct nv50_disp_impl { ...@@ -64,10 +64,10 @@ struct nv50_disp_impl {
} head; } head;
}; };
int nv50_disp_base_scanoutpos(NV50_DISP_MTHD_V0); int nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0);
int nv50_disp_base_mthd(struct nouveau_object *, u32, void *, u32); int nv50_disp_main_mthd(struct nouveau_object *, u32, void *, u32);
int nvd0_disp_base_scanoutpos(NV50_DISP_MTHD_V0); int nvd0_disp_main_scanoutpos(NV50_DISP_MTHD_V0);
int nv50_dac_power(NV50_DISP_MTHD_V1); int nv50_dac_power(NV50_DISP_MTHD_V1);
int nv50_dac_sense(NV50_DISP_MTHD_V1); int nv50_dac_sense(NV50_DISP_MTHD_V1);
...@@ -170,18 +170,18 @@ struct nv50_disp_mthd_chan { ...@@ -170,18 +170,18 @@ struct nv50_disp_mthd_chan {
} data[]; } data[];
}; };
extern struct nv50_disp_chan_impl nv50_disp_mast_ofuncs; extern struct nv50_disp_chan_impl nv50_disp_core_ofuncs;
int nv50_disp_mast_ctor(struct nouveau_object *, struct nouveau_object *, int nv50_disp_core_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32, struct nouveau_oclass *, void *, u32,
struct nouveau_object **); struct nouveau_object **);
extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_base; extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_base;
extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_sor; extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_sor;
extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_pior; extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_pior;
extern struct nv50_disp_chan_impl nv50_disp_sync_ofuncs; extern struct nv50_disp_chan_impl nv50_disp_base_ofuncs;
int nv50_disp_sync_ctor(struct nouveau_object *, struct nouveau_object *, int nv50_disp_base_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32, struct nouveau_oclass *, void *, u32,
struct nouveau_object **); struct nouveau_object **);
extern const struct nv50_disp_mthd_list nv50_disp_sync_mthd_image; extern const struct nv50_disp_mthd_list nv50_disp_base_mthd_image;
extern struct nv50_disp_chan_impl nv50_disp_ovly_ofuncs; extern struct nv50_disp_chan_impl nv50_disp_ovly_ofuncs;
int nv50_disp_ovly_ctor(struct nouveau_object *, struct nouveau_object *, int nv50_disp_ovly_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32, struct nouveau_oclass *, void *, u32,
...@@ -195,12 +195,12 @@ extern struct nv50_disp_chan_impl nv50_disp_curs_ofuncs; ...@@ -195,12 +195,12 @@ extern struct nv50_disp_chan_impl nv50_disp_curs_ofuncs;
int nv50_disp_curs_ctor(struct nouveau_object *, struct nouveau_object *, int nv50_disp_curs_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32, struct nouveau_oclass *, void *, u32,
struct nouveau_object **); struct nouveau_object **);
extern struct nouveau_ofuncs nv50_disp_base_ofuncs; extern struct nouveau_ofuncs nv50_disp_main_ofuncs;
int nv50_disp_base_ctor(struct nouveau_object *, struct nouveau_object *, int nv50_disp_main_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32, struct nouveau_oclass *, void *, u32,
struct nouveau_object **); struct nouveau_object **);
void nv50_disp_base_dtor(struct nouveau_object *); void nv50_disp_main_dtor(struct nouveau_object *);
extern struct nouveau_omthds nv50_disp_base_omthds[]; extern struct nouveau_omthds nv50_disp_main_omthds[];
extern struct nouveau_oclass nv50_disp_cclass; extern struct nouveau_oclass nv50_disp_cclass;
void nv50_disp_mthd_chan(struct nv50_disp_priv *, int debug, int head, void nv50_disp_mthd_chan(struct nv50_disp_priv *, int debug, int head,
const struct nv50_disp_mthd_chan *); const struct nv50_disp_mthd_chan *);
...@@ -208,31 +208,31 @@ void nv50_disp_intr_supervisor(struct work_struct *); ...@@ -208,31 +208,31 @@ void nv50_disp_intr_supervisor(struct work_struct *);
void nv50_disp_intr(struct nouveau_subdev *); void nv50_disp_intr(struct nouveau_subdev *);
extern const struct nvkm_event_func nv50_disp_vblank_func; extern const struct nvkm_event_func nv50_disp_vblank_func;
extern const struct nv50_disp_mthd_chan nv84_disp_mast_mthd_chan; extern const struct nv50_disp_mthd_chan nv84_disp_core_mthd_chan;
extern const struct nv50_disp_mthd_list nv84_disp_mast_mthd_dac; extern const struct nv50_disp_mthd_list nv84_disp_core_mthd_dac;
extern const struct nv50_disp_mthd_list nv84_disp_mast_mthd_head; extern const struct nv50_disp_mthd_list nv84_disp_core_mthd_head;
extern const struct nv50_disp_mthd_chan nv84_disp_sync_mthd_chan; extern const struct nv50_disp_mthd_chan nv84_disp_base_mthd_chan;
extern const struct nv50_disp_mthd_chan nv84_disp_ovly_mthd_chan; extern const struct nv50_disp_mthd_chan nv84_disp_ovly_mthd_chan;
extern const struct nv50_disp_mthd_chan nv94_disp_mast_mthd_chan; extern const struct nv50_disp_mthd_chan nv94_disp_core_mthd_chan;
extern struct nv50_disp_chan_impl nvd0_disp_mast_ofuncs; extern struct nv50_disp_chan_impl nvd0_disp_core_ofuncs;
extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_base; extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_base;
extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_dac; extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_dac;
extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_sor; extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_sor;
extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_pior; extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_pior;
extern struct nv50_disp_chan_impl nvd0_disp_sync_ofuncs; extern struct nv50_disp_chan_impl nvd0_disp_base_ofuncs;
extern struct nv50_disp_chan_impl nvd0_disp_ovly_ofuncs; extern struct nv50_disp_chan_impl nvd0_disp_ovly_ofuncs;
extern const struct nv50_disp_mthd_chan nvd0_disp_sync_mthd_chan; extern const struct nv50_disp_mthd_chan nvd0_disp_base_mthd_chan;
extern struct nv50_disp_chan_impl nvd0_disp_oimm_ofuncs; extern struct nv50_disp_chan_impl nvd0_disp_oimm_ofuncs;
extern struct nv50_disp_chan_impl nvd0_disp_curs_ofuncs; extern struct nv50_disp_chan_impl nvd0_disp_curs_ofuncs;
extern struct nouveau_ofuncs nvd0_disp_base_ofuncs; extern struct nouveau_ofuncs nvd0_disp_main_ofuncs;
extern struct nouveau_oclass nvd0_disp_cclass; extern struct nouveau_oclass nvd0_disp_cclass;
void nvd0_disp_intr_supervisor(struct work_struct *); void nvd0_disp_intr_supervisor(struct work_struct *);
void nvd0_disp_intr(struct nouveau_subdev *); void nvd0_disp_intr(struct nouveau_subdev *);
extern const struct nvkm_event_func nvd0_disp_vblank_func; extern const struct nvkm_event_func nvd0_disp_vblank_func;
extern const struct nv50_disp_mthd_chan nve0_disp_mast_mthd_chan; extern const struct nv50_disp_mthd_chan nve0_disp_core_mthd_chan;
extern const struct nv50_disp_mthd_chan nve0_disp_ovly_mthd_chan; extern const struct nv50_disp_mthd_chan nve0_disp_ovly_mthd_chan;
extern struct nvkm_output_dp_impl nv50_pior_dp_impl; extern struct nvkm_output_dp_impl nv50_pior_dp_impl;
......
drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
View file @ 2832271d
...@@ -34,7 +34,7 @@ ...@@ -34,7 +34,7 @@
******************************************************************************/ ******************************************************************************/
const struct nv50_disp_mthd_list const struct nv50_disp_mthd_list
nv84_disp_mast_mthd_dac = { nv84_disp_core_mthd_dac = {
.mthd = 0x0080, .mthd = 0x0080,
.addr = 0x000008, .addr = 0x000008,
.data = { .data = {
...@@ -46,7 +46,7 @@ nv84_disp_mast_mthd_dac = { ...@@ -46,7 +46,7 @@ nv84_disp_mast_mthd_dac = {
}; };
const struct nv50_disp_mthd_list const struct nv50_disp_mthd_list
nv84_disp_mast_mthd_head = { nv84_disp_core_mthd_head = {
.mthd = 0x0400, .mthd = 0x0400,
.addr = 0x000540, .addr = 0x000540,
.data = { .data = {
...@@ -98,15 +98,15 @@ nv84_disp_mast_mthd_head = { ...@@ -98,15 +98,15 @@ nv84_disp_mast_mthd_head = {
}; };
const struct nv50_disp_mthd_chan const struct nv50_disp_mthd_chan
nv84_disp_mast_mthd_chan = { nv84_disp_core_mthd_chan = {
.name = "Core", .name = "Core",
.addr = 0x000000, .addr = 0x000000,
.data = { .data = {
{ "Global", 1, &nv50_disp_mast_mthd_base }, { "Global", 1, &nv50_disp_core_mthd_base },
{ "DAC", 3, &nv84_disp_mast_mthd_dac }, { "DAC", 3, &nv84_disp_core_mthd_dac },
{ "SOR", 2, &nv50_disp_mast_mthd_sor }, { "SOR", 2, &nv50_disp_core_mthd_sor },
{ "PIOR", 3, &nv50_disp_mast_mthd_pior }, { "PIOR", 3, &nv50_disp_core_mthd_pior },
{ "HEAD", 2, &nv84_disp_mast_mthd_head }, { "HEAD", 2, &nv84_disp_core_mthd_head },
{} {}
} }
}; };
...@@ -116,7 +116,7 @@ nv84_disp_mast_mthd_chan = { ...@@ -116,7 +116,7 @@ nv84_disp_mast_mthd_chan = {
******************************************************************************/ ******************************************************************************/
static const struct nv50_disp_mthd_list static const struct nv50_disp_mthd_list
nv84_disp_sync_mthd_base = { nv84_disp_base_mthd_base = {
.mthd = 0x0000, .mthd = 0x0000,
.addr = 0x000000, .addr = 0x000000,
.data = { .data = {
...@@ -146,12 +146,12 @@ nv84_disp_sync_mthd_base = { ...@@ -146,12 +146,12 @@ nv84_disp_sync_mthd_base = {
}; };
const struct nv50_disp_mthd_chan const struct nv50_disp_mthd_chan
nv84_disp_sync_mthd_chan = { nv84_disp_base_mthd_chan = {
.name = "Base", .name = "Base",
.addr = 0x000540, .addr = 0x000540,
.data = { .data = {
{ "Global", 1, &nv84_disp_sync_mthd_base }, { "Global", 1, &nv84_disp_base_mthd_base },
{ "Image", 2, &nv50_disp_sync_mthd_image }, { "Image", 2, &nv50_disp_base_mthd_image },
{} {}
} }
}; };
...@@ -204,8 +204,8 @@ nv84_disp_ovly_mthd_chan = { ...@@ -204,8 +204,8 @@ nv84_disp_ovly_mthd_chan = {
static struct nouveau_oclass static struct nouveau_oclass
nv84_disp_sclass[] = { nv84_disp_sclass[] = {
{ G82_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base }, { G82_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
{ G82_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base }, { G82_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
{ G82_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base }, { G82_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
{ G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base }, { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
{ G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base }, { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
...@@ -213,8 +213,8 @@ nv84_disp_sclass[] = { ...@@ -213,8 +213,8 @@ nv84_disp_sclass[] = {
}; };
static struct nouveau_oclass static struct nouveau_oclass
nv84_disp_base_oclass[] = { nv84_disp_main_oclass[] = {
{ G82_DISP, &nv50_disp_base_ofuncs }, { G82_DISP, &nv50_disp_main_ofuncs },
{} {}
}; };
...@@ -240,7 +240,7 @@ nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -240,7 +240,7 @@ nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret) if (ret)
return ret; return ret;
nv_engine(priv)->sclass = nv84_disp_base_oclass; nv_engine(priv)->sclass = nv84_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass; nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = nv50_disp_intr; nv_subdev(priv)->intr = nv50_disp_intr;
INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
...@@ -268,9 +268,9 @@ nv84_disp_oclass = &(struct nv50_disp_impl) { ...@@ -268,9 +268,9 @@ nv84_disp_oclass = &(struct nv50_disp_impl) {
}, },
.base.vblank = &nv50_disp_vblank_func, .base.vblank = &nv50_disp_vblank_func,
.base.outp = nv50_disp_outp_sclass, .base.outp = nv50_disp_outp_sclass,
.mthd.core = &nv84_disp_mast_mthd_chan, .mthd.core = &nv84_disp_core_mthd_chan,
.mthd.base = &nv84_disp_sync_mthd_chan, .mthd.base = &nv84_disp_base_mthd_chan,
.mthd.ovly = &nv84_disp_ovly_mthd_chan, .mthd.ovly = &nv84_disp_ovly_mthd_chan,
.mthd.prev = 0x000004, .mthd.prev = 0x000004,
.head.scanoutpos = nv50_disp_base_scanoutpos, .head.scanoutpos = nv50_disp_main_scanoutpos,
}.base.base; }.base.base;
drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
View file @ 2832271d
...@@ -34,7 +34,7 @@ ...@@ -34,7 +34,7 @@
******************************************************************************/ ******************************************************************************/
const struct nv50_disp_mthd_list const struct nv50_disp_mthd_list
nv94_disp_mast_mthd_sor = { nv94_disp_core_mthd_sor = {
.mthd = 0x0040, .mthd = 0x0040,
.addr = 0x000008, .addr = 0x000008,
.data = { .data = {
...@@ -44,15 +44,15 @@ nv94_disp_mast_mthd_sor = { ...@@ -44,15 +44,15 @@ nv94_disp_mast_mthd_sor = {
}; };
const struct nv50_disp_mthd_chan const struct nv50_disp_mthd_chan
nv94_disp_mast_mthd_chan = { nv94_disp_core_mthd_chan = {
.name = "Core", .name = "Core",
.addr = 0x000000, .addr = 0x000000,
.data = { .data = {
{ "Global", 1, &nv50_disp_mast_mthd_base }, { "Global", 1, &nv50_disp_core_mthd_base },
{ "DAC", 3, &nv84_disp_mast_mthd_dac }, { "DAC", 3, &nv84_disp_core_mthd_dac },
{ "SOR", 4, &nv94_disp_mast_mthd_sor }, { "SOR", 4, &nv94_disp_core_mthd_sor },
{ "PIOR", 3, &nv50_disp_mast_mthd_pior }, { "PIOR", 3, &nv50_disp_core_mthd_pior },
{ "HEAD", 2, &nv84_disp_mast_mthd_head }, { "HEAD", 2, &nv84_disp_core_mthd_head },
{} {}
} }
}; };
...@@ -63,8 +63,8 @@ nv94_disp_mast_mthd_chan = { ...@@ -63,8 +63,8 @@ nv94_disp_mast_mthd_chan = {
static struct nouveau_oclass static struct nouveau_oclass
nv94_disp_sclass[] = { nv94_disp_sclass[] = {
{ GT206_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base }, { GT206_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
{ GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base }, { GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
{ GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base }, { GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
{ G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base }, { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
{ G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base }, { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
...@@ -72,8 +72,8 @@ nv94_disp_sclass[] = { ...@@ -72,8 +72,8 @@ nv94_disp_sclass[] = {
}; };
static struct nouveau_oclass static struct nouveau_oclass
nv94_disp_base_oclass[] = { nv94_disp_main_oclass[] = {
{ GT206_DISP, &nv50_disp_base_ofuncs }, { GT206_DISP, &nv50_disp_main_ofuncs },
{} {}
}; };
...@@ -99,7 +99,7 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -99,7 +99,7 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret) if (ret)
return ret; return ret;
nv_engine(priv)->sclass = nv94_disp_base_oclass; nv_engine(priv)->sclass = nv94_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass; nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = nv50_disp_intr; nv_subdev(priv)->intr = nv50_disp_intr;
INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
...@@ -134,9 +134,9 @@ nv94_disp_oclass = &(struct nv50_disp_impl) { ...@@ -134,9 +134,9 @@ nv94_disp_oclass = &(struct nv50_disp_impl) {
}, },
.base.vblank = &nv50_disp_vblank_func, .base.vblank = &nv50_disp_vblank_func,
.base.outp = nv94_disp_outp_sclass, .base.outp = nv94_disp_outp_sclass,
.mthd.core = &nv94_disp_mast_mthd_chan, .mthd.core = &nv94_disp_core_mthd_chan,
.mthd.base = &nv84_disp_sync_mthd_chan, .mthd.base = &nv84_disp_base_mthd_chan,
.mthd.ovly = &nv84_disp_ovly_mthd_chan, .mthd.ovly = &nv84_disp_ovly_mthd_chan,
.mthd.prev = 0x000004, .mthd.prev = 0x000004,
.head.scanoutpos = nv50_disp_base_scanoutpos, .head.scanoutpos = nv50_disp_main_scanoutpos,
}.base.base; }.base.base;
drivers/gpu/drm/nouveau/core/engine/disp/nva0.c
View file @ 2832271d
...@@ -80,8 +80,8 @@ nva0_disp_ovly_mthd_chan = { ...@@ -80,8 +80,8 @@ nva0_disp_ovly_mthd_chan = {
static struct nouveau_oclass static struct nouveau_oclass
nva0_disp_sclass[] = { nva0_disp_sclass[] = {
{ GT200_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base }, { GT200_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
{ GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base }, { GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
{ GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base }, { GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
{ G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base }, { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
{ G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base }, { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
...@@ -89,8 +89,8 @@ nva0_disp_sclass[] = { ...@@ -89,8 +89,8 @@ nva0_disp_sclass[] = {
}; };
static struct nouveau_oclass static struct nouveau_oclass
nva0_disp_base_oclass[] = { nva0_disp_main_oclass[] = {
{ GT200_DISP, &nv50_disp_base_ofuncs }, { GT200_DISP, &nv50_disp_main_ofuncs },
{} {}
}; };
...@@ -116,7 +116,7 @@ nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -116,7 +116,7 @@ nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret) if (ret)
return ret; return ret;
nv_engine(priv)->sclass = nva0_disp_base_oclass; nv_engine(priv)->sclass = nva0_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass; nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = nv50_disp_intr; nv_subdev(priv)->intr = nv50_disp_intr;
INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
...@@ -144,9 +144,9 @@ nva0_disp_oclass = &(struct nv50_disp_impl) { ...@@ -144,9 +144,9 @@ nva0_disp_oclass = &(struct nv50_disp_impl) {
}, },
.base.vblank = &nv50_disp_vblank_func, .base.vblank = &nv50_disp_vblank_func,
.base.outp = nv50_disp_outp_sclass, .base.outp = nv50_disp_outp_sclass,
.mthd.core = &nv84_disp_mast_mthd_chan, .mthd.core = &nv84_disp_core_mthd_chan,
.mthd.base = &nv84_disp_sync_mthd_chan, .mthd.base = &nv84_disp_base_mthd_chan,
.mthd.ovly = &nva0_disp_ovly_mthd_chan, .mthd.ovly = &nva0_disp_ovly_mthd_chan,
.mthd.prev = 0x000004, .mthd.prev = 0x000004,
.head.scanoutpos = nv50_disp_base_scanoutpos, .head.scanoutpos = nv50_disp_main_scanoutpos,
}.base.base; }.base.base;
drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
View file @ 2832271d
...@@ -35,8 +35,8 @@ ...@@ -35,8 +35,8 @@
static struct nouveau_oclass static struct nouveau_oclass
nva3_disp_sclass[] = { nva3_disp_sclass[] = {
{ GT214_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base }, { GT214_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
{ GT214_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base }, { GT214_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
{ GT214_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base }, { GT214_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
{ GT214_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base }, { GT214_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
{ GT214_DISP_CURSOR, &nv50_disp_curs_ofuncs.base }, { GT214_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
...@@ -44,8 +44,8 @@ nva3_disp_sclass[] = { ...@@ -44,8 +44,8 @@ nva3_disp_sclass[] = {
}; };
static struct nouveau_oclass static struct nouveau_oclass
nva3_disp_base_oclass[] = { nva3_disp_main_oclass[] = {
{ GT214_DISP, &nv50_disp_base_ofuncs }, { GT214_DISP, &nv50_disp_main_ofuncs },
{} {}
}; };
...@@ -71,7 +71,7 @@ nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -71,7 +71,7 @@ nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret) if (ret)
return ret; return ret;
nv_engine(priv)->sclass = nva3_disp_base_oclass; nv_engine(priv)->sclass = nva3_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass; nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = nv50_disp_intr; nv_subdev(priv)->intr = nv50_disp_intr;
INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
...@@ -100,9 +100,9 @@ nva3_disp_oclass = &(struct nv50_disp_impl) { ...@@ -100,9 +100,9 @@ nva3_disp_oclass = &(struct nv50_disp_impl) {
}, },
.base.vblank = &nv50_disp_vblank_func, .base.vblank = &nv50_disp_vblank_func,
.base.outp = nv94_disp_outp_sclass, .base.outp = nv94_disp_outp_sclass,
.mthd.core = &nv94_disp_mast_mthd_chan, .mthd.core = &nv94_disp_core_mthd_chan,
.mthd.base = &nv84_disp_sync_mthd_chan, .mthd.base = &nv84_disp_base_mthd_chan,
.mthd.ovly = &nv84_disp_ovly_mthd_chan, .mthd.ovly = &nv84_disp_ovly_mthd_chan,
.mthd.prev = 0x000004, .mthd.prev = 0x000004,
.head.scanoutpos = nv50_disp_base_scanoutpos, .head.scanoutpos = nv50_disp_main_scanoutpos,
}.base.base; }.base.base;
drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
View file @ 2832271d
...@@ -151,7 +151,7 @@ nvd0_disp_dmac_fini(struct nouveau_object *object, bool suspend) ...@@ -151,7 +151,7 @@ nvd0_disp_dmac_fini(struct nouveau_object *object, bool suspend)
******************************************************************************/ ******************************************************************************/
const struct nv50_disp_mthd_list const struct nv50_disp_mthd_list
nvd0_disp_mast_mthd_base = { nvd0_disp_core_mthd_base = {
.mthd = 0x0000, .mthd = 0x0000,
.addr = 0x000000, .addr = 0x000000,
.data = { .data = {
...@@ -164,7 +164,7 @@ nvd0_disp_mast_mthd_base = { ...@@ -164,7 +164,7 @@ nvd0_disp_mast_mthd_base = {
}; };
const struct nv50_disp_mthd_list const struct nv50_disp_mthd_list
nvd0_disp_mast_mthd_dac = { nvd0_disp_core_mthd_dac = {
.mthd = 0x0020, .mthd = 0x0020,
.addr = 0x000020, .addr = 0x000020,
.data = { .data = {
...@@ -177,7 +177,7 @@ nvd0_disp_mast_mthd_dac = { ...@@ -177,7 +177,7 @@ nvd0_disp_mast_mthd_dac = {
}; };
const struct nv50_disp_mthd_list const struct nv50_disp_mthd_list
nvd0_disp_mast_mthd_sor = { nvd0_disp_core_mthd_sor = {
.mthd = 0x0020, .mthd = 0x0020,
.addr = 0x000020, .addr = 0x000020,
.data = { .data = {
...@@ -190,7 +190,7 @@ nvd0_disp_mast_mthd_sor = { ...@@ -190,7 +190,7 @@ nvd0_disp_mast_mthd_sor = {
}; };
const struct nv50_disp_mthd_list const struct nv50_disp_mthd_list
nvd0_disp_mast_mthd_pior = { nvd0_disp_core_mthd_pior = {
.mthd = 0x0020, .mthd = 0x0020,
.addr = 0x000020, .addr = 0x000020,
.data = { .data = {
...@@ -203,7 +203,7 @@ nvd0_disp_mast_mthd_pior = { ...@@ -203,7 +203,7 @@ nvd0_disp_mast_mthd_pior = {
}; };
static const struct nv50_disp_mthd_list static const struct nv50_disp_mthd_list
nvd0_disp_mast_mthd_head = { nvd0_disp_core_mthd_head = {
.mthd = 0x0300, .mthd = 0x0300,
.addr = 0x000300, .addr = 0x000300,
.data = { .data = {
...@@ -277,21 +277,21 @@ nvd0_disp_mast_mthd_head = { ...@@ -277,21 +277,21 @@ nvd0_disp_mast_mthd_head = {
}; };
static const struct nv50_disp_mthd_chan static const struct nv50_disp_mthd_chan
nvd0_disp_mast_mthd_chan = { nvd0_disp_core_mthd_chan = {
.name = "Core", .name = "Core",
.addr = 0x000000, .addr = 0x000000,
.data = { .data = {
{ "Global", 1, &nvd0_disp_mast_mthd_base }, { "Global", 1, &nvd0_disp_core_mthd_base },
{ "DAC", 3, &nvd0_disp_mast_mthd_dac }, { "DAC", 3, &nvd0_disp_core_mthd_dac },
{ "SOR", 8, &nvd0_disp_mast_mthd_sor }, { "SOR", 8, &nvd0_disp_core_mthd_sor },
{ "PIOR", 4, &nvd0_disp_mast_mthd_pior }, { "PIOR", 4, &nvd0_disp_core_mthd_pior },
{ "HEAD", 4, &nvd0_disp_mast_mthd_head }, { "HEAD", 4, &nvd0_disp_core_mthd_head },
{} {}
} }
}; };
static int static int
nvd0_disp_mast_init(struct nouveau_object *object) nvd0_disp_core_init(struct nouveau_object *object)
{ {
struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_dmac *mast = (void *)object; struct nv50_disp_dmac *mast = (void *)object;
...@@ -322,7 +322,7 @@ nvd0_disp_mast_init(struct nouveau_object *object) ...@@ -322,7 +322,7 @@ nvd0_disp_mast_init(struct nouveau_object *object)
} }
static int static int
nvd0_disp_mast_fini(struct nouveau_object *object, bool suspend) nvd0_disp_core_fini(struct nouveau_object *object, bool suspend)
{ {
struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_dmac *mast = (void *)object; struct nv50_disp_dmac *mast = (void *)object;
...@@ -344,11 +344,11 @@ nvd0_disp_mast_fini(struct nouveau_object *object, bool suspend) ...@@ -344,11 +344,11 @@ nvd0_disp_mast_fini(struct nouveau_object *object, bool suspend)
} }
struct nv50_disp_chan_impl struct nv50_disp_chan_impl
nvd0_disp_mast_ofuncs = { nvd0_disp_core_ofuncs = {
.base.ctor = nv50_disp_mast_ctor, .base.ctor = nv50_disp_core_ctor,
.base.dtor = nv50_disp_dmac_dtor, .base.dtor = nv50_disp_dmac_dtor,
.base.init = nvd0_disp_mast_init, .base.init = nvd0_disp_core_init,
.base.fini = nvd0_disp_mast_fini, .base.fini = nvd0_disp_core_fini,
.base.ntfy = nv50_disp_chan_ntfy, .base.ntfy = nv50_disp_chan_ntfy,
.base.map = nv50_disp_chan_map, .base.map = nv50_disp_chan_map,
.base.rd32 = nv50_disp_chan_rd32, .base.rd32 = nv50_disp_chan_rd32,
...@@ -363,7 +363,7 @@ nvd0_disp_mast_ofuncs = { ...@@ -363,7 +363,7 @@ nvd0_disp_mast_ofuncs = {
******************************************************************************/ ******************************************************************************/
static const struct nv50_disp_mthd_list static const struct nv50_disp_mthd_list
nvd0_disp_sync_mthd_base = { nvd0_disp_base_mthd_base = {
.mthd = 0x0000, .mthd = 0x0000,
.addr = 0x000000, .addr = 0x000000,
.data = { .data = {
...@@ -413,7 +413,7 @@ nvd0_disp_sync_mthd_base = { ...@@ -413,7 +413,7 @@ nvd0_disp_sync_mthd_base = {
}; };
static const struct nv50_disp_mthd_list static const struct nv50_disp_mthd_list
nvd0_disp_sync_mthd_image = { nvd0_disp_base_mthd_image = {
.mthd = 0x0400, .mthd = 0x0400,
.addr = 0x000400, .addr = 0x000400,
.data = { .data = {
...@@ -427,19 +427,19 @@ nvd0_disp_sync_mthd_image = { ...@@ -427,19 +427,19 @@ nvd0_disp_sync_mthd_image = {
}; };
const struct nv50_disp_mthd_chan const struct nv50_disp_mthd_chan
nvd0_disp_sync_mthd_chan = { nvd0_disp_base_mthd_chan = {
.name = "Base", .name = "Base",
.addr = 0x001000, .addr = 0x001000,
.data = { .data = {
{ "Global", 1, &nvd0_disp_sync_mthd_base }, { "Global", 1, &nvd0_disp_base_mthd_base },
{ "Image", 2, &nvd0_disp_sync_mthd_image }, { "Image", 2, &nvd0_disp_base_mthd_image },
{} {}
} }
}; };
struct nv50_disp_chan_impl struct nv50_disp_chan_impl
nvd0_disp_sync_ofuncs = { nvd0_disp_base_ofuncs = {
.base.ctor = nv50_disp_sync_ctor, .base.ctor = nv50_disp_base_ctor,
.base.dtor = nv50_disp_dmac_dtor, .base.dtor = nv50_disp_dmac_dtor,
.base.init = nvd0_disp_dmac_init, .base.init = nvd0_disp_dmac_init,
.base.fini = nvd0_disp_dmac_fini, .base.fini = nvd0_disp_dmac_fini,
...@@ -624,7 +624,7 @@ nvd0_disp_curs_ofuncs = { ...@@ -624,7 +624,7 @@ nvd0_disp_curs_ofuncs = {
******************************************************************************/ ******************************************************************************/
int int
nvd0_disp_base_scanoutpos(NV50_DISP_MTHD_V0) nvd0_disp_main_scanoutpos(NV50_DISP_MTHD_V0)
{ {
const u32 total = nv_rd32(priv, 0x640414 + (head * 0x300)); const u32 total = nv_rd32(priv, 0x640414 + (head * 0x300));
const u32 blanke = nv_rd32(priv, 0x64041c + (head * 0x300)); const u32 blanke = nv_rd32(priv, 0x64041c + (head * 0x300));
...@@ -656,7 +656,7 @@ nvd0_disp_base_scanoutpos(NV50_DISP_MTHD_V0) ...@@ -656,7 +656,7 @@ nvd0_disp_base_scanoutpos(NV50_DISP_MTHD_V0)
} }
static int static int
nvd0_disp_base_init(struct nouveau_object *object) nvd0_disp_main_init(struct nouveau_object *object)
{ {
struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_base *base = (void *)object; struct nv50_disp_base *base = (void *)object;
...@@ -725,7 +725,7 @@ nvd0_disp_base_init(struct nouveau_object *object) ...@@ -725,7 +725,7 @@ nvd0_disp_base_init(struct nouveau_object *object)
} }
static int static int
nvd0_disp_base_fini(struct nouveau_object *object, bool suspend) nvd0_disp_main_fini(struct nouveau_object *object, bool suspend)
{ {
struct nv50_disp_priv *priv = (void *)object->engine; struct nv50_disp_priv *priv = (void *)object->engine;
struct nv50_disp_base *base = (void *)object; struct nv50_disp_base *base = (void *)object;
...@@ -737,25 +737,25 @@ nvd0_disp_base_fini(struct nouveau_object *object, bool suspend) ...@@ -737,25 +737,25 @@ nvd0_disp_base_fini(struct nouveau_object *object, bool suspend)
} }
struct nouveau_ofuncs struct nouveau_ofuncs
nvd0_disp_base_ofuncs = { nvd0_disp_main_ofuncs = {
.ctor = nv50_disp_base_ctor, .ctor = nv50_disp_main_ctor,
.dtor = nv50_disp_base_dtor, .dtor = nv50_disp_main_dtor,
.init = nvd0_disp_base_init, .init = nvd0_disp_main_init,
.fini = nvd0_disp_base_fini, .fini = nvd0_disp_main_fini,
.mthd = nv50_disp_base_mthd, .mthd = nv50_disp_main_mthd,
.ntfy = nouveau_disp_ntfy, .ntfy = nouveau_disp_ntfy,
}; };
static struct nouveau_oclass static struct nouveau_oclass
nvd0_disp_base_oclass[] = { nvd0_disp_main_oclass[] = {
{ GF110_DISP, &nvd0_disp_base_ofuncs }, { GF110_DISP, &nvd0_disp_main_ofuncs },
{} {}
}; };
static struct nouveau_oclass static struct nouveau_oclass
nvd0_disp_sclass[] = { nvd0_disp_sclass[] = {
{ GF110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base }, { GF110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
{ GF110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base }, { GF110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
{ GF110_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base }, { GF110_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
{ GF110_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base }, { GF110_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
{ GF110_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base }, { GF110_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
...@@ -1270,7 +1270,7 @@ nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -1270,7 +1270,7 @@ nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret) if (ret)
return ret; return ret;
nv_engine(priv)->sclass = nvd0_disp_base_oclass; nv_engine(priv)->sclass = nvd0_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass; nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = nvd0_disp_intr; nv_subdev(priv)->intr = nvd0_disp_intr;
INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor); INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
...@@ -1303,9 +1303,9 @@ nvd0_disp_oclass = &(struct nv50_disp_impl) { ...@@ -1303,9 +1303,9 @@ nvd0_disp_oclass = &(struct nv50_disp_impl) {
}, },
.base.vblank = &nvd0_disp_vblank_func, .base.vblank = &nvd0_disp_vblank_func,
.base.outp = nvd0_disp_outp_sclass, .base.outp = nvd0_disp_outp_sclass,
.mthd.core = &nvd0_disp_mast_mthd_chan, .mthd.core = &nvd0_disp_core_mthd_chan,
.mthd.base = &nvd0_disp_sync_mthd_chan, .mthd.base = &nvd0_disp_base_mthd_chan,
.mthd.ovly = &nvd0_disp_ovly_mthd_chan, .mthd.ovly = &nvd0_disp_ovly_mthd_chan,
.mthd.prev = -0x020000, .mthd.prev = -0x020000,
.head.scanoutpos = nvd0_disp_base_scanoutpos, .head.scanoutpos = nvd0_disp_main_scanoutpos,
}.base.base; }.base.base;
drivers/gpu/drm/nouveau/core/engine/disp/nve0.c
View file @ 2832271d
...@@ -34,7 +34,7 @@ ...@@ -34,7 +34,7 @@
******************************************************************************/ ******************************************************************************/
static const struct nv50_disp_mthd_list static const struct nv50_disp_mthd_list
nve0_disp_mast_mthd_head = { nve0_disp_core_mthd_head = {
.mthd = 0x0300, .mthd = 0x0300,
.addr = 0x000300, .addr = 0x000300,
.data = { .data = {
...@@ -113,15 +113,15 @@ nve0_disp_mast_mthd_head = { ...@@ -113,15 +113,15 @@ nve0_disp_mast_mthd_head = {
}; };
const struct nv50_disp_mthd_chan const struct nv50_disp_mthd_chan
nve0_disp_mast_mthd_chan = { nve0_disp_core_mthd_chan = {
.name = "Core", .name = "Core",
.addr = 0x000000, .addr = 0x000000,
.data = { .data = {
{ "Global", 1, &nvd0_disp_mast_mthd_base }, { "Global", 1, &nvd0_disp_core_mthd_base },
{ "DAC", 3, &nvd0_disp_mast_mthd_dac }, { "DAC", 3, &nvd0_disp_core_mthd_dac },
{ "SOR", 8, &nvd0_disp_mast_mthd_sor }, { "SOR", 8, &nvd0_disp_core_mthd_sor },
{ "PIOR", 4, &nvd0_disp_mast_mthd_pior }, { "PIOR", 4, &nvd0_disp_core_mthd_pior },
{ "HEAD", 4, &nve0_disp_mast_mthd_head }, { "HEAD", 4, &nve0_disp_core_mthd_head },
{} {}
} }
}; };
...@@ -200,8 +200,8 @@ nve0_disp_ovly_mthd_chan = { ...@@ -200,8 +200,8 @@ nve0_disp_ovly_mthd_chan = {
static struct nouveau_oclass static struct nouveau_oclass
nve0_disp_sclass[] = { nve0_disp_sclass[] = {
{ GK104_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base }, { GK104_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
{ GK104_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base }, { GK104_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
{ GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base }, { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
{ GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base }, { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
{ GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base }, { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
...@@ -209,8 +209,8 @@ nve0_disp_sclass[] = { ...@@ -209,8 +209,8 @@ nve0_disp_sclass[] = {
}; };
static struct nouveau_oclass static struct nouveau_oclass
nve0_disp_base_oclass[] = { nve0_disp_main_oclass[] = {
{ GK104_DISP, &nvd0_disp_base_ofuncs }, { GK104_DISP, &nvd0_disp_main_ofuncs },
{} {}
}; };
...@@ -237,7 +237,7 @@ nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -237,7 +237,7 @@ nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret) if (ret)
return ret; return ret;
nv_engine(priv)->sclass = nve0_disp_base_oclass; nv_engine(priv)->sclass = nve0_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass; nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = nvd0_disp_intr; nv_subdev(priv)->intr = nvd0_disp_intr;
INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor); INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
...@@ -264,9 +264,9 @@ nve0_disp_oclass = &(struct nv50_disp_impl) { ...@@ -264,9 +264,9 @@ nve0_disp_oclass = &(struct nv50_disp_impl) {
}, },
.base.vblank = &nvd0_disp_vblank_func, .base.vblank = &nvd0_disp_vblank_func,
.base.outp = nvd0_disp_outp_sclass, .base.outp = nvd0_disp_outp_sclass,
.mthd.core = &nve0_disp_mast_mthd_chan, .mthd.core = &nve0_disp_core_mthd_chan,
.mthd.base = &nvd0_disp_sync_mthd_chan, .mthd.base = &nvd0_disp_base_mthd_chan,
.mthd.ovly = &nve0_disp_ovly_mthd_chan, .mthd.ovly = &nve0_disp_ovly_mthd_chan,
.mthd.prev = -0x020000, .mthd.prev = -0x020000,
.head.scanoutpos = nvd0_disp_base_scanoutpos, .head.scanoutpos = nvd0_disp_main_scanoutpos,
}.base.base; }.base.base;
drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c
View file @ 2832271d
...@@ -35,8 +35,8 @@ ...@@ -35,8 +35,8 @@
static struct nouveau_oclass static struct nouveau_oclass
nvf0_disp_sclass[] = { nvf0_disp_sclass[] = {
{ GK110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base }, { GK110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
{ GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base }, { GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
{ GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base }, { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
{ GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base }, { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
{ GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base }, { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
...@@ -44,8 +44,8 @@ nvf0_disp_sclass[] = { ...@@ -44,8 +44,8 @@ nvf0_disp_sclass[] = {
}; };
static struct nouveau_oclass static struct nouveau_oclass
nvf0_disp_base_oclass[] = { nvf0_disp_main_oclass[] = {
{ GK110_DISP, &nvd0_disp_base_ofuncs }, { GK110_DISP, &nvd0_disp_main_ofuncs },
{} {}
}; };
...@@ -72,7 +72,7 @@ nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, ...@@ -72,7 +72,7 @@ nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret) if (ret)
return ret; return ret;
nv_engine(priv)->sclass = nvf0_disp_base_oclass; nv_engine(priv)->sclass = nvf0_disp_main_oclass;
nv_engine(priv)->cclass = &nv50_disp_cclass; nv_engine(priv)->cclass = &nv50_disp_cclass;
nv_subdev(priv)->intr = nvd0_disp_intr; nv_subdev(priv)->intr = nvd0_disp_intr;
INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor); INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
...@@ -99,9 +99,9 @@ nvf0_disp_oclass = &(struct nv50_disp_impl) { ...@@ -99,9 +99,9 @@ nvf0_disp_oclass = &(struct nv50_disp_impl) {
}, },
.base.vblank = &nvd0_disp_vblank_func, .base.vblank = &nvd0_disp_vblank_func,
.base.outp = nvd0_disp_outp_sclass, .base.outp = nvd0_disp_outp_sclass,
.mthd.core = &nve0_disp_mast_mthd_chan, .mthd.core = &nve0_disp_core_mthd_chan,
.mthd.base = &nvd0_disp_sync_mthd_chan, .mthd.base = &nvd0_disp_base_mthd_chan,
.mthd.ovly = &nve0_disp_ovly_mthd_chan, .mthd.ovly = &nve0_disp_ovly_mthd_chan,
.mthd.prev = -0x020000, .mthd.prev = -0x020000,
.head.scanoutpos = nvd0_disp_base_scanoutpos, .head.scanoutpos = nvd0_disp_main_scanoutpos,
}.base.base; }.base.base;
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