Commit 285484e2 authored by Jerome Glisse's avatar Jerome Glisse Committed by Dave Airlie

drm/radeon: add support for evergreen/ni tiling informations v11

evergreen and northern island gpu needs more informations for 2D tiling
than previous r6xx/r7xx. Add field to tiling ioctl to allow userspace
to provide those.

The v8 cs checking change to track color view on r6xx/r7xx doesn't
affect old userspace as old userspace always emited 0 for this register.

v2 fix r6xx/r7xx 2D tiling computation
v3 fix r6xx/r7xx height align for untiled surface & add support for
   tile split on evergreen and newer
v4 improve tiling debugging output
v5 fix tile split code for evergreen and newer
v6 set proper tile split for crtc register
v7 fix tile split limit value
v8 add COLOR_VIEW checking to r6xx/r7xx checker, add evergreen cs
   checking, update safe reg for r600, evergreen and cayman.
   Evergreen checking need some work around for stencil alignment
   issues
v9 fix tile split value range, fix compressed texture handling and
   mipmap calculation, allow evergreen check to be silencious in
   front of current broken userspace (depth/stencil alignment issue)
v10 fix eg 3d texture and compressed texture, fix r600 depth array,
    fix r600 color view computation, add support for evergreen stencil
    split
v11 more verbose debugging in some case
Signed-off-by: default avatarJerome Glisse <jglisse@redhat.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent dd220a00
...@@ -1031,6 +1031,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, ...@@ -1031,6 +1031,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
struct radeon_bo *rbo; struct radeon_bo *rbo;
uint64_t fb_location; uint64_t fb_location;
uint32_t fb_format, fb_pitch_pixels, tiling_flags; uint32_t fb_format, fb_pitch_pixels, tiling_flags;
unsigned bankw, bankh, mtaspect, tile_split;
u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
u32 tmp, viewport_w, viewport_h; u32 tmp, viewport_w, viewport_h;
int r; int r;
...@@ -1121,20 +1122,13 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, ...@@ -1121,20 +1122,13 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
break; break;
} }
switch ((tmp & 0xf000) >> 12) {
case 0: /* 1KB rows */
default:
fb_format |= EVERGREEN_GRPH_TILE_SPLIT(EVERGREEN_ADDR_SURF_TILE_SPLIT_1KB);
break;
case 1: /* 2KB rows */
fb_format |= EVERGREEN_GRPH_TILE_SPLIT(EVERGREEN_ADDR_SURF_TILE_SPLIT_2KB);
break;
case 2: /* 4KB rows */
fb_format |= EVERGREEN_GRPH_TILE_SPLIT(EVERGREEN_ADDR_SURF_TILE_SPLIT_4KB);
break;
}
fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
} else if (tiling_flags & RADEON_TILING_MICRO) } else if (tiling_flags & RADEON_TILING_MICRO)
fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
......
...@@ -43,6 +43,37 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev); ...@@ -43,6 +43,37 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev, extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
int ring, u32 cp_int_cntl); int ring, u32 cp_int_cntl);
void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
unsigned *bankh, unsigned *mtaspect,
unsigned *tile_split)
{
*bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
*bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
*mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
*tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
switch (*bankw) {
default:
case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
}
switch (*bankh) {
default:
case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
}
switch (*mtaspect) {
default:
case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
}
}
void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
{ {
u16 ctl, v; u16 ctl, v;
......
This diff is collapsed.
This diff is collapsed.
...@@ -55,6 +55,7 @@ struct r600_cs_track { ...@@ -55,6 +55,7 @@ struct r600_cs_track {
struct radeon_bo *cb_color_frag_bo[8]; struct radeon_bo *cb_color_frag_bo[8];
struct radeon_bo *cb_color_tile_bo[8]; struct radeon_bo *cb_color_tile_bo[8];
u32 cb_color_info[8]; u32 cb_color_info[8];
u32 cb_color_view[8];
u32 cb_color_size_idx[8]; u32 cb_color_size_idx[8];
u32 cb_target_mask; u32 cb_target_mask;
u32 cb_shader_mask; u32 cb_shader_mask;
...@@ -77,9 +78,9 @@ struct r600_cs_track { ...@@ -77,9 +78,9 @@ struct r600_cs_track {
#define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 } #define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 }
#define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 } #define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 }
#define FMT_24_BIT(fmt) [fmt] = { 1, 1, 3, 0, CHIP_R600 } #define FMT_24_BIT(fmt) [fmt] = { 1, 1, 4, 0, CHIP_R600 }
#define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 } #define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 }
#define FMT_48_BIT(fmt) [fmt] = { 1, 1, 6, 0, CHIP_R600 } #define FMT_48_BIT(fmt) [fmt] = { 1, 1, 8, 0, CHIP_R600 }
#define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 } #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 }
#define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 } #define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 }
#define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 } #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }
...@@ -166,7 +167,7 @@ static const struct gpu_formats color_formats_table[] = { ...@@ -166,7 +167,7 @@ static const struct gpu_formats color_formats_table[] = {
[V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR}, [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR},
}; };
static bool fmt_is_valid_color(u32 format) bool r600_fmt_is_valid_color(u32 format)
{ {
if (format >= ARRAY_SIZE(color_formats_table)) if (format >= ARRAY_SIZE(color_formats_table))
return false; return false;
...@@ -177,7 +178,7 @@ static bool fmt_is_valid_color(u32 format) ...@@ -177,7 +178,7 @@ static bool fmt_is_valid_color(u32 format)
return false; return false;
} }
static bool fmt_is_valid_texture(u32 format, enum radeon_family family) bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)
{ {
if (format >= ARRAY_SIZE(color_formats_table)) if (format >= ARRAY_SIZE(color_formats_table))
return false; return false;
...@@ -191,7 +192,7 @@ static bool fmt_is_valid_texture(u32 format, enum radeon_family family) ...@@ -191,7 +192,7 @@ static bool fmt_is_valid_texture(u32 format, enum radeon_family family)
return false; return false;
} }
static int fmt_get_blocksize(u32 format) int r600_fmt_get_blocksize(u32 format)
{ {
if (format >= ARRAY_SIZE(color_formats_table)) if (format >= ARRAY_SIZE(color_formats_table))
return 0; return 0;
...@@ -199,7 +200,7 @@ static int fmt_get_blocksize(u32 format) ...@@ -199,7 +200,7 @@ static int fmt_get_blocksize(u32 format)
return color_formats_table[format].blocksize; return color_formats_table[format].blocksize;
} }
static int fmt_get_nblocksx(u32 format, u32 w) int r600_fmt_get_nblocksx(u32 format, u32 w)
{ {
unsigned bw; unsigned bw;
...@@ -213,7 +214,7 @@ static int fmt_get_nblocksx(u32 format, u32 w) ...@@ -213,7 +214,7 @@ static int fmt_get_nblocksx(u32 format, u32 w)
return (w + bw - 1) / bw; return (w + bw - 1) / bw;
} }
static int fmt_get_nblocksy(u32 format, u32 h) int r600_fmt_get_nblocksy(u32 format, u32 h)
{ {
unsigned bh; unsigned bh;
...@@ -260,7 +261,7 @@ static int r600_get_array_mode_alignment(struct array_mode_checker *values, ...@@ -260,7 +261,7 @@ static int r600_get_array_mode_alignment(struct array_mode_checker *values,
break; break;
case ARRAY_LINEAR_ALIGNED: case ARRAY_LINEAR_ALIGNED:
*pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize)); *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
*height_align = tile_height; *height_align = 1;
*depth_align = 1; *depth_align = 1;
*base_align = values->group_size; *base_align = values->group_size;
break; break;
...@@ -273,10 +274,9 @@ static int r600_get_array_mode_alignment(struct array_mode_checker *values, ...@@ -273,10 +274,9 @@ static int r600_get_array_mode_alignment(struct array_mode_checker *values,
*base_align = values->group_size; *base_align = values->group_size;
break; break;
case ARRAY_2D_TILED_THIN1: case ARRAY_2D_TILED_THIN1:
*pitch_align = max((u32)macro_tile_width, *pitch_align = max((u32)macro_tile_width * tile_width,
(u32)(((values->group_size / tile_height) / (u32)((values->group_size * values->nbanks) /
(values->blocksize * values->nsamples)) * (values->blocksize * values->nsamples * tile_width)));
values->nbanks)) * tile_width;
*height_align = macro_tile_height * tile_height; *height_align = macro_tile_height * tile_height;
*depth_align = 1; *depth_align = 1;
*base_align = max(macro_tile_bytes, *base_align = max(macro_tile_bytes,
...@@ -300,6 +300,7 @@ static void r600_cs_track_init(struct r600_cs_track *track) ...@@ -300,6 +300,7 @@ static void r600_cs_track_init(struct r600_cs_track *track)
track->cb_color_size[i] = 0; track->cb_color_size[i] = 0;
track->cb_color_size_idx[i] = 0; track->cb_color_size_idx[i] = 0;
track->cb_color_info[i] = 0; track->cb_color_info[i] = 0;
track->cb_color_view[i] = 0xFFFFFFFF;
track->cb_color_bo[i] = NULL; track->cb_color_bo[i] = NULL;
track->cb_color_bo_offset[i] = 0xFFFFFFFF; track->cb_color_bo_offset[i] = 0xFFFFFFFF;
track->cb_color_bo_mc[i] = 0xFFFFFFFF; track->cb_color_bo_mc[i] = 0xFFFFFFFF;
...@@ -333,13 +334,14 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) ...@@ -333,13 +334,14 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
volatile u32 *ib = p->ib->ptr; volatile u32 *ib = p->ib->ptr;
unsigned array_mode; unsigned array_mode;
u32 format; u32 format;
if (G_0280A0_TILE_MODE(track->cb_color_info[i])) { if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n"); dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
return -EINVAL; return -EINVAL;
} }
size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i]; size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
format = G_0280A0_FORMAT(track->cb_color_info[i]); format = G_0280A0_FORMAT(track->cb_color_info[i]);
if (!fmt_is_valid_color(format)) { if (!r600_fmt_is_valid_color(format)) {
dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n", dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
__func__, __LINE__, format, __func__, __LINE__, format,
i, track->cb_color_info[i]); i, track->cb_color_info[i]);
...@@ -360,7 +362,7 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) ...@@ -360,7 +362,7 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
array_check.nbanks = track->nbanks; array_check.nbanks = track->nbanks;
array_check.npipes = track->npipes; array_check.npipes = track->npipes;
array_check.nsamples = track->nsamples; array_check.nsamples = track->nsamples;
array_check.blocksize = fmt_get_blocksize(format); array_check.blocksize = r600_fmt_get_blocksize(format);
if (r600_get_array_mode_alignment(&array_check, if (r600_get_array_mode_alignment(&array_check,
&pitch_align, &height_align, &depth_align, &base_align)) { &pitch_align, &height_align, &depth_align, &base_align)) {
dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
...@@ -404,7 +406,18 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) ...@@ -404,7 +406,18 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
} }
/* check offset */ /* check offset */
tmp = fmt_get_nblocksy(format, height) * fmt_get_nblocksx(format, pitch) * fmt_get_blocksize(format); tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) * r600_fmt_get_blocksize(format);
switch (array_mode) {
default:
case V_0280A0_ARRAY_LINEAR_GENERAL:
case V_0280A0_ARRAY_LINEAR_ALIGNED:
tmp += track->cb_color_view[i] & 0xFF;
break;
case V_0280A0_ARRAY_1D_TILED_THIN1:
case V_0280A0_ARRAY_2D_TILED_THIN1:
tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
break;
}
if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) { if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) { if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
/* the initial DDX does bad things with the CB size occasionally */ /* the initial DDX does bad things with the CB size occasionally */
...@@ -414,10 +427,13 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) ...@@ -414,10 +427,13 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
* broken userspace. * broken userspace.
*/ */
} else { } else {
dev_warn(p->dev, "%s offset[%d] %d %d %d %lu too big\n", __func__, i, dev_warn(p->dev, "%s offset[%d] %d %d %d %lu too big (%d %d) (%d %d %d)\n",
array_mode, __func__, i, array_mode,
track->cb_color_bo_offset[i], tmp, track->cb_color_bo_offset[i], tmp,
radeon_bo_size(track->cb_color_bo[i])); radeon_bo_size(track->cb_color_bo[i]),
pitch, height, r600_fmt_get_nblocksx(format, pitch),
r600_fmt_get_nblocksy(format, height),
r600_fmt_get_blocksize(format));
return -EINVAL; return -EINVAL;
} }
} }
...@@ -1075,6 +1091,17 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) ...@@ -1075,6 +1091,17 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
} }
break; break;
case R_028080_CB_COLOR0_VIEW:
case R_028084_CB_COLOR1_VIEW:
case R_028088_CB_COLOR2_VIEW:
case R_02808C_CB_COLOR3_VIEW:
case R_028090_CB_COLOR4_VIEW:
case R_028094_CB_COLOR5_VIEW:
case R_028098_CB_COLOR6_VIEW:
case R_02809C_CB_COLOR7_VIEW:
tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
break;
case R_028060_CB_COLOR0_SIZE: case R_028060_CB_COLOR0_SIZE:
case R_028064_CB_COLOR1_SIZE: case R_028064_CB_COLOR1_SIZE:
case R_028068_CB_COLOR2_SIZE: case R_028068_CB_COLOR2_SIZE:
...@@ -1259,7 +1286,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) ...@@ -1259,7 +1286,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
return 0; return 0;
} }
static unsigned mip_minify(unsigned size, unsigned level) unsigned r600_mip_minify(unsigned size, unsigned level)
{ {
unsigned val; unsigned val;
...@@ -1281,22 +1308,22 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel, ...@@ -1281,22 +1308,22 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
unsigned nlevels = llevel - blevel + 1; unsigned nlevels = llevel - blevel + 1;
*l0_size = -1; *l0_size = -1;
blocksize = fmt_get_blocksize(format); blocksize = r600_fmt_get_blocksize(format);
w0 = mip_minify(w0, 0); w0 = r600_mip_minify(w0, 0);
h0 = mip_minify(h0, 0); h0 = r600_mip_minify(h0, 0);
d0 = mip_minify(d0, 0); d0 = r600_mip_minify(d0, 0);
for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) { for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
width = mip_minify(w0, i); width = r600_mip_minify(w0, i);
nbx = fmt_get_nblocksx(format, width); nbx = r600_fmt_get_nblocksx(format, width);
nbx = round_up(nbx, block_align); nbx = round_up(nbx, block_align);
height = mip_minify(h0, i); height = r600_mip_minify(h0, i);
nby = fmt_get_nblocksy(format, height); nby = r600_fmt_get_nblocksy(format, height);
nby = round_up(nby, height_align); nby = round_up(nby, height_align);
depth = mip_minify(d0, i); depth = r600_mip_minify(d0, i);
size = nbx * nby * blocksize; size = nbx * nby * blocksize;
if (nfaces) if (nfaces)
...@@ -1387,7 +1414,7 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, ...@@ -1387,7 +1414,7 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
return -EINVAL; return -EINVAL;
} }
format = G_038004_DATA_FORMAT(word1); format = G_038004_DATA_FORMAT(word1);
if (!fmt_is_valid_texture(format, p->family)) { if (!r600_fmt_is_valid_texture(format, p->family)) {
dev_warn(p->dev, "%s:%d texture invalid format %d\n", dev_warn(p->dev, "%s:%d texture invalid format %d\n",
__func__, __LINE__, format); __func__, __LINE__, format);
return -EINVAL; return -EINVAL;
...@@ -1400,7 +1427,7 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, ...@@ -1400,7 +1427,7 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
array_check.nbanks = track->nbanks; array_check.nbanks = track->nbanks;
array_check.npipes = track->npipes; array_check.npipes = track->npipes;
array_check.nsamples = 1; array_check.nsamples = 1;
array_check.blocksize = fmt_get_blocksize(format); array_check.blocksize = r600_fmt_get_blocksize(format);
if (r600_get_array_mode_alignment(&array_check, if (r600_get_array_mode_alignment(&array_check,
&pitch_align, &height_align, &depth_align, &base_align)) { &pitch_align, &height_align, &depth_align, &base_align)) {
dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n", dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
...@@ -1433,6 +1460,10 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, ...@@ -1433,6 +1460,10 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
word1 = radeon_get_ib_value(p, idx + 5); word1 = radeon_get_ib_value(p, idx + 5);
blevel = G_038010_BASE_LEVEL(word0); blevel = G_038010_BASE_LEVEL(word0);
llevel = G_038014_LAST_LEVEL(word1); llevel = G_038014_LAST_LEVEL(word1);
if (blevel > llevel) {
dev_warn(p->dev, "texture blevel %d > llevel %d\n",
blevel, llevel);
}
if (array == 1) { if (array == 1) {
barray = G_038014_BASE_ARRAY(word1); barray = G_038014_BASE_ARRAY(word1);
larray = G_038014_LAST_ARRAY(word1); larray = G_038014_LAST_ARRAY(word1);
...@@ -1444,8 +1475,10 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, ...@@ -1444,8 +1475,10 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
&l0_size, &mipmap_size); &l0_size, &mipmap_size);
/* using get ib will give us the offset into the texture bo */ /* using get ib will give us the offset into the texture bo */
if ((l0_size + word2) > radeon_bo_size(texture)) { if ((l0_size + word2) > radeon_bo_size(texture)) {
dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n", dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n",
w0, h0, format, word2, l0_size, radeon_bo_size(texture)); w0, h0, pitch_align, height_align,
array_check.array_mode, format, word2,
l0_size, radeon_bo_size(texture));
dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align); dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align);
return -EINVAL; return -EINVAL;
} }
......
...@@ -78,6 +78,20 @@ ...@@ -78,6 +78,20 @@
#define CB_COLOR0_SIZE 0x28060 #define CB_COLOR0_SIZE 0x28060
#define CB_COLOR0_VIEW 0x28080 #define CB_COLOR0_VIEW 0x28080
#define R_028080_CB_COLOR0_VIEW 0x028080
#define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0)
#define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF)
#define C_028080_SLICE_START 0xFFFFF800
#define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13)
#define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF)
#define C_028080_SLICE_MAX 0xFF001FFF
#define R_028084_CB_COLOR1_VIEW 0x028084
#define R_028088_CB_COLOR2_VIEW 0x028088
#define R_02808C_CB_COLOR3_VIEW 0x02808C
#define R_028090_CB_COLOR4_VIEW 0x028090
#define R_028094_CB_COLOR5_VIEW 0x028094
#define R_028098_CB_COLOR6_VIEW 0x028098
#define R_02809C_CB_COLOR7_VIEW 0x02809C
#define CB_COLOR0_INFO 0x280a0 #define CB_COLOR0_INFO 0x280a0
# define CB_FORMAT(x) ((x) << 2) # define CB_FORMAT(x) ((x) << 2)
# define CB_ARRAY_MODE(x) ((x) << 8) # define CB_ARRAY_MODE(x) ((x) << 8)
......
...@@ -242,6 +242,9 @@ extern int rv6xx_get_temp(struct radeon_device *rdev); ...@@ -242,6 +242,9 @@ extern int rv6xx_get_temp(struct radeon_device *rdev);
extern int rv770_get_temp(struct radeon_device *rdev); extern int rv770_get_temp(struct radeon_device *rdev);
extern int evergreen_get_temp(struct radeon_device *rdev); extern int evergreen_get_temp(struct radeon_device *rdev);
extern int sumo_get_temp(struct radeon_device *rdev); extern int sumo_get_temp(struct radeon_device *rdev);
extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
unsigned *bankh, unsigned *mtaspect,
unsigned *tile_split);
/* /*
* Fences. * Fences.
...@@ -1749,6 +1752,16 @@ int radeon_vm_bo_rmv(struct radeon_device *rdev, ...@@ -1749,6 +1752,16 @@ int radeon_vm_bo_rmv(struct radeon_device *rdev,
int r600_vram_scratch_init(struct radeon_device *rdev); int r600_vram_scratch_init(struct radeon_device *rdev);
void r600_vram_scratch_fini(struct radeon_device *rdev); void r600_vram_scratch_fini(struct radeon_device *rdev);
/*
* r600 cs checking helper
*/
unsigned r600_mip_minify(unsigned size, unsigned level);
bool r600_fmt_is_valid_color(u32 format);
bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family);
int r600_fmt_get_blocksize(u32 format);
int r600_fmt_get_nblocksx(u32 format, u32 w);
int r600_fmt_get_nblocksy(u32 format, u32 h);
/* /*
* r600 functions used by radeon_encoder.c * r600 functions used by radeon_encoder.c
*/ */
......
...@@ -55,9 +55,10 @@ ...@@ -55,9 +55,10 @@
* 2.11.0 - backend map, initial compute support for the CS checker * 2.11.0 - backend map, initial compute support for the CS checker
* 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
* 2.13.0 - virtual memory support, streamout * 2.13.0 - virtual memory support, streamout
* 2.14.0 - add evergreen tiling informations
*/ */
#define KMS_DRIVER_MAJOR 2 #define KMS_DRIVER_MAJOR 2
#define KMS_DRIVER_MINOR 13 #define KMS_DRIVER_MINOR 14
#define KMS_DRIVER_PATCHLEVEL 0 #define KMS_DRIVER_PATCHLEVEL 0
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
int radeon_driver_unload_kms(struct drm_device *dev); int radeon_driver_unload_kms(struct drm_device *dev);
......
...@@ -445,8 +445,54 @@ static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) ...@@ -445,8 +445,54 @@ static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
int radeon_bo_set_tiling_flags(struct radeon_bo *bo, int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
uint32_t tiling_flags, uint32_t pitch) uint32_t tiling_flags, uint32_t pitch)
{ {
struct radeon_device *rdev = bo->rdev;
int r; int r;
if (rdev->family >= CHIP_CEDAR) {
unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
switch (bankw) {
case 0:
case 1:
case 2:
case 4:
case 8:
break;
default:
return -EINVAL;
}
switch (bankh) {
case 0:
case 1:
case 2:
case 4:
case 8:
break;
default:
return -EINVAL;
}
switch (mtaspect) {
case 0:
case 1:
case 2:
case 4:
case 8:
break;
default:
return -EINVAL;
}
if (tilesplit > 6) {
return -EINVAL;
}
if (stilesplit > 6) {
return -EINVAL;
}
}
r = radeon_bo_reserve(bo, false); r = radeon_bo_reserve(bo, false);
if (unlikely(r != 0)) if (unlikely(r != 0))
return r; return r;
......
...@@ -80,7 +80,6 @@ cayman 0x9400 ...@@ -80,7 +80,6 @@ cayman 0x9400
0x0002802C DB_DEPTH_CLEAR 0x0002802C DB_DEPTH_CLEAR
0x00028030 PA_SC_SCREEN_SCISSOR_TL 0x00028030 PA_SC_SCREEN_SCISSOR_TL
0x00028034 PA_SC_SCREEN_SCISSOR_BR 0x00028034 PA_SC_SCREEN_SCISSOR_BR
0x0002805C DB_DEPTH_SLICE
0x00028140 SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x00028140 SQ_ALU_CONST_BUFFER_SIZE_PS_0
0x00028144 SQ_ALU_CONST_BUFFER_SIZE_PS_1 0x00028144 SQ_ALU_CONST_BUFFER_SIZE_PS_1
0x00028148 SQ_ALU_CONST_BUFFER_SIZE_PS_2 0x00028148 SQ_ALU_CONST_BUFFER_SIZE_PS_2
......
...@@ -96,7 +96,6 @@ evergreen 0x9400 ...@@ -96,7 +96,6 @@ evergreen 0x9400
0x0002802C DB_DEPTH_CLEAR 0x0002802C DB_DEPTH_CLEAR
0x00028030 PA_SC_SCREEN_SCISSOR_TL 0x00028030 PA_SC_SCREEN_SCISSOR_TL
0x00028034 PA_SC_SCREEN_SCISSOR_BR 0x00028034 PA_SC_SCREEN_SCISSOR_BR
0x0002805C DB_DEPTH_SLICE
0x00028140 SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x00028140 SQ_ALU_CONST_BUFFER_SIZE_PS_0
0x00028144 SQ_ALU_CONST_BUFFER_SIZE_PS_1 0x00028144 SQ_ALU_CONST_BUFFER_SIZE_PS_1
0x00028148 SQ_ALU_CONST_BUFFER_SIZE_PS_2 0x00028148 SQ_ALU_CONST_BUFFER_SIZE_PS_2
......
...@@ -754,14 +754,6 @@ r600 0x9400 ...@@ -754,14 +754,6 @@ r600 0x9400
0x00028114 CB_COLOR5_MASK 0x00028114 CB_COLOR5_MASK
0x00028118 CB_COLOR6_MASK 0x00028118 CB_COLOR6_MASK
0x0002811C CB_COLOR7_MASK 0x0002811C CB_COLOR7_MASK
0x00028080 CB_COLOR0_VIEW
0x00028084 CB_COLOR1_VIEW
0x00028088 CB_COLOR2_VIEW
0x0002808C CB_COLOR3_VIEW
0x00028090 CB_COLOR4_VIEW
0x00028094 CB_COLOR5_VIEW
0x00028098 CB_COLOR6_VIEW
0x0002809C CB_COLOR7_VIEW
0x00028808 CB_COLOR_CONTROL 0x00028808 CB_COLOR_CONTROL
0x0002842C CB_FOG_BLUE 0x0002842C CB_FOG_BLUE
0x00028428 CB_FOG_GREEN 0x00028428 CB_FOG_GREEN
......
...@@ -808,9 +808,19 @@ struct drm_radeon_gem_create { ...@@ -808,9 +808,19 @@ struct drm_radeon_gem_create {
#define RADEON_TILING_MICRO 0x2 #define RADEON_TILING_MICRO 0x2
#define RADEON_TILING_SWAP_16BIT 0x4 #define RADEON_TILING_SWAP_16BIT 0x4
#define RADEON_TILING_SWAP_32BIT 0x8 #define RADEON_TILING_SWAP_32BIT 0x8
#define RADEON_TILING_SURFACE 0x10 /* this object requires a surface /* this object requires a surface when mapped - i.e. front buffer */
* when mapped - i.e. front buffer */ #define RADEON_TILING_SURFACE 0x10
#define RADEON_TILING_MICRO_SQUARE 0x20 #define RADEON_TILING_MICRO_SQUARE 0x20
#define RADEON_TILING_EG_BANKW_SHIFT 8
#define RADEON_TILING_EG_BANKW_MASK 0xf
#define RADEON_TILING_EG_BANKH_SHIFT 12
#define RADEON_TILING_EG_BANKH_MASK 0xf
#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16
#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf
#define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24
#define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf
#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28
#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
struct drm_radeon_gem_set_tiling { struct drm_radeon_gem_set_tiling {
uint32_t handle; uint32_t handle;
......
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