Commit 2858f876 authored by Mark Brown's avatar Mark Brown

Add master clock handling for nau8824

Merge series from Maxim Kochetkov <fido_max@inbox.ru>:

nau8824 has external MCLK pin. So add enable/disable external clock
management.
parents 83d43ab0 1d3724c9
...@@ -23,6 +23,14 @@ properties: ...@@ -23,6 +23,14 @@ properties:
'#sound-dai-cells': '#sound-dai-cells':
const: 0 const: 0
clocks:
items:
- description: The phandle of the master clock to the CODEC
clock-names:
items:
- const: mclk
interrupts: interrupts:
maxItems: 1 maxItems: 1
......
...@@ -506,6 +506,7 @@ static int system_clock_control(struct snd_soc_dapm_widget *w, ...@@ -506,6 +506,7 @@ static int system_clock_control(struct snd_soc_dapm_widget *w,
struct regmap *regmap = nau8824->regmap; struct regmap *regmap = nau8824->regmap;
unsigned int value; unsigned int value;
bool clk_fll, error; bool clk_fll, error;
int ret;
if (SND_SOC_DAPM_EVENT_OFF(event)) { if (SND_SOC_DAPM_EVENT_OFF(event)) {
dev_dbg(nau8824->dev, "system clock control : POWER OFF\n"); dev_dbg(nau8824->dev, "system clock control : POWER OFF\n");
...@@ -520,8 +521,15 @@ static int system_clock_control(struct snd_soc_dapm_widget *w, ...@@ -520,8 +521,15 @@ static int system_clock_control(struct snd_soc_dapm_widget *w,
} else { } else {
nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0); nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
} }
clk_disable_unprepare(nau8824->mclk);
} else { } else {
dev_dbg(nau8824->dev, "system clock control : POWER ON\n"); dev_dbg(nau8824->dev, "system clock control : POWER ON\n");
ret = clk_prepare_enable(nau8824->mclk);
if (ret)
return ret;
/* Check the clock source setting is proper or not /* Check the clock source setting is proper or not
* no matter the source is from FLL or MCLK. * no matter the source is from FLL or MCLK.
*/ */
...@@ -563,16 +571,21 @@ static int dmic_clock_control(struct snd_soc_dapm_widget *w, ...@@ -563,16 +571,21 @@ static int dmic_clock_control(struct snd_soc_dapm_widget *w,
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component); struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
int src; int src;
unsigned int freq;
freq = clk_get_rate(nau8824->mclk);
if (!freq)
freq = nau8824->fs * 256;
/* The DMIC clock is gotten from system clock (256fs) divided by /* The DMIC clock is gotten from system clock (256fs) divided by
* DMIC_SRC (1, 2, 4, 8, 16, 32). The clock has to be equal or * DMIC_SRC (1, 2, 4, 8, 16, 32). The clock has to be equal or
* less than 3.072 MHz. * less than 3.072 MHz.
*/ */
for (src = 0; src < 5; src++) { for (src = 0; src < 5; src++) {
if ((0x1 << (8 - src)) * nau8824->fs <= DMIC_CLK) if (freq / (0x1 << src) <= DMIC_CLK)
break; break;
} }
dev_dbg(nau8824->dev, "dmic src %d for mclk %d\n", src, nau8824->fs * 256); dev_dbg(nau8824->dev, "dmic src %d for mclk %d\n", src, freq);
regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER, regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
NAU8824_CLK_DMIC_SRC_MASK, (src << NAU8824_CLK_DMIC_SRC_SFT)); NAU8824_CLK_DMIC_SRC_MASK, (src << NAU8824_CLK_DMIC_SRC_SFT));
...@@ -1871,6 +1884,10 @@ static int nau8824_read_device_properties(struct device *dev, ...@@ -1871,6 +1884,10 @@ static int nau8824_read_device_properties(struct device *dev,
if (ret) if (ret)
nau8824->jack_eject_debounce = 1; nau8824->jack_eject_debounce = 1;
nau8824->mclk = devm_clk_get_optional(dev, "mclk");
if (IS_ERR(nau8824->mclk))
return PTR_ERR(nau8824->mclk);
return 0; return 0;
} }
......
...@@ -434,6 +434,7 @@ struct nau8824 { ...@@ -434,6 +434,7 @@ struct nau8824 {
struct snd_soc_jack *jack; struct snd_soc_jack *jack;
struct work_struct jdet_work; struct work_struct jdet_work;
struct semaphore jd_sem; struct semaphore jd_sem;
struct clk *mclk;
int fs; int fs;
int irq; int irq;
int resume_lock; int resume_lock;
......
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