Commit 29ee463d authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'for-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux

Pull hardware timestamp engine updates from Dipen Patel:
 "The changes for the hte subsystem include:

   - Add Tegra234 HTE provider and relevant DT bindings

   - Update MAINTAINERS file for the HTE subsystem"

* tag 'for-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux:
  hte: tegra-194: Use proper includes
  hte: Use device_match_of_node()
  hte: tegra-194: Fix off by one in tegra_hte_map_to_line_id()
  hte: tegra: fix 'struct of_device_id' build error
  hte: Use of_property_present() for testing DT property presence
  gpio: tegra186: Add Tegra234 hte support
  hte: handle nvidia,gpio-controller property
  hte: Deprecate nvidia,slices property
  hte: Add Tegra234 provider
  hte: Re-phrase tegra API document
  arm64: tegra: Add Tegra234 GTE nodes
  dt-bindings: timestamp: Deprecate nvidia,slices property
  dt-bindings: timestamp: Add Tegra234 support
  MAINTAINERS: Add HTE/timestamp subsystem details
parents 348551dd ca3d1a4b
......@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Tegra194 on chip generic hardware timestamping engine (HTE)
title: Tegra on chip generic hardware timestamping engine (HTE) provider
maintainers:
- Dipen Patel <dipenp@nvidia.com>
......@@ -23,6 +23,8 @@ properties:
enum:
- nvidia,tegra194-gte-aon
- nvidia,tegra194-gte-lic
- nvidia,tegra234-gte-aon
- nvidia,tegra234-gte-lic
reg:
maxItems: 1
......@@ -40,12 +42,20 @@ properties:
nvidia,slices:
$ref: /schemas/types.yaml#/definitions/uint32
deprecated: true
description:
HTE lines are arranged in 32 bit slice where each bit represents different
line/signal that it can enable/configure for the timestamp. It is u32
property and depends on the HTE instance in the chip. The value 3 is for
GPIO GTE and 11 for IRQ GTE.
enum: [3, 11]
property and the value depends on the HTE instance in the chip. The AON
GTE instances for both Tegra194 and Tegra234 has 3 slices. The Tegra194
LIC instance has 11 slices and Tegra234 LIC has 17 slices.
enum: [3, 11, 17]
nvidia,gpio-controller:
$ref: /schemas/types.yaml#/definitions/phandle
description:
The phandle to AON gpio controller instance. This is required to handle
namespace conversion between GPIO and GTE.
'#timestamp-cells':
description:
......@@ -59,9 +69,53 @@ required:
- compatible
- reg
- interrupts
- nvidia,slices
- "#timestamp-cells"
allOf:
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra194-gte-aon
- nvidia,tegra234-gte-aon
then:
properties:
nvidia,slices:
const: 3
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra194-gte-lic
then:
properties:
nvidia,slices:
const: 11
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra234-gte-lic
then:
properties:
nvidia,slices:
const: 17
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra234-gte-aon
then:
required:
- nvidia,gpio-controller
additionalProperties: false
examples:
......@@ -71,7 +125,6 @@ examples:
reg = <0xc1e0000 0x10000>;
interrupts = <0 13 0x4>;
nvidia,int-threshold = <1>;
nvidia,slices = <3>;
#timestamp-cells = <1>;
};
......@@ -81,7 +134,6 @@ examples:
reg = <0x3aa0000 0x10000>;
interrupts = <0 11 0x4>;
nvidia,int-threshold = <1>;
nvidia,slices = <11>;
#timestamp-cells = <1>;
};
......
......@@ -18,5 +18,5 @@ HTE Tegra Provider
.. toctree::
:maxdepth: 1
tegra194-hte
tegra-hte
......@@ -5,25 +5,25 @@ HTE Kernel provider driver
Description
-----------
The Nvidia tegra194 HTE provider driver implements two GTE
(Generic Timestamping Engine) instances: 1) GPIO GTE and 2) LIC
(Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the
timestamp from the system counter TSC which has 31.25MHz clock rate, and the
driver converts clock tick rate to nanoseconds before storing it as timestamp
value.
The Nvidia tegra HTE provider also known as GTE (Generic Timestamping Engine)
driver implements two GTE instances: 1) GPIO GTE and 2) LIC
(Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the timestamp
from the system counter TSC which has 31.25MHz clock rate, and the driver
converts clock tick rate to nanoseconds before storing it as timestamp value.
GPIO GTE
--------
This GTE instance timestamps GPIO in real time. For that to happen GPIO
needs to be configured as input. The always on (AON) GPIO controller instance
supports timestamping GPIOs in real time and it has 39 GPIO lines. The GPIO GTE
and AON GPIO controller are tightly coupled as it requires very specific bits
to be set in GPIO config register before GPIO GTE can be used, for that GPIOLIB
adds two optional APIs as below. The GPIO GTE code supports both kernel
and userspace consumers. The kernel space consumers can directly talk to HTE
subsystem while userspace consumers timestamp requests go through GPIOLIB CDEV
framework to HTE subsystem.
needs to be configured as input. Only the always on (AON) GPIO controller
instance supports timestamping GPIOs in real time as it is tightly coupled with
the GPIO GTE. To support this, GPIOLIB adds two optional APIs as mentioned
below. The GPIO GTE code supports both kernel and userspace consumers. The
kernel space consumers can directly talk to HTE subsystem while userspace
consumers timestamp requests go through GPIOLIB CDEV framework to HTE
subsystem. The hte devicetree binding described at
``Documentation/devicetree/bindings/timestamp`` provides an example of how a
consumer can request an GPIO line.
See gpiod_enable_hw_timestamp_ns() and gpiod_disable_hw_timestamp_ns().
......@@ -34,9 +34,8 @@ returns the timestamp in nanoseconds.
LIC (Legacy Interrupt Controller) IRQ GTE
-----------------------------------------
This GTE instance timestamps LIC IRQ lines in real time. There are 352 IRQ
lines which this instance can add timestamps to in real time. The hte
devicetree binding described at ``Documentation/devicetree/bindings/timestamp``
This GTE instance timestamps LIC IRQ lines in real time. The hte devicetree
binding described at ``Documentation/devicetree/bindings/timestamp``
provides an example of how a consumer can request an IRQ line. Since it is a
one-to-one mapping with IRQ GTE provider, consumers can simply specify the IRQ
number that they are interested in. There is no userspace consumer support for
......
......@@ -9489,6 +9489,9 @@ F: drivers/input/touchscreen/htcpen.c
HTE SUBSYSTEM
M: Dipen Patel <dipenp@nvidia.com>
L: timestamp@lists.linux.dev
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux.git
Q: https://patchwork.kernel.org/project/timestamp/list/
S: Maintained
F: Documentation/devicetree/bindings/timestamp/
F: Documentation/driver-api/hte/
......
......@@ -1154,6 +1154,14 @@ fuse@3810000 {
clock-names = "fuse";
};
hte_lic: hardware-timestamp@3aa0000 {
compatible = "nvidia,tegra234-gte-lic";
reg = <0x0 0x3aa0000 0x0 0x10000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
nvidia,int-threshold = <1>;
#timestamp-cells = <1>;
};
hsp_top0: hsp@3c00000 {
compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
reg = <0x0 0x03c00000 0x0 0xa0000>;
......@@ -1671,6 +1679,15 @@ hsp_aon: hsp@c150000 {
#mbox-cells = <2>;
};
hte_aon: hardware-timestamp@c1e0000 {
compatible = "nvidia,tegra234-gte-aon";
reg = <0x0 0xc1e0000 0x0 0x10000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
nvidia,int-threshold = <1>;
nvidia,gpio-controller = <&gpio_aon>;
#timestamp-cells = <1>;
};
gen2_i2c: i2c@c240000 {
compatible = "nvidia,tegra194-i2c";
reg = <0x0 0xc240000 0x0 0x100>;
......
......@@ -1134,6 +1134,7 @@ static const struct tegra_gpio_soc tegra234_aon_soc = {
.name = "tegra234-gpio-aon",
.instance = 1,
.num_irqs_per_bank = 8,
.has_gte = true,
};
#define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
......
......@@ -16,7 +16,7 @@
#include <linux/workqueue.h>
/*
* This sample HTE GPIO test driver demonstrates HTE API usage by enabling
* This sample HTE test driver demonstrates HTE API usage by enabling
* hardware timestamp on gpio_in and specified LIC IRQ lines.
*
* Note: gpio_out and gpio_in need to be shorted externally in order for this
......
......@@ -62,6 +62,10 @@
#define NV_AON_HTE_SLICE2_IRQ_GPIO_25 25
#define NV_AON_HTE_SLICE2_IRQ_GPIO_26 26
#define NV_AON_HTE_SLICE2_IRQ_GPIO_27 27
#define NV_AON_HTE_SLICE2_IRQ_GPIO_28 28
#define NV_AON_HTE_SLICE2_IRQ_GPIO_29 29
#define NV_AON_HTE_SLICE2_IRQ_GPIO_30 30
#define NV_AON_HTE_SLICE2_IRQ_GPIO_31 31
#define HTE_TECTRL 0x0
#define HTE_TETSCH 0x4
......@@ -114,6 +118,7 @@ struct tegra_hte_line_data {
struct tegra_hte_data {
enum tegra_hte_type type;
u32 slices;
u32 map_sz;
u32 sec_map_sz;
const struct tegra_hte_line_mapped *map;
......@@ -220,18 +225,129 @@ static const struct tegra_hte_line_mapped tegra194_aon_gpio_sec_map[] = {
[39] = {NV_AON_SLICE_INVALID, 0},
};
static const struct tegra_hte_data aon_hte = {
static const struct tegra_hte_line_mapped tegra234_aon_gpio_map[] = {
/* gpio, slice, bit_index */
/* AA port */
[0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
[1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
[2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
[3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
[4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
[5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
[6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
[7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
/* BB port */
[8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
[9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
[10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
[11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
/* CC port */
[12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
[13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
[14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
[15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
[16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
[17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
[18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
[19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
/* DD port */
[20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
[21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
[22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
/* EE port */
[23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31},
[24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30},
[25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29},
[26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28},
[27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
[28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
[29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
[30] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
/* GG port */
[31] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
};
static const struct tegra_hte_line_mapped tegra234_aon_gpio_sec_map[] = {
/* gpio, slice, bit_index */
/* AA port */
[0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
[1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
[2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
[3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
[4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
[5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
[6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
[7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
/* BB port */
[8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
[9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
[10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
[11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
[12] = {NV_AON_SLICE_INVALID, 0},
[13] = {NV_AON_SLICE_INVALID, 0},
[14] = {NV_AON_SLICE_INVALID, 0},
[15] = {NV_AON_SLICE_INVALID, 0},
/* CC port */
[16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
[17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
[18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
[19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
[20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
[21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
[22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
[23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
/* DD port */
[24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
[25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
[26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
[27] = {NV_AON_SLICE_INVALID, 0},
[28] = {NV_AON_SLICE_INVALID, 0},
[29] = {NV_AON_SLICE_INVALID, 0},
[30] = {NV_AON_SLICE_INVALID, 0},
[31] = {NV_AON_SLICE_INVALID, 0},
/* EE port */
[32] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31},
[33] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30},
[34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29},
[35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28},
[36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
[37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
[38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
[39] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
/* GG port */
[40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
};
static const struct tegra_hte_data t194_aon_hte = {
.map_sz = ARRAY_SIZE(tegra194_aon_gpio_map),
.map = tegra194_aon_gpio_map,
.sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map),
.sec_map = tegra194_aon_gpio_sec_map,
.type = HTE_TEGRA_TYPE_GPIO,
.slices = 3,
};
static const struct tegra_hte_data t234_aon_hte = {
.map_sz = ARRAY_SIZE(tegra234_aon_gpio_map),
.map = tegra234_aon_gpio_map,
.sec_map_sz = ARRAY_SIZE(tegra234_aon_gpio_sec_map),
.sec_map = tegra234_aon_gpio_sec_map,
.type = HTE_TEGRA_TYPE_GPIO,
.slices = 3,
};
static const struct tegra_hte_data t194_lic_hte = {
.map_sz = 0,
.map = NULL,
.type = HTE_TEGRA_TYPE_LIC,
.slices = 11,
};
static const struct tegra_hte_data lic_hte = {
static const struct tegra_hte_data t234_lic_hte = {
.map_sz = 0,
.map = NULL,
.type = HTE_TEGRA_TYPE_LIC,
.slices = 17,
};
static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg)
......@@ -251,7 +367,7 @@ static int tegra_hte_map_to_line_id(u32 eid,
{
if (m) {
if (eid > map_sz)
if (eid >= map_sz)
return -EINVAL;
if (m[eid].slice == NV_AON_SLICE_INVALID)
return -EINVAL;
......@@ -534,8 +650,10 @@ static bool tegra_hte_match_from_linedata(const struct hte_chip *chip,
}
static const struct of_device_id tegra_hte_of_match[] = {
{ .compatible = "nvidia,tegra194-gte-lic", .data = &lic_hte},
{ .compatible = "nvidia,tegra194-gte-aon", .data = &aon_hte},
{ .compatible = "nvidia,tegra194-gte-lic", .data = &t194_lic_hte},
{ .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte},
{ .compatible = "nvidia,tegra234-gte-lic", .data = &t234_lic_hte},
{ .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte},
{ }
};
MODULE_DEVICE_TABLE(of, tegra_hte_of_match);
......@@ -561,6 +679,11 @@ static int tegra_get_gpiochip_from_name(struct gpio_chip *chip, void *data)
return !strcmp(chip->label, data);
}
static int tegra_gpiochip_match(struct gpio_chip *chip, void *data)
{
return chip->fwnode == of_node_to_fwnode(data);
}
static int tegra_hte_probe(struct platform_device *pdev)
{
int ret;
......@@ -569,16 +692,10 @@ static int tegra_hte_probe(struct platform_device *pdev)
struct device *dev;
struct tegra_hte_soc *hte_dev;
struct hte_chip *gc;
struct device_node *gpio_ctrl;
dev = &pdev->dev;
ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices);
if (ret != 0) {
dev_err(dev, "Could not read slices\n");
return -EINVAL;
}
nlines = slices << 5;
hte_dev = devm_kzalloc(dev, sizeof(*hte_dev), GFP_KERNEL);
if (!hte_dev)
return -ENOMEM;
......@@ -590,6 +707,13 @@ static int tegra_hte_probe(struct platform_device *pdev)
dev_set_drvdata(&pdev->dev, hte_dev);
hte_dev->prov_data = of_device_get_match_data(&pdev->dev);
ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices);
if (ret != 0)
slices = hte_dev->prov_data->slices;
dev_dbg(dev, "slices:%d\n", slices);
nlines = slices << 5;
hte_dev->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(hte_dev->regs))
return PTR_ERR(hte_dev->regs);
......@@ -635,8 +759,25 @@ static int tegra_hte_probe(struct platform_device *pdev)
gc->match_from_linedata = tegra_hte_match_from_linedata;
if (of_device_is_compatible(dev->of_node,
"nvidia,tegra194-gte-aon")) {
hte_dev->c = gpiochip_find("tegra194-gpio-aon",
tegra_get_gpiochip_from_name);
} else {
gpio_ctrl = of_parse_phandle(dev->of_node,
"nvidia,gpio-controller",
0);
if (!gpio_ctrl) {
dev_err(dev,
"gpio controller node not found\n");
return -ENODEV;
}
hte_dev->c = gpiochip_find(gpio_ctrl,
tegra_gpiochip_match);
of_node_put(gpio_ctrl);
}
if (!hte_dev->c)
return dev_err_probe(dev, -EPROBE_DEFER,
"wait for gpio controller\n");
......
......@@ -444,7 +444,7 @@ static struct hte_device *of_node_to_htedevice(struct device_node *np)
list_for_each_entry(gdev, &hte_devices, list)
if (gdev->chip && gdev->chip->dev &&
gdev->chip->dev->of_node == np) {
device_match_of_node(gdev->chip->dev, np)) {
spin_unlock(&hte_lock);
return gdev;
}
......
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