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Commit 2e04d1bd authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'qcom-arm64-for-5.6' of... 

Merge tag 'qcom-arm64-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Qualcomm ARM64 DT updates for v5.6

* Align SDM845 firmware paths with linux-firmware
* Make WiFi work on Dragonboard845c
* Wire up wakeup controller for SDM845
* Critical thermal interrupt support for SDM845, MSM8996 and MSM8998
* Enable UFS for SM8150
* Add remoteproc enablers and nodes for SM8150
* Add CPUfreq for SM8150
* Add RPMH power-domain node for SM8150
* Cleanup and refactor MSM8996 dts structure
* Add initial Inforce Computing IFC6640 dts
* Increase MSM8996 core voltage
* Fix MSM8996 USB phy settings
* Add missing alias for BLSP UART in MSM8998 MTP
* Add remoteproc nodes for ADSP, modem and sensor core for MSM8998
* Enable WiFI for MSM8998
* Introduce the SC7180 platform and the IDP development board
* Add CPUfreq, QUPs, USB, remoteproc etc for SC7180
* Enable USB OTG for Dragonboard 410c
* Add vibrator motor node for PM8916
* Properly specify APCS clocks for MSM8916
* Add CPR and HFPLL for QCS404
* Enable full CPUfreq (with AVS) for QCS404

* tag 'qcom-arm64-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (88 commits)
  arm64: dts: qcom: sdm845: move gpu zap nodes to per-device dts
  arm64: dts: qcom: sm8150: Hard code rpmhpd constants
  arm64: dts: apq8096-db820c: Fix VDD core voltage
  arm64: dts: qcom: qcs404-evb: Set vdd_apc regulator in high power mode
  arm64: dts: qcom: msm8998-mtp: Add alias for blsp1_uart3
  arm64: dts: qcom: sc7180: Add critical interrupt and cooling maps for TSENS in SC7180
  arm64: dts: qcom: msm8996: Fix venus iommu nodename error
  arm64: dts: qcom: sdm845: add the ufs reset
  arm64: dts: qcom: sm8150: Fix UFS phy register size
  arm64: dts: qcom: sm8150-mtp: Add UFS gpio reset
  arm64: dts: qcom: qcs404: Add CPR and populate OPP table
  arm64: dts: qcom: qcs404: Add DVFS support
  arm64: dts: qcom: qcs404: Add the clocks for APCS mux/divider
  arm64: dts: qcom: qcs404: Add HFPLL node
  arm64: dts: qcom: msm8916: Add the clocks for the APCS mux/divider
  arm64: dts: qcom: sc7180: Add rpmh power-domain node
  arm64: dts: pm8004: Add SPMI regulator and add phandles to lsids
  arm64: dts: msm8998: thermal: Add critical interrupt support
  arm64: dts: msm8996: thermal: Add critical interrupt support
  arm64: dts: qcom: db845c: Move remoteproc firmware to sdm845
  ...

Link: https://lore.kernel.org/r/20200113204225.GB3325@yogaSigned-off-by: default avatarOlof Johansson <olof@lixom.net>
parents e59760f7 f489b13d
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Documentation/devicetree/bindings/arm/qcom.yaml
View file @ 2e04d1bd
......@@ -24,28 +24,30 @@ description: |
The 'SoC' element must be one of the following strings:
apq8016
apq8074
apq8084
apq8096
msm8916
msm8974
msm8992
msm8994
msm8996
mdm9615
ipq8074
sdm845
apq8016
apq8074
apq8084
apq8096
ipq8074
mdm9615
msm8916
msm8974
msm8992
msm8994
msm8996
sc7180
sdm845
The 'board' element must be one of the following strings:
cdp
liquid
dragonboard
mtp
sbc
hk01
qrd
cdp
dragonboard
hk01
idp
liquid
mtp
qrd
sbc
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
where the minor number may be omitted when it's zero, i.e. v1.0 is the same
......@@ -144,4 +146,8 @@ properties:
- qcom,ipq8074-hk01
- const: qcom,ipq8074
- items:
- enum:
- qcom,sc7180-idp
- const: qcom,sc7180
...
arch/arm64/boot/dts/qcom/Makefile
View file @ 2e04d1bd
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb
......@@ -13,6 +14,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
......
arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
View file @ 2e04d1bd
......@@ -5,6 +5,15 @@
&pm8916_gpios {
usb_hub_reset_pm: usb_hub_reset_pm {
pinconf {
pins = "gpio3";
function = PMIC_GPIO_FUNC_NORMAL;
input-disable;
output-high;
};
};
usb_hub_reset_pm_device: usb_hub_reset_pm_device {
pinconf {
pins = "gpio3";
function = PMIC_GPIO_FUNC_NORMAL;
......@@ -22,6 +31,16 @@ pinconf {
};
};
usb_sw_sel_pm_device: usb_sw_sel_pm_device {
pinconf {
pins = "gpio4";
function = PMIC_GPIO_FUNC_NORMAL;
power-source = <PM8916_GPIO_VPH>;
input-disable;
output-low;
};
};
pm8916_gpios_leds: pm8916_gpios_leds {
pinconf {
pins = "gpio1", "gpio2";
......
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
View file @ 2e04d1bd
......@@ -358,14 +358,15 @@ sdhci@7864000 {
};
usb@78d9000 {
extcon = <&usb_id>;
extcon = <&usb_id>, <&usb_id>;
status = "okay";
adp-disable;
hnp-disable;
srp-disable;
dr_mode = "host";
pinctrl-names = "default";
pinctrl-0 = <&usb_sw_sel_pm>;
dr_mode = "otg";
pinctrl-names = "default", "device";
pinctrl-0 = <&usb_sw_sel_pm &usb_hub_reset_pm>;
pinctrl-1 = <&usb_sw_sel_pm_device &usb_hub_reset_pm_device>;
ulpi {
phy {
v1p8-supply = <&pm8916_l7>;
......@@ -504,7 +505,7 @@ usb2513 {
usb_id: usb-id {
compatible = "linux,extcon-usb-gpio";
vbus-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>;
id-gpio = <&msmgpio 121 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_id_default>;
};
......
arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi deleted 100644 → 0
View file @ e59760f7
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
*/
&msmgpio {
sdc2_cd_on: sdc2_cd_on {
mux {
pins = "gpio38";
function = "gpio";
};
config {
pins = "gpio38";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
};
sdc2_cd_off: sdc2_cd_off {
mux {
pins = "gpio38";
function = "gpio";
};
config {
pins = "gpio38";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
};
blsp1_uart1_default: blsp1_uart1_default {
mux {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "blsp_uart2";
};
config {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
drive-strength = <16>;
bias-disable;
};
};
blsp1_uart1_sleep: blsp1_uart1_sleep {
mux {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "gpio";
};
config {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
drive-strength = <2>;
bias-disable;
};
};
hdmi_hpd_active: hdmi_hpd_active {
mux {
pins = "gpio34";
function = "hdmi_hot";
};
config {
pins = "gpio34";
bias-pull-down;
drive-strength = <16>;
};
};
hdmi_hpd_suspend: hdmi_hpd_suspend {
mux {
pins = "gpio34";
function = "hdmi_hot";
};
config {
pins = "gpio34";
bias-pull-down;
drive-strength = <2>;
};
};
hdmi_ddc_active: hdmi_ddc_active {
mux {
pins = "gpio32", "gpio33";
function = "hdmi_ddc";
};
config {
pins = "gpio32", "gpio33";
drive-strength = <2>;
bias-pull-up;
};
};
hdmi_ddc_suspend: hdmi_ddc_suspend {
mux {
pins = "gpio32", "gpio33";
function = "hdmi_ddc";
};
config {
pins = "gpio32", "gpio33";
drive-strength = <2>;
bias-pull-down;
};
};
};
arch/arm64/boot/dts/qcom/apq8096-db820c-pmic-pins.dtsi deleted 100644 → 0
View file @ e59760f7
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
&pm8994_gpios {
pinctrl-names = "default";
pinctrl-0 = <&ls_exp_gpio_f &bt_en_gpios>;
ls_exp_gpio_f: pm8994_gpio5 {
pinconf {
pins = "gpio5";
output-low;
power-source = <2>; // PM8994_GPIO_S4, 1.8V
};
};
bt_en_gpios: bt_en_gpios {
pinconf {
pins = "gpio19";
function = PMIC_GPIO_FUNC_NORMAL;
output-low;
power-source = <PM8994_GPIO_S4>; // 1.8V
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
bias-pull-down;
};
};
wlan_en_gpios: wlan_en_gpios {
pinconf {
pins = "gpio8";
function = PMIC_GPIO_FUNC_NORMAL;
output-low;
power-source = <PM8994_GPIO_S4>; // 1.8V
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
bias-pull-down;
};
};
audio_mclk: clk_div1 {
pinconf {
pins = "gpio15";
function = "func1";
power-source = <PM8994_GPIO_S4>; // 1.8V
};
};
volume_up_gpio: pm8996_gpio2 {
pinconf {
pins = "gpio2";
function = "normal";
input-enable;
drive-push-pull;
bias-pull-up;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
power-source = <PM8994_GPIO_S4>; // 1.8V
};
};
divclk4_pin_a: divclk4 {
pinconf {
pins = "gpio18";
function = PMIC_GPIO_FUNC_FUNC2;
bias-disable;
power-source = <PM8994_GPIO_S4>;
};
};
usb3_vbus_det_gpio: pm8996_gpio22 {
pinconf {
pins = "gpio22";
function = PMIC_GPIO_FUNC_NORMAL;
input-enable;
bias-pull-down;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
power-source = <PM8994_GPIO_S4>; // 1.8V
};
};
};
&pmi8994_gpios {
usb2_vbus_det_gpio: pmi8996_gpio6 {
pinconf {
pins = "gpio6";
function = PMIC_GPIO_FUNC_NORMAL;
input-enable;
bias-pull-down;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
power-source = <PM8994_GPIO_S4>; // 1.8V
};
};
};
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
View file @ 2e04d1bd
......@@ -6,10 +6,9 @@
#include "msm8996.dtsi"
#include "pm8994.dtsi"
#include "pmi8994.dtsi"
#include "apq8096-db820c-pins.dtsi"
#include "apq8096-db820c-pmic-pins.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
......@@ -78,611 +77,837 @@ div1_mclk: divclk1 {
};
};
soc {
serial@7570000 {
label = "BT-UART";
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart1_default>;
pinctrl-1 = <&blsp1_uart1_sleep>;
bluetooth {
compatible = "qcom,qca6174-bt";
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
/* bt_disable_n gpio */
enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&volume_up_gpio>;
clocks = <&divclk4>;
};
button@0 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>;
};
};
serial@75b0000 {
label = "LS-UART1";
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_uart1_2pins_default>;
pinctrl-1 = <&blsp2_uart1_2pins_sleep>;
};
serial@75b1000 {
label = "LS-UART0";
status = "disabled";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_uart2_4pins_default>;
pinctrl-1 = <&blsp2_uart2_4pins_sleep>;
};
i2c@7577000 {
/* On Low speed expansion */
label = "LS-I2C0";
status = "okay";
};
i2c@75b6000 {
/* On Low speed expansion */
label = "LS-I2C1";
status = "okay";
};
spi@7575000 {
/* On Low speed expansion */
label = "LS-SPI0";
status = "okay";
};
i2c@75b5000 {
/* On High speed expansion */
label = "HS-I2C2";
status = "okay";
};
spi@75ba000{
/* On High speed expansion */
label = "HS-SPI1";
status = "okay";
};
sdhci@74a4900 {
/* External SD card */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
cd-gpios = <&msmgpio 38 0x1>;
vmmc-supply = <&pm8994_l21>;
vqmmc-supply = <&pm8994_l13>;
status = "okay";
};
phy@627000 {
status = "okay";
};
ufshc@624000 {
status = "okay";
};
pinctrl@1010000 {
gpio-line-names =
"[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */
"[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */
"[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC pin 12 */
"[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC pin 8 */
"[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC pin 11 */
"[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC pin 13 */
"[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC pin 21 */
"[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC pin 19 */
"GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 */
"TP93", /* GPIO_9 */
"GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 */
"[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */
"NC", /* GPIO_12 */
"[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC pin 15 */
"[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */
"[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC pin 17 */
"TP99", /* GPIO_16 */
"[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC pin 34 */
"[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC pin 32 */
"[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */
"[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */
"FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */
"FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */
"GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */
"GPIO-D", /* GPIO_24, LSEC pin 26 */
"GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */
"GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 32 */
"BLSP6_I2C_SDA", /* GPIO_27 */
"BLSP6_I2C_SCL", /* GPIO_28 */
"GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 */
"GPIO30", /* GPIO_30, S HSEC pin 4 */
"HDMI_CEC", /* GPIO_31 */
"HDMI_DDC_CLOCK", /* GPIO_32 */
"HDMI_DDC_DATA", /* GPIO_33 */
"HDMI_HOT_PLUG_DETECT", /* GPIO_34 */
"PCIE0_RST_N", /* GPIO_35 */
"PCIE0_CLKREQ_N", /* GPIO_36 */
"PCIE0_WAKE", /* GPIO_37 */
"SD_CARD_DET_N", /* GPIO_38 */
"TSIF1_SYNC", /* GPIO_39, S HSEC pin 48 */
"W_DISABLE_N", /* GPIO_40 */
"[BLSP9_UART_TX]", /* GPIO_41 */
"[BLSP9_UART_RX]", /* GPIO_42 */
"[BLSP2_UART_CTS_N]", /* GPIO_43 */
"[BLSP2_UART_RFR_N]", /* GPIO_44 */
"[BLSP3_UART_TX]", /* GPIO_45 */
"[BLSP3_UART_RX]", /* GPIO_46 */
"[I2C0_SDA]", /* GPIO_47, LS_I2C0_SDA, LSEC pin 17 */
"[I2C0_SCL]", /* GPIO_48, LS_I2C0_SCL, LSEC pin 15 */
"[UART0_TxD]", /* GPIO_49, BLSP9_UART_TX, LSEC pin 5 */
"[UART0_RxD]", /* GPIO_50, BLSP9_UART_RX, LSEC pin 7 */
"[UART0_CTS]", /* GPIO_51, BLSP9_UART_CTS_N, LSEC pin 3 */
"[UART0_RTS]", /* GPIO_52, BLSP9_UART_RFR_N, LSEC pin 9 */
"[CODEC_INT1_N]", /* GPIO_53 */
"[CODEC_INT2_N]", /* GPIO_54 */
"[BLSP7_I2C_SDA]", /* GPIO_55 */
"[BLSP7_I2C_SCL]", /* GPIO_56 */
"MI2S_MCLK", /* GPIO_57, S HSEC pin 3 */
"[PCM_CLK]", /* GPIO_58, QUA_MI2S_SCK, LSEC pin 18 */
"[PCM_FS]", /* GPIO_59, QUA_MI2S_WS, LSEC pin 16 */
"[PCM_DO]", /* GPIO_60, QUA_MI2S_DATA0, LSEC pin 20 */
"[PCM_DI]", /* GPIO_61, QUA_MI2S_DATA1, LSEC pin 22 */
"GPIO-E", /* GPIO_62, LSEC pin 27 */
"TP87", /* GPIO_63 */
"[CODEC_RST_N]", /* GPIO_64 */
"[PCM1_CLK]", /* GPIO_65 */
"[PCM1_SYNC]", /* GPIO_66 */
"[PCM1_DIN]", /* GPIO_67 */
"[PCM1_DOUT]", /* GPIO_68 */
"AUDIO_REF_CLK", /* GPIO_69 */
"SLIMBUS_CLK", /* GPIO_70 */
"SLIMBUS_DATA0", /* GPIO_71 */
"SLIMBUS_DATA1", /* GPIO_72 */
"NC", /* GPIO_73 */
"NC", /* GPIO_74 */
"NC", /* GPIO_75 */
"NC", /* GPIO_76 */
"TP94", /* GPIO_77 */
"NC", /* GPIO_78 */
"TP95", /* GPIO_79 */
"GPIO-A", /* GPIO_80, MEMS_RESET_N, LSEC pin 23 */
"TP88", /* GPIO_81 */
"TP89", /* GPIO_82 */
"TP90", /* GPIO_83 */
"TP91", /* GPIO_84 */
"[SD_DAT0]", /* GPIO_85, BLSP12_SPI_MOSI, P HSEC pin 1 */
"[SD_CMD]", /* GPIO_86, BLSP12_SPI_MISO, P HSEC pin 11 */
"[SD_DAT3]", /* GPIO_87, BLSP12_SPI_CS_N, P HSEC pin 7 */
"[SD_SCLK]", /* GPIO_88, BLSP12_SPI_CLK, P HSEC pin 9 */
"TSIF1_CLK", /* GPIO_89, S HSEC pin 42 */
"TSIF1_EN", /* GPIO_90, S HSEC pin 46 */
"TSIF1_DATA", /* GPIO_91, S HSEC pin 44 */
"NC", /* GPIO_92 */
"TSIF2_CLK", /* GPIO_93, S HSEC pin 52 */
"TSIF2_EN", /* GPIO_94, S HSEC pin 56 */
"TSIF2_DATA", /* GPIO_95, S HSEC pin 54 */
"TSIF2_SYNC", /* GPIO_96, S HSEC pin 58 */
"NC", /* GPIO_97 */
"CAM1_STANDBY_N", /* GPIO_98 */
"NC", /* GPIO_99 */
"NC", /* GPIO_100 */
"[LCD1_RESET_N]", /* GPIO_101, S HSEC pin 51 */
"BOOT_CONFIG1", /* GPIO_102 */
"USB_HUB_RESET", /* GPIO_103 */
"CAM1_RST_N", /* GPIO_104 */
"NC", /* GPIO_105 */
"NC", /* GPIO_106 */
"NC", /* GPIO_107 */
"NC", /* GPIO_108 */
"NC", /* GPIO_109 */
"NC", /* GPIO_110 */
"NC", /* GPIO_111 */
"NC", /* GPIO_112 */
"PMI8994_BUA", /* GPIO_113 */
"PCIE2_RST_N", /* GPIO_114 */
"PCIE2_CLKREQ_N", /* GPIO_115 */
"PCIE2_WAKE", /* GPIO_116 */
"SSC_IRQ_0", /* GPIO_117 */
"SSC_IRQ_1", /* GPIO_118 */
"SSC_IRQ_2", /* GPIO_119 */
"NC", /* GPIO_120 */
"GPIO121", /* GPIO_121, S HSEC pin 2 */
"NC", /* GPIO_122 */
"SSC_IRQ_6", /* GPIO_123 */
"SSC_IRQ_7", /* GPIO_124 */
"GPIO-C", /* GPIO_125, TS_INT0, LSEC pin 25 */
"BOOT_CONFIG5", /* GPIO_126 */
"NC", /* GPIO_127 */
"NC", /* GPIO_128 */
"BOOT_CONFIG7", /* GPIO_129 */
"PCIE1_RST_N", /* GPIO_130 */
"PCIE1_CLKREQ_N", /* GPIO_131 */
"PCIE1_WAKE", /* GPIO_132 */
"GPIO-L", /* GPIO_133, CAM2_STANDBY_N, LSEC pin 34 */
"NC", /* GPIO_134 */
"NC", /* GPIO_135 */
"BOOT_CONFIG8", /* GPIO_136 */
"NC", /* GPIO_137 */
"NC", /* GPIO_138 */
"GPS_SSBI2", /* GPIO_139 */
"GPS_SSBI1", /* GPIO_140 */
"NC", /* GPIO_141 */
"NC", /* GPIO_142 */
"NC", /* GPIO_143 */
"BOOT_CONFIG6", /* GPIO_144 */
"NC", /* GPIO_145 */
"NC", /* GPIO_146 */
"NC", /* GPIO_147 */
"NC", /* GPIO_148 */
"NC"; /* GPIO_149 */
};
qcom,spmi@400f000 {
pmic@0 {
gpios@c000 {
gpio-line-names =
"NC",
"KEY_VOLP_N",
"NC",
"BL1_PWM",
"GPIO-F", /* BL0_PWM, LSEC pin 28 */
"BL1_EN",
"NC",
"WLAN_EN",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"DIVCLK1",
"DIVCLK2",
"DIVCLK3",
"DIVCLK4",
"BT_EN",
"PMIC_SLB",
"PMIC_BUA",
"USB_VBUS_DET";
};
mpps@a000 {
gpio-line-names =
"VDDPX_BIAS",
"WIFI_LED",
"NC",
"BT_LED",
"PM_MPP05",
"PM_MPP06",
"PM_MPP07",
"NC";
};
};
usb2_id: usb2-id {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb2_vbus_det_gpio>;
};
pmic@2 {
gpios@c000 {
gpio-line-names =
"NC",
"SPKR_AMP_EN1",
"SPKR_AMP_EN2",
"TP61",
"NC",
"USB2_VBUS_DET",
"NC",
"NC",
"NC",
"NC";
};
};
};
usb3_id: usb3-id {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb3_vbus_det_gpio>;
};
phy@34000 {
status = "okay";
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
};
vreg_s8a_l3a_input: vreg-s8a-l3a-input {
compatible = "regulator-fixed";
regulator-name = "vreg_s8a_l3a_input";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <0>;
regulator-max-microvolt = <0>;
};
wlan_en: wlan-en-1-8v {
pinctrl-names = "default";
pinctrl-0 = <&wlan_en_gpios>;
compatible = "regulator-fixed";
regulator-name = "wlan-en-regulator";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&pm8994_gpios 8 0>;
/* WLAN card specific delay */
startup-delay-us = <70000>;
enable-active-high;
};
};
&blsp1_i2c2 {
/* On Low speed expansion */
label = "LS-I2C0";
status = "okay";
};
&blsp1_spi0 {
/* On Low speed expansion */
label = "LS-SPI0";
status = "okay";
};
&blsp1_uart1 {
label = "BT-UART";
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart1_default>;
pinctrl-1 = <&blsp1_uart1_sleep>;
bluetooth {
compatible = "qcom,qca6174-bt";
/* bt_disable_n gpio */
enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
clocks = <&divclk4>;
};
};
&blsp2_i2c0 {
/* On High speed expansion */
label = "HS-I2C2";
status = "okay";
};
&blsp2_i2c1 {
/* On Low speed expansion */
label = "LS-I2C1";
status = "okay";
};
&blsp2_spi5 {
/* On High speed expansion */
label = "HS-SPI1";
status = "okay";
};
&blsp2_uart1 {
label = "LS-UART1";
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_uart1_2pins_default>;
pinctrl-1 = <&blsp2_uart1_2pins_sleep>;
};
&blsp2_uart2 {
label = "LS-UART0";
status = "disabled";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_uart2_4pins_default>;
pinctrl-1 = <&blsp2_uart2_4pins_sleep>;
};
&camss {
vdda-supply = <&vreg_l2a_1p25>;
};
&hdmi {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
core-vdda-supply = <&vreg_l12a_1p8>;
core-vcc-supply = <&vreg_s4a_1p8>;
};
&hdmi_phy {
status = "okay";
vddio-supply = <&vreg_l12a_1p8>;
vcca-supply = <&vreg_l28a_0p925>;
#phy-cells = <0>;
};
&hsusb_phy1 {
status = "okay";
vdda-pll-supply = <&vreg_l12a_1p8>;
vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
};
&hsusb_phy2 {
status = "okay";
vdda-pll-supply = <&vreg_l12a_1p8>;
vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
};
&mdp {
status = "okay";
};
&mdss {
status = "okay";
};
phy@7410000 {
status = "okay";
&msmgpio {
gpio-line-names =
"[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */
"[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */
"[SPI0_CS]", /* GPIO_2, BLSP1_SPI_CS_N, LSEC pin 12 */
"[SPI0_SCLK]", /* GPIO_3, BLSP1_SPI_CLK, LSEC pin 8 */
"[UART1_TxD]", /* GPIO_4, BLSP8_UART_TX, LSEC pin 11 */
"[UART1_RxD]", /* GPIO_5, BLSP8_UART_RX, LSEC pin 13 */
"[I2C1_SDA]", /* GPIO_6, BLSP8_I2C_SDA, LSEC pin 21 */
"[I2C1_SCL]", /* GPIO_7, BLSP8_I2C_SCL, LSEC pin 19 */
"GPIO-H", /* GPIO_8, LCD0_RESET_N, LSEC pin 30 */
"TP93", /* GPIO_9 */
"GPIO-G", /* GPIO_10, MDP_VSYNC_P, LSEC pin 29 */
"[MDP_VSYNC_S]", /* GPIO_11, S HSEC pin 55 */
"NC", /* GPIO_12 */
"[CSI0_MCLK]", /* GPIO_13, CAM_MCLK0, P HSEC pin 15 */
"[CAM_MCLK1]", /* GPIO_14, J14 pin 11 */
"[CSI1_MCLK]", /* GPIO_15, CAM_MCLK2, P HSEC pin 17 */
"TP99", /* GPIO_16 */
"[I2C2_SDA]", /* GPIO_17, CCI_I2C_SDA0, P HSEC pin 34 */
"[I2C2_SCL]", /* GPIO_18, CCI_I2C_SCL0, P HSEC pin 32 */
"[CCI_I2C_SDA1]", /* GPIO_19, S HSEC pin 38 */
"[CCI_I2C_SCL1]", /* GPIO_20, S HSEC pin 36 */
"FLASH_STROBE_EN", /* GPIO_21, S HSEC pin 5 */
"FLASH_STROBE_TRIG", /* GPIO_22, S HSEC pin 1 */
"GPIO-K", /* GPIO_23, CAM2_RST_N, LSEC pin 33 */
"GPIO-D", /* GPIO_24, LSEC pin 26 */
"GPIO-I", /* GPIO_25, CAM0_RST_N, LSEC pin 31 */
"GPIO-J", /* GPIO_26, CAM0_STANDBY_N, LSEC pin 32 */
"BLSP6_I2C_SDA", /* GPIO_27 */
"BLSP6_I2C_SCL", /* GPIO_28 */
"GPIO-B", /* GPIO_29, TS0_RESET_N, LSEC pin 24 */
"GPIO30", /* GPIO_30, S HSEC pin 4 */
"HDMI_CEC", /* GPIO_31 */
"HDMI_DDC_CLOCK", /* GPIO_32 */
"HDMI_DDC_DATA", /* GPIO_33 */
"HDMI_HOT_PLUG_DETECT", /* GPIO_34 */
"PCIE0_RST_N", /* GPIO_35 */
"PCIE0_CLKREQ_N", /* GPIO_36 */
"PCIE0_WAKE", /* GPIO_37 */
"SD_CARD_DET_N", /* GPIO_38 */
"TSIF1_SYNC", /* GPIO_39, S HSEC pin 48 */
"W_DISABLE_N", /* GPIO_40 */
"[BLSP9_UART_TX]", /* GPIO_41 */
"[BLSP9_UART_RX]", /* GPIO_42 */
"[BLSP2_UART_CTS_N]", /* GPIO_43 */
"[BLSP2_UART_RFR_N]", /* GPIO_44 */
"[BLSP3_UART_TX]", /* GPIO_45 */
"[BLSP3_UART_RX]", /* GPIO_46 */
"[I2C0_SDA]", /* GPIO_47, LS_I2C0_SDA, LSEC pin 17 */
"[I2C0_SCL]", /* GPIO_48, LS_I2C0_SCL, LSEC pin 15 */
"[UART0_TxD]", /* GPIO_49, BLSP9_UART_TX, LSEC pin 5 */
"[UART0_RxD]", /* GPIO_50, BLSP9_UART_RX, LSEC pin 7 */
"[UART0_CTS]", /* GPIO_51, BLSP9_UART_CTS_N, LSEC pin 3 */
"[UART0_RTS]", /* GPIO_52, BLSP9_UART_RFR_N, LSEC pin 9 */
"[CODEC_INT1_N]", /* GPIO_53 */
"[CODEC_INT2_N]", /* GPIO_54 */
"[BLSP7_I2C_SDA]", /* GPIO_55 */
"[BLSP7_I2C_SCL]", /* GPIO_56 */
"MI2S_MCLK", /* GPIO_57, S HSEC pin 3 */
"[PCM_CLK]", /* GPIO_58, QUA_MI2S_SCK, LSEC pin 18 */
"[PCM_FS]", /* GPIO_59, QUA_MI2S_WS, LSEC pin 16 */
"[PCM_DO]", /* GPIO_60, QUA_MI2S_DATA0, LSEC pin 20 */
"[PCM_DI]", /* GPIO_61, QUA_MI2S_DATA1, LSEC pin 22 */
"GPIO-E", /* GPIO_62, LSEC pin 27 */
"TP87", /* GPIO_63 */
"[CODEC_RST_N]", /* GPIO_64 */
"[PCM1_CLK]", /* GPIO_65 */
"[PCM1_SYNC]", /* GPIO_66 */
"[PCM1_DIN]", /* GPIO_67 */
"[PCM1_DOUT]", /* GPIO_68 */
"AUDIO_REF_CLK", /* GPIO_69 */
"SLIMBUS_CLK", /* GPIO_70 */
"SLIMBUS_DATA0", /* GPIO_71 */
"SLIMBUS_DATA1", /* GPIO_72 */
"NC", /* GPIO_73 */
"NC", /* GPIO_74 */
"NC", /* GPIO_75 */
"NC", /* GPIO_76 */
"TP94", /* GPIO_77 */
"NC", /* GPIO_78 */
"TP95", /* GPIO_79 */
"GPIO-A", /* GPIO_80, MEMS_RESET_N, LSEC pin 23 */
"TP88", /* GPIO_81 */
"TP89", /* GPIO_82 */
"TP90", /* GPIO_83 */
"TP91", /* GPIO_84 */
"[SD_DAT0]", /* GPIO_85, BLSP12_SPI_MOSI, P HSEC pin 1 */
"[SD_CMD]", /* GPIO_86, BLSP12_SPI_MISO, P HSEC pin 11 */
"[SD_DAT3]", /* GPIO_87, BLSP12_SPI_CS_N, P HSEC pin 7 */
"[SD_SCLK]", /* GPIO_88, BLSP12_SPI_CLK, P HSEC pin 9 */
"TSIF1_CLK", /* GPIO_89, S HSEC pin 42 */
"TSIF1_EN", /* GPIO_90, S HSEC pin 46 */
"TSIF1_DATA", /* GPIO_91, S HSEC pin 44 */
"NC", /* GPIO_92 */
"TSIF2_CLK", /* GPIO_93, S HSEC pin 52 */
"TSIF2_EN", /* GPIO_94, S HSEC pin 56 */
"TSIF2_DATA", /* GPIO_95, S HSEC pin 54 */
"TSIF2_SYNC", /* GPIO_96, S HSEC pin 58 */
"NC", /* GPIO_97 */
"CAM1_STANDBY_N", /* GPIO_98 */
"NC", /* GPIO_99 */
"NC", /* GPIO_100 */
"[LCD1_RESET_N]", /* GPIO_101, S HSEC pin 51 */
"BOOT_CONFIG1", /* GPIO_102 */
"USB_HUB_RESET", /* GPIO_103 */
"CAM1_RST_N", /* GPIO_104 */
"NC", /* GPIO_105 */
"NC", /* GPIO_106 */
"NC", /* GPIO_107 */
"NC", /* GPIO_108 */
"NC", /* GPIO_109 */
"NC", /* GPIO_110 */
"NC", /* GPIO_111 */
"NC", /* GPIO_112 */
"PMI8994_BUA", /* GPIO_113 */
"PCIE2_RST_N", /* GPIO_114 */
"PCIE2_CLKREQ_N", /* GPIO_115 */
"PCIE2_WAKE", /* GPIO_116 */
"SSC_IRQ_0", /* GPIO_117 */
"SSC_IRQ_1", /* GPIO_118 */
"SSC_IRQ_2", /* GPIO_119 */
"NC", /* GPIO_120 */
"GPIO121", /* GPIO_121, S HSEC pin 2 */
"NC", /* GPIO_122 */
"SSC_IRQ_6", /* GPIO_123 */
"SSC_IRQ_7", /* GPIO_124 */
"GPIO-C", /* GPIO_125, TS_INT0, LSEC pin 25 */
"BOOT_CONFIG5", /* GPIO_126 */
"NC", /* GPIO_127 */
"NC", /* GPIO_128 */
"BOOT_CONFIG7", /* GPIO_129 */
"PCIE1_RST_N", /* GPIO_130 */
"PCIE1_CLKREQ_N", /* GPIO_131 */
"PCIE1_WAKE", /* GPIO_132 */
"GPIO-L", /* GPIO_133, CAM2_STANDBY_N, LSEC pin 34 */
"NC", /* GPIO_134 */
"NC", /* GPIO_135 */
"BOOT_CONFIG8", /* GPIO_136 */
"NC", /* GPIO_137 */
"NC", /* GPIO_138 */
"GPS_SSBI2", /* GPIO_139 */
"GPS_SSBI1", /* GPIO_140 */
"NC", /* GPIO_141 */
"NC", /* GPIO_142 */
"NC", /* GPIO_143 */
"BOOT_CONFIG6", /* GPIO_144 */
"NC", /* GPIO_145 */
"NC", /* GPIO_146 */
"NC", /* GPIO_147 */
"NC", /* GPIO_148 */
"NC"; /* GPIO_149 */
sdc2_cd_on: sdc2_cd_on {
mux {
pins = "gpio38";
function = "gpio";
};
phy@7411000 {
status = "okay";
config {
pins = "gpio38";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
};
phy@7412000 {
status = "okay";
sdc2_cd_off: sdc2_cd_off {
mux {
pins = "gpio38";
function = "gpio";
};
usb@6af8800 {
status = "okay";
extcon = <&usb3_id>;
config {
pins = "gpio38";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
};
dwc3@6a00000 {
extcon = <&usb3_id>;
dr_mode = "otg";
};
blsp1_uart1_default: blsp1_uart1_default {
mux {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "blsp_uart2";
};
usb3_id: usb3-id {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb3_vbus_det_gpio>;
config {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
drive-strength = <16>;
bias-disable;
};
};
usb@76f8800 {
status = "okay";
extcon = <&usb2_id>;
blsp1_uart1_sleep: blsp1_uart1_sleep {
mux {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "gpio";
};
dwc3@7600000 {
extcon = <&usb2_id>;
dr_mode = "otg";
maximum-speed = "high-speed";
};
config {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
drive-strength = <2>;
bias-disable;
};
};
usb2_id: usb2-id {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb2_vbus_det_gpio>;
hdmi_hpd_active: hdmi_hpd_active {
mux {
pins = "gpio34";
function = "hdmi_hot";
};
wlan_en: wlan-en-1-8v {
pinctrl-names = "default";
pinctrl-0 = <&wlan_en_gpios>;
compatible = "regulator-fixed";
regulator-name = "wlan-en-regulator";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
config {
pins = "gpio34";
bias-pull-down;
drive-strength = <16>;
};
};
gpio = <&pm8994_gpios 8 0>;
hdmi_hpd_suspend: hdmi_hpd_suspend {
mux {
pins = "gpio34";
function = "hdmi_hot";
};
/* WLAN card specific delay */
startup-delay-us = <70000>;
enable-active-high;
config {
pins = "gpio34";
bias-pull-down;
drive-strength = <2>;
};
};
agnoc@0 {
pcie@600000 {
status = "okay";
perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&wlan_en>;
};
hdmi_ddc_active: hdmi_ddc_active {
mux {
pins = "gpio32", "gpio33";
function = "hdmi_ddc";
};
pcie@608000 {
status = "okay";
perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>;
};
config {
pins = "gpio32", "gpio33";
drive-strength = <2>;
bias-pull-up;
};
};
pcie@610000 {
status = "okay";
perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
};
hdmi_ddc_suspend: hdmi_ddc_suspend {
mux {
pins = "gpio32", "gpio33";
function = "hdmi_ddc";
};
slim_msm: slim@91c0000 {
ngd@1 {
wcd9335: codec@1{
clock-names = "mclk", "slimbus";
clocks = <&div1_mclk>,
<&rpmcc RPM_SMD_BB_CLK1>;
};
};
config {
pins = "gpio32", "gpio33";
drive-strength = <2>;
bias-pull-down;
};
};
};
mdss@900000 {
status = "okay";
&pcie0 {
status = "okay";
perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&vreg_l28a_0p925>;
};
mdp@901000 {
status = "okay";
};
&pcie1 {
status = "okay";
perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>;
vdda-supply = <&vreg_l28a_0p925>;
};
hdmi-phy@9a0600 {
status = "okay";
&pcie2 {
status = "okay";
perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
vdda-supply = <&vreg_l28a_0p925>;
};
vddio-supply = <&pm8994_l12>;
vcca-supply = <&pm8994_l28>;
#phy-cells = <0>;
};
&pcie_phy {
status = "okay";
hdmi-tx@9a0000 {
status = "okay";
vdda-phy-supply = <&vreg_l28a_0p925>;
vdda-pll-supply = <&vreg_l12a_1p8>;
};
pinctrl-names = "default", "sleep";
pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>;
&pm8994_gpios {
gpio-line-names =
"NC",
"KEY_VOLP_N",
"NC",
"BL1_PWM",
"GPIO-F", /* BL0_PWM, LSEC pin 28 */
"BL1_EN",
"NC",
"WLAN_EN",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"DIVCLK1",
"DIVCLK2",
"DIVCLK3",
"DIVCLK4",
"BT_EN",
"PMIC_SLB",
"PMIC_BUA",
"USB_VBUS_DET";
pinctrl-names = "default";
pinctrl-0 = <&ls_exp_gpio_f &bt_en_gpios>;
ls_exp_gpio_f: pm8994_gpio5 {
pinconf {
pins = "gpio5";
output-low;
power-source = <2>; // PM8994_GPIO_S4, 1.8V
};
};
core-vdda-supply = <&pm8994_l12>;
core-vcc-supply = <&pm8994_s4>;
};
bt_en_gpios: bt_en_gpios {
pinconf {
pins = "gpio19";
function = PMIC_GPIO_FUNC_NORMAL;
output-low;
power-source = <PM8994_GPIO_S4>; // 1.8V
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
bias-pull-down;
};
};
wlan_en_gpios: wlan_en_gpios {
pinconf {
pins = "gpio8";
function = PMIC_GPIO_FUNC_NORMAL;
output-low;
power-source = <PM8994_GPIO_S4>; // 1.8V
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
bias-pull-down;
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
audio_mclk: clk_div1 {
pinconf {
pins = "gpio15";
function = "func1";
power-source = <PM8994_GPIO_S4>; // 1.8V
};
};
pinctrl-names = "default";
pinctrl-0 = <&volume_up_gpio>;
volume_up_gpio: pm8996_gpio2 {
pinconf {
pins = "gpio2";
function = "normal";
input-enable;
drive-push-pull;
bias-pull-up;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
power-source = <PM8994_GPIO_S4>; // 1.8V
};
};
button@0 {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>;
divclk4_pin_a: divclk4 {
pinconf {
pins = "gpio18";
function = PMIC_GPIO_FUNC_FUNC2;
bias-disable;
power-source = <PM8994_GPIO_S4>;
};
};
rpm-glink {
rpm_requests {
pm8994-regulators {
vdd_l1-supply = <&pm8994_s3>;
vdd_l2_l26_l28-supply = <&pm8994_s3>;
vdd_l3_l11-supply = <&pm8994_s3>;
vdd_l4_l27_l31-supply = <&pm8994_s3>;
vdd_l5_l7-supply = <&pm8994_s5>;
vdd_l14_l15-supply = <&pm8994_s5>;
vdd_l20_l21-supply = <&pm8994_s5>;
vdd_l25-supply = <&pm8994_s3>;
s3 {
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
};
/**
* 1.8v required on LS expansion
* for mezzanine boards
*/
s4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
s5 {
regulator-min-microvolt = <2150000>;
regulator-max-microvolt = <2150000>;
};
s7 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
};
l1 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
l2 {
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
};
l3 {
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
};
l4 {
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
};
l6 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
l8 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l9 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l10 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l11 {
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
};
l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l13 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
l14 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l16 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
};
l17 {
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
l18 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2900000>;
};
l19 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
l20 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
};
l21 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
regulator-system-load = <200000>;
};
l22 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
l23 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
l24 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
};
l25 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-allow-set-load;
};
l27 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
l28 {
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <925000>;
regulator-allow-set-load;
};
l29 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
l30 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
l32 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
usb3_vbus_det_gpio: pm8996_gpio22 {
pinconf {
pins = "gpio22";
function = PMIC_GPIO_FUNC_NORMAL;
input-enable;
bias-pull-down;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
power-source = <PM8994_GPIO_S4>; // 1.8V
};
};
};
&spmi_bus {
pmic@0 {
pon@800 {
resin {
compatible = "qcom,pm8941-resin";
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_VOLUMEDOWN>;
};
&pm8994_mpps {
gpio-line-names =
"VDDPX_BIAS",
"WIFI_LED",
"NC",
"BT_LED",
"PM_MPP05",
"PM_MPP06",
"PM_MPP07",
"NC";
};
&pm8994_spmi_regulators {
qcom,saw-reg = <&saw3>;
s9 {
qcom,saw-slave;
};
s10 {
qcom,saw-slave;
};
s11 {
qcom,saw-leader;
regulator-always-on;
regulator-min-microvolt = <1230000>;
regulator-max-microvolt = <1230000>;
};
};
&pmi8994_gpios {
gpio-line-names =
"NC",
"SPKR_AMP_EN1",
"SPKR_AMP_EN2",
"TP61",
"NC",
"USB2_VBUS_DET",
"NC",
"NC",
"NC",
"NC";
usb2_vbus_det_gpio: pmi8996_gpio6 {
pinconf {
pins = "gpio6";
function = PMIC_GPIO_FUNC_NORMAL;
input-enable;
bias-pull-down;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
power-source = <PM8994_GPIO_S4>; // 1.8V
};
};
};
&rpm_requests {
pm8994-regulators {
compatible = "qcom,rpm-pm8994-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_s2-supply = <&vph_pwr>;
vdd_s3-supply = <&vph_pwr>;
vdd_s4-supply = <&vph_pwr>;
vdd_s5-supply = <&vph_pwr>;
vdd_s6-supply = <&vph_pwr>;
vdd_s7-supply = <&vph_pwr>;
vdd_s8-supply = <&vph_pwr>;
vdd_s9-supply = <&vph_pwr>;
vdd_s10-supply = <&vph_pwr>;
vdd_s11-supply = <&vph_pwr>;
vdd_s12-supply = <&vph_pwr>;
vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>;
vdd_l3_l11-supply = <&vreg_s8a_l3a_input>;
vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>;
vdd_l5_l7-supply = <&vreg_s5a_2p15>;
vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>;
vdd_l8_l16_l30-supply = <&vph_pwr>;
vdd_l14_l15-supply = <&vreg_s5a_2p15>;
vdd_l25-supply = <&vreg_s3a_1p3>;
vdd_lvs1_2-supply = <&vreg_s4a_1p8>;
vreg_s3a_1p3: s3 {
regulator-name = "vreg_s3a_1p3";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
};
/**
* 1.8v required on LS expansion
* for mezzanine boards
*/
vreg_s4a_1p8: s4 {
regulator-name = "vreg_s4a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vreg_s5a_2p15: s5 {
regulator-name = "vreg_s5a_2p15";
regulator-min-microvolt = <2150000>;
regulator-max-microvolt = <2150000>;
};
vreg_s7a_1p0: s7 {
regulator-name = "vreg_s7a_1p0";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
};
vreg_l1a_1p0: l1 {
regulator-name = "vreg_l1a_1p0";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
vreg_l2a_1p25: l2 {
regulator-name = "vreg_l2a_1p25";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
};
vreg_l3a_0p875: l3 {
regulator-name = "vreg_l3a_0p875";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
};
vreg_l4a_1p225: l4 {
regulator-name = "vreg_l4a_1p225";
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
};
vreg_l6a_1p2: l6 {
regulator-name = "vreg_l6a_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
vreg_l8a_1p8: l8 {
regulator-name = "vreg_l8a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l9a_1p8: l9 {
regulator-name = "vreg_l9a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l10a_1p8: l10 {
regulator-name = "vreg_l10a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l11a_1p15: l11 {
regulator-name = "vreg_l11a_1p15";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
};
vreg_l12a_1p8: l12 {
regulator-name = "vreg_l12a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l13a_2p95: l13 {
regulator-name = "vreg_l13a_2p95";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
vreg_l14a_1p8: l14 {
regulator-name = "vreg_l14a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l15a_1p8: l15 {
regulator-name = "vreg_l15a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l16a_2p7: l16 {
regulator-name = "vreg_l16a_2p7";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
};
vreg_l17a_2p8: l17 {
regulator-name = "vreg_l17a_2p8";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
vreg_l18a_2p85: l18 {
regulator-name = "vreg_l18a_2p85";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2900000>;
};
vreg_l19a_2p8: l19 {
regulator-name = "vreg_l19a_2p8";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
vreg_l20a_2p95: l20 {
regulator-name = "vreg_l20a_2p95";
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
};
vreg_l21a_2p95: l21 {
regulator-name = "vreg_l21a_2p95";
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
regulator-system-load = <200000>;
};
vreg_l22a_3p0: l22 {
regulator-name = "vreg_l22a_3p0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vreg_l23a_2p8: l23 {
regulator-name = "vreg_l23a_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
vreg_l24a_3p075: l24 {
regulator-name = "vreg_l24a_3p075";
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
};
vreg_l25a_1p2: l25 {
regulator-name = "vreg_l25a_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-allow-set-load;
};
vreg_l26a_0p8: l27 {
regulator-name = "vreg_l26a_0p8";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
vreg_l28a_0p925: l28 {
regulator-name = "vreg_l28a_0p925";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <925000>;
regulator-allow-set-load;
};
vreg_l29a_2p8: l29 {
regulator-name = "vreg_l29a_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
vreg_l30a_1p8: l30 {
regulator-name = "vreg_l30a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l32a_1p8: l32 {
regulator-name = "vreg_l32a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_lvs1a_1p8: lvs1 {
regulator-name = "vreg_lvs1a_1p8";
};
vreg_lvs2a_1p8: lvs2 {
regulator-name = "vreg_lvs2a_1p8";
};
};
};
&sdhc2 {
/* External SD card */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
cd-gpios = <&msmgpio 38 0x1>;
vmmc-supply = <&vreg_l21a_2p95>;
vqmmc-supply = <&vreg_l13a_2p95>;
status = "okay";
};
&sound {
compatible = "qcom,apq8096-sndcard";
model = "DB820c";
......@@ -754,3 +979,84 @@ codec {
};
};
};
&spmi_bus {
pmic@0 {
pon@800 {
resin {
compatible = "qcom,pm8941-resin";
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_VOLUMEDOWN>;
};
};
};
};
&ufsphy {
status = "okay";
vdda-phy-supply = <&vreg_l28a_0p925>;
vdda-pll-supply = <&vreg_l12a_1p8>;
vdda-phy-max-microamp = <18380>;
vdda-pll-max-microamp = <9440>;
vddp-ref-clk-supply = <&vreg_l25a_1p2>;
vddp-ref-clk-max-microamp = <100>;
vddp-ref-clk-always-on;
};
&ufshc {
status = "okay";
vcc-supply = <&vreg_l20a_2p95>;
vccq-supply = <&vreg_l25a_1p2>;
vccq2-supply = <&vreg_s4a_1p8>;
vcc-max-microamp = <600000>;
vccq-max-microamp = <450000>;
vccq2-max-microamp = <450000>;
};
&usb2 {
status = "okay";
extcon = <&usb2_id>;
dwc3@7600000 {
extcon = <&usb2_id>;
dr_mode = "otg";
maximum-speed = "high-speed";
};
};
&usb3 {
status = "okay";
extcon = <&usb3_id>;
dwc3@6a00000 {
extcon = <&usb3_id>;
dr_mode = "otg";
};
};
&usb3phy {
status = "okay";
vdda-phy-supply = <&vreg_l28a_0p925>;
vdda-pll-supply = <&vreg_l12a_1p8>;
};
&wcd9335 {
clock-names = "mclk", "slimbus";
clocks = <&div1_mclk>,
<&rpmcc RPM_SMD_BB_CLK1>;
vdd-buck-supply = <&vreg_s4a_1p8>;
vdd-buck-sido-supply = <&vreg_s4a_1p8>;
vdd-tx-supply = <&vreg_s4a_1p8>;
vdd-rx-supply = <&vreg_s4a_1p8>;
vdd-io-supply = <&vreg_s4a_1p8>;
};
arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts 0 → 100644
View file @ 2e04d1bd
// SPDX-License-Identifier: BSD-3-Clause
/dts-v1/;
#include "msm8996.dtsi"
#include "pm8994.dtsi"
#include "pmi8994.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
model = "Inforce 6640 Single Board Computer";
compatible = "inforce,ifc6640", "qcom,apq8096-sbc", "qcom,apq8096";
qcom,msm-id = <291 0x00030001>;
qcom,board-id = <0x00010018 0>;
aliases {
serial0 = &blsp2_uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
v1p05: v1p05-regulator {
compatible = "regulator-fixed";
reglator-name = "v1p05";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
vin-supply = <&v5p0>;
};
v12_poe: v12-poe-regulator {
compatible = "regulator-fixed";
reglator-name = "v12_poe";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
v3p3: v3p3-regulator {
compatible = "regulator-fixed";
regulator-name = "v3p3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&v12_poe>;
};
v5p0: v5p0-regulator {
compatible = "regulator-fixed";
regulator-name = "v5p0";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&v12_poe>;
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3800000>;
regulator-max-microvolt = <3800000>;
};
};
&blsp2_uart1 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_uart1_2pins_default>;
pinctrl-1 = <&blsp2_uart1_2pins_sleep>;
};
&msmgpio {
sdc2_pins_default: sdc2-pins-default {
clk {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
cmd {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
data {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
cd {
pins = "gpio38";
function = "gpio";
bias-pull-up;
drive-strength = <16>;
};
};
sdc2_pins_sleep: sdc2-pins-sleep {
clk {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
cmd {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
data {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
};
cd {
pins = "gpio38";
function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
};
};
&rpm_requests {
pm8994-regulators {
compatible = "qcom,rpm-pm8994-regulators";
vdd_s1-supply = <&vph_pwr>;
vdd_s2-supply = <&vph_pwr>;
vdd_s3-supply = <&vph_pwr>;
vdd_s4-supply = <&vph_pwr>;
vdd_s5-supply = <&vph_pwr>;
vdd_s6-supply = <&vph_pwr>;
vdd_s7-supply = <&vph_pwr>;
vdd_s8-supply = <&vph_pwr>;
vdd_s9-supply = <&vph_pwr>;
vdd_s10-supply = <&vph_pwr>;
vdd_s11-supply = <&vph_pwr>;
vdd_s12-supply = <&vph_pwr>;
vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>;
vdd_l3_l11-supply = <&vreg_s3a_1p3>;
vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>;
vdd_l5_l7-supply = <&vreg_s5a_2p15>;
vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>;
vdd_l8_l16_l30-supply = <&vph_pwr>;
vdd_l25-supply = <&vreg_s3a_1p3>;
vdd_lvs1_2-supply = <&vreg_s4a_1p8>;
vreg_s3a_1p3: s3 {
regulator-name = "vreg_s3a_1p3";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
};
vreg_s4a_1p8: s4 {
regulator-name = "vreg_s4a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
vreg_s5a_2p15: s5 {
regulator-name = "vreg_s5a_2p15";
regulator-min-microvolt = <2150000>;
regulator-max-microvolt = <2150000>;
};
vreg_s7a_1p0: s7 {
regulator-name = "vreg_s7a_1p0";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
};
vreg_l1a_1p0: l1 {
regulator-name = "vreg_l1a_1p0";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
vreg_l2a_1p25: l2 {
regulator-name = "vreg_l2a_1p25";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <1250000>;
};
vreg_l3a_0p875: l3 {
regulator-name = "vreg_l3a_0p875";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
};
vreg_l4a_1p225: l4 {
regulator-name = "vreg_l4a_1p225";
regulator-min-microvolt = <1225000>;
regulator-max-microvolt = <1225000>;
};
vreg_l6a_1p2: l6 {
regulator-name = "vreg_l6a_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
vreg_l8a_1p8: l8 {
regulator-name = "vreg_l8a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l9a_1p8: l9 {
regulator-name = "vreg_l9a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l10a_1p8: l10 {
regulator-name = "vreg_l10a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l11a_1p15: l11 {
regulator-name = "vreg_l11a_1p15";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
};
vreg_l12a_1p8: l12 {
regulator-name = "vreg_l12a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l13a_2p95: l13 {
regulator-name = "vreg_l13a_2p95";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
vreg_l14a_1p8: l14 {
regulator-name = "vreg_l14a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l15a_1p8: l15 {
regulator-name = "vreg_l15a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l16a_2p7: l16 {
regulator-name = "vreg_l16a_2p7";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2700000>;
};
vreg_l17a_2p8: l17 {
regulator-name = "vreg_l17a_2p8";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
vreg_l18a_2p85: l18 {
regulator-name = "vreg_l18a_2p85";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <2900000>;
};
vreg_l19a_2p8: l19 {
regulator-name = "vreg_l19a_2p8";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
vreg_l20a_2p95: l20 {
regulator-name = "vreg_l20a_2p95";
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
regulator-allow-set-load;
};
vreg_l21a_2p95: l21 {
regulator-name = "vreg_l21a_2p95";
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
};
vreg_l22a_3p0: l22 {
regulator-name = "vreg_l22a_3p0";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vreg_l23a_2p8: l23 {
regulator-name = "vreg_l23a_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
vreg_l24a_3p075: l24 {
regulator-name = "vreg_l24a_3p075";
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3075000>;
};
vreg_l25a_1p2: l25 {
regulator-name = "vreg_l25a_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-allow-set-load;
};
vreg_l26a_0p8: l27 {
regulator-name = "vreg_l26a_0p8";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
};
vreg_l28a_0p925: l28 {
regulator-name = "vreg_l28a_0p925";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <925000>;
regulator-allow-set-load;
};
vreg_l29a_2p8: l29 {
regulator-name = "vreg_l29a_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
vreg_l30a_1p8: l30 {
regulator-name = "vreg_l30a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_l32a_1p8: l32 {
regulator-name = "vreg_l32a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_lvs1a_1p8: lvs1 {
regulator-name = "vreg_lvs1a_1p8";
};
vreg_lvs2a_1p8: lvs2 {
regulator-name = "vreg_lvs2a_1p8";
};
};
};
&sdhc2 {
status = "okay";
bus-width = <4>;
cd-gpios = <&msmgpio 38 0x1>;
vmmc-supply = <&vreg_l21a_2p95>;
vqmmc-supply = <&vreg_l13a_2p95>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_pins_default>;
pinctrl-1 = <&sdc2_pins_sleep>;
};
&ufshc {
status = "okay";
vcc-supply = <&vreg_l20a_2p95>;
vccq-supply = <&vreg_l25a_1p2>;
vccq2-supply = <&vreg_s4a_1p8>;
vcc-max-microamp = <600000>;
vccq-max-microamp = <450000>;
vccq2-max-microamp = <450000>;
};
&ufsphy {
status = "okay";
vdda-phy-supply = <&vreg_l28a_0p925>;
vdda-pll-supply = <&vreg_l12a_1p8>;
vdda-phy-max-microamp = <18380>;
vdda-pll-max-microamp = <9440>;
};
arch/arm64/boot/dts/qcom/msm8916.dtsi
View file @ 2e04d1bd
......@@ -429,7 +429,8 @@ apcs: mailbox@b011000 {
compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
reg = <0xb011000 0x1000>;
#mbox-cells = <1>;
clocks = <&a53pll>;
clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
clock-names = "pll", "aux";
#clock-cells = <0>;
};
......@@ -816,6 +817,8 @@ tsens: thermal-sensor@4a9000 {
nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
nvmem-cell-names = "calib", "calib_sel";
#qcom,sensors = <5>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";
#thermal-sensor-cells = <1>;
};
......
arch/arm64/boot/dts/qcom/msm8996.dtsi
View file @ 2e04d1bd
......@@ -16,72 +16,19 @@ / {
chosen { };
memory {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
mba_region: mba@91500000 {
reg = <0x0 0x91500000 0x0 0x200000>;
no-map;
};
slpi_region: slpi@90b00000 {
reg = <0x0 0x90b00000 0x0 0xa00000>;
no-map;
};
venus_region: venus@90400000 {
reg = <0x0 0x90400000 0x0 0x700000>;
no-map;
};
adsp_region: adsp@8ea00000 {
reg = <0x0 0x8ea00000 0x0 0x1a00000>;
no-map;
};
mpss_region: mpss@88800000 {
reg = <0x0 0x88800000 0x0 0x6200000>;
no-map;
};
smem_mem: smem-mem@86000000 {
reg = <0x0 0x86000000 0x0 0x200000>;
no-map;
};
memory@85800000 {
reg = <0x0 0x85800000 0x0 0x800000>;
no-map;
};
memory@86200000 {
reg = <0x0 0x86200000 0x0 0x2600000>;
no-map;
};
rmtfs@86700000 {
compatible = "qcom,rmtfs-mem";
size = <0x0 0x200000>;
alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
no-map;
qcom,client-id = <1>;
qcom,vmid = <15>;
clocks {
xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
clock-output-names = "xo_board";
};
zap_shader_region: gpu@8f200000 {
compatible = "shared-dma-pool";
reg = <0x0 0x90b00000 0x0 0xa00000>;
no-map;
sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32764>;
clock-output-names = "sleep_clk";
};
};
......@@ -173,307 +120,109 @@ CPU_SLEEP_0: cpu-sleep-0 {
};
};
thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
firmware {
scm {
compatible = "qcom,scm-msm8996";
qcom,dload-mode = <&tcsr 0x13000>;
};
};
thermal-sensors = <&tsens0 3>;
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x1000>;
#hwlock-cells = <1>;
};
trips {
cpu0_alert0: trip-point@0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
memory {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
};
cpu0_crit: cpu_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
cpu1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
thermal-sensors = <&tsens0 5>;
mba_region: mba@91500000 {
reg = <0x0 0x91500000 0x0 0x200000>;
no-map;
};
trips {
cpu1_alert0: trip-point@0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
slpi_region: slpi@90b00000 {
reg = <0x0 0x90b00000 0x0 0xa00000>;
no-map;
};
cpu1_crit: cpu_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
venus_region: venus@90400000 {
reg = <0x0 0x90400000 0x0 0x700000>;
no-map;
};
cpu2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
adsp_region: adsp@8ea00000 {
reg = <0x0 0x8ea00000 0x0 0x1a00000>;
no-map;
};
thermal-sensors = <&tsens0 8>;
mpss_region: mpss@88800000 {
reg = <0x0 0x88800000 0x0 0x6200000>;
no-map;
};
trips {
cpu2_alert0: trip-point@0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
smem_mem: smem-mem@86000000 {
reg = <0x0 0x86000000 0x0 0x200000>;
no-map;
};
cpu2_crit: cpu_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
memory@85800000 {
reg = <0x0 0x85800000 0x0 0x800000>;
no-map;
};
cpu3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
memory@86200000 {
reg = <0x0 0x86200000 0x0 0x2600000>;
no-map;
};
thermal-sensors = <&tsens0 10>;
rmtfs@86700000 {
compatible = "qcom,rmtfs-mem";
trips {
cpu3_alert0: trip-point@0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
size = <0x0 0x200000>;
alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
no-map;
cpu3_crit: cpu_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
qcom,client-id = <1>;
qcom,vmid = <15>;
};
gpu-thermal-top {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 6>;
trips {
gpu1_alert0: trip-point@0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
zap_shader_region: gpu@8f200000 {
compatible = "shared-dma-pool";
reg = <0x0 0x90b00000 0x0 0xa00000>;
no-map;
};
};
gpu-thermal-bottom {
polling-delay-passive = <250>;
polling-delay = <1000>;
rpm-glink {
compatible = "qcom,glink-rpm";
thermal-sensors = <&tsens1 7>;
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
trips {
gpu2_alert0: trip-point@0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
qcom,rpm-msg-ram = <&rpm_msg_ram>;
m4m-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
mboxes = <&apcs_glb 0>;
thermal-sensors = <&tsens0 1>;
rpm_requests: rpm-requests {
compatible = "qcom,rpm-msm8996";
qcom,glink-channels = "rpm_requests";
trips {
m4m_alert0: trip-point@0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
l3-or-venus-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 2>;
trips {
l3_or_venus_alert0: trip-point@0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
cluster0-l2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 7>;
trips {
cluster0_l2_alert0: trip-point@0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
cluster1-l2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 12>;
trips {
cluster1_l2_alert0: trip-point@0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
camera-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 1>;
trips {
camera_alert0: trip-point@0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
q6-dsp-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 2>;
trips {
q6_dsp_alert0: trip-point@0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
mem-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 3>;
trips {
mem_alert0: trip-point@0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
modemtx-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 4>;
trips {
modemtx_alert0: trip-point@0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
clocks {
xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
clock-output-names = "xo_board";
};
sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32764>;
clock-output-names = "sleep_clk";
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
firmware {
scm {
compatible = "qcom,scm-msm8996";
qcom,dload-mode = <&tcsr 0x13000>;
};
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x1000>;
#hwlock-cells = <1>;
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
};
rpm-glink {
compatible = "qcom,glink-rpm";
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
qcom,rpm-msg-ram = <&rpm_msg_ram>;
mboxes = <&apcs_glb 0>;
rpm_requests {
compatible = "qcom,rpm-msm8996";
qcom,glink-channels = "rpm_requests";
rpmcc: qcom,rpmcc {
compatible = "qcom,rpmcc-msm8996";
#clock-cells = <1>;
rpmcc: qcom,rpmcc {
compatible = "qcom,rpmcc-msm8996";
#clock-cells = <1>;
};
rpmpd: power-controller {
......@@ -509,856 +258,633 @@ rpmpd_opp6: opp6 {
};
};
};
pm8994-regulators {
compatible = "qcom,rpm-pm8994-regulators";
pm8994_s1: s1 {};
pm8994_s2: s2 {};
pm8994_s3: s3 {};
pm8994_s4: s4 {};
pm8994_s5: s5 {};
pm8994_s6: s6 {};
pm8994_s7: s7 {};
pm8994_s8: s8 {};
pm8994_s9: s9 {};
pm8994_s10: s10 {};
pm8994_s11: s11 {};
pm8994_s12: s12 {};
pm8994_l1: l1 {};
pm8994_l2: l2 {};
pm8994_l3: l3 {};
pm8994_l4: l4 {};
pm8994_l5: l5 {};
pm8994_l6: l6 {};
pm8994_l7: l7 {};
pm8994_l8: l8 {};
pm8994_l9: l9 {};
pm8994_l10: l10 {};
pm8994_l11: l11 {};
pm8994_l12: l12 {};
pm8994_l13: l13 {};
pm8994_l14: l14 {};
pm8994_l15: l15 {};
pm8994_l16: l16 {};
pm8994_l17: l17 {};
pm8994_l18: l18 {};
pm8994_l19: l19 {};
pm8994_l20: l20 {};
pm8994_l21: l21 {};
pm8994_l22: l22 {};
pm8994_l23: l23 {};
pm8994_l24: l24 {};
pm8994_l25: l25 {};
pm8994_l26: l26 {};
pm8994_l27: l27 {};
pm8994_l28: l28 {};
pm8994_l29: l29 {};
pm8994_l30: l30 {};
pm8994_l31: l31 {};
pm8994_l32: l32 {};
};
};
};
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
};
rpm_msg_ram: memory@68000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x68000 0x6000>;
};
smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
rng: rng@83000 {
compatible = "qcom,prng-ee";
reg = <0x00083000 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
tcsr_mutex_regs: syscon@740000 {
compatible = "syscon";
reg = <0x740000 0x20000>;
};
mboxes = <&apcs_glb 10>;
tsens0: thermal-sensor@4a9000 {
compatible = "qcom,msm8996-tsens";
reg = <0x4a9000 0x1000>, /* TM */
<0x4a8000 0x1000>; /* SROT */
#qcom,sensors = <13>;
interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";
#thermal-sensor-cells = <1>;
};
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
tsens1: thermal-sensor@4ad000 {
compatible = "qcom,msm8996-tsens";
reg = <0x4ad000 0x1000>, /* TM */
<0x4ac000 0x1000>; /* SROT */
#qcom,sensors = <8>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";
#thermal-sensor-cells = <1>;
smp2p_adsp_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
tcsr: syscon@7a0000 {
compatible = "qcom,tcsr-msm8996", "syscon";
reg = <0x7a0000 0x18000>;
};
smp2p_adsp_in: slave-kernel {
qcom,entry-name = "slave-kernel";
intc: interrupt-controller@9bc0000 {
compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x40000>;
reg = <0x09bc0000 0x10000>,
<0x09c00000 0x100000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
};
apcs_glb: mailbox@9820000 {
compatible = "qcom,msm8996-apcs-hmss-global";
reg = <0x9820000 0x1000>;
smp2p-modem {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
#mbox-cells = <1>;
};
interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
gcc: clock-controller@300000 {
compatible = "qcom,gcc-msm8996";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x300000 0x90000>;
};
mboxes = <&apcs_glb 14>;
stm@3002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x3002000 0x1000>,
<0x8280000 0x180000>;
reg-names = "stm-base", "stm-stimulus-base";
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
modem_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
out-ports {
port {
stm_out: endpoint {
remote-endpoint =
<&funnel0_in>;
};
};
};
};
tpiu@3020000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0x3020000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
modem_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
in-ports {
port {
tpiu_in: endpoint {
remote-endpoint =
<&replicator_out1>;
};
};
};
interrupt-controller;
#interrupt-cells = <2>;
};
};
funnel@3021000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3021000 0x1000>;
smp2p-slpi {
compatible = "qcom,smp2p";
qcom,smem = <481>, <430>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
in-ports {
#address-cells = <1>;
#size-cells = <0>;
mboxes = <&apcs_glb 26>;
port@7 {
reg = <7>;
funnel0_in: endpoint {
remote-endpoint =
<&stm_out>;
};
};
};
qcom,local-pid = <0>;
qcom,remote-pid = <3>;
out-ports {
port {
funnel0_out: endpoint {
remote-endpoint =
<&merge_funnel_in0>;
};
};
};
smp2p_slpi_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
funnel@3022000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3022000 0x1000>;
smp2p_slpi_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
};
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
pcie_phy: phy@34000 {
compatible = "qcom,msm8996-qmp-pcie-phy";
reg = <0x00034000 0x488>;
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
port@6 {
reg = <6>;
funnel1_in: endpoint {
remote-endpoint =
<&apss_merge_funnel_out>;
};
};
};
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
<&gcc GCC_PCIE_CLKREF_CLK>;
clock-names = "aux", "cfg_ahb", "ref";
out-ports {
port {
funnel1_out: endpoint {
remote-endpoint =
<&merge_funnel_in1>;
};
};
};
};
resets = <&gcc GCC_PCIE_PHY_BCR>,
<&gcc GCC_PCIE_PHY_COM_BCR>,
<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
reset-names = "phy", "common", "cfg";
status = "disabled";
funnel@3023000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3023000 0x1000>;
pciephy_0: lane@35000 {
reg = <0x00035000 0x130>,
<0x00035200 0x200>,
<0x00035400 0x1dc>;
#phy-cells = <0>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
clock-output-names = "pcie_0_pipe_clk_src";
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "lane0";
};
pciephy_1: lane@36000 {
reg = <0x00036000 0x130>,
<0x00036200 0x200>,
<0x00036400 0x1dc>;
#phy-cells = <0>;
out-ports {
port {
funnel2_out: endpoint {
remote-endpoint =
<&merge_funnel_in2>;
};
};
clock-output-names = "pcie_1_pipe_clk_src";
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "pipe1";
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "lane1";
};
};
funnel@3025000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3025000 0x1000>;
pciephy_2: lane@37000 {
reg = <0x00037000 0x130>,
<0x00037200 0x200>,
<0x00037400 0x1dc>;
#phy-cells = <0>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
clock-output-names = "pcie_2_pipe_clk_src";
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
clock-names = "pipe2";
resets = <&gcc GCC_PCIE_2_PHY_BCR>;
reset-names = "lane2";
};
};
in-ports {
#address-cells = <1>;
#size-cells = <0>;
rpm_msg_ram: memory@68000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x00068000 0x6000>;
};
port@0 {
reg = <0>;
merge_funnel_in0: endpoint {
remote-endpoint =
<&funnel0_out>;
};
};
qfprom@74000 {
compatible = "qcom,qfprom";
reg = <0x00074000 0x8ff>;
#address-cells = <1>;
#size-cells = <1>;
port@1 {
reg = <1>;
merge_funnel_in1: endpoint {
remote-endpoint =
<&funnel1_out>;
};
};
qusb2p_hstx_trim: hstx_trim@24e {
reg = <0x24e 0x2>;
bits = <5 4>;
};
port@2 {
reg = <2>;
merge_funnel_in2: endpoint {
remote-endpoint =
<&funnel2_out>;
};
};
qusb2s_hstx_trim: hstx_trim@24f {
reg = <0x24f 0x1>;
bits = <1 4>;
};
out-ports {
port {
merge_funnel_out: endpoint {
remote-endpoint =
<&etf_in>;
};
};
gpu_speed_bin: gpu_speed_bin@133 {
reg = <0x133 0x1>;
bits = <5 3>;
};
};
replicator@3026000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x3026000 0x1000>;
rng: rng@83000 {
compatible = "qcom,prng-ee";
reg = <0x00083000 0x1000>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
gcc: clock-controller@300000 {
compatible = "qcom,gcc-msm8996";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x00300000 0x90000>;
};
in-ports {
port {
replicator_in: endpoint {
remote-endpoint =
<&etf_out>;
};
};
};
tsens0: thermal-sensor@4a9000 {
compatible = "qcom,msm8996-tsens";
reg = <0x004a9000 0x1000>, /* TM */
<0x004a8000 0x1000>; /* SROT */
#qcom,sensors = <13>;
interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
};
out-ports {
#address-cells = <1>;
#size-cells = <0>;
tsens1: thermal-sensor@4ad000 {
compatible = "qcom,msm8996-tsens";
reg = <0x004ad000 0x1000>, /* TM */
<0x004ac000 0x1000>; /* SROT */
#qcom,sensors = <8>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
};
port@0 {
reg = <0>;
replicator_out0: endpoint {
remote-endpoint =
<&etr_in>;
};
};
tcsr_mutex_regs: syscon@740000 {
compatible = "syscon";
reg = <0x00740000 0x20000>;
};
port@1 {
reg = <1>;
replicator_out1: endpoint {
remote-endpoint =
<&tpiu_in>;
};
};
};
tcsr: syscon@7a0000 {
compatible = "qcom,tcsr-msm8996", "syscon";
reg = <0x007a0000 0x18000>;
};
etf@3027000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x3027000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
mmcc: clock-controller@8c0000 {
compatible = "qcom,mmcc-msm8996";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x008c0000 0x40000>;
assigned-clocks = <&mmcc MMPLL9_PLL>,
<&mmcc MMPLL1_PLL>,
<&mmcc MMPLL3_PLL>,
<&mmcc MMPLL4_PLL>,
<&mmcc MMPLL5_PLL>;
assigned-clock-rates = <624000000>,
<810000000>,
<980000000>,
<960000000>,
<825000000>;
};
in-ports {
port {
etf_in: endpoint {
remote-endpoint =
<&merge_funnel_out>;
};
};
};
mdss: mdss@900000 {
compatible = "qcom,mdss";
out-ports {
port {
etf_out: endpoint {
remote-endpoint =
<&replicator_in>;
};
};
};
};
reg = <0x00900000 0x1000>,
<0x009b0000 0x1040>,
<0x009b8000 0x1040>;
reg-names = "mdss_phys",
"vbif_phys",
"vbif_nrt_phys";
etr@3028000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x3028000 0x1000>;
power-domains = <&mmcc MDSS_GDSC>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
arm,scatter-gather;
interrupt-controller;
#interrupt-cells = <1>;
in-ports {
port {
etr_in: endpoint {
remote-endpoint =
<&replicator_out0>;
};
};
};
};
clocks = <&mmcc MDSS_AHB_CLK>;
clock-names = "iface";
debug@3810000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x3810000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
mdp: mdp@901000 {
compatible = "qcom,mdp5";
reg = <0x00901000 0x90000>;
reg-names = "mdp_phys";
cpu = <&CPU0>;
};
interrupt-parent = <&mdss>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
etm@3840000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x3840000 0x1000>;
clocks = <&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
<&mmcc MDSS_MDP_CLK>,
<&mmcc SMMU_MDP_AXI_CLK>,
<&mmcc MDSS_VSYNC_CLK>;
clock-names = "iface",
"bus",
"core",
"iommu",
"vsync";
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
iommus = <&mdp_smmu 0>;
cpu = <&CPU0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
out-ports {
port {
etm0_out: endpoint {
remote-endpoint =
<&apss_funnel0_in0>;
port@0 {
reg = <0>;
mdp5_intf3_out: endpoint {
remote-endpoint = <&hdmi_in>;
};
};
};
};
};
debug@3910000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x3910000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
hdmi: hdmi-tx@9a0000 {
compatible = "qcom,hdmi-tx-8996";
reg = <0x009a0000 0x50c>,
<0x00070000 0x6158>,
<0x009e0000 0xfff>;
reg-names = "core_physical",
"qfprom_physical",
"hdcp_physical";
cpu = <&CPU1>;
};
interrupt-parent = <&mdss>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
etm@3940000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x3940000 0x1000>;
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_HDMI_CLK>,
<&mmcc MDSS_HDMI_AHB_CLK>,
<&mmcc MDSS_EXTPCLK_CLK>;
clock-names =
"mdp_core",
"iface",
"core",
"alt_iface",
"extp";
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
phys = <&hdmi_phy>;
phy-names = "hdmi_phy";
#sound-dai-cells = <1>;
cpu = <&CPU1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
out-ports {
port {
etm1_out: endpoint {
remote-endpoint =
<&apss_funnel0_in1>;
port@0 {
reg = <0>;
hdmi_in: endpoint {
remote-endpoint = <&mdp5_intf3_out>;
};
};
};
};
};
funnel@39b0000 { /* APSS Funnel 0 */
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x39b0000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
apss_funnel0_in0: endpoint {
remote-endpoint = <&etm0_out>;
};
};
port@1 {
reg = <1>;
apss_funnel0_in1: endpoint {
remote-endpoint = <&etm1_out>;
};
};
};
hdmi_phy: hdmi-phy@9a0600 {
#phy-cells = <0>;
compatible = "qcom,hdmi-phy-8996";
reg = <0x009a0600 0x1c4>,
<0x009a0a00 0x124>,
<0x009a0c00 0x124>,
<0x009a0e00 0x124>,
<0x009a1000 0x124>,
<0x009a1200 0x0c8>;
reg-names = "hdmi_pll",
"hdmi_tx_l0",
"hdmi_tx_l1",
"hdmi_tx_l2",
"hdmi_tx_l3",
"hdmi_phy";
out-ports {
port {
apss_funnel0_out: endpoint {
remote-endpoint =
<&apss_merge_funnel_in0>;
};
};
clocks = <&mmcc MDSS_AHB_CLK>,
<&gcc GCC_HDMI_CLKREF_CLK>;
clock-names = "iface",
"ref";
};
};
gpu@b00000 {
compatible = "qcom,adreno-530.2", "qcom,adreno";
#stream-id-cells = <16>;
debug@3a10000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x3a10000 0x1000>;
reg = <0x00b00000 0x3f000>;
reg-names = "kgsl_3d0_reg_memory";
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
cpu = <&CPU2>;
};
clocks = <&mmcc GPU_GX_GFX3D_CLK>,
<&mmcc GPU_AHB_CLK>,
<&mmcc GPU_GX_RBBMTIMER_CLK>,
<&gcc GCC_BIMC_GFX_CLK>,
<&gcc GCC_MMSS_BIMC_GFX_CLK>;
etm@3a40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x3a40000 0x1000>;
clock-names = "core",
"iface",
"rbbmtimer",
"mem",
"mem_iface";
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
power-domains = <&mmcc GPU_GDSC>;
iommus = <&adreno_smmu 0>;
cpu = <&CPU2>;
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
out-ports {
port {
etm2_out: endpoint {
remote-endpoint =
<&apss_funnel1_in0>;
};
};
};
};
qcom,gpu-quirk-two-pass-use-wfi;
qcom,gpu-quirk-fault-detect-mask;
debug@3b10000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x3b10000 0x1000>;
operating-points-v2 = <&gpu_opp_table>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU3>;
};
gpu_opp_table: opp-table {
compatible ="operating-points-v2";
etm@3b40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x3b40000 0x1000>;
/*
* 624Mhz and 560Mhz are only available on speed
* bin (1 << 0). All the rest are available on
* all bins of the hardware
*/
opp-624000000 {
opp-hz = /bits/ 64 <624000000>;
opp-supported-hw = <0x01>;
};
opp-560000000 {
opp-hz = /bits/ 64 <560000000>;
opp-supported-hw = <0x01>;
};
opp-510000000 {
opp-hz = /bits/ 64 <510000000>;
opp-supported-hw = <0xFF>;
};
opp-401800000 {
opp-hz = /bits/ 64 <401800000>;
opp-supported-hw = <0xFF>;
};
opp-315000000 {
opp-hz = /bits/ 64 <315000000>;
opp-supported-hw = <0xFF>;
};
opp-214000000 {
opp-hz = /bits/ 64 <214000000>;
opp-supported-hw = <0xFF>;
};
opp-133000000 {
opp-hz = /bits/ 64 <133000000>;
opp-supported-hw = <0xFF>;
};
};
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
zap-shader {
memory-region = <&zap_shader_region>;
};
};
cpu = <&CPU3>;
msmgpio: pinctrl@1010000 {
compatible = "qcom,msm8996-pinctrl";
reg = <0x01010000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
out-ports {
port {
etm3_out: endpoint {
remote-endpoint =
<&apss_funnel1_in1>;
};
};
};
spmi_bus: qcom,spmi@400f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0400f000 0x1000>,
<0x04400000 0x800000>,
<0x04c00000 0x800000>,
<0x05800000 0x200000>,
<0x0400a000 0x002100>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
};
funnel@3bb0000 { /* APSS Funnel 1 */
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3bb0000 0x1000>;
agnoc@0 {
power-domains = <&gcc AGGRE0_NOC_GDSC>;
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
pcie0: pcie@600000 {
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
status = "disabled";
power-domains = <&gcc PCIE0_GDSC>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
in-ports {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00600000 0x2000>,
<0x0c000000 0xf1d>,
<0x0c000f20 0xa8>,
<0x0c100000 0x100000>;
reg-names = "parf", "dbi", "elbi","config";
port@0 {
reg = <0>;
apss_funnel1_in0: endpoint {
remote-endpoint = <&etm2_out>;
};
};
phys = <&pciephy_0>;
phy-names = "pciephy";
port@1 {
reg = <1>;
apss_funnel1_in1: endpoint {
remote-endpoint = <&etm3_out>;
};
};
};
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
out-ports {
port {
apss_funnel1_out: endpoint {
remote-endpoint =
<&apss_merge_funnel_in1>;
};
};
};
};
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
funnel@3bc0000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3bc0000 0x1000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
linux,pci-domain = <0>;
in-ports {
#address-cells = <1>;
#size-cells = <0>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
port@0 {
reg = <0>;
apss_merge_funnel_in0: endpoint {
remote-endpoint =
<&apss_funnel0_out>;
};
};
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave";
port@1 {
reg = <1>;
apss_merge_funnel_in1: endpoint {
remote-endpoint =
<&apss_funnel1_out>;
};
};
};
out-ports {
port {
apss_merge_funnel_out: endpoint {
remote-endpoint =
<&funnel1_in>;
};
};
};
};
pcie1: pcie@608000 {
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
power-domains = <&gcc PCIE1_GDSC>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
kryocc: clock-controller@6400000 {
compatible = "qcom,apcc-msm8996";
reg = <0x6400000 0x90000>;
#clock-cells = <1>;
};
status = "disabled";
blsp1_uart1: serial@7570000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x07570000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
reg = <0x00608000 0x2000>,
<0x0d000000 0xf1d>,
<0x0d000f20 0xa8>,
<0x0d100000 0x100000>;
blsp1_spi0: spi@7575000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07575000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_spi0_default>;
pinctrl-1 = <&blsp1_spi0_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
reg-names = "parf", "dbi", "elbi","config";
blsp2_i2c0: i2c@75b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b5000 0x1000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c0_default>;
pinctrl-1 = <&blsp2_i2c0_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
phys = <&pciephy_1>;
phy-names = "pciephy";
blsp2_uart1: serial@75b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x75b0000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
blsp2_i2c1: i2c@75b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b6000 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c1_default>;
pinctrl-1 = <&blsp2_i2c1_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_uart2: serial@75b1000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x075b1000 0x1000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
blsp1_i2c2: i2c@7577000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07577000 0x1000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c2_default>;
pinctrl-1 = <&blsp1_i2c2_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
blsp2_spi5: spi@75ba000{
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x075ba000 0x600>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_spi5_default>;
pinctrl-1 = <&blsp2_spi5_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
sdhc2: sdhci@74a4900 {
status = "disabled";
compatible = "qcom,sdhci-msm-v4";
reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
<0 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clock-names = "iface", "core", "xo";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&xo_board>;
bus-width = <4>;
};
msmgpio: pinctrl@1010000 {
compatible = "qcom,msm8996-pinctrl";
reg = <0x01010000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
timer@9840000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x09840000 0x1000>;
clock-frequency = <19200000>;
interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
frame@9850000 {
frame-number = <0>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x09850000 0x1000>,
<0x09860000 0x1000>;
};
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
frame@9870000 {
frame-number = <1>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x09870000 0x1000>;
status = "disabled";
};
linux,pci-domain = <1>;
frame@9880000 {
frame-number = <2>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x09880000 0x1000>;
status = "disabled";
};
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
<&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_AXI_CLK>;
frame@9890000 {
frame-number = <3>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x09890000 0x1000>;
status = "disabled";
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave";
};
frame@98a0000 {
frame-number = <4>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x098a0000 0x1000>;
pcie2: pcie@610000 {
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
power-domains = <&gcc PCIE2_GDSC>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
status = "disabled";
};
reg = <0x00610000 0x2000>,
<0x0e000000 0xf1d>,
<0x0e000f20 0xa8>,
<0x0e100000 0x100000>;
frame@98b0000 {
frame-number = <5>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x098b0000 0x1000>;
status = "disabled";
};
reg-names = "parf", "dbi", "elbi","config";
frame@98c0000 {
frame-number = <6>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x098c0000 0x1000>;
status = "disabled";
};
};
phys = <&pciephy_2>;
phy-names = "pciephy";
spmi_bus: qcom,spmi@400f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x400f000 0x1000>,
<0x4400000 0x800000>,
<0x4c00000 0x800000>,
<0x5800000 0x200000>,
<0x400a000 0x002100>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
};
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
<0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
ufsphy: phy@627000 {
compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
reg = <0x627000 0xda8>;
reg-names = "phy_mem";
#phy-cells = <0>;
device_type = "pci";
vdda-phy-supply = <&pm8994_l28>;
vdda-pll-supply = <&pm8994_l12>;
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
vdda-phy-max-microamp = <18380>;
vdda-pll-max-microamp = <9440>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
vddp-ref-clk-supply = <&pm8994_l25>;
vddp-ref-clk-max-microamp = <100>;
vddp-ref-clk-always-on;
linux,pci-domain = <2>;
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
<&gcc GCC_PCIE_2_AUX_CLK>,
<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_2_SLV_AXI_CLK>;
clock-names = "ref_clk_src", "ref_clk";
clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
<&gcc GCC_UFS_CLKREF_CLK>;
resets = <&ufshc 0>;
status = "disabled";
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave";
};
};
ufshc: ufshc@624000 {
compatible = "qcom,ufshc";
reg = <0x624000 0x2500>;
reg = <0x00624000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy>;
phy-names = "ufsphy";
vcc-supply = <&pm8994_l20>;
vccq-supply = <&pm8994_l25>;
vccq2-supply = <&pm8994_s4>;
vcc-max-microamp = <600000>;
vccq-max-microamp = <450000>;
vccq2-max-microamp = <450000>;
power-domains = <&gcc UFS_GDSC>;
clock-names =
......@@ -1407,266 +933,35 @@ ufs_variant {
};
};
mmcc: clock-controller@8c0000 {
compatible = "qcom,mmcc-msm8996";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x8c0000 0x40000>;
assigned-clocks = <&mmcc MMPLL9_PLL>,
<&mmcc MMPLL1_PLL>,
<&mmcc MMPLL3_PLL>,
<&mmcc MMPLL4_PLL>,
<&mmcc MMPLL5_PLL>;
assigned-clock-rates = <624000000>,
<810000000>,
<980000000>,
<960000000>,
<825000000>;
};
qfprom@74000 {
compatible = "qcom,qfprom";
reg = <0x74000 0x8ff>;
#address-cells = <1>;
#size-cells = <1>;
qusb2p_hstx_trim: hstx_trim@24e {
reg = <0x24e 0x2>;
bits = <5 4>;
};
qusb2s_hstx_trim: hstx_trim@24f {
reg = <0x24f 0x1>;
bits = <1 4>;
};
ufsphy: phy@627000 {
compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
reg = <0x00627000 0xda8>;
reg-names = "phy_mem";
#phy-cells = <0>;
gpu_speed_bin: gpu_speed_bin@133 {
reg = <0x133 0x1>;
bits = <5 3>;
};
};
phy@34000 {
compatible = "qcom,msm8996-qmp-pcie-phy";
reg = <0x34000 0x488>;
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
<&gcc GCC_PCIE_CLKREF_CLK>;
clock-names = "aux", "cfg_ahb", "ref";
vdda-phy-supply = <&pm8994_l28>;
vdda-pll-supply = <&pm8994_l12>;
resets = <&gcc GCC_PCIE_PHY_BCR>,
<&gcc GCC_PCIE_PHY_COM_BCR>,
<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
reset-names = "phy", "common", "cfg";
status = "disabled";
pciephy_0: lane@35000 {
reg = <0x035000 0x130>,
<0x035200 0x200>,
<0x035400 0x1dc>;
#phy-cells = <0>;
clock-output-names = "pcie_0_pipe_clk_src";
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "lane0";
};
pciephy_1: lane@36000 {
reg = <0x036000 0x130>,
<0x036200 0x200>,
<0x036400 0x1dc>;
#phy-cells = <0>;
clock-output-names = "pcie_1_pipe_clk_src";
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "pipe1";
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "lane1";
};
pciephy_2: lane@37000 {
reg = <0x037000 0x130>,
<0x037200 0x200>,
<0x037400 0x1dc>;
#phy-cells = <0>;
clock-output-names = "pcie_2_pipe_clk_src";
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
clock-names = "pipe2";
resets = <&gcc GCC_PCIE_2_PHY_BCR>;
reset-names = "lane2";
};
};
phy@7410000 {
compatible = "qcom,msm8996-qmp-usb3-phy";
reg = <0x7410000 0x1c4>;
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_CLKREF_CLK>;
clock-names = "aux", "cfg_ahb", "ref";
vdda-phy-supply = <&pm8994_l28>;
vdda-pll-supply = <&pm8994_l12>;
resets = <&gcc GCC_USB3_PHY_BCR>,
<&gcc GCC_USB3PHY_PHY_BCR>;
reset-names = "phy", "common";
status = "disabled";
ssusb_phy_0: lane@7410200 {
reg = <0x7410200 0x200>,
<0x7410400 0x130>,
<0x7410600 0x1a8>;
#phy-cells = <0>;
clock-output-names = "usb3_phy_pipe_clk_src";
clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
clock-names = "pipe0";
};
};
hsusb_phy1: phy@7411000 {
compatible = "qcom,msm8996-qusb2-phy";
reg = <0x7411000 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_RX1_USB2_CLKREF_CLK>;
clock-names = "cfg_ahb", "ref";
vdda-pll-supply = <&pm8994_l12>;
vdda-phy-dpdm-supply = <&pm8994_l24>;
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
nvmem-cells = <&qusb2p_hstx_trim>;
status = "disabled";
};
hsusb_phy2: phy@7412000 {
compatible = "qcom,msm8996-qusb2-phy";
reg = <0x7412000 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_RX2_USB2_CLKREF_CLK>;
clock-names = "cfg_ahb", "ref";
vdda-pll-supply = <&pm8994_l12>;
vdda-phy-dpdm-supply = <&pm8994_l24>;
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
nvmem-cells = <&qusb2s_hstx_trim>;
status = "disabled";
};
usb2: usb@76f8800 {
compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
reg = <0x76f8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
<&gcc GCC_USB20_MASTER_CLK>,
<&gcc GCC_USB20_MOCK_UTMI_CLK>,
<&gcc GCC_USB20_SLEEP_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
<&gcc GCC_USB20_MASTER_CLK>;
assigned-clock-rates = <19200000>, <60000000>;
power-domains = <&gcc USB30_GDSC>;
status = "disabled";
dwc3@7600000 {
compatible = "snps,dwc3";
reg = <0x7600000 0xcc00>;
interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hsusb_phy2>;
phy-names = "usb2-phy";
};
};
usb3: usb@6af8800 {
compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
reg = <0x6af8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>,
<&gcc GCC_AGGRE2_USB3_AXI_CLK>,
<&gcc GCC_USB30_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SLEEP_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <120000000>;
power-domains = <&gcc USB30_GDSC>;
status = "disabled";
dwc3@6a00000 {
compatible = "snps,dwc3";
reg = <0x6a00000 0xcc00>;
interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hsusb_phy1>, <&ssusb_phy_0>;
phy-names = "usb2-phy", "usb3-phy";
};
};
vfe_smmu: iommu@da0000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
reg = <0xda0000 0x10000>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
clocks = <&mmcc SMMU_VFE_AHB_CLK>,
<&mmcc SMMU_VFE_AXI_CLK>;
clock-names = "iface",
"bus";
#iommu-cells = <1>;
clock-names = "ref_clk_src", "ref_clk";
clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
<&gcc GCC_UFS_CLKREF_CLK>;
resets = <&ufshc 0>;
status = "disabled";
};
camss: camss@a00000 {
compatible = "qcom,msm8996-camss";
reg = <0xa34000 0x1000>,
<0xa00030 0x4>,
<0xa35000 0x1000>,
<0xa00038 0x4>,
<0xa36000 0x1000>,
<0xa00040 0x4>,
<0xa30000 0x100>,
<0xa30400 0x100>,
<0xa30800 0x100>,
<0xa30c00 0x100>,
<0xa31000 0x500>,
<0xa00020 0x10>,
<0xa10000 0x1000>,
<0xa14000 0x1000>;
reg = <0x00a34000 0x1000>,
<0x00a00030 0x4>,
<0x00a35000 0x1000>,
<0x00a00038 0x4>,
<0x00a36000 0x1000>,
<0x00a00040 0x4>,
<0x00a30000 0x100>,
<0x00a30400 0x100>,
<0x00a30800 0x100>,
<0x00a30c00 0x100>,
<0x00a31000 0x500>,
<0x00a00020 0x10>,
<0x00a10000 0x1000>,
<0x00a14000 0x1000>;
reg-names = "csiphy0",
"csiphy0_clk_mux",
"csiphy1",
......@@ -1774,7 +1069,6 @@ camss: camss@a00000 {
"vfe1_stream",
"vfe_ahb",
"vfe_axi";
vdda-supply = <&pm8994_l2>;
iommus = <&vfe_smmu 0>,
<&vfe_smmu 1>,
<&vfe_smmu 2>,
......@@ -1788,7 +1082,7 @@ ports {
adreno_smmu: iommu@b40000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
reg = <0xb40000 0x10000>;
reg = <0x00b40000 0x10000>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
......@@ -1803,9 +1097,57 @@ adreno_smmu: iommu@b40000 {
power-domains = <&mmcc GPU_GDSC>;
};
video-codec@c00000 {
compatible = "qcom,msm8996-venus";
reg = <0x00c00000 0xff000>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc VENUS_GDSC>;
clocks = <&mmcc VIDEO_CORE_CLK>,
<&mmcc VIDEO_AHB_CLK>,
<&mmcc VIDEO_AXI_CLK>,
<&mmcc VIDEO_MAXI_CLK>;
clock-names = "core", "iface", "bus", "mbus";
iommus = <&venus_smmu 0x00>,
<&venus_smmu 0x01>,
<&venus_smmu 0x0a>,
<&venus_smmu 0x07>,
<&venus_smmu 0x0e>,
<&venus_smmu 0x0f>,
<&venus_smmu 0x08>,
<&venus_smmu 0x09>,
<&venus_smmu 0x0b>,
<&venus_smmu 0x0c>,
<&venus_smmu 0x0d>,
<&venus_smmu 0x10>,
<&venus_smmu 0x11>,
<&venus_smmu 0x21>,
<&venus_smmu 0x28>,
<&venus_smmu 0x29>,
<&venus_smmu 0x2b>,
<&venus_smmu 0x2c>,
<&venus_smmu 0x2d>,
<&venus_smmu 0x31>;
memory-region = <&venus_region>;
status = "okay";
video-decoder {
compatible = "venus-decoder";
clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
clock-names = "core";
power-domains = <&mmcc VENUS_CORE0_GDSC>;
};
video-encoder {
compatible = "venus-encoder";
clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
clock-names = "core";
power-domains = <&mmcc VENUS_CORE1_GDSC>;
};
};
mdp_smmu: iommu@d00000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
reg = <0xd00000 0x10000>;
reg = <0x00d00000 0x10000>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
......@@ -1819,9 +1161,45 @@ mdp_smmu: iommu@d00000 {
power-domains = <&mmcc MDSS_GDSC>;
};
venus_smmu: iommu@d40000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
reg = <0x00d40000 0x20000>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
<&mmcc SMMU_VIDEO_AXI_CLK>;
clock-names = "iface", "bus";
#iommu-cells = <1>;
status = "okay";
};
vfe_smmu: iommu@da0000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
reg = <0x00da0000 0x10000>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
clocks = <&mmcc SMMU_VFE_AHB_CLK>,
<&mmcc SMMU_VFE_AXI_CLK>;
clock-names = "iface",
"bus";
#iommu-cells = <1>;
};
lpass_q6_smmu: iommu@1600000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
reg = <0x1600000 0x20000>;
reg = <0x01600000 0x20000>;
#iommu-cells = <1>;
power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
......@@ -1845,648 +1223,1182 @@ lpass_q6_smmu: iommu@1600000 {
clock-names = "iface", "bus";
};
agnoc@0 {
power-domains = <&gcc AGGRE0_NOC_GDSC>;
compatible = "simple-pm-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
stm@3002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x3002000 0x1000>,
<0x8280000 0x180000>;
reg-names = "stm-base", "stm-stimulus-base";
pcie0: pcie@600000 {
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
status = "disabled";
power-domains = <&gcc PCIE0_GDSC>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
out-ports {
port {
stm_out: endpoint {
remote-endpoint =
<&funnel0_in>;
};
};
};
};
tpiu@3020000 {
compatible = "arm,coresight-tpiu", "arm,primecell";
reg = <0x3020000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
port {
tpiu_in: endpoint {
remote-endpoint =
<&replicator_out1>;
};
};
};
};
funnel@3021000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3021000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@7 {
reg = <7>;
funnel0_in: endpoint {
remote-endpoint =
<&stm_out>;
};
};
};
out-ports {
port {
funnel0_out: endpoint {
remote-endpoint =
<&merge_funnel_in0>;
};
};
};
};
funnel@3022000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3022000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@6 {
reg = <6>;
funnel1_in: endpoint {
remote-endpoint =
<&apss_merge_funnel_out>;
};
};
};
out-ports {
port {
funnel1_out: endpoint {
remote-endpoint =
<&merge_funnel_in1>;
};
};
};
};
funnel@3023000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3023000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
out-ports {
port {
funnel2_out: endpoint {
remote-endpoint =
<&merge_funnel_in2>;
};
};
};
};
funnel@3025000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3025000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
merge_funnel_in0: endpoint {
remote-endpoint =
<&funnel0_out>;
};
};
port@1 {
reg = <1>;
merge_funnel_in1: endpoint {
remote-endpoint =
<&funnel1_out>;
};
};
port@2 {
reg = <2>;
merge_funnel_in2: endpoint {
remote-endpoint =
<&funnel2_out>;
};
};
};
out-ports {
port {
merge_funnel_out: endpoint {
remote-endpoint =
<&etf_in>;
};
};
};
};
replicator@3026000 {
compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
reg = <0x3026000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
port {
replicator_in: endpoint {
remote-endpoint =
<&etf_out>;
};
};
};
out-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
replicator_out0: endpoint {
remote-endpoint =
<&etr_in>;
};
};
port@1 {
reg = <1>;
replicator_out1: endpoint {
remote-endpoint =
<&tpiu_in>;
};
};
};
};
etf@3027000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x3027000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
port {
etf_in: endpoint {
remote-endpoint =
<&merge_funnel_out>;
};
};
};
out-ports {
port {
etf_out: endpoint {
remote-endpoint =
<&replicator_in>;
};
};
};
};
etr@3028000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x3028000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
arm,scatter-gather;
in-ports {
port {
etr_in: endpoint {
remote-endpoint =
<&replicator_out0>;
};
};
};
};
debug@3810000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x3810000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU0>;
};
etm@3840000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x3840000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU0>;
out-ports {
port {
etm0_out: endpoint {
remote-endpoint =
<&apss_funnel0_in0>;
};
};
};
};
debug@3910000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x3910000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU1>;
};
etm@3940000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x3940000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU1>;
out-ports {
port {
etm1_out: endpoint {
remote-endpoint =
<&apss_funnel0_in1>;
};
};
};
};
funnel@39b0000 { /* APSS Funnel 0 */
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x39b0000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
apss_funnel0_in0: endpoint {
remote-endpoint = <&etm0_out>;
};
};
port@1 {
reg = <1>;
apss_funnel0_in1: endpoint {
remote-endpoint = <&etm1_out>;
};
};
};
out-ports {
port {
apss_funnel0_out: endpoint {
remote-endpoint =
<&apss_merge_funnel_in0>;
};
};
};
};
debug@3a10000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x3a10000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
reg = <0x00600000 0x2000>,
<0x0c000000 0xf1d>,
<0x0c000f20 0xa8>,
<0x0c100000 0x100000>;
reg-names = "parf", "dbi", "elbi","config";
cpu = <&CPU2>;
};
phys = <&pciephy_0>;
phy-names = "pciephy";
etm@3a40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x3a40000 0x1000>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
cpu = <&CPU2>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
out-ports {
port {
etm2_out: endpoint {
remote-endpoint =
<&apss_funnel1_in0>;
};
};
};
};
debug@3b10000 {
compatible = "arm,coresight-cpu-debug", "arm,primecell";
reg = <0x3b10000 0x1000>;
vdda-supply = <&pm8994_l28>;
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
linux,pci-domain = <0>;
cpu = <&CPU3>;
};
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>;
etm@3b40000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x3b40000 0x1000>;
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave";
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
};
cpu = <&CPU3>;
pcie1: pcie@608000 {
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
power-domains = <&gcc PCIE1_GDSC>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
out-ports {
port {
etm3_out: endpoint {
remote-endpoint =
<&apss_funnel1_in1>;
};
};
};
};
status = "disabled";
funnel@3bb0000 { /* APSS Funnel 1 */
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3bb0000 0x1000>;
reg = <0x00608000 0x2000>,
<0x0d000000 0xf1d>,
<0x0d000f20 0xa8>,
<0x0d100000 0x100000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
reg-names = "parf", "dbi", "elbi","config";
in-ports {
#address-cells = <1>;
#size-cells = <0>;
phys = <&pciephy_1>;
phy-names = "pciephy";
port@0 {
reg = <0>;
apss_funnel1_in0: endpoint {
remote-endpoint = <&etm2_out>;
};
};
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
port@1 {
reg = <1>;
apss_funnel1_in1: endpoint {
remote-endpoint = <&etm3_out>;
};
};
};
interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
out-ports {
port {
apss_funnel1_out: endpoint {
remote-endpoint =
<&apss_merge_funnel_in1>;
};
};
};
};
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
funnel@3bc0000 {
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x3bc0000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
vdda-supply = <&pm8994_l28>;
linux,pci-domain = <1>;
in-ports {
#address-cells = <1>;
#size-cells = <0>;
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
<&gcc GCC_PCIE_1_AUX_CLK>,
<&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_1_SLV_AXI_CLK>;
port@0 {
reg = <0>;
apss_merge_funnel_in0: endpoint {
remote-endpoint =
<&apss_funnel0_out>;
};
};
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave";
port@1 {
reg = <1>;
apss_merge_funnel_in1: endpoint {
remote-endpoint =
<&apss_funnel1_out>;
};
};
};
pcie2: pcie@610000 {
compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
power-domains = <&gcc PCIE2_GDSC>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
status = "disabled";
reg = <0x00610000 0x2000>,
<0x0e000000 0xf1d>,
<0x0e000f20 0xa8>,
<0x0e100000 0x100000>;
out-ports {
port {
apss_merge_funnel_out: endpoint {
remote-endpoint =
<&funnel1_in>;
};
};
};
};
kryocc: clock-controller@6400000 {
compatible = "qcom,apcc-msm8996";
reg = <0x06400000 0x90000>;
#clock-cells = <1>;
};
reg-names = "parf", "dbi", "elbi","config";
usb3: usb@6af8800 {
compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
reg = <0x06af8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
phys = <&pciephy_2>;
phy-names = "pciephy";
clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>,
<&gcc GCC_AGGRE2_USB3_AXI_CLK>,
<&gcc GCC_USB30_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SLEEP_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
<0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>;
assigned-clock-rates = <19200000>, <120000000>;
device_type = "pci";
power-domains = <&gcc USB30_GDSC>;
status = "disabled";
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
dwc3@6a00000 {
compatible = "snps,dwc3";
reg = <0x06a00000 0xcc00>;
interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hsusb_phy1>, <&ssusb_phy_0>;
phy-names = "usb2-phy", "usb3-phy";
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
};
};
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
usb3phy: phy@7410000 {
compatible = "qcom,msm8996-qmp-usb3-phy";
reg = <0x07410000 0x1c4>;
#clock-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
vdda-supply = <&pm8994_l28>;
clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_CLKREF_CLK>;
clock-names = "aux", "cfg_ahb", "ref";
linux,pci-domain = <2>;
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
<&gcc GCC_PCIE_2_AUX_CLK>,
<&gcc GCC_PCIE_2_CFG_AHB_CLK>,
<&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_2_SLV_AXI_CLK>;
resets = <&gcc GCC_USB3_PHY_BCR>,
<&gcc GCC_USB3PHY_PHY_BCR>;
reset-names = "phy", "common";
status = "disabled";
clock-names = "pipe",
"aux",
"cfg",
"bus_master",
"bus_slave";
ssusb_phy_0: lane@7410200 {
reg = <0x07410200 0x200>,
<0x07410400 0x130>,
<0x07410600 0x1a8>;
#phy-cells = <0>;
clock-output-names = "usb3_phy_pipe_clk_src";
clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
clock-names = "pipe0";
};
};
slimbam:dma@9184000
{
compatible = "qcom,bam-v1.7.0";
qcom,controlled-remotely;
reg = <0x9184000 0x32000>;
num-channels = <31>;
interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
qcom,ee = <1>;
qcom,num-ees = <2>;
hsusb_phy1: phy@7411000 {
compatible = "qcom,msm8996-qusb2-phy";
reg = <0x07411000 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_RX1_USB2_CLKREF_CLK>;
clock-names = "cfg_ahb", "ref";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
nvmem-cells = <&qusb2p_hstx_trim>;
status = "disabled";
};
slim_msm: slim@91c0000 {
compatible = "qcom,slim-ngd-v1.5.0";
reg = <0x91c0000 0x2C000>;
reg-names = "ctrl";
interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&slimbam 3>, <&slimbam 4>,
<&slimbam 5>, <&slimbam 6>;
dma-names = "rx", "tx", "tx2", "rx2";
#address-cells = <1>;
#size-cells = <0>;
ngd@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <1>;
hsusb_phy2: phy@7412000 {
compatible = "qcom,msm8996-qusb2-phy";
reg = <0x07412000 0x180>;
#phy-cells = <0>;
tasha_ifd: tas-ifd {
compatible = "slim217,1a0";
reg = <0 0>;
};
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_RX2_USB2_CLKREF_CLK>;
clock-names = "cfg_ahb", "ref";
wcd9335: codec@1{
pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
pinctrl-names = "default";
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
nvmem-cells = <&qusb2s_hstx_trim>;
status = "disabled";
};
compatible = "slim217,1a0";
reg = <1 0>;
sdhc2: sdhci@74a4900 {
status = "disabled";
compatible = "qcom,sdhci-msm-v4";
reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupt-parent = <&msmgpio>;
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
<53 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr1", "intr2";
interrupt-controller;
#interrupt-cells = <1>;
reset-gpios = <&msmgpio 64 0>;
interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
<0 221 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
slim-ifc-dev = <&tasha_ifd>;
clock-names = "iface", "core", "xo";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&xo_board>;
bus-width = <4>;
};
vdd-buck-supply = <&pm8994_s4>;
vdd-buck-sido-supply = <&pm8994_s4>;
vdd-tx-supply = <&pm8994_s4>;
vdd-rx-supply = <&pm8994_s4>;
vdd-io-supply = <&pm8994_s4>;
blsp1_uart1: serial@7570000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x07570000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
#sound-dai-cells = <1>;
};
};
blsp1_spi0: spi@7575000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07575000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_spi0_default>;
pinctrl-1 = <&blsp1_spi0_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
gpu@b00000 {
compatible = "qcom,adreno-530.2", "qcom,adreno";
#stream-id-cells = <16>;
blsp1_i2c2: i2c@7577000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07577000 0x1000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c2_default>;
pinctrl-1 = <&blsp1_i2c2_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
reg = <0xb00000 0x3f000>;
reg-names = "kgsl_3d0_reg_memory";
blsp2_uart1: serial@75b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x075b0000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
blsp2_uart2: serial@75b1000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x075b1000 0x1000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
clocks = <&mmcc GPU_GX_GFX3D_CLK>,
<&mmcc GPU_AHB_CLK>,
<&mmcc GPU_GX_RBBMTIMER_CLK>,
<&gcc GCC_BIMC_GFX_CLK>,
<&gcc GCC_MMSS_BIMC_GFX_CLK>;
blsp2_i2c0: i2c@75b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b5000 0x1000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c0_default>;
pinctrl-1 = <&blsp2_i2c0_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
clock-names = "core",
"iface",
"rbbmtimer",
"mem",
"mem_iface";
blsp2_i2c1: i2c@75b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b6000 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_AHB_CLK>,
<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c1_default>;
pinctrl-1 = <&blsp2_i2c1_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
power-domains = <&mmcc GPU_GDSC>;
iommus = <&adreno_smmu 0>;
blsp2_spi5: spi@75ba000{
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x075ba000 0x600>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_spi5_default>;
pinctrl-1 = <&blsp2_spi5_sleep>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
nvmem-cells = <&gpu_speed_bin>;
nvmem-cell-names = "speed_bin";
usb2: usb@76f8800 {
compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
reg = <0x076f8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
qcom,gpu-quirk-two-pass-use-wfi;
qcom,gpu-quirk-fault-detect-mask;
clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
<&gcc GCC_USB20_MASTER_CLK>,
<&gcc GCC_USB20_MOCK_UTMI_CLK>,
<&gcc GCC_USB20_SLEEP_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
operating-points-v2 = <&gpu_opp_table>;
assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
<&gcc GCC_USB20_MASTER_CLK>;
assigned-clock-rates = <19200000>, <60000000>;
gpu_opp_table: opp-table {
compatible ="operating-points-v2";
power-domains = <&gcc USB30_GDSC>;
status = "disabled";
/*
* 624Mhz and 560Mhz are only available on speed
* bin (1 << 0). All the rest are available on
* all bins of the hardware
*/
opp-624000000 {
opp-hz = /bits/ 64 <624000000>;
opp-supported-hw = <0x01>;
};
opp-560000000 {
opp-hz = /bits/ 64 <560000000>;
opp-supported-hw = <0x01>;
};
opp-510000000 {
opp-hz = /bits/ 64 <510000000>;
opp-supported-hw = <0xFF>;
};
opp-401800000 {
opp-hz = /bits/ 64 <401800000>;
opp-supported-hw = <0xFF>;
};
opp-315000000 {
opp-hz = /bits/ 64 <315000000>;
opp-supported-hw = <0xFF>;
};
opp-214000000 {
opp-hz = /bits/ 64 <214000000>;
opp-supported-hw = <0xFF>;
};
opp-133000000 {
opp-hz = /bits/ 64 <133000000>;
opp-supported-hw = <0xFF>;
dwc3@7600000 {
compatible = "snps,dwc3";
reg = <0x07600000 0xcc00>;
interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hsusb_phy2>;
phy-names = "usb2-phy";
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
};
};
slimbam: dma@9184000 {
compatible = "qcom,bam-v1.7.0";
qcom,controlled-remotely;
reg = <0x09184000 0x32000>;
num-channels = <31>;
interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
qcom,ee = <1>;
qcom,num-ees = <2>;
};
slim_msm: slim@91c0000 {
compatible = "qcom,slim-ngd-v1.5.0";
reg = <0x091c0000 0x2C000>;
reg-names = "ctrl";
interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&slimbam 3>, <&slimbam 4>,
<&slimbam 5>, <&slimbam 6>;
dma-names = "rx", "tx", "tx2", "rx2";
#address-cells = <1>;
#size-cells = <0>;
ngd@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <1>;
tasha_ifd: tas-ifd {
compatible = "slim217,1a0";
reg = <0 0>;
};
};
zap-shader {
memory-region = <&zap_shader_region>;
};
};
wcd9335: codec@1{
pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
pinctrl-names = "default";
mdss: mdss@900000 {
compatible = "qcom,mdss";
compatible = "slim217,1a0";
reg = <1 0>;
reg = <0x900000 0x1000>,
<0x9b0000 0x1040>,
<0x9b8000 0x1040>;
reg-names = "mdss_phys",
"vbif_phys",
"vbif_nrt_phys";
interrupt-parent = <&msmgpio>;
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
<53 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr1", "intr2";
interrupt-controller;
#interrupt-cells = <1>;
reset-gpios = <&msmgpio 64 0>;
power-domains = <&mmcc MDSS_GDSC>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
slim-ifc-dev = <&tasha_ifd>;
interrupt-controller;
#interrupt-cells = <1>;
#sound-dai-cells = <1>;
};
};
};
clocks = <&mmcc MDSS_AHB_CLK>;
clock-names = "iface";
adsp_pil: remoteproc@9300000 {
compatible = "qcom,msm8996-adsp-pil";
reg = <0x09300000 0x80000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
mdp: mdp@901000 {
compatible = "qcom,mdp5";
reg = <0x901000 0x90000>;
reg-names = "mdp_phys";
clocks = <&xo_board>;
clock-names = "xo";
interrupt-parent = <&mdss>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&adsp_region>;
clocks = <&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_AXI_CLK>,
<&mmcc MDSS_MDP_CLK>,
<&mmcc SMMU_MDP_AXI_CLK>,
<&mmcc MDSS_VSYNC_CLK>;
clock-names = "iface",
"bus",
"core",
"iommu",
"vsync";
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
iommus = <&mdp_smmu 0>;
smd-edge {
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
ports {
label = "lpass";
mboxes = <&apcs_glb 8>;
qcom,smd-edge = <1>;
qcom,remote-pid = <2>;
#address-cells = <1>;
#size-cells = <0>;
apr {
power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
compatible = "qcom,apr-v2";
qcom,smd-channels = "apr_audio_svc";
qcom,apr-domain = <APR_DOMAIN_ADSP>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdp5_intf3_out: endpoint {
remote-endpoint = <&hdmi_in>;
q6core {
reg = <APR_SVC_ADSP_CORE>;
compatible = "qcom,q6core";
};
q6afe: q6afe {
compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>;
q6afedai: dais {
compatible = "qcom,q6afe-dais";
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
hdmi@1 {
reg = <1>;
};
};
};
};
};
hdmi: hdmi-tx@9a0000 {
compatible = "qcom,hdmi-tx-8996";
reg = <0x009a0000 0x50c>,
<0x00070000 0x6158>,
<0x009e0000 0xfff>;
reg-names = "core_physical",
"qfprom_physical",
"hdcp_physical";
q6asm: q6asm {
compatible = "qcom,q6asm";
reg = <APR_SVC_ASM>;
q6asmdai: dais {
compatible = "qcom,q6asm-dais";
#sound-dai-cells = <1>;
iommus = <&lpass_q6_smmu 1>;
};
};
interrupt-parent = <&mdss>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
q6adm: q6adm {
compatible = "qcom,q6adm";
reg = <APR_SVC_ADM>;
q6routing: routing {
compatible = "qcom,q6adm-routing";
#sound-dai-cells = <0>;
};
};
};
clocks = <&mmcc MDSS_MDP_CLK>,
<&mmcc MDSS_AHB_CLK>,
<&mmcc MDSS_HDMI_CLK>,
<&mmcc MDSS_HDMI_AHB_CLK>,
<&mmcc MDSS_EXTPCLK_CLK>;
clock-names =
"mdp_core",
"iface",
"core",
"alt_iface",
"extp";
};
};
phys = <&hdmi_phy>;
phy-names = "hdmi_phy";
#sound-dai-cells = <1>;
apcs_glb: mailbox@9820000 {
compatible = "qcom,msm8996-apcs-hmss-global";
reg = <0x09820000 0x1000>;
ports {
#address-cells = <1>;
#size-cells = <0>;
#mbox-cells = <1>;
};
port@0 {
reg = <0>;
hdmi_in: endpoint {
remote-endpoint = <&mdp5_intf3_out>;
};
};
};
timer@9840000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x09840000 0x1000>;
clock-frequency = <19200000>;
frame@9850000 {
frame-number = <0>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x09850000 0x1000>,
<0x09860000 0x1000>;
};
hdmi_phy: hdmi-phy@9a0600 {
#phy-cells = <0>;
compatible = "qcom,hdmi-phy-8996";
reg = <0x9a0600 0x1c4>,
<0x9a0a00 0x124>,
<0x9a0c00 0x124>,
<0x9a0e00 0x124>,
<0x9a1000 0x124>,
<0x9a1200 0x0c8>;
reg-names = "hdmi_pll",
"hdmi_tx_l0",
"hdmi_tx_l1",
"hdmi_tx_l2",
"hdmi_tx_l3",
"hdmi_phy";
frame@9870000 {
frame-number = <1>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x09870000 0x1000>;
status = "disabled";
};
clocks = <&mmcc MDSS_AHB_CLK>,
<&gcc GCC_HDMI_CLKREF_CLK>;
clock-names = "iface",
"ref";
frame@9880000 {
frame-number = <2>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x09880000 0x1000>;
status = "disabled";
};
};
venus_smmu: arm,smmu-venus@d40000 {
compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
reg = <0xd40000 0x20000>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
<&mmcc SMMU_VIDEO_AXI_CLK>;
clock-names = "iface", "bus";
#iommu-cells = <1>;
status = "okay";
};
frame@9890000 {
frame-number = <3>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x09890000 0x1000>;
status = "disabled";
};
video-codec@c00000 {
compatible = "qcom,msm8996-venus";
reg = <0x00c00000 0xff000>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&mmcc VENUS_GDSC>;
clocks = <&mmcc VIDEO_CORE_CLK>,
<&mmcc VIDEO_AHB_CLK>,
<&mmcc VIDEO_AXI_CLK>,
<&mmcc VIDEO_MAXI_CLK>;
clock-names = "core", "iface", "bus", "mbus";
iommus = <&venus_smmu 0x00>,
<&venus_smmu 0x01>,
<&venus_smmu 0x0a>,
<&venus_smmu 0x07>,
<&venus_smmu 0x0e>,
<&venus_smmu 0x0f>,
<&venus_smmu 0x08>,
<&venus_smmu 0x09>,
<&venus_smmu 0x0b>,
<&venus_smmu 0x0c>,
<&venus_smmu 0x0d>,
<&venus_smmu 0x10>,
<&venus_smmu 0x11>,
<&venus_smmu 0x21>,
<&venus_smmu 0x28>,
<&venus_smmu 0x29>,
<&venus_smmu 0x2b>,
<&venus_smmu 0x2c>,
<&venus_smmu 0x2d>,
<&venus_smmu 0x31>;
memory-region = <&venus_region>;
status = "okay";
frame@98a0000 {
frame-number = <4>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x098a0000 0x1000>;
status = "disabled";
};
video-decoder {
compatible = "venus-decoder";
clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
clock-names = "core";
power-domains = <&mmcc VENUS_CORE0_GDSC>;
frame@98b0000 {
frame-number = <5>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x098b0000 0x1000>;
status = "disabled";
};
video-encoder {
compatible = "venus-encoder";
clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
clock-names = "core";
power-domains = <&mmcc VENUS_CORE1_GDSC>;
frame@98c0000 {
frame-number = <6>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x098c0000 0x1000>;
status = "disabled";
};
};
saw3: syscon@9a10000 {
compatible = "syscon";
reg = <0x09a10000 0x1000>;
};
intc: interrupt-controller@9bc0000 {
compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x40000>;
reg = <0x09bc0000 0x10000>,
<0x09c00000 0x100000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
};
sound: sound {
};
adsp-pil {
compatible = "qcom,msm8996-adsp-pil";
thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
thermal-sensors = <&tsens0 3>;
clocks = <&xo_board>;
clock-names = "xo";
trips {
cpu0_alert0: trip-point@0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
memory-region = <&adsp_region>;
cpu0_crit: cpu_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
cpu1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
smd-edge {
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
thermal-sensors = <&tsens0 5>;
label = "lpass";
mboxes = <&apcs_glb 8>;
qcom,smd-edge = <1>;
qcom,remote-pid = <2>;
#address-cells = <1>;
#size-cells = <0>;
apr {
power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
compatible = "qcom,apr-v2";
qcom,smd-channels = "apr_audio_svc";
qcom,apr-domain = <APR_DOMAIN_ADSP>;
#address-cells = <1>;
#size-cells = <0>;
trips {
cpu1_alert0: trip-point@0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
q6core {
reg = <APR_SVC_ADSP_CORE>;
compatible = "qcom,q6core";
};
q6afe: q6afe {
compatible = "qcom,q6afe";
reg = <APR_SVC_AFE>;
q6afedai: dais {
compatible = "qcom,q6afe-dais";
#address-cells = <1>;
#size-cells = <0>;
#sound-dai-cells = <1>;
hdmi@1 {
reg = <1>;
};
};
cpu1_crit: cpu_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
q6asm: q6asm {
compatible = "qcom,q6asm";
reg = <APR_SVC_ASM>;
q6asmdai: dais {
compatible = "qcom,q6asm-dais";
#sound-dai-cells = <1>;
iommus = <&lpass_q6_smmu 1>;
};
cpu2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 8>;
trips {
cpu2_alert0: trip-point@0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
q6adm: q6adm {
compatible = "qcom,q6adm";
reg = <APR_SVC_ADM>;
q6routing: routing {
compatible = "qcom,q6adm-routing";
#sound-dai-cells = <0>;
};
cpu2_crit: cpu_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
cpu3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 10>;
trips {
cpu3_alert0: trip-point@0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu3_crit: cpu_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
adsp-smp2p {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
gpu-thermal-top {
polling-delay-passive = <250>;
polling-delay = <1000>;
interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
thermal-sensors = <&tsens1 6>;
mboxes = <&apcs_glb 10>;
trips {
gpu1_alert0: trip-point@0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
gpu-thermal-bottom {
polling-delay-passive = <250>;
polling-delay = <1000>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
thermal-sensors = <&tsens1 7>;
trips {
gpu2_alert0: trip-point@0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
m4m-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
interrupt-controller;
#interrupt-cells = <2>;
thermal-sensors = <&tsens0 1>;
trips {
m4m_alert0: trip-point@0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
};
modem-smp2p {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
l3-or-venus-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
thermal-sensors = <&tsens0 2>;
mboxes = <&apcs_glb 14>;
trips {
l3_or_venus_alert0: trip-point@0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
cluster0-l2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
modem_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
thermal-sensors = <&tsens0 7>;
trips {
cluster0_l2_alert0: trip-point@0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
modem_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
cluster1-l2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
interrupt-controller;
#interrupt-cells = <2>;
thermal-sensors = <&tsens0 12>;
trips {
cluster1_l2_alert0: trip-point@0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
};
smp2p-slpi {
compatible = "qcom,smp2p";
qcom,smem = <481>, <430>;
camera-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
thermal-sensors = <&tsens1 1>;
mboxes = <&apcs_glb 26>;
trips {
camera_alert0: trip-point@0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
qcom,local-pid = <0>;
qcom,remote-pid = <3>;
q6-dsp-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
slpi_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
thermal-sensors = <&tsens1 2>;
trips {
q6_dsp_alert0: trip-point@0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
slpi_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
mem-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 3>;
trips {
mem_alert0: trip-point@0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
modemtx-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 4>;
trips {
modemtx_alert0: trip-point@0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};
#include "msm8996-pins.dtsi"
arch/arm64/boot/dts/qcom/msm8998-clamshell.dtsi
View file @ 2e04d1bd
......@@ -74,6 +74,23 @@ &CPU7 {
cpu-idle-states = <&BIG_CPU_SLEEP_1>;
};
&pm8005_lsid1 {
pm8005-regulators {
compatible = "qcom,pm8005-regulators";
vdd_s1-supply = <&vph_pwr>;
pm8005_s1: s1 { /* VDD_GFX supply */
regulator-min-microvolt = <524000>;
regulator-max-microvolt = <1100000>;
regulator-enable-ramp-delay = <500>;
/* hack until we rig up the gpu consumer */
regulator-always-on;
};
};
};
&qusb2phy {
status = "okay";
......@@ -292,3 +309,35 @@ &usb3phy {
vdda-phy-supply = <&vreg_l1a_0p875>;
vdda-pll-supply = <&vreg_l2a_1p2>;
};
&wifi {
status = "okay";
vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
};
/* PINCTRL - board-specific pinctrl */
&blsp1_uart3_on {
rx {
/delete-property/ bias-disable;
/*
* Configure a pull-up on 45 (RX). This is needed to
* avoid garbage data when the TX pin of the Bluetooth
* module is in tri-state (module powered off or not
* driving the signal yet).
*/
bias-pull-up;
};
cts {
/delete-property/ bias-disable;
/*
* Configure a pull-down on 47 (CTS) to match the pull
* of the Bluetooth module.
*/
bias-pull-down;
};
};
arch/arm64/boot/dts/qcom/msm8998-mtp.dtsi
View file @ 2e04d1bd
......@@ -9,6 +9,7 @@
/ {
aliases {
serial0 = &blsp2_uart1;
serial1 = &blsp1_uart3;
};
chosen {
......@@ -311,6 +312,14 @@ vreg_bob: bob {
};
};
&remoteproc_adsp {
status = "okay";
};
&remoteproc_slpi {
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <0 4>, <81 4>;
};
......@@ -364,3 +373,35 @@ &usb3phy {
vdda-phy-supply = <&vreg_l1a_0p875>;
vdda-pll-supply = <&vreg_l2a_1p2>;
};
&wifi {
status = "okay";
vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
};
/* PINCTRL - board-specific pinctrl */
&blsp1_uart3_on {
rx {
/delete-property/ bias-disable;
/*
* Configure a pull-up on 45 (RX). This is needed to
* avoid garbage data when the TX pin of the Bluetooth
* module is in tri-state (module powered off or not
* driving the signal yet).
*/
bias-pull-up;
};
cts {
/delete-property/ bias-disable;
/*
* Configure a pull-down on 47 (CTS) to match the pull
* of the Bluetooth module.
*/
bias-pull-down;
};
};
arch/arm64/boot/dts/qcom/msm8998-pins.dtsi
View file @ 2e04d1bd
......@@ -77,13 +77,30 @@ config {
};
blsp1_uart3_on: blsp1_uart3_on {
mux {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
tx {
pins = "gpio45";
function = "blsp_uart3_a";
drive-strength = <2>;
bias-disable;
};
config {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
rx {
pins = "gpio46";
function = "blsp_uart3_a";
drive-strength = <2>;
bias-disable;
};
cts {
pins = "gpio47";
function = "blsp_uart3_a";
drive-strength = <2>;
bias-disable;
};
rfr {
pins = "gpio48";
function = "blsp_uart3_a";
drive-strength = <2>;
bias-disable;
};
......
arch/arm64/boot/dts/qcom/msm8998.dtsi
View file @ 2e04d1bd
......@@ -3,6 +3,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8998.h>
#include <dt-bindings/clock/qcom,gpucc-msm8998.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/gpio/gpio.h>
......@@ -28,8 +29,13 @@ reserved-memory {
#size-cells = <2>;
ranges;
memory@85800000 {
reg = <0x0 0x85800000 0x0 0x800000>;
hyp_mem: memory@85800000 {
reg = <0x0 0x85800000 0x0 0x600000>;
no-map;
};
xbl_mem: memory@85e00000 {
reg = <0x0 0x85e00000 0x0 0x100000>;
no-map;
};
......@@ -38,21 +44,69 @@ smem_mem: smem-mem@86000000 {
no-map;
};
memory@86200000 {
tz_mem: memory@86200000 {
reg = <0x0 0x86200000 0x0 0x2d00000>;
no-map;
};
rmtfs {
rmtfs_mem: memory@88f00000 {
compatible = "qcom,rmtfs-mem";
size = <0x0 0x200000>;
alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
reg = <0x0 0x88f00000 0x0 0x200000>;
no-map;
qcom,client-id = <1>;
qcom,vmid = <15>;
};
spss_mem: memory@8ab00000 {
reg = <0x0 0x8ab00000 0x0 0x700000>;
no-map;
};
adsp_mem: memory@8b200000 {
reg = <0x0 0x8b200000 0x0 0x1a00000>;
no-map;
};
mpss_mem: memory@8cc00000 {
reg = <0x0 0x8cc00000 0x0 0x7000000>;
no-map;
};
venus_mem: memory@93c00000 {
reg = <0x0 0x93c00000 0x0 0x500000>;
no-map;
};
mba_mem: memory@94100000 {
reg = <0x0 0x94100000 0x0 0x200000>;
no-map;
};
slpi_mem: memory@94300000 {
reg = <0x0 0x94300000 0x0 0xf00000>;
no-map;
};
ipa_fw_mem: memory@95200000 {
reg = <0x0 0x95200000 0x0 0x10000>;
no-map;
};
ipa_gsi_mem: memory@95210000 {
reg = <0x0 0x95210000 0x0 0x5000>;
no-map;
};
gpu_mem: memory@95600000 {
reg = <0x0 0x95600000 0x0 0x100000>;
no-map;
};
wlan_msa_mem: memory@95700000 {
reg = <0x0 0x95700000 0x0 0x100000>;
no-map;
};
};
clocks {
......@@ -817,8 +871,9 @@ tsens0: thermal@10ab000 {
reg = <0x010ab000 0x1000>, /* TM */
<0x010aa000 0x1000>; /* SROT */
#qcom,sensors = <14>;
interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";
interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
};
......@@ -827,8 +882,9 @@ tsens1: thermal@10ae000 {
reg = <0x010ae000 0x1000>, /* TM */
<0x010ad000 0x1000>; /* SROT */
#qcom,sensors = <8>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
};
......@@ -847,6 +903,25 @@ anoc1_smmu: iommu@1680000 {
<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
};
anoc2_smmu: iommu@16c0000 {
compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
reg = <0x016c0000 0x40000>;
#iommu-cells = <1>;
#global-interrupts = <0>;
interrupts =
<GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 374 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 375 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 377 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 378 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 462 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
};
pcie0: pci@1c00000 {
compatible = "qcom,pcie-msm8996";
reg = <0x01c00000 0x2000>,
......@@ -987,7 +1062,7 @@ ufsphy_lanes: lanes@1da7400 {
tcsr_mutex_regs: syscon@1f40000 {
compatible = "syscon";
reg = <0x01f40000 0x20000>;
reg = <0x01f40000 0x40000>;
};
tlmm: pinctrl@3400000 {
......@@ -1000,6 +1075,110 @@ tlmm: pinctrl@3400000 {
#interrupt-cells = <0x2>;
};
remoteproc_mss: remoteproc@4080000 {
compatible = "qcom,msm8998-mss-pil";
reg = <0x04080000 0x100>, <0x04180000 0x20>;
reg-names = "qdsp6", "rmb";
interrupts-extended =
<&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack",
"shutdown-ack";
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
<&gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
<&gcc GCC_BOOT_ROM_AHB_CLK>,
<&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
<&gcc GCC_MSS_SNOC_AXI_CLK>,
<&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
<&rpmcc RPM_SMD_QDSS_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "bus", "mem", "gpll0_mss",
"snoc_axi", "mnoc_axi", "qdss", "xo";
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
resets = <&gcc GCC_MSS_RESTART>;
reset-names = "mss_restart";
qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
power-domains = <&rpmpd MSM8998_VDDCX>,
<&rpmpd MSM8998_VDDMX>;
power-domain-names = "cx", "mx";
mba {
memory-region = <&mba_mem>;
};
mpss {
memory-region = <&mpss_mem>;
};
glink-edge {
interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
label = "modem";
qcom,remote-pid = <1>;
mboxes = <&apcs_glb 15>;
};
};
gpucc: clock-controller@5065000 {
compatible = "qcom,msm8998-gpucc";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0x05065000 0x9000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GPLL0_OUT_MAIN>;
clock-names = "xo",
"gpll0";
};
remoteproc_slpi: remoteproc@5800000 {
compatible = "qcom,msm8998-slpi-pas";
reg = <0x05800000 0x4040>;
interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
<&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
px-supply = <&vreg_lvs2a_1p8>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&rpmcc RPM_SMD_AGGR2_NOC_CLK>;
clock-names = "xo", "aggre2";
memory-region = <&slpi_mem>;
qcom,smem-states = <&slpi_smp2p_out 0>;
qcom,smem-state-names = "stop";
power-domains = <&rpmpd MSM8998_SSCCX>;
power-domain-names = "ssc_cx";
status = "disabled";
glink-edge {
interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
label = "dsps";
qcom,remote-pid = <3>;
mboxes = <&apcs_glb 27>;
};
};
stm: stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x06002000 0x1000>,
......@@ -1792,6 +1971,39 @@ blsp2_i2c5: i2c@c1ba000 {
#size-cells = <0>;
};
remoteproc_adsp: remoteproc@17300000 {
compatible = "qcom,msm8998-adsp-pas";
reg = <0x17300000 0x4040>;
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "xo";
memory-region = <&adsp_mem>;
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
power-domains = <&rpmpd MSM8998_VDDCX>;
power-domain-names = "cx";
status = "disabled";
glink-edge {
interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
label = "lpass";
qcom,remote-pid = <2>;
mboxes = <&apcs_glb 9>;
};
};
apcs_glb: mailbox@17911000 {
compatible = "qcom,msm8998-apcs-hmss-global";
reg = <0x17911000 0x1000>;
......@@ -1870,6 +2082,32 @@ intc: interrupt-controller@17a00000 {
redistributor-stride = <0x0 0x20000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
wifi: wifi@18800000 {
compatible = "qcom,wcn3990-wifi";
status = "disabled";
reg = <0x18800000 0x800000>;
reg-names = "membase";
memory-region = <&wlan_msa_mem>;
clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>;
clock-names = "cxo_ref_clk_pin";
interrupts =
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&anoc2_smmu 0x1900>,
<&anoc2_smmu 0x1901>;
qcom,snoc-host-cap-8bit-quirk;
};
};
};
......
arch/arm64/boot/dts/qcom/pm6150.dtsi 0 → 100644
View file @ 2e04d1bd
// SPDX-License-Identifier: BSD-3-Clause
// Copyright (c) 2019, The Linux Foundation. All rights reserved.
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/thermal/thermal.h>
&spmi_bus {
pm6150_lsid0: pmic@0 {
compatible = "qcom,pm6150", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm6150_pon: pon@800 {
compatible = "qcom,pm8998-pon";
reg = <0x800>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_POWER>;
};
};
pm6150_temp: temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
io-channels = <&pm6150_adc ADC5_DIE_TEMP>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
pm6150_adc: adc@3100 {
compatible = "qcom,spmi-adc5";
reg = <0x3100>;
interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
adc-chan@6 {
reg = <ADC5_DIE_TEMP>;
label = "die_temp";
};
};
pm6150_gpio: gpios@c000 {
compatible = "qcom,pm6150-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pm6150_gpio 0 0 10>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pm6150_lsid1: pmic@1 {
compatible = "qcom,pm6150", "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
};
};
arch/arm64/boot/dts/qcom/pm6150l.dtsi 0 → 100644
View file @ 2e04d1bd
// SPDX-License-Identifier: BSD-3-Clause
// Copyright (c) 2019, The Linux Foundation. All rights reserved.
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pm6150l_lsid4: pmic@4 {
compatible = "qcom,pm6150l", "qcom,spmi-pmic";
reg = <0x4 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm6150l_gpio: gpios@c000 {
compatible = "qcom,pm6150l-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
gpio-ranges = <&pm6150l_gpio 0 0 12>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pm6150l_lsid5: pmic@5 {
compatible = "qcom,pm6150l", "qcom,spmi-pmic";
reg = <0x5 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
};
};
arch/arm64/boot/dts/qcom/pm8004.dtsi
View file @ 2e04d1bd
......@@ -4,17 +4,23 @@
&spmi_bus {
pmic@4 {
pm8004_lsid4: pmic@4 {
compatible = "qcom,pm8004", "qcom,spmi-pmic";
reg = <0x4 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
pmic@5 {
pm8004_lsid5: pmic@5 {
compatible = "qcom,pm8004", "qcom,spmi-pmic";
reg = <0x5 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
pm8004_spmi_regulators: regulators {
compatible = "qcom,pm8004-regulators";
};
};
};
arch/arm64/boot/dts/qcom/pm8916.dtsi
View file @ 2e04d1bd
......@@ -111,6 +111,12 @@ pm8916_1: pm8916@1 {
#address-cells = <1>;
#size-cells = <0>;
pm8916_vib: vibrator@c000 {
compatible = "qcom,pm8916-vib";
reg = <0xc000>;
status = "disabled";
};
wcd_codec: codec@f000 {
compatible = "qcom,pm8916-wcd-analog-codec";
reg = <0xf000 0x200>;
......
arch/arm64/boot/dts/qcom/pm8994.dtsi
View file @ 2e04d1bd
......@@ -85,5 +85,9 @@ pmic@1 {
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8994_spmi_regulators: regulators {
compatible = "qcom,pm8994-regulators";
};
};
};
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
View file @ 2e04d1bd
......@@ -73,6 +73,7 @@ pms405_s3: s3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd_apc";
regulator-initial-mode = <1>;
regulator-min-microvolt = <1048000>;
regulator-max-microvolt = <1384000>;
};
......
arch/arm64/boot/dts/qcom/qcs404.dtsi
View file @ 2e04d1bd
......@@ -42,6 +42,10 @@ CPU0: cpu@100 {
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
clocks = <&apcs_glb>;
operating-points-v2 = <&cpu_opp_table>;
power-domains = <&cpr>;
power-domain-names = "cpr";
};
CPU1: cpu@101 {
......@@ -52,6 +56,10 @@ CPU1: cpu@101 {
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
clocks = <&apcs_glb>;
operating-points-v2 = <&cpu_opp_table>;
power-domains = <&cpr>;
power-domain-names = "cpr";
};
CPU2: cpu@102 {
......@@ -62,6 +70,10 @@ CPU2: cpu@102 {
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
clocks = <&apcs_glb>;
operating-points-v2 = <&cpu_opp_table>;
power-domains = <&cpr>;
power-domain-names = "cpr";
};
CPU3: cpu@103 {
......@@ -72,6 +84,10 @@ CPU3: cpu@103 {
cpu-idle-states = <&CPU_SLEEP_0>;
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
clocks = <&apcs_glb>;
operating-points-v2 = <&cpu_opp_table>;
power-domains = <&cpr>;
power-domain-names = "cpr";
};
L2_0: l2-cache {
......@@ -94,6 +110,41 @@ CPU_SLEEP_0: cpu-sleep-0 {
};
};
cpu_opp_table: cpu-opp-table {
compatible = "operating-points-v2-kryo-cpu";
opp-shared;
opp-1094400000 {
opp-hz = /bits/ 64 <1094400000>;
required-opps = <&cpr_opp1>;
};
opp-1248000000 {
opp-hz = /bits/ 64 <1248000000>;
required-opps = <&cpr_opp2>;
};
opp-1401600000 {
opp-hz = /bits/ 64 <1401600000>;
required-opps = <&cpr_opp3>;
};
};
cpr_opp_table: cpr-opp-table {
compatible = "operating-points-v2-qcom-level";
cpr_opp1: opp1 {
opp-level = <1>;
qcom,opp-fuse-level = <1>;
};
cpr_opp2: opp2 {
opp-level = <2>;
qcom,opp-fuse-level = <2>;
};
cpr_opp3: opp3 {
opp-level = <3>;
qcom,opp-fuse-level = <3>;
};
};
firmware {
scm: scm {
compatible = "qcom,scm-qcs404", "qcom,scm";
......@@ -280,6 +331,62 @@ qfprom: qfprom@a4000 {
tsens_caldata: caldata@d0 {
reg = <0x1f8 0x14>;
};
cpr_efuse_speedbin: speedbin@13c {
reg = <0x13c 0x4>;
bits = <2 3>;
};
cpr_efuse_quot_offset1: qoffset1@231 {
reg = <0x231 0x4>;
bits = <4 7>;
};
cpr_efuse_quot_offset2: qoffset2@232 {
reg = <0x232 0x4>;
bits = <3 7>;
};
cpr_efuse_quot_offset3: qoffset3@233 {
reg = <0x233 0x4>;
bits = <2 7>;
};
cpr_efuse_init_voltage1: ivoltage1@229 {
reg = <0x229 0x4>;
bits = <4 6>;
};
cpr_efuse_init_voltage2: ivoltage2@22a {
reg = <0x22a 0x4>;
bits = <2 6>;
};
cpr_efuse_init_voltage3: ivoltage3@22b {
reg = <0x22b 0x4>;
bits = <0 6>;
};
cpr_efuse_quot1: quot1@22b {
reg = <0x22b 0x4>;
bits = <6 12>;
};
cpr_efuse_quot2: quot2@22d {
reg = <0x22d 0x4>;
bits = <2 12>;
};
cpr_efuse_quot3: quot3@230 {
reg = <0x230 0x4>;
bits = <0 12>;
};
cpr_efuse_ring1: ring1@228 {
reg = <0x228 0x4>;
bits = <0 3>;
};
cpr_efuse_ring2: ring2@228 {
reg = <0x228 0x4>;
bits = <4 3>;
};
cpr_efuse_ring3: ring3@229 {
reg = <0x229 0x4>;
bits = <0 3>;
};
cpr_efuse_revision: revision@218 {
reg = <0x218 0x4>;
bits = <3 3>;
};
};
rng: rng@e3000 {
......@@ -902,14 +1009,65 @@ apcs_glb: mailbox@b011000 {
compatible = "qcom,qcs404-apcs-apps-global", "syscon";
reg = <0x0b011000 0x1000>;
#mbox-cells = <1>;
clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;
clock-names = "pll", "aux";
#clock-cells = <0>;
};
apcs_hfpll: clock-controller@b016000 {
compatible = "qcom,hfpll";
reg = <0x0b016000 0x30>;
#clock-cells = <0>;
clock-output-names = "apcs_hfpll";
clocks = <&xo_board>;
clock-names = "xo";
};
watchdog@b017000 {
compatible = "qcom,kpss-wdt";
compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt";
reg = <0x0b017000 0x1000>;
clocks = <&sleep_clk>;
};
cpr: power-controller@b018000 {
compatible = "qcom,qcs404-cpr", "qcom,cpr";
reg = <0x0b018000 0x1000>;
interrupts = <0 15 IRQ_TYPE_EDGE_RISING>;
clocks = <&xo_board>;
clock-names = "ref";
vdd-apc-supply = <&pms405_s3>;
#power-domain-cells = <0>;
operating-points-v2 = <&cpr_opp_table>;
acc-syscon = <&tcsr>;
nvmem-cells = <&cpr_efuse_quot_offset1>,
<&cpr_efuse_quot_offset2>,
<&cpr_efuse_quot_offset3>,
<&cpr_efuse_init_voltage1>,
<&cpr_efuse_init_voltage2>,
<&cpr_efuse_init_voltage3>,
<&cpr_efuse_quot1>,
<&cpr_efuse_quot2>,
<&cpr_efuse_quot3>,
<&cpr_efuse_ring1>,
<&cpr_efuse_ring2>,
<&cpr_efuse_ring3>,
<&cpr_efuse_revision>;
nvmem-cell-names = "cpr_quotient_offset1",
"cpr_quotient_offset2",
"cpr_quotient_offset3",
"cpr_init_voltage1",
"cpr_init_voltage2",
"cpr_init_voltage3",
"cpr_quotient1",
"cpr_quotient2",
"cpr_quotient3",
"cpr_ring_osc1",
"cpr_ring_osc2",
"cpr_ring_osc3",
"cpr_fuse_revision";
};
timer@b120000 {
#address-cells = <1>;
#size-cells = <1>;
......
arch/arm64/boot/dts/qcom/sc7180-idp.dts 0 → 100644
View file @ 2e04d1bd
// SPDX-License-Identifier: BSD-3-Clause
/*
* SC7180 IDP board device tree source
*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sc7180.dtsi"
#include "pm6150.dtsi"
#include "pm6150l.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SC7180 IDP";
compatible = "qcom,sc7180-idp", "qcom,sc7180";
aliases {
hsuart0 = &uart3;
serial0 = &uart8;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&apps_rsc {
pm6150-rpmh-regulators {
compatible = "qcom,pm6150-rpmh-regulators";
qcom,pmic-id = "a";
vreg_s1a_1p1: smps1 {
regulator-min-microvolt = <1128000>;
regulator-max-microvolt = <1128000>;
};
vreg_s4a_1p0: smps4 {
regulator-min-microvolt = <824000>;
regulator-max-microvolt = <1120000>;
};
vreg_s5a_2p0: smps5 {
regulator-min-microvolt = <1744000>;
regulator-max-microvolt = <2040000>;
};
vreg_l1a_1p2: ldo1 {
regulator-min-microvolt = <1178000>;
regulator-max-microvolt = <1256000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l2a_1p0: ldo2 {
regulator-min-microvolt = <944000>;
regulator-max-microvolt = <1056000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l3a_1p0: ldo3 {
regulator-min-microvolt = <968000>;
regulator-max-microvolt = <1064000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l4a_0p8: ldo4 {
regulator-min-microvolt = <824000>;
regulator-max-microvolt = <928000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l5a_2p7: ldo5 {
regulator-min-microvolt = <2496000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l6a_0p6: ldo6 {
regulator-min-microvolt = <568000>;
regulator-max-microvolt = <648000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l9a_0p6: ldo9 {
regulator-min-microvolt = <488000>;
regulator-max-microvolt = <800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l10a_1p8: ldo10 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1832000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l11a_1p8: ldo11 {
regulator-min-microvolt = <1696000>;
regulator-max-microvolt = <1904000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l12a_1p8: ldo12 {
regulator-min-microvolt = <1696000>;
regulator-max-microvolt = <1952000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l13a_1p8: ldo13 {
regulator-min-microvolt = <1696000>;
regulator-max-microvolt = <1904000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l14a_1p8: ldo14 {
regulator-min-microvolt = <1728000>;
regulator-max-microvolt = <1832000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l15a_1p8: ldo15 {
regulator-min-microvolt = <1696000>;
regulator-max-microvolt = <1904000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l16a_2p7: ldo16 {
regulator-min-microvolt = <2496000>;
regulator-max-microvolt = <3304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l17a_3p0: ldo17 {
regulator-min-microvolt = <2920000>;
regulator-max-microvolt = <3232000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l18a_2p8: ldo18 {
regulator-min-microvolt = <2496000>;
regulator-max-microvolt = <3304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l19a_2p9: ldo19 {
regulator-min-microvolt = <2696000>;
regulator-max-microvolt = <3304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
};
pm6150l-rpmh-regulators {
compatible = "qcom,pm6150l-rpmh-regulators";
qcom,pmic-id = "c";
vreg_s8c_1p3: smps8 {
regulator-min-microvolt = <1120000>;
regulator-max-microvolt = <1408000>;
};
vreg_l1c_1p8: ldo1 {
regulator-min-microvolt = <1616000>;
regulator-max-microvolt = <1984000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l2c_1p3: ldo2 {
regulator-min-microvolt = <1168000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l3c_1p2: ldo3 {
regulator-min-microvolt = <1144000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l4c_1p8: ldo4 {
regulator-min-microvolt = <1648000>;
regulator-max-microvolt = <3304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l5c_1p8: ldo5 {
regulator-min-microvolt = <1648000>;
regulator-max-microvolt = <3304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l6c_2p9: ldo6 {
regulator-min-microvolt = <2696000>;
regulator-max-microvolt = <3304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l7c_3p0: ldo7 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l8c_1p8: ldo8 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1904000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l9c_2p9: ldo9 {
regulator-min-microvolt = <2952000>;
regulator-max-microvolt = <3304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l10c_3p3: ldo10 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3400000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_l11c_3p3: ldo11 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3400000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
};
vreg_bob: bob {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
};
};
};
&qspi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};
};
&qupv3_id_0 {
status = "okay";
};
&qupv3_id_1 {
status = "okay";
};
&uart3 {
status = "okay";
};
&uart8 {
status = "okay";
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "host";
};
&usb_1_hsphy {
status = "okay";
vdd-supply = <&vreg_l4a_0p8>;
vdda-pll-supply = <&vreg_l11a_1p8>;
vdda-phy-dpdm-supply = <&vreg_l17a_3p0>;
qcom,imp-res-offset-value = <8>;
qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
};
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l3c_1p2>;
vdda-pll-supply = <&vreg_l4a_0p8>;
};
/* PINCTRL - additions to nodes defined in sc7180.dtsi */
&qspi_clk {
pinconf {
pins = "gpio63";
bias-disable;
};
};
&qspi_cs0 {
pinconf {
pins = "gpio68";
bias-disable;
};
};
&qspi_data01 {
pinconf {
pins = "gpio64", "gpio65";
/* High-Z when no transfers; nice to park the lines */
bias-pull-up;
};
};
&qup_i2c2_default {
pinconf {
pins = "gpio15", "gpio16";
drive-strength = <2>;
/* Has external pullup */
bias-disable;
};
};
&qup_i2c4_default {
pinconf {
pins = "gpio115", "gpio116";
drive-strength = <2>;
/* Has external pullup */
bias-disable;
};
};
&qup_i2c7_default {
pinconf {
pins = "gpio6", "gpio7";
drive-strength = <2>;
/* Has external pullup */
bias-disable;
};
};
&qup_i2c9_default {
pinconf {
pins = "gpio46", "gpio47";
drive-strength = <2>;
/* Has external pullup */
bias-disable;
};
};
&qup_uart3_default {
pinconf-cts {
/*
* Configure a pull-down on 38 (CTS) to match the pull of
* the Bluetooth module.
*/
pins = "gpio38";
bias-pull-down;
output-high;
};
pinconf-rts {
/* We'll drive 39 (RTS), so no pull */
pins = "gpio39";
drive-strength = <2>;
bias-disable;
};
pinconf-tx {
/* We'll drive 40 (TX), so no pull */
pins = "gpio40";
drive-strength = <2>;
bias-disable;
output-high;
};
pinconf-rx {
/*
* Configure a pull-up on 41 (RX). This is needed to avoid
* garbage data when the TX pin of the Bluetooth module is
* in tri-state (module powered off or not driving the
* signal yet).
*/
pins = "gpio41";
bias-pull-up;
};
};
&qup_uart8_default {
pinconf-tx {
pins = "gpio44";
drive-strength = <2>;
bias-disable;
};
pinconf-rx {
pins = "gpio45";
drive-strength = <2>;
bias-pull-up;
};
};
&qup_spi0_default {
pinconf {
pins = "gpio34", "gpio35", "gpio36", "gpio37";
drive-strength = <2>;
bias-disable;
};
};
&qup_spi6_default {
pinconf {
pins = "gpio59", "gpio60", "gpio61", "gpio62";
drive-strength = <2>;
bias-disable;
};
};
&qup_spi10_default {
pinconf {
pins = "gpio86", "gpio87", "gpio88", "gpio89";
drive-strength = <2>;
bias-disable;
};
};
arch/arm64/boot/dts/qcom/sc7180.dtsi 0 → 100644
View file @ 2e04d1bd
// SPDX-License-Identifier: BSD-3-Clause
/*
* SC7180 SoC device tree source
*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
i2c8 = &i2c8;
i2c9 = &i2c9;
i2c10 = &i2c10;
i2c11 = &i2c11;
spi0 = &spi0;
spi1 = &spi1;
spi3 = &spi3;
spi5 = &spi5;
spi6 = &spi6;
spi8 = &spi8;
spi10 = &spi10;
spi11 = &spi11;
};
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
clock-frequency = <38400000>;
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32764>;
#clock-cells = <0>;
};
};
reserved_memory: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
aop_cmd_db_mem: memory@80820000 {
reg = <0x0 0x80820000 0x0 0x20000>;
compatible = "qcom,cmd-db";
};
smem_mem: memory@80900000 {
reg = <0x0 0x80900000 0x0 0x200000>;
no-map;
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
};
};
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_100>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&L2_200>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&L2_300>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x400>;
enable-method = "psci";
next-level-cache = <&L2_400>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x500>;
enable-method = "psci";
next-level-cache = <&L2_500>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x600>;
enable-method = "psci";
next-level-cache = <&L2_600>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x700>;
enable-method = "psci";
next-level-cache = <&L2_700>;
#cooling-cells = <2>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0 0x80000000 0 0>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
};
firmware {
scm {
compatible = "qcom,scm-sc7180", "qcom,scm";
};
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x1000>;
#hwlock-cells = <1>;
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
};
smp2p-cdsp {
compatible = "qcom,smp2p";
qcom,smem = <94>, <432>;
interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 6>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
cdsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
cdsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-lpass {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 10>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-mpss {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
modem_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
modem_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
soc: soc {
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0 0 0 0x10 0>;
dma-ranges = <0 0 0 0 0x10 0>;
compatible = "simple-bus";
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sc7180";
reg = <0 0x00100000 0 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>;
clock-names = "bi_tcxo", "bi_tcxo_ao";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
qfprom@784000 {
compatible = "qcom,qfprom";
reg = <0 0x00784000 0 0x8ff>;
#address-cells = <1>;
#size-cells = <1>;
qusb2p_hstx_trim: hstx-trim-primary@25b {
reg = <0x25b 0x1>;
bits = <1 3>;
};
};
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x008c0000 0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
i2c0: i2c@880000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00880000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi0: spi@880000 {
compatible = "qcom,geni-spi";
reg = <0 0x00880000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart0: serial@880000 {
compatible = "qcom,geni-uart";
reg = <0 0x00880000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c1: i2c@884000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00884000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@884000 {
compatible = "qcom,geni-spi";
reg = <0 0x00884000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart1: serial@884000 {
compatible = "qcom,geni-uart";
reg = <0 0x00884000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c2: i2c@888000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00888000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart2: serial@888000 {
compatible = "qcom,geni-uart";
reg = <0 0x00888000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c3: i2c@88c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0088c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c3_default>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi3: spi@88c000 {
compatible = "qcom,geni-spi";
reg = <0 0x0088c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi3_default>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart3: serial@88c000 {
compatible = "qcom,geni-uart";
reg = <0 0x0088c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart3_default>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c4: i2c@890000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00890000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c4_default>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart4: serial@890000 {
compatible = "qcom,geni-uart";
reg = <0 0x00890000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart4_default>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c5: i2c@894000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00894000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi5: spi@894000 {
compatible = "qcom,geni-spi";
reg = <0 0x00894000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart5: serial@894000 {
compatible = "qcom,geni-uart";
reg = <0 0x00894000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x00ac0000 0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
i2c6: i2c@a80000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a80000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c6_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi6: spi@a80000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a80000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi6_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart6: serial@a80000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a80000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart6_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c7: i2c@a84000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a84000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c7_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart7: serial@a84000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a84000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart7_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c8: i2c@a88000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a88000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c8_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi8: spi@a88000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a88000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi8_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart8: serial@a88000 {
compatible = "qcom,geni-debug-uart";
reg = <0 0x00a88000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart8_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c9: i2c@a8c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a8c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c9_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart9: serial@a8c000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a8c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart9_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c10: i2c@a90000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a90000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c10_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi10: spi@a90000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a90000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi10_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart10: serial@a90000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a90000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart10_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
i2c11: i2c@a94000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a94000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c11_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi11: spi@a94000 {
compatible = "qcom,geni-spi";
reg = <0 0x00a94000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi11_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart11: serial@a94000 {
compatible = "qcom,geni-uart";
reg = <0 0x00a94000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart11_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
tcsr_mutex_regs: syscon@1f40000 {
compatible = "syscon";
reg = <0 0x01f40000 0 0x40000>;
};
tlmm: pinctrl@3500000 {
compatible = "qcom,sc7180-pinctrl";
reg = <0 0x03500000 0 0x300000>,
<0 0x03900000 0 0x300000>,
<0 0x03d00000 0 0x300000>;
reg-names = "west", "north", "south";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 120>;
wakeup-parent = <&pdc>;
qspi_clk: qspi-clk {
pinmux {
pins = "gpio63";
function = "qspi_clk";
};
};
qspi_cs0: qspi-cs0 {
pinmux {
pins = "gpio68";
function = "qspi_cs";
};
};
qspi_cs1: qspi-cs1 {
pinmux {
pins = "gpio72";
function = "qspi_cs";
};
};
qspi_data01: qspi-data01 {
pinmux-data {
pins = "gpio64", "gpio65";
function = "qspi_data";
};
};
qspi_data12: qspi-data12 {
pinmux-data {
pins = "gpio66", "gpio67";
function = "qspi_data";
};
};
qup_i2c0_default: qup-i2c0-default {
pinmux {
pins = "gpio34", "gpio35";
function = "qup00";
};
};
qup_i2c1_default: qup-i2c1-default {
pinmux {
pins = "gpio0", "gpio1";
function = "qup01";
};
};
qup_i2c2_default: qup-i2c2-default {
pinmux {
pins = "gpio15", "gpio16";
function = "qup02_i2c";
};
};
qup_i2c3_default: qup-i2c3-default {
pinmux {
pins = "gpio38", "gpio39";
function = "qup03";
};
};
qup_i2c4_default: qup-i2c4-default {
pinmux {
pins = "gpio115", "gpio116";
function = "qup04_i2c";
};
};
qup_i2c5_default: qup-i2c5-default {
pinmux {
pins = "gpio25", "gpio26";
function = "qup05";
};
};
qup_i2c6_default: qup-i2c6-default {
pinmux {
pins = "gpio59", "gpio60";
function = "qup10";
};
};
qup_i2c7_default: qup-i2c7-default {
pinmux {
pins = "gpio6", "gpio7";
function = "qup11_i2c";
};
};
qup_i2c8_default: qup-i2c8-default {
pinmux {
pins = "gpio42", "gpio43";
function = "qup12";
};
};
qup_i2c9_default: qup-i2c9-default {
pinmux {
pins = "gpio46", "gpio47";
function = "qup13_i2c";
};
};
qup_i2c10_default: qup-i2c10-default {
pinmux {
pins = "gpio86", "gpio87";
function = "qup14";
};
};
qup_i2c11_default: qup-i2c11-default {
pinmux {
pins = "gpio53", "gpio54";
function = "qup15";
};
};
qup_spi0_default: qup-spi0-default {
pinmux {
pins = "gpio34", "gpio35",
"gpio36", "gpio37";
function = "qup00";
};
};
qup_spi1_default: qup-spi1-default {
pinmux {
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
function = "qup01";
};
};
qup_spi3_default: qup-spi3-default {
pinmux {
pins = "gpio38", "gpio39",
"gpio40", "gpio41";
function = "qup03";
};
};
qup_spi5_default: qup-spi5-default {
pinmux {
pins = "gpio25", "gpio26",
"gpio27", "gpio28";
function = "qup05";
};
};
qup_spi6_default: qup-spi6-default {
pinmux {
pins = "gpio59", "gpio60",
"gpio61", "gpio62";
function = "qup10";
};
};
qup_spi8_default: qup-spi8-default {
pinmux {
pins = "gpio42", "gpio43",
"gpio44", "gpio45";
function = "qup12";
};
};
qup_spi10_default: qup-spi10-default {
pinmux {
pins = "gpio86", "gpio87",
"gpio88", "gpio89";
function = "qup14";
};
};
qup_spi11_default: qup-spi11-default {
pinmux {
pins = "gpio53", "gpio54",
"gpio55", "gpio56";
function = "qup15";
};
};
qup_uart0_default: qup-uart0-default {
pinmux {
pins = "gpio34", "gpio35",
"gpio36", "gpio37";
function = "qup00";
};
};
qup_uart1_default: qup-uart1-default {
pinmux {
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
function = "qup01";
};
};
qup_uart2_default: qup-uart2-default {
pinmux {
pins = "gpio15", "gpio16";
function = "qup02_uart";
};
};
qup_uart3_default: qup-uart3-default {
pinmux {
pins = "gpio38", "gpio39",
"gpio40", "gpio41";
function = "qup03";
};
};
qup_uart4_default: qup-uart4-default {
pinmux {
pins = "gpio115", "gpio116";
function = "qup04_uart";
};
};
qup_uart5_default: qup-uart5-default {
pinmux {
pins = "gpio25", "gpio26",
"gpio27", "gpio28";
function = "qup05";
};
};
qup_uart6_default: qup-uart6-default {
pinmux {
pins = "gpio59", "gpio60",
"gpio61", "gpio62";
function = "qup10";
};
};
qup_uart7_default: qup-uart7-default {
pinmux {
pins = "gpio6", "gpio7";
function = "qup11_uart";
};
};
qup_uart8_default: qup-uart8-default {
pinmux {
pins = "gpio44", "gpio45";
function = "qup12";
};
};
qup_uart9_default: qup-uart9-default {
pinmux {
pins = "gpio46", "gpio47";
function = "qup13_uart";
};
};
qup_uart10_default: qup-uart10-default {
pinmux {
pins = "gpio86", "gpio87",
"gpio88", "gpio89";
function = "qup14";
};
};
qup_uart11_default: qup-uart11-default {
pinmux {
pins = "gpio53", "gpio54",
"gpio55", "gpio56";
function = "qup15";
};
};
};
qspi: spi@88dc000 {
compatible = "qcom,qspi-v1";
reg = <0 0x088dc000 0 0x600>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<&gcc GCC_QSPI_CORE_CLK>;
clock-names = "iface", "core";
status = "disabled";
};
usb_1_hsphy: phy@88e3000 {
compatible = "qcom,sc7180-qusb2-phy";
reg = <0 0x088e3000 0 0x400>;
status = "disabled";
#phy-cells = <0>;
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "cfg_ahb", "ref";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
nvmem-cells = <&qusb2p_hstx_trim>;
};
usb_1_qmpphy: phy-wrapper@88e9000 {
compatible = "qcom,sc7180-qmp-usb3-phy";
reg = <0 0x088e9000 0 0x18c>,
<0 0x088e8000 0 0x38>;
reg-names = "reg-base", "dp_com";
status = "disabled";
#clock-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "com_aux";
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "phy", "common";
usb_1_ssphy: phy@88e9200 {
reg = <0 0x088e9200 0 0x128>,
<0 0x088e9400 0 0x200>,
<0 0x088e9c00 0 0x218>,
<0 0x088e9600 0 0x128>,
<0 0x088e9800 0 0x200>,
<0 0x088e9a00 0 0x18>;
#clock-cells = <0>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
};
system-cache-controller@9200000 {
compatible = "qcom,sc7180-llcc";
reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
usb_1: usb@a6f8800 {
compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma-ranges;
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
clock-names = "cfg_noc", "core", "iface", "mock_utmi",
"sleep";
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
resets = <&gcc GCC_USB30_PRIM_BCR>;
usb_1_dwc3: dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xe000>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0x540 0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc7180-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>;
qcom,pdc-ranges = <0 480 15>, <17 497 98>,
<119 634 4>, <124 639 1>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
pdc_reset: reset-controller@b2e0000 {
compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
reg = <0 0x0b2e0000 0 0x20000>;
#reset-cells = <1>;
};
tsens0: thermal-sensor@c263000 {
compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
reg = <0 0x0c263000 0 0x1ff>, /* TM */
<0 0x0c222000 0 0x1ff>; /* SROT */
#qcom,sensors = <15>;
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow","critical";
#thermal-sensor-cells = <1>;
};
tsens1: thermal-sensor@c265000 {
compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
reg = <0 0x0c265000 0 0x1ff>, /* TM */
<0 0x0c223000 0 0x1ff>; /* SROT */
#qcom,sensors = <10>;
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow","critical";
#thermal-sensor-cells = <1>;
};
aoss_reset: reset-controller@c2a0000 {
compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
reg = <0 0x0c2a0000 0 0x31000>;
#reset-cells = <1>;
};
aoss_qmp: qmp@c300000 {
compatible = "qcom,sc7180-aoss-qmp";
reg = <0 0x0c300000 0 0x100000>;
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
#power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0 0x0c440000 0 0x1100>,
<0 0x0c600000 0 0x2000000>,
<0 0x0e600000 0 0x100000>,
<0 0x0e700000 0 0xa0000>,
<0 0x0c40a000 0 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <4>;
cell-index = <0>;
};
apps_smmu: iommu@15000000 {
compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
#size-cells = <2>;
ranges;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0 0x17a00000 0 0x10000>, /* GICD */
<0 0x17a60000 0 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
msi-controller@17a40000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0 0x17a40000 0 0x20000>;
status = "disabled";
};
};
apss_shared: mailbox@17c00000 {
compatible = "qcom,sc7180-apss-shared";
reg = <0 0x17c00000 0 0x10000>;
#mbox-cells = <1>;
};
watchdog@17c10000 {
compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
};
timer@17c20000{
#address-cells = <2>;
#size-cells = <2>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0 0x17c20000 0 0x1000>;
frame@17c21000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c21000 0 0x1000>,
<0 0x17c22000 0 0x1000>;
};
frame@17c23000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c23000 0 0x1000>;
status = "disabled";
};
frame@17c25000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c25000 0 0x1000>;
status = "disabled";
};
frame@17c27000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c27000 0 0x1000>;
status = "disabled";
};
frame@17c29000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c29000 0 0x1000>;
status = "disabled";
};
frame@17c2b000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c2b000 0 0x1000>;
status = "disabled";
};
frame@17c2d000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c2d000 0 0x1000>;
status = "disabled";
};
};
apps_rsc: rsc@18200000 {
compatible = "qcom,rpmh-rsc";
reg = <0 0x18200000 0 0x10000>,
<0 0x18210000 0 0x10000>,
<0 0x18220000 0 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
rpmhcc: clock-controller {
compatible = "qcom,sc7180-rpmh-clk";
clocks = <&xo_board>;
clock-names = "xo";
#clock-cells = <1>;
};
rpmhpd: power-controller {
compatible = "qcom,sc7180-rpmhpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmhpd_opp_table>;
rpmhpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmhpd_opp_ret: opp1 {
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
};
rpmhpd_opp_min_svs: opp2 {
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
};
rpmhpd_opp_low_svs: opp3 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
};
rpmhpd_opp_svs: opp4 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};
rpmhpd_opp_svs_l1: opp5 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};
rpmhpd_opp_svs_l2: opp6 {
opp-level = <224>;
};
rpmhpd_opp_nom: opp7 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
};
rpmhpd_opp_nom_l1: opp8 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
};
rpmhpd_opp_nom_l2: opp9 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
};
rpmhpd_opp_turbo: opp10 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
};
rpmhpd_opp_turbo_l1: opp11 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
};
};
};
};
cpufreq_hw: cpufreq@18323000 {
compatible = "qcom,cpufreq-hw";
reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
reg-names = "freq-domain0", "freq-domain1";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
};
};
thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 1>;
trips {
cpu0_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu0_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu0_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu0_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu0_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 2>;
trips {
cpu1_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu1_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu1_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu1_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu1_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 3>;
trips {
cpu2_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu2_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu2_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu2_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu2_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 4>;
trips {
cpu3_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu3_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu3_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu3_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu3_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu4-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 5>;
trips {
cpu4_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu4_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu4_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu4_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu4_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu5-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 6>;
trips {
cpu5_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu5_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu5_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu5_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu5_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu6-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 9>;
trips {
cpu6_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu6_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu6_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu6_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu6_alert1>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu7-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 10>;
trips {
cpu7_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu7_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu7_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu7_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu7_alert1>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu8-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 11>;
trips {
cpu8_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu8_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu8_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu8_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu8_alert1>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu9-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 12>;
trips {
cpu9_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "passive";
};
cpu9_alert1: trip-point1 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
cpu9_crit: cpu_crit {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu9_alert0>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
map1 {
trip = <&cpu9_alert1>;
cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
aoss0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 0>;
trips {
aoss0_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
cpuss0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 7>;
trips {
cpuss0_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
cpuss0_crit: cluster0_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
cpuss1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 8>;
trips {
cpuss1_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
cpuss1_crit: cluster0_crit {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
gpuss0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 13>;
trips {
gpuss0_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
gpuss1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 14>;
trips {
gpuss1_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
aoss1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 0>;
trips {
aoss1_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
cwlan-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 1>;
trips {
cwlan_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
audio-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 2>;
trips {
audio_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
ddr-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 3>;
trips {
ddr_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
q6-hvx-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 4>;
trips {
q6_hvx_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
camera-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 5>;
trips {
camera_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
mdm-core-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 6>;
trips {
mdm_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
mdm-dsp-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 7>;
trips {
mdm_dsp_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
npu-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 8>;
trips {
npu_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
video-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens1 9>;
trips {
video_alert0: trip-point0 {
temperature = <90000>;
hysteresis = <2000>;
type = "hot";
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
};
};
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
View file @ 2e04d1bd
......@@ -165,7 +165,6 @@ panel_in_edp: endpoint {
/delete-node/ &venus_mem;
/delete-node/ &cdsp_mem;
/delete-node/ &cdsp_pas;
/delete-node/ &zap_shader;
/delete-node/ &gpu_mem;
/* Increase the size from 120 MB to 128 MB */
......@@ -651,6 +650,20 @@ &spi0 {
status = "okay";
};
&spi5 {
status = "okay";
tpm@0 {
compatible = "google,cr50";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&h1_ap_int_odl>;
spi-max-frequency = <800000>;
interrupt-parent = <&tlmm>;
interrupts = <129 IRQ_TYPE_EDGE_RISING>;
};
};
&spi10 {
status = "okay";
......
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
View file @ 2e04d1bd
......@@ -197,7 +197,7 @@ vph_pwr: vph-pwr-regulator {
&adsp_pas {
status = "okay";
firmware-name = "qcom/db845c/adsp.mdt";
firmware-name = "qcom/sdm845/adsp.mdt";
};
&apps_rsc {
......@@ -343,7 +343,7 @@ vreg_bob: bob {
&cdsp_pas {
status = "okay";
firmware-name = "qcom/db845c/cdsp.mdt";
firmware-name = "qcom/sdm845/cdsp.mdt";
};
&gcc {
......@@ -352,6 +352,18 @@ &gcc {
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
};
&gpu {
zap-shader {
memory-region = <&gpu_mem>;
firmware-name = "qcom/sdm845/a630_zap.mbn";
};
};
&mss_pil {
status = "okay";
firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mbn";
};
&pm8998_gpio {
vol_up_pin_a: vol-up-active {
pins = "gpio6";
......@@ -529,6 +541,8 @@ &wifi {
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
qcom,snoc-host-cap-8bit-quirk;
};
/* PINCTRL - additions to nodes defined in sdm845.dtsi */
......
arch/arm64/boot/dts/qcom/sdm845-mtp.dts
View file @ 2e04d1bd
......@@ -360,6 +360,13 @@ &gcc {
<GCC_LPASS_SWAY_CLK>;
};
&gpu {
zap-shader {
memory-region = <&gpu_mem>;
firmware-name = "qcom/sdm845/a630_zap.mbn";
};
};
&i2c10 {
status = "okay";
clock-frequency = <400000>;
......
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file @ 2e04d1bd
......@@ -1357,7 +1357,7 @@ uart15: serial@a9c000 {
};
};
cache-controller@1100000 {
system-cache-controller@1100000 {
compatible = "qcom,sdm845-llcc";
reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
......@@ -1374,6 +1374,8 @@ ufs_mem_hc: ufshc@1d84000 {
lanes-per-direction = <2>;
power-domains = <&gcc UFS_PHY_GDSC>;
#reset-cells = <1>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
iommus = <&apps_smmu 0x100 0xf>;
......@@ -1447,6 +1449,7 @@ tlmm: pinctrl@3400000 {
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 150>;
wakeup-parent = <&pdc_intc>;
qspi_clk: qspi-clk {
pinmux {
......@@ -2804,7 +2807,7 @@ dsi1_phy: dsi-phy@ae96400 {
};
};
gpu@5000000 {
gpu: gpu@5000000 {
compatible = "qcom,adreno-630.2", "qcom,adreno";
#stream-id-cells = <16>;
......@@ -2824,10 +2827,6 @@ gpu@5000000 {
qcom,gmu = <&gmu>;
zap_shader: zap-shader {
memory-region = <&gpu_mem>;
};
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
......@@ -2939,6 +2938,15 @@ dispcc: clock-controller@af00000 {
#power-domain-cells = <1>;
};
pdc_intc: interrupt-controller@b220000 {
compatible = "qcom,sdm845-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>;
qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
pdc_reset: reset-controller@b2e0000 {
compatible = "qcom,sdm845-pdc-global";
reg = <0 0x0b2e0000 0 0x20000>;
......@@ -2950,8 +2958,9 @@ tsens0: thermal-sensor@c263000 {
reg = <0 0x0c263000 0 0x1ff>, /* TM */
<0 0x0c222000 0 0x1ff>; /* SROT */
#qcom,sensors = <13>;
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
};
......@@ -2960,8 +2969,9 @@ tsens1: thermal-sensor@c265000 {
reg = <0 0x0c265000 0 0x1ff>, /* TM */
<0 0x0c223000 0 0x1ff>; /* SROT */
#qcom,sensors = <8>;
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow";
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "uplow", "critical";
#thermal-sensor-cells = <1>;
};
......@@ -3191,7 +3201,7 @@ intc: interrupt-controller@17a00000 {
<0 0x17a60000 0 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gic-its@17a40000 {
msi-controller@17a40000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
......
arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
View file @ 2e04d1bd
......@@ -245,6 +245,13 @@ &gcc {
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>;
};
&gpu {
zap-shader {
memory-region = <&gpu_mem>;
firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn";
};
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
......
arch/arm64/boot/dts/qcom/sm8150-mtp.dts
View file @ 2e04d1bd
......@@ -7,6 +7,7 @@
/dts-v1/;
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/gpio/gpio.h>
#include "sm8150.dtsi"
#include "pm8150.dtsi"
#include "pm8150b.dtsi"
......@@ -366,6 +367,18 @@ resin {
};
};
&remoteproc_adsp {
status = "okay";
};
&remoteproc_cdsp {
status = "okay";
};
&remoteproc_slpi {
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <0 4>, <126 4>;
};
......@@ -373,3 +386,25 @@ &tlmm {
&uart2 {
status = "okay";
};
&ufs_mem_hc {
status = "okay";
reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l10a_2p5>;
vcc-max-microamp = <750000>;
vccq-supply = <&vreg_l9a_1p2>;
vccq-max-microamp = <700000>;
vccq2-supply = <&vreg_s4a_1p8>;
vccq2-max-microamp = <750000>;
};
&ufs_mem_phy {
status = "okay";
vdda-phy-supply = <&vdda_ufs_2ln_core_1>;
vdda-max-microamp = <90200>;
vdda-pll-supply = <&vreg_l3c_1p2>;
vdda-pll-max-microamp = <19000>;
};
arch/arm64/boot/dts/qcom/sm8150.dtsi
View file @ 2e04d1bd
......@@ -5,8 +5,11 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,gcc-sm8150.h>
/ {
interrupt-parent = <&intc>;
......@@ -42,6 +45,7 @@ CPU0: cpu@0 {
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
......@@ -57,6 +61,7 @@ CPU1: cpu@100 {
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_100>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
......@@ -70,6 +75,7 @@ CPU2: cpu@200 {
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&L2_200>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
......@@ -82,6 +88,7 @@ CPU3: cpu@300 {
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&L2_300>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
......@@ -94,6 +101,7 @@ CPU4: cpu@400 {
reg = <0x0 0x400>;
enable-method = "psci";
next-level-cache = <&L2_400>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
......@@ -106,6 +114,7 @@ CPU5: cpu@500 {
reg = <0x0 0x500>;
enable-method = "psci";
next-level-cache = <&L2_500>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
......@@ -118,6 +127,7 @@ CPU6: cpu@600 {
reg = <0x0 0x600>;
enable-method = "psci";
next-level-cache = <&L2_600>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
......@@ -130,6 +140,7 @@ CPU7: cpu@700 {
reg = <0x0 0x700>;
enable-method = "psci";
next-level-cache = <&L2_700>;
qcom,freq-domain = <&cpufreq_hw 2>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
......@@ -283,6 +294,102 @@ smem {
hwlocks = <&tcsr_mutex 3>;
};
smp2p-cdsp {
compatible = "qcom,smp2p";
qcom,smem = <94>, <432>;
interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 6>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
cdsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
cdsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-lpass {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 10>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
adsp_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
adsp_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-mpss {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
modem_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
modem_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-slpi {
compatible = "qcom,smp2p";
qcom,smem = <481>, <430>;
interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 26>;
qcom,local-pid = <0>;
qcom,remote-pid = <3>;
slpi_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
slpi_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
......@@ -306,8 +413,8 @@ qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc 123>,
<&gcc 124>;
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
......@@ -317,17 +424,120 @@ uart2: serial@a90000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x00a90000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc 105>;
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
<37500000 300000000>,
<0 0>,
<0 0>,
<37500000 300000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
status = "disabled";
};
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sm8150-qmp-ufs-phy";
reg = <0 0x01d87000 0 0x1c0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clock-names = "ref",
"ref_aux";
clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
status = "disabled";
ufs_mem_phy_lanes: lanes@1d87400 {
reg = <0 0x01d87400 0 0x108>,
<0 0x01d87600 0 0x1e0>,
<0 0x01d87c00 0 0x1dc>,
<0 0x01d87800 0 0x108>,
<0 0x01d87a00 0 0x1e0>;
#phy-cells = <0>;
};
};
tcsr_mutex_regs: syscon@1f40000 {
compatible = "syscon";
reg = <0x0 0x01f40000 0x0 0x40000>;
};
remoteproc_slpi: remoteproc@2400000 {
compatible = "qcom,sm8150-slpi-pas";
reg = <0x0 0x02400000 0x0 0x4040>;
interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
<&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
<&rpmhpd 3>,
<&rpmhpd 2>;
power-domain-names = "load_state", "lcx", "lmx";
memory-region = <&slpi_mem>;
qcom,smem-states = <&slpi_smp2p_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
label = "dsps";
qcom,remote-pid = <3>;
mboxes = <&apss_shared 24>;
};
};
tlmm: pinctrl@3100000 {
compatible = "qcom,sm8150-pinctrl";
reg = <0x0 0x03100000 0x0 0x300000>,
......@@ -343,6 +553,74 @@ tlmm: pinctrl@3100000 {
#interrupt-cells = <2>;
};
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sm8150-mpss-pas";
reg = <0x0 0x04080000 0x0 0x4040>;
interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack", "shutdown-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
<&rpmhpd 7>,
<&rpmhpd 0>;
power-domain-names = "load_state", "cx", "mss";
memory-region = <&mpss_mem>;
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
glink-edge {
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
label = "modem";
qcom,remote-pid = <1>;
mboxes = <&apss_shared 12>;
};
};
remoteproc_cdsp: remoteproc@8300000 {
compatible = "qcom,sm8150-cdsp-pas";
reg = <0x0 0x08300000 0x0 0x4040>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
<&rpmhpd 7>;
power-domain-names = "load_state", "cx";
memory-region = <&cdsp_mem>;
qcom,smem-states = <&cdsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
label = "cdsp";
qcom,remote-pid = <5>;
mboxes = <&apss_shared 4>;
};
};
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sm8150-aoss-qmp";
reg = <0x0 0x0c300000 0x0 0x100000>;
......@@ -372,6 +650,40 @@ spmi_bus: spmi@c440000 {
cell-index = <0>;
};
remoteproc_adsp: remoteproc@17300000 {
compatible = "qcom,sm8150-adsp-pas";
reg = <0x0 0x17300000 0x0 0x4040>;
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
<&rpmhpd 7>;
power-domain-names = "load_state", "cx";
memory-region = <&adsp_mem>;
qcom,smem-states = <&adsp_smp2p_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
label = "lpass";
qcom,remote-pid = <2>;
mboxes = <&apss_shared 8>;
};
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
interrupt-controller;
......@@ -387,6 +699,12 @@ apss_shared: mailbox@17c00000 {
#mbox-cells = <1>;
};
watchdog@17c10000 {
compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
};
timer@17c20000 {
#address-cells = <2>;
#size-cells = <2>;
......@@ -469,6 +787,73 @@ rpmhcc: clock-controller {
clock-names = "xo";
clocks = <&xo_board>;
};
rpmhpd: power-controller {
compatible = "qcom,sm8150-rpmhpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmhpd_opp_table>;
rpmhpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmhpd_opp_ret: opp1 {
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
};
rpmhpd_opp_min_svs: opp2 {
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
};
rpmhpd_opp_low_svs: opp3 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
};
rpmhpd_opp_svs: opp4 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};
rpmhpd_opp_svs_l1: opp5 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};
rpmhpd_opp_svs_l2: opp6 {
opp-level = <224>;
};
rpmhpd_opp_nom: opp7 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
};
rpmhpd_opp_nom_l1: opp8 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
};
rpmhpd_opp_nom_l2: opp9 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
};
rpmhpd_opp_turbo: opp10 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
};
rpmhpd_opp_turbo_l1: opp11 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
};
};
};
};
cpufreq_hw: cpufreq@18323000 {
compatible = "qcom,cpufreq-hw";
reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
<0 0x18327800 0 0x1400>;
reg-names = "freq-domain0", "freq-domain1",
"freq-domain2";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
};
};
......
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