Skip to content

L
linux
Commit 31192234 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Stephen Boyd
Browse files
Options

clk: qcom: gcc-sm8250: use parent_hws where possible 

Switch to using parent_hws instead of parent_data when parents are
defined in this driver and so accessible using clk_hw.
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-24-dmitry.baryshkov@linaro.orgSigned-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 6326cc38
Hide whitespace changes
Inline Side-by-side
Showing with 126 additions and 126 deletions
drivers/clk/qcom/gcc-sm8250.c
View file @ 31192234
...@@ -63,8 +63,8 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = { ...@@ -63,8 +63,8 @@ static struct clk_alpha_pll_postdiv gpll0_out_even = {
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gpll0_out_even", .name = "gpll0_out_even",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gpll0.clkr.hw, &gpll0.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_ops, .ops = &clk_alpha_pll_postdiv_lucid_ops,
...@@ -1015,8 +1015,8 @@ static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = { ...@@ -1015,8 +1015,8 @@ static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = {
.width = 4, .width = 4,
.clkr.hw.init = &(struct clk_init_data) { .clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_cpuss_ahb_postdiv_clk_src", .name = "gcc_cpuss_ahb_postdiv_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_cpuss_ahb_clk_src.clkr.hw, &gcc_cpuss_ahb_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1030,8 +1030,8 @@ static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { ...@@ -1030,8 +1030,8 @@ static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
.width = 2, .width = 2,
.clkr.hw.init = &(struct clk_init_data) { .clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1045,8 +1045,8 @@ static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = { ...@@ -1045,8 +1045,8 @@ static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = {
.width = 2, .width = 2,
.clkr.hw.init = &(struct clk_init_data) { .clkr.hw.init = &(struct clk_init_data) {
.name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src", .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1077,8 +1077,8 @@ static struct clk_branch gcc_aggre_ufs_card_axi_clk = { ...@@ -1077,8 +1077,8 @@ static struct clk_branch gcc_aggre_ufs_card_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_card_axi_clk", .name = "gcc_aggre_ufs_card_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_card_axi_clk_src.clkr.hw, &gcc_ufs_card_axi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1097,8 +1097,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { ...@@ -1097,8 +1097,8 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_aggre_ufs_phy_axi_clk", .name = "gcc_aggre_ufs_phy_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, &gcc_ufs_phy_axi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1115,8 +1115,8 @@ static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { ...@@ -1115,8 +1115,8 @@ static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_prim_axi_clk", .name = "gcc_aggre_usb3_prim_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb30_prim_master_clk_src.clkr.hw, &gcc_usb30_prim_master_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1133,8 +1133,8 @@ static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { ...@@ -1133,8 +1133,8 @@ static struct clk_branch gcc_aggre_usb3_sec_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_aggre_usb3_sec_axi_clk", .name = "gcc_aggre_usb3_sec_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb30_sec_master_clk_src.clkr.hw, &gcc_usb30_sec_master_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1205,8 +1205,8 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { ...@@ -1205,8 +1205,8 @@ static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_prim_axi_clk", .name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb30_prim_master_clk_src.clkr.hw, &gcc_usb30_prim_master_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1223,8 +1223,8 @@ static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { ...@@ -1223,8 +1223,8 @@ static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_cfg_noc_usb3_sec_axi_clk", .name = "gcc_cfg_noc_usb3_sec_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb30_sec_master_clk_src.clkr.hw, &gcc_usb30_sec_master_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1241,8 +1241,8 @@ static struct clk_branch gcc_cpuss_ahb_clk = { ...@@ -1241,8 +1241,8 @@ static struct clk_branch gcc_cpuss_ahb_clk = {
.enable_mask = BIT(21), .enable_mask = BIT(21),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk", .name = "gcc_cpuss_ahb_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
...@@ -1337,8 +1337,8 @@ static struct clk_branch gcc_gp1_clk = { ...@@ -1337,8 +1337,8 @@ static struct clk_branch gcc_gp1_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk", .name = "gcc_gp1_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_gp1_clk_src.clkr.hw, &gcc_gp1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1355,8 +1355,8 @@ static struct clk_branch gcc_gp2_clk = { ...@@ -1355,8 +1355,8 @@ static struct clk_branch gcc_gp2_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk", .name = "gcc_gp2_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_gp2_clk_src.clkr.hw, &gcc_gp2_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1373,8 +1373,8 @@ static struct clk_branch gcc_gp3_clk = { ...@@ -1373,8 +1373,8 @@ static struct clk_branch gcc_gp3_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk", .name = "gcc_gp3_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_gp3_clk_src.clkr.hw, &gcc_gp3_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1390,8 +1390,8 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = { ...@@ -1390,8 +1390,8 @@ static struct clk_branch gcc_gpu_gpll0_clk_src = {
.enable_mask = BIT(15), .enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_clk_src", .name = "gcc_gpu_gpll0_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gpll0.clkr.hw, &gpll0.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1407,8 +1407,8 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = { ...@@ -1407,8 +1407,8 @@ static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
.enable_mask = BIT(16), .enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_gpu_gpll0_div_clk_src", .name = "gcc_gpu_gpll0_div_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gpll0_out_even.clkr.hw, &gpll0_out_even.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1530,8 +1530,8 @@ static struct clk_branch gcc_npu_gpll0_clk_src = { ...@@ -1530,8 +1530,8 @@ static struct clk_branch gcc_npu_gpll0_clk_src = {
.enable_mask = BIT(18), .enable_mask = BIT(18),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_npu_gpll0_clk_src", .name = "gcc_npu_gpll0_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gpll0.clkr.hw, &gpll0.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1547,8 +1547,8 @@ static struct clk_branch gcc_npu_gpll0_div_clk_src = { ...@@ -1547,8 +1547,8 @@ static struct clk_branch gcc_npu_gpll0_div_clk_src = {
.enable_mask = BIT(19), .enable_mask = BIT(19),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_npu_gpll0_div_clk_src", .name = "gcc_npu_gpll0_div_clk_src",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gpll0_out_even.clkr.hw, &gpll0_out_even.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1565,8 +1565,8 @@ static struct clk_branch gcc_pcie0_phy_refgen_clk = { ...@@ -1565,8 +1565,8 @@ static struct clk_branch gcc_pcie0_phy_refgen_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie0_phy_refgen_clk", .name = "gcc_pcie0_phy_refgen_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_pcie_phy_refgen_clk_src.clkr.hw, &gcc_pcie_phy_refgen_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1583,8 +1583,8 @@ static struct clk_branch gcc_pcie1_phy_refgen_clk = { ...@@ -1583,8 +1583,8 @@ static struct clk_branch gcc_pcie1_phy_refgen_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie1_phy_refgen_clk", .name = "gcc_pcie1_phy_refgen_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_pcie_phy_refgen_clk_src.clkr.hw, &gcc_pcie_phy_refgen_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1601,8 +1601,8 @@ static struct clk_branch gcc_pcie2_phy_refgen_clk = { ...@@ -1601,8 +1601,8 @@ static struct clk_branch gcc_pcie2_phy_refgen_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie2_phy_refgen_clk", .name = "gcc_pcie2_phy_refgen_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_pcie_phy_refgen_clk_src.clkr.hw, &gcc_pcie_phy_refgen_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1619,8 +1619,8 @@ static struct clk_branch gcc_pcie_0_aux_clk = { ...@@ -1619,8 +1619,8 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
.enable_mask = BIT(3), .enable_mask = BIT(3),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk", .name = "gcc_pcie_0_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_pcie_0_aux_clk_src.clkr.hw, &gcc_pcie_0_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1706,8 +1706,8 @@ static struct clk_branch gcc_pcie_1_aux_clk = { ...@@ -1706,8 +1706,8 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
.enable_mask = BIT(29), .enable_mask = BIT(29),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk", .name = "gcc_pcie_1_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_pcie_1_aux_clk_src.clkr.hw, &gcc_pcie_1_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1793,8 +1793,8 @@ static struct clk_branch gcc_pcie_2_aux_clk = { ...@@ -1793,8 +1793,8 @@ static struct clk_branch gcc_pcie_2_aux_clk = {
.enable_mask = BIT(14), .enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_2_aux_clk", .name = "gcc_pcie_2_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_pcie_2_aux_clk_src.clkr.hw, &gcc_pcie_2_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1893,8 +1893,8 @@ static struct clk_branch gcc_pcie_phy_aux_clk = { ...@@ -1893,8 +1893,8 @@ static struct clk_branch gcc_pcie_phy_aux_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pcie_phy_aux_clk", .name = "gcc_pcie_phy_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_pcie_0_aux_clk_src.clkr.hw, &gcc_pcie_0_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -1937,8 +1937,8 @@ static struct clk_branch gcc_pdm2_clk = { ...@@ -1937,8 +1937,8 @@ static struct clk_branch gcc_pdm2_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk", .name = "gcc_pdm2_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_pdm2_clk_src.clkr.hw, &gcc_pdm2_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2097,8 +2097,8 @@ static struct clk_branch gcc_qupv3_wrap0_s0_clk = { ...@@ -2097,8 +2097,8 @@ static struct clk_branch gcc_qupv3_wrap0_s0_clk = {
.enable_mask = BIT(10), .enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk", .name = "gcc_qupv3_wrap0_s0_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, &gcc_qupv3_wrap0_s0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2115,8 +2115,8 @@ static struct clk_branch gcc_qupv3_wrap0_s1_clk = { ...@@ -2115,8 +2115,8 @@ static struct clk_branch gcc_qupv3_wrap0_s1_clk = {
.enable_mask = BIT(11), .enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk", .name = "gcc_qupv3_wrap0_s1_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, &gcc_qupv3_wrap0_s1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2133,8 +2133,8 @@ static struct clk_branch gcc_qupv3_wrap0_s2_clk = { ...@@ -2133,8 +2133,8 @@ static struct clk_branch gcc_qupv3_wrap0_s2_clk = {
.enable_mask = BIT(12), .enable_mask = BIT(12),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk", .name = "gcc_qupv3_wrap0_s2_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, &gcc_qupv3_wrap0_s2_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2151,8 +2151,8 @@ static struct clk_branch gcc_qupv3_wrap0_s3_clk = { ...@@ -2151,8 +2151,8 @@ static struct clk_branch gcc_qupv3_wrap0_s3_clk = {
.enable_mask = BIT(13), .enable_mask = BIT(13),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk", .name = "gcc_qupv3_wrap0_s3_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, &gcc_qupv3_wrap0_s3_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2169,8 +2169,8 @@ static struct clk_branch gcc_qupv3_wrap0_s4_clk = { ...@@ -2169,8 +2169,8 @@ static struct clk_branch gcc_qupv3_wrap0_s4_clk = {
.enable_mask = BIT(14), .enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk", .name = "gcc_qupv3_wrap0_s4_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, &gcc_qupv3_wrap0_s4_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2187,8 +2187,8 @@ static struct clk_branch gcc_qupv3_wrap0_s5_clk = { ...@@ -2187,8 +2187,8 @@ static struct clk_branch gcc_qupv3_wrap0_s5_clk = {
.enable_mask = BIT(15), .enable_mask = BIT(15),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk", .name = "gcc_qupv3_wrap0_s5_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, &gcc_qupv3_wrap0_s5_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2205,8 +2205,8 @@ static struct clk_branch gcc_qupv3_wrap0_s6_clk = { ...@@ -2205,8 +2205,8 @@ static struct clk_branch gcc_qupv3_wrap0_s6_clk = {
.enable_mask = BIT(16), .enable_mask = BIT(16),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s6_clk", .name = "gcc_qupv3_wrap0_s6_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, &gcc_qupv3_wrap0_s6_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2223,8 +2223,8 @@ static struct clk_branch gcc_qupv3_wrap0_s7_clk = { ...@@ -2223,8 +2223,8 @@ static struct clk_branch gcc_qupv3_wrap0_s7_clk = {
.enable_mask = BIT(17), .enable_mask = BIT(17),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s7_clk", .name = "gcc_qupv3_wrap0_s7_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, &gcc_qupv3_wrap0_s7_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2267,8 +2267,8 @@ static struct clk_branch gcc_qupv3_wrap1_s0_clk = { ...@@ -2267,8 +2267,8 @@ static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.enable_mask = BIT(22), .enable_mask = BIT(22),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk", .name = "gcc_qupv3_wrap1_s0_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, &gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2285,8 +2285,8 @@ static struct clk_branch gcc_qupv3_wrap1_s1_clk = { ...@@ -2285,8 +2285,8 @@ static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.enable_mask = BIT(23), .enable_mask = BIT(23),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk", .name = "gcc_qupv3_wrap1_s1_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, &gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2303,8 +2303,8 @@ static struct clk_branch gcc_qupv3_wrap1_s2_clk = { ...@@ -2303,8 +2303,8 @@ static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.enable_mask = BIT(24), .enable_mask = BIT(24),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk", .name = "gcc_qupv3_wrap1_s2_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, &gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2321,8 +2321,8 @@ static struct clk_branch gcc_qupv3_wrap1_s3_clk = { ...@@ -2321,8 +2321,8 @@ static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.enable_mask = BIT(25), .enable_mask = BIT(25),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk", .name = "gcc_qupv3_wrap1_s3_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, &gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2339,8 +2339,8 @@ static struct clk_branch gcc_qupv3_wrap1_s4_clk = { ...@@ -2339,8 +2339,8 @@ static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.enable_mask = BIT(26), .enable_mask = BIT(26),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk", .name = "gcc_qupv3_wrap1_s4_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, &gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2357,8 +2357,8 @@ static struct clk_branch gcc_qupv3_wrap1_s5_clk = { ...@@ -2357,8 +2357,8 @@ static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.enable_mask = BIT(27), .enable_mask = BIT(27),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk", .name = "gcc_qupv3_wrap1_s5_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, &gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2401,8 +2401,8 @@ static struct clk_branch gcc_qupv3_wrap2_s0_clk = { ...@@ -2401,8 +2401,8 @@ static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
.enable_mask = BIT(4), .enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s0_clk", .name = "gcc_qupv3_wrap2_s0_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, &gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2419,8 +2419,8 @@ static struct clk_branch gcc_qupv3_wrap2_s1_clk = { ...@@ -2419,8 +2419,8 @@ static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
.enable_mask = BIT(5), .enable_mask = BIT(5),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s1_clk", .name = "gcc_qupv3_wrap2_s1_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, &gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2437,8 +2437,8 @@ static struct clk_branch gcc_qupv3_wrap2_s2_clk = { ...@@ -2437,8 +2437,8 @@ static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
.enable_mask = BIT(6), .enable_mask = BIT(6),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s2_clk", .name = "gcc_qupv3_wrap2_s2_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, &gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2455,8 +2455,8 @@ static struct clk_branch gcc_qupv3_wrap2_s3_clk = { ...@@ -2455,8 +2455,8 @@ static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
.enable_mask = BIT(7), .enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s3_clk", .name = "gcc_qupv3_wrap2_s3_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, &gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2473,8 +2473,8 @@ static struct clk_branch gcc_qupv3_wrap2_s4_clk = { ...@@ -2473,8 +2473,8 @@ static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
.enable_mask = BIT(8), .enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s4_clk", .name = "gcc_qupv3_wrap2_s4_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, &gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2491,8 +2491,8 @@ static struct clk_branch gcc_qupv3_wrap2_s5_clk = { ...@@ -2491,8 +2491,8 @@ static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
.enable_mask = BIT(9), .enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s5_clk", .name = "gcc_qupv3_wrap2_s5_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, &gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2606,8 +2606,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = { ...@@ -2606,8 +2606,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk", .name = "gcc_sdcc2_apps_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_sdcc2_apps_clk_src.clkr.hw, &gcc_sdcc2_apps_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2637,8 +2637,8 @@ static struct clk_branch gcc_sdcc4_apps_clk = { ...@@ -2637,8 +2637,8 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk", .name = "gcc_sdcc4_apps_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_sdcc4_apps_clk_src.clkr.hw, &gcc_sdcc4_apps_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2681,8 +2681,8 @@ static struct clk_branch gcc_tsif_ref_clk = { ...@@ -2681,8 +2681,8 @@ static struct clk_branch gcc_tsif_ref_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ref_clk", .name = "gcc_tsif_ref_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_tsif_ref_clk_src.clkr.hw, &gcc_tsif_ref_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2729,8 +2729,8 @@ static struct clk_branch gcc_ufs_card_axi_clk = { ...@@ -2729,8 +2729,8 @@ static struct clk_branch gcc_ufs_card_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_axi_clk", .name = "gcc_ufs_card_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_card_axi_clk_src.clkr.hw, &gcc_ufs_card_axi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2749,8 +2749,8 @@ static struct clk_branch gcc_ufs_card_ice_core_clk = { ...@@ -2749,8 +2749,8 @@ static struct clk_branch gcc_ufs_card_ice_core_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ice_core_clk", .name = "gcc_ufs_card_ice_core_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_card_ice_core_clk_src.clkr.hw, &gcc_ufs_card_ice_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2769,8 +2769,8 @@ static struct clk_branch gcc_ufs_card_phy_aux_clk = { ...@@ -2769,8 +2769,8 @@ static struct clk_branch gcc_ufs_card_phy_aux_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_phy_aux_clk", .name = "gcc_ufs_card_phy_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_card_phy_aux_clk_src.clkr.hw, &gcc_ufs_card_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2828,8 +2828,8 @@ static struct clk_branch gcc_ufs_card_unipro_core_clk = { ...@@ -2828,8 +2828,8 @@ static struct clk_branch gcc_ufs_card_unipro_core_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_unipro_core_clk", .name = "gcc_ufs_card_unipro_core_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_card_unipro_core_clk_src.clkr.hw, &gcc_ufs_card_unipro_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2863,8 +2863,8 @@ static struct clk_branch gcc_ufs_phy_axi_clk = { ...@@ -2863,8 +2863,8 @@ static struct clk_branch gcc_ufs_phy_axi_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk", .name = "gcc_ufs_phy_axi_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, &gcc_ufs_phy_axi_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2883,8 +2883,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = { ...@@ -2883,8 +2883,8 @@ static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk", .name = "gcc_ufs_phy_ice_core_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, &gcc_ufs_phy_ice_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2903,8 +2903,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = { ...@@ -2903,8 +2903,8 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk", .name = "gcc_ufs_phy_phy_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, &gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2962,8 +2962,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = { ...@@ -2962,8 +2962,8 @@ static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk", .name = "gcc_ufs_phy_unipro_core_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, &gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -2980,8 +2980,8 @@ static struct clk_branch gcc_usb30_prim_master_clk = { ...@@ -2980,8 +2980,8 @@ static struct clk_branch gcc_usb30_prim_master_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk", .name = "gcc_usb30_prim_master_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb30_prim_master_clk_src.clkr.hw, &gcc_usb30_prim_master_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3030,8 +3030,8 @@ static struct clk_branch gcc_usb30_sec_master_clk = { ...@@ -3030,8 +3030,8 @@ static struct clk_branch gcc_usb30_sec_master_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk", .name = "gcc_usb30_sec_master_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb30_sec_master_clk_src.clkr.hw, &gcc_usb30_sec_master_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3080,8 +3080,8 @@ static struct clk_branch gcc_usb3_prim_phy_aux_clk = { ...@@ -3080,8 +3080,8 @@ static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk", .name = "gcc_usb3_prim_phy_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3098,8 +3098,8 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { ...@@ -3098,8 +3098,8 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_com_aux_clk", .name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, &gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3142,8 +3142,8 @@ static struct clk_branch gcc_usb3_sec_phy_aux_clk = { ...@@ -3142,8 +3142,8 @@ static struct clk_branch gcc_usb3_sec_phy_aux_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_aux_clk", .name = "gcc_usb3_sec_phy_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
...@@ -3160,8 +3160,8 @@ static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { ...@@ -3160,8 +3160,8 @@ static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = {
.enable_mask = BIT(0), .enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_com_aux_clk", .name = "gcc_usb3_sec_phy_com_aux_clk",
.parent_data = &(const struct clk_parent_data){ .parent_hws = (const struct clk_hw*[]){
.hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, &gcc_usb3_sec_phy_aux_clk_src.clkr.hw,
}, },
.num_parents = 1, .num_parents = 1,
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7