Commit 332ef7c8 authored by Alex Elder's avatar Alex Elder Committed by David S. Miller

net: ipa: ignore endianness if there is no header

If we program an RX endpoint to have no header (header length is 0),
header-related endpoint configuration values are meaningless and are
ignored.

The only case we support that defines a header is QMAP endpoints.
In ipa_endpoint_init_hdr_ext() we set the endianness mask value
unconditionally, but it should not be done if there is no header
(meaning it is not configured for QMAP).

Set the endianness conditionally, and rearrange the logic in that
function slightly to avoid testing the qmap flag twice.

Delete an incorrect comment in ipa_endpoint_init_aggr().
Signed-off-by: default avatarAlex Elder <elder@linaro.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent c9d92cf2
...@@ -587,20 +587,24 @@ static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint) ...@@ -587,20 +587,24 @@ static void ipa_endpoint_init_hdr_ext(struct ipa_endpoint *endpoint)
struct ipa *ipa = endpoint->ipa; struct ipa *ipa = endpoint->ipa;
u32 val = 0; u32 val = 0;
if (endpoint->data->qmap) {
/* We have a header, so we must specify its endianness */
val |= HDR_ENDIANNESS_FMASK; /* big endian */ val |= HDR_ENDIANNESS_FMASK; /* big endian */
/* A QMAP header contains a 6 bit pad field at offset 0. The RMNet /* A QMAP header contains a 6 bit pad field at offset 0.
* driver assumes this field is meaningful in packets it receives, * The RMNet driver assumes this field is meaningful in
* and assumes the header's payload length includes that padding. * packets it receives, and assumes the header's payload
* The RMNet driver does *not* pad packets it sends, however, so * length includes that padding. The RMNet driver does
* the pad field (although 0) should be ignored. * *not* pad packets it sends, however, so the pad field
* (although 0) should be ignored.
*/ */
if (endpoint->data->qmap && !endpoint->toward_ipa) { if (!endpoint->toward_ipa) {
val |= HDR_TOTAL_LEN_OR_PAD_VALID_FMASK; val |= HDR_TOTAL_LEN_OR_PAD_VALID_FMASK;
/* HDR_TOTAL_LEN_OR_PAD is 0 (pad, not total_len) */ /* HDR_TOTAL_LEN_OR_PAD is 0 (pad, not total_len) */
val |= HDR_PAYLOAD_LEN_INC_PADDING_FMASK; val |= HDR_PAYLOAD_LEN_INC_PADDING_FMASK;
/* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0 */ /* HDR_TOTAL_LEN_OR_PAD_OFFSET is 0 */
} }
}
/* HDR_PAYLOAD_LEN_INC_PADDING is 0 */ /* HDR_PAYLOAD_LEN_INC_PADDING is 0 */
if (!endpoint->toward_ipa) if (!endpoint->toward_ipa)
...@@ -759,8 +763,6 @@ static void ipa_endpoint_init_aggr(struct ipa_endpoint *endpoint) ...@@ -759,8 +763,6 @@ static void ipa_endpoint_init_aggr(struct ipa_endpoint *endpoint)
close_eof = rx_data->aggr_close_eof; close_eof = rx_data->aggr_close_eof;
val |= aggr_sw_eof_active_encoded(version, close_eof); val |= aggr_sw_eof_active_encoded(version, close_eof);
/* AGGR_HARD_BYTE_LIMIT_ENABLE is 0 */
} else { } else {
val |= u32_encode_bits(IPA_ENABLE_DEAGGR, val |= u32_encode_bits(IPA_ENABLE_DEAGGR,
AGGR_EN_FMASK); AGGR_EN_FMASK);
......
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