Commit 35891d40 authored by Michael Ellerman's avatar Michael Ellerman

Merge remote-tracking branch 'scottwood/next' into next

Scott says:

"Highlights include a bunch of 8xx optimizations, device tree bindings
for Freescale BMan, QMan, and FMan datapath components, misc device tree
updates, and inbound rio window support."
parents 80fa93fc 76f3e292
......@@ -62,6 +62,8 @@ Required properties:
It takes parent's clock-frequency as its clock.
* "fsl,qoriq-sysclk-2.0": for input system clock (v2.0).
It takes parent's clock-frequency as its clock.
* "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
* "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
- #clock-cells: From common clock binding. The number of cells in a
clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
......@@ -128,8 +130,16 @@ Example for clock block and clock provider:
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux1";
};
platform-pll: platform-pll@c00 {
#clock-cells = <1>;
reg = <0xc00 0x4>;
compatible = "fsl,qoriq-platform-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "platform-pll", "platform-pll-div2";
};
};
}
};
Example for clock consumer:
......@@ -139,4 +149,4 @@ Example for clock consumer:
clocks = <&mux0>;
...
};
}
};
=============================================================================
Freescale Frame Manager Device Bindings
CONTENTS
- FMan Node
- FMan Port Node
- FMan MURAM Node
- FMan dTSEC/XGEC/mEMAC Node
- FMan IEEE 1588 Node
- Example
=============================================================================
FMan Node
DESCRIPTION
Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
etc.) the FMan node will have child nodes for each of them.
PROPERTIES
- compatible
Usage: required
Value type: <stringlist>
Definition: Must include "fsl,fman"
FMan version can be determined via FM_IP_REV_1 register in the
FMan block. The offset is 0xc4 from the beginning of the
Frame Processing Manager memory map (0xc3000 from the
beginning of the FMan node).
- cell-index
Usage: required
Value type: <u32>
Definition: Specifies the index of the FMan unit.
The cell-index value may be used by the SoC, to identify the
FMan unit in the SoC memory map. In the table bellow,
there's a description of the cell-index use in each SoC:
- P1023:
register[bit] FMan unit cell-index
============================================================
DEVDISR[1] 1 0
- P2041, P3041, P4080 P5020, P5040:
register[bit] FMan unit cell-index
============================================================
DCFG_DEVDISR2[6] 1 0
DCFG_DEVDISR2[14] 2 1
(Second FM available only in P4080 and P5040)
- B4860, T1040, T2080, T4240:
register[bit] FMan unit cell-index
============================================================
DCFG_CCSR_DEVDISR2[24] 1 0
DCFG_CCSR_DEVDISR2[25] 2 1
(Second FM available only in T4240)
DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
the specific SoC "Device Configuration/Pin Control" Memory
Map.
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property. Specifies the offset of the
following configuration registers:
- BMI configuration registers.
- QMI configuration registers.
- DMA configuration registers.
- FPM configuration registers.
- FMan controller configuration registers.
- ranges
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property.
- clocks
Usage: required
Value type: <prop-encoded-array>
Definition: phandle for the fman input clock.
- clock-names
usage: required
Value type: <stringlist>
Definition: "fmanclk" for the fman input clock.
- interrupts
Usage: required
Value type: <prop-encoded-array>
Definition: A pair of IRQs are specified in this property.
The first element is associated with the event interrupts and
the second element is associated with the error interrupts.
- fsl,qman-channel-range
Usage: required
Value type: <prop-encoded-array>
Definition: Specifies the range of the available dedicated
channels in the FMan. The first cell specifies the beginning
of the range and the second cell specifies the number of
channels.
Further information available at:
"Work Queue (WQ) Channel Assignments in the QMan" section
in DPAA Reference Manual.
- fsl,qman
- fsl,bman
Usage: required
Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt
=============================================================================
FMan MURAM Node
DESCRIPTION
FMan Internal memory - shared between all the FMan modules.
It contains data structures that are common and written to or read by
the modules.
FMan internal memory is split into the following parts:
Packet buffering (Tx/Rx FIFOs)
Frames internal context
PROPERTIES
- compatible
Usage: required
Value type: <stringlist>
Definition: Must include "fsl,fman-muram"
- ranges
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property.
Specifies the multi-user memory offset and the size within
the FMan.
EXAMPLE
muram@0 {
compatible = "fsl,fman-muram";
ranges = <0 0x000000 0x28000>;
};
=============================================================================
FMan Port Node
DESCRIPTION
The Frame Manager (FMan) supports several types of hardware ports:
Ethernet receiver (RX)
Ethernet transmitter (TX)
Offline/Host command (O/H)
PROPERTIES
- compatible
Usage: required
Value type: <stringlist>
Definition: A standard property.
Must include one of the following:
- "fsl,fman-v2-port-oh" for FManV2 OH ports
- "fsl,fman-v2-port-rx" for FManV2 RX ports
- "fsl,fman-v2-port-tx" for FManV2 TX ports
- "fsl,fman-v3-port-oh" for FManV3 OH ports
- "fsl,fman-v3-port-rx" for FManV3 RX ports
- "fsl,fman-v3-port-tx" for FManV3 TX ports
- cell-index
Usage: required
Value type: <u32>
Definition: Specifies the hardware port id.
Each hardware port on the FMan has its own hardware PortID.
Super set of all hardware Port IDs available at FMan Reference
Manual under "FMan Hardware Ports in Freescale Devices" table.
Each hardware port is assigned a 4KB, port-specific page in
the FMan hardware port memory region (which is part of the
FMan memory map). The first 4 KB in the FMan hardware ports
memory region is used for what are called common registers.
The subsequent 63 4KB pages are allocated to the hardware
ports.
The page of a specific port is determined by the cell-index.
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: There is one reg region describing the port
configuration registers.
EXAMPLE
port@a8000 {
cell-index = <0x28>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xa8000 0x1000>;
};
port@88000 {
cell-index = <0x8>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x88000 0x1000>;
};
port@81000 {
cell-index = <0x1>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x81000 0x1000>;
};
=============================================================================
FMan dTSEC/XGEC/mEMAC Node
DESCRIPTION
mEMAC/dTSEC/XGEC are the Ethernet network interfaces
PROPERTIES
- compatible
Usage: required
Value type: <stringlist>
Definition: A standard property.
Must include one of the following:
- "fsl,fman-dtsec" for dTSEC MAC
- "fsl,fman-xgec" for XGEC MAC
- "fsl,fman-memac for mEMAC MAC
- cell-index
Usage: required
Value type: <u32>
Definition: Specifies the MAC id.
The cell-index value may be used by the FMan or the SoC, to
identify the MAC unit in the FMan (or SoC) memory map.
In the tables bellow there's a description of the cell-index
use, there are two tables, one describes the use of cell-index
by the FMan, the second describes the use by the SoC:
1. FMan Registers
FManV2:
register[bit] MAC cell-index
============================================================
FM_EPI[16] XGEC 8
FM_EPI[16+n] dTSECn n-1
FM_NPI[11+n] dTSECn n-1
n = 1,..,5
FManV3:
register[bit] MAC cell-index
============================================================
FM_EPI[16+n] mEMACn n-1
FM_EPI[25] mEMAC10 9
FM_NPI[11+n] mEMACn n-1
FM_NPI[10] mEMAC10 9
FM_NPI[11] mEMAC9 8
n = 1,..8
FM_EPI and FM_NPI are located in the FMan memory map.
2. SoC registers:
- P2041, P3041, P4080 P5020, P5040:
register[bit] FMan MAC cell
Unit index
============================================================
DCFG_DEVDISR2[7] 1 XGEC 8
DCFG_DEVDISR2[7+n] 1 dTSECn n-1
DCFG_DEVDISR2[15] 2 XGEC 8
DCFG_DEVDISR2[15+n] 2 dTSECn n-1
n = 1,..5
- T1040, T2080, T4240, B4860:
register[bit] FMan MAC cell
Unit index
============================================================
DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1
DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1
n = 1,..6,9,10
EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
the specific SoC "Device Configuration/Pin Control" Memory
Map.
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property.
- fsl,fman-ports
Usage: required
Value type: <prop-encoded-array>
Definition: An array of two phandles - the first references is
the FMan RX port and the second is the TX port used by this
MAC.
- ptp-timer
Usage required
Value type: <phandle>
Definition: A phandle for 1EEE1588 timer.
EXAMPLE
fman1_tx28: port@a8000 {
cell-index = <0x28>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xa8000 0x1000>;
};
fman1_rx8: port@88000 {
cell-index = <0x8>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x88000 0x1000>;
};
ptp-timer: ptp_timer@fe000 {
compatible = "fsl,fman-ptp-timer";
reg = <0xfe000 0x1000>;
};
ethernet@e0000 {
compatible = "fsl,fman-dtsec";
cell-index = <0>;
reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman1_rx8 &fman1_tx28>;
ptp-timer = <&ptp-timer>;
};
============================================================================
FMan IEEE 1588 Node
DESCRIPTION
The FMan interface to support IEEE 1588
PROPERTIES
- compatible
Usage: required
Value type: <stringlist>
Definition: A standard property.
Must include "fsl,fman-ptp-timer".
- reg
Usage: required
Value type: <prop-encoded-array>
Definition: A standard property.
EXAMPLE
ptp-timer@fe000 {
compatible = "fsl,fman-ptp-timer";
reg = <0xfe000 0x1000>;
};
=============================================================================
Example
fman@400000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
compatible = "fsl,fman"
ranges = <0 0x400000 0x100000>;
reg = <0x400000 0x100000>;
clocks = <&fman_clk>;
clock-names = "fmanclk";
interrupts = <
96 2 0 0
16 2 1 1>;
fsl,qman-channel-range = <0x40 0xc>;
muram@0 {
compatible = "fsl,fman-muram";
reg = <0x0 0x28000>;
};
port@81000 {
cell-index = <1>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x81000 0x1000>;
};
port@82000 {
cell-index = <2>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x82000 0x1000>;
};
port@83000 {
cell-index = <3>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x83000 0x1000>;
};
port@84000 {
cell-index = <4>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x84000 0x1000>;
};
port@85000 {
cell-index = <5>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x85000 0x1000>;
};
port@86000 {
cell-index = <6>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x86000 0x1000>;
};
fman1_rx_0x8: port@88000 {
cell-index = <0x8>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x88000 0x1000>;
};
fman1_rx_0x9: port@89000 {
cell-index = <0x9>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x89000 0x1000>;
};
fman1_rx_0xa: port@8a000 {
cell-index = <0xa>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x8a000 0x1000>;
};
fman1_rx_0xb: port@8b000 {
cell-index = <0xb>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x8b000 0x1000>;
};
fman1_rx_0xc: port@8c000 {
cell-index = <0xc>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x8c000 0x1000>;
};
fman1_rx_0x10: port@90000 {
cell-index = <0x10>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x90000 0x1000>;
};
fman1_tx_0x28: port@a8000 {
cell-index = <0x28>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xa8000 0x1000>;
};
fman1_tx_0x29: port@a9000 {
cell-index = <0x29>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xa9000 0x1000>;
};
fman1_tx_0x2a: port@aa000 {
cell-index = <0x2a>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xaa000 0x1000>;
};
fman1_tx_0x2b: port@ab000 {
cell-index = <0x2b>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xab000 0x1000>;
};
fman1_tx_0x2c: port@ac0000 {
cell-index = <0x2c>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xac000 0x1000>;
};
fman1_tx_0x30: port@b0000 {
cell-index = <0x30>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xb0000 0x1000>;
};
ethernet@e0000 {
compatible = "fsl,fman-dtsec";
cell-index = <0>;
reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
};
ethernet@e2000 {
compatible = "fsl,fman-dtsec";
cell-index = <1>;
reg = <0xe2000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>;
};
ethernet@e4000 {
compatible = "fsl,fman-dtsec";
cell-index = <2>;
reg = <0xe4000 0x1000>;
fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>;
};
ethernet@e6000 {
compatible = "fsl,fman-dtsec";
cell-index = <3>;
reg = <0xe6000 0x1000>;
fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>;
};
ethernet@e8000 {
compatible = "fsl,fman-dtsec";
cell-index = <4>;
reg = <0xf0000 0x1000>;
fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>;
ethernet@f0000 {
cell-index = <8>;
compatible = "fsl,fman-xgec";
reg = <0xf0000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
};
ptp-timer@fe000 {
compatible = "fsl,fman-ptp-timer";
reg = <0xfe000 0x1000>;
};
};
QorIQ DPAA Buffer Manager Portals Device Tree Binding
Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
CONTENTS
- BMan Portal
- Example
BMan Portal Node
Portals are memory mapped interfaces to BMan that allow low-latency, lock-less
interaction by software running on processor cores, accelerators and network
interfaces with the BMan
PROPERTIES
- compatible
Usage: Required
Value type: <stringlist>
Definition: Must include "fsl,bman-portal-<hardware revision>"
May include "fsl,<SoC>-bman-portal" or "fsl,bman-portal"
- reg
Usage: Required
Value type: <prop-encoded-array>
Definition: Two regions. The first is the cache-enabled region of
the portal. The second is the cache-inhibited region of
the portal
- interrupts
Usage: Required
Value type: <prop-encoded-array>
Definition: Standard property
EXAMPLE
The example below shows a (P4080) BMan portals container/bus node with two portals
bman-portals@ff4000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0 0xf 0xf4000000 0x200000>;
bman-portal@0 {
compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
reg = <0x0 0x4000>, <0x100000 0x1000>;
interrupts = <105 2 0 0>;
};
bman-portal@4000 {
compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
reg = <0x4000 0x4000>, <0x101000 0x1000>;
interrupts = <107 2 0 0>;
};
};
QorIQ DPAA Buffer Manager Device Tree Bindings
Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
CONTENTS
- BMan Node
- BMan Private Memory Node
- Example
BMan Node
The Buffer Manager is part of the Data-Path Acceleration Architecture (DPAA).
BMan supports hardware allocation and deallocation of buffers belonging to pools
originally created by software with configurable depletion thresholds. This
binding covers the CCSR space programming model
PROPERTIES
- compatible
Usage: Required
Value type: <stringlist>
Definition: Must include "fsl,bman"
May include "fsl,<SoC>-bman"
- reg
Usage: Required
Value type: <prop-encoded-array>
Definition: Registers region within the CCSR address space
The BMan revision information is located in the BMAN_IP_REV_1/2 registers which
are located at offsets 0xbf8 and 0xbfc
- interrupts
Usage: Required
Value type: <prop-encoded-array>
Definition: Standard property. The error interrupt
- fsl,liodn
Usage: See pamu.txt
Value type: <prop-encoded-array>
Definition: PAMU property used for static LIODN assignment
- fsl,iommu-parent
Usage: See pamu.txt
Value type: <phandle>
Definition: PAMU property used for dynamic LIODN assignment
For additional details about the PAMU/LIODN binding(s) see pamu.txt
Devices connected to a BMan instance via Direct Connect Portals (DCP) must link
to the respective BMan instance
- fsl,bman
Usage: Required
Value type: <prop-encoded-array>
Description: List of phandle and DCP index pairs, to the BMan instance
to which this device is connected via the DCP
BMan Private Memory Node
BMan requires a contiguous range of physical memory used for the backing store
for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as a
node under the /reserved-memory node
The BMan FBPR memory node must be named "bman-fbpr"
PROPERTIES
- compatible
Usage: required
Value type: <stringlist>
Definition: Must inclide "fsl,bman-fbpr"
The following constraints are relevant to the FBPR private memory:
- The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to
16 GiB
- The alignment must be a muliptle of the memory size
The size of the FBPR must be chosen by observing the hardware features configured
via the Reset Configuration Word (RCW) and that are relevant to a specific board
(e.g. number of MAC(s) pinned-out, number of offline/host command FMan ports,
etc.). The size configured in the DT must reflect the hardware capabilities and
not the specific needs of an application
For additional details about reserved memory regions see reserved-memory.txt
EXAMPLE
The example below shows a BMan FBPR dynamic allocation memory node
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
bman_fbpr: bman-fbpr {
compatible = "fsl,bman-fbpr";
alloc-ranges = <0 0 0xf 0xffffffff>;
size = <0 0x1000000>;
alignment = <0 0x1000000>;
};
};
The example below shows a (P4080) BMan CCSR-space node
crypto@300000 {
...
fsl,bman = <&bman, 2>;
...
};
bman: bman@31a000 {
compatible = "fsl,bman";
reg = <0x31a000 0x1000>;
interrupts = <16 2 1 2>;
fsl,liodn = <0x17>;
memory-region = <&bman_fbpr>;
};
fman@400000 {
...
fsl,bman = <&bman, 0>;
...
};
QorIQ DPAA Queue Manager Portals Device Tree Binding
Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
CONTENTS
- QMan Portal
- QMan Pool Channel
- Example
QMan Portal Node
Portals are memory mapped interfaces to QMan that allow low-latency, lock-less
interaction by software running on processor cores, accelerators and network
interfaces with the QMan
PROPERTIES
- compatible
Usage: Required
Value type: <stringlist>
Definition: Must include "fsl,qman-portal-<hardware revision>"
May include "fsl,<SoC>-qman-portal" or "fsl,qman-portal"
- reg
Usage: Required
Value type: <prop-encoded-array>
Definition: Two regions. The first is the cache-enabled region of
the portal. The second is the cache-inhibited region of
the portal
- interrupts
Usage: Required
Value type: <prop-encoded-array>
Definition: Standard property
- fsl,liodn
Usage: See pamu.txt
Value type: <prop-encoded-array>
Definition: Two LIODN(s). DQRR LIODN (DLIODN) and Frame LIODN
(FLIODN)
- fsl,iommu-parent
Usage: See pamu.txt
Value type: <phandle>
Definition: PAMU property used for dynamic LIODN assignment
For additional details about the PAMU/LIODN binding(s) see pamu.txt
- fsl,qman-channel-id
Usage: Required
Value type: <u32>
Definition: The hardware index of the channel. This can also be
determined by dividing any of the channel's 8 work queue
IDs by 8
In addition to these properties the qman-portals should have sub-nodes to
represent the HW devices/portals that are connected to the software portal
described here
The currently supported sub-nodes are:
* fman0
* fman1
* pme
* crypto
These subnodes should have the following properties:
- fsl,liodn
Usage: See pamu.txt
Value type: <prop-encoded-array>
Definition: PAMU property used for static LIODN assignment
- fsl,iommu-parent
Usage: See pamu.txt
Value type: <phandle>
Definition: PAMU property used for dynamic LIODN assignment
- dev-handle
Usage: Required
Value type: <phandle>
Definition: The phandle to the particular hardware device that this
portal is connected to.
DPAA QMan Pool Channel Nodes
Pool Channels are defined with the following properties.
PROPERTIES
- compatible
Usage: Required
Value type: <stringlist>
Definition: Must include "fsl,qman-pool-channel"
May include "fsl,<SoC>-qman-pool-channel"
- fsl,qman-channel-id
Usage: Required
Value type: <u32>
Definition: The hardware index of the channel. This can also be
determined by dividing any of the channel's 8 work queue
IDs by 8
EXAMPLE
The example below shows a (P4080) QMan portals container/bus node with two portals
qman-portals@ff4200000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges = <0 0xf 0xf4200000 0x200000>;
qman-portal@0 {
compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";
reg = <0 0x4000>, <0x100000 0x1000>;
interrupts = <104 2 0 0>;
fsl,liodn = <1 2>;
fsl,qman-channel-id = <0>;
fman0 {
fsl,liodn = <0x21>;
dev-handle = <&fman0>;
};
fman1 {
fsl,liodn = <0xa1>;
dev-handle = <&fman1>;
};
crypto {
fsl,liodn = <0x41 0x66>;
dev-handle = <&crypto>;
};
};
qman-portal@4000 {
compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";
reg = <0x4000 0x4000>, <0x101000 0x1000>;
interrupts = <106 2 0 0>;
fsl,liodn = <3 4>;
fsl,qman-channel-id = <1>;
fman0 {
fsl,liodn = <0x22>;
dev-handle = <&fman0>;
};
fman1 {
fsl,liodn = <0xa2>;
dev-handle = <&fman1>;
};
crypto {
fsl,liodn = <0x42 0x67>;
dev-handle = <&crypto>;
};
};
};
QorIQ DPAA Queue Manager Device Tree Binding
Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
CONTENTS
- QMan Node
- QMan Private Memory Nodes
- Example
QMan Node
The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA). QMan
supports queuing and QoS scheduling of frames to CPUs, network interfaces and
DPAA logic modules, maintains packet ordering within flows. Besides providing
flow-level queuing, is also responsible for congestion management functions such
as RED/WRED, congestion notifications and tail discards. This binding covers the
CCSR space programming model
PROPERTIES
- compatible
Usage: Required
Value type: <stringlist>
Definition: Must include "fsl,qman"
May include "fsl,<SoC>-qman"
- reg
Usage: Required
Value type: <prop-encoded-array>
Definition: Registers region within the CCSR address space
The QMan revision information is located in the QMAN_IP_REV_1/2 registers which
are located at offsets 0xbf8 and 0xbfc
- interrupts
Usage: Required
Value type: <prop-encoded-array>
Definition: Standard property. The error interrupt
- fsl,liodn
Usage: See pamu.txt
Value type: <prop-encoded-array>
Definition: PAMU property used for static LIODN assignment
- fsl,iommu-parent
Usage: See pamu.txt
Value type: <phandle>
Definition: PAMU property used for dynamic LIODN assignment
For additional details about the PAMU/LIODN binding(s) see pamu.txt
- clocks
Usage: See clock-bindings.txt and qoriq-clock.txt
Value type: <prop-encoded-array>
Definition: Reference input clock. Its frequency is half of the
platform clock
Devices connected to a QMan instance via Direct Connect Portals (DCP) must link
to the respective QMan instance
- fsl,qman
Usage: Required
Value type: <prop-encoded-array>
Description: List of phandle and DCP index pairs, to the QMan instance
to which this device is connected via the DCP
QMan Private Memory Nodes
QMan requires two contiguous range of physical memory used for the backing store
for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record (PFDR).
This memory is reserved/allocated as a nodes under the /reserved-memory node
The QMan FQD memory node must be named "qman-fqd"
PROPERTIES
- compatible
Usage: required
Value type: <stringlist>
Definition: Must inclide "fsl,qman-fqd"
The QMan PFDR memory node must be named "qman-pfdr"
PROPERTIES
- compatible
Usage: required
Value type: <stringlist>
Definition: Must inclide "fsl,qman-pfdr"
The following constraints are relevant to the FQD and PFDR private memory:
- The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to
1 GiB
- The alignment must be a muliptle of the memory size
The size of the FQD and PFDP must be chosen by observing the hardware features
configured via the Reset Configuration Word (RCW) and that are relevant to a
specific board (e.g. number of MAC(s) pinned-out, number of offline/host command
FMan ports, etc.). The size configured in the DT must reflect the hardware
capabilities and not the specific needs of an application
For additional details about reserved memory regions see reserved-memory.txt
EXAMPLE
The example below shows a QMan FQD and a PFDR dynamic allocation memory nodes
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
qman_fqd: qman-fqd {
compatible = "fsl,qman-fqd";
alloc-ranges = <0 0 0xf 0xffffffff>;
size = <0 0x400000>;
alignment = <0 0x400000>;
};
qman_pfdr: qman-pfdr {
compatible = "fsl,qman-pfdr";
alloc-ranges = <0 0 0xf 0xffffffff>;
size = <0 0x2000000>;
alignment = <0 0x2000000>;
};
};
The example below shows a (P4080) QMan CCSR-space node
clockgen: global-utilities@e1000 {
...
sysclk: sysclk {
...
};
...
platform_pll: platform-pll@c00 {
#clock-cells = <1>;
reg = <0xc00 0x4>;
compatible = "fsl,qoriq-platform-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "platform-pll", "platform-pll-div2";
};
...
};
crypto@300000 {
...
fsl,qman = <&qman, 2>;
...
};
qman: qman@318000 {
compatible = "fsl,qman";
reg = <0x318000 0x1000>;
interrupts = <16 2 1 3>
fsl,liodn = <0x16>;
memory-region = <&qman_fqd &qman_pfdr>;
clocks = <&platform_pll 1>;
};
fman@400000 {
...
fsl,qman = <&qman, 0>;
...
};
......@@ -552,7 +552,7 @@ config PPC_4K_PAGES
bool "4k page size"
config PPC_16K_PAGES
bool "16k page size" if 44x
bool "16k page size" if 44x || PPC_8xx
config PPC_64K_PAGES
bool "64k page size" if 44x || PPC_STD_MMU_64 || PPC_BOOK3E_64
......
......@@ -193,9 +193,9 @@ guts: global-utilities@e0000 {
fsl,liodn-bits = <12>;
};
clockgen: global-utilities@e1000 {
/include/ "fsl/qoriq-clockgen2.dtsi"
global-utilities@e1000 {
compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
reg = <0xe1000 0x1000>;
};
/include/ "fsl/qoriq-dma-0.dtsi"
......
......@@ -152,6 +152,29 @@ rtc@68 {
reg = <0x68>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
ina220@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <1000>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
adt7461@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
};
};
};
......
......@@ -40,31 +40,6 @@ nand@0,0 {
compatible = "fsl,ifc-nand";
reg = <0x0 0x0 0x4000>;
partition@0 {
/* This location must not be altered */
/* 3MB for u-boot Bootloader Image */
reg = <0x0 0x00300000>;
label = "NAND U-Boot Image";
read-only;
};
partition@300000 {
/* 1MB for DTB Image */
reg = <0x00300000 0x00100000>;
label = "NAND DTB Image";
};
partition@400000 {
/* 8MB for Linux Kernel Image */
reg = <0x00400000 0x00800000>;
label = "NAND Linux Kernel Image";
};
partition@c00000 {
/* Rest space for Root file System Image */
reg = <0x00c00000 0x07400000>;
label = "NAND RFS Image";
};
};
};
......@@ -82,31 +57,6 @@ flash@0 {
reg = <0>;
spi-max-frequency = <50000000>;
/* 512KB for u-boot Bootloader Image */
partition@0 {
reg = <0x0 0x00080000>;
label = "SPI Flash U-Boot Image";
read-only;
};
/* 512KB for DTB Image */
partition@80000 {
reg = <0x00080000 0x00080000>;
label = "SPI Flash DTB Image";
};
/* 4MB for Linux Kernel Image */
partition@100000 {
reg = <0x00100000 0x00400000>;
label = "SPI Flash Kernel Image";
};
/*11MB for RFS Image */
partition@500000 {
reg = <0x00500000 0x00B00000>;
label = "SPI Flash RFS Image";
};
};
};
......
......@@ -80,33 +80,9 @@ guts: global-utilities@e0000 {
compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
};
clockgen: global-utilities@e1000 {
/include/ "qoriq-clockgen2.dtsi"
global-utilities@e1000 {
compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
ranges = <0x0 0xe1000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fsl,qoriq-sysclk-2.0";
clock-output-names = "sysclk";
};
pll0: pll0@800 {
#clock-cells = <1>;
reg = <0x800 0x4>;
compatible = "fsl,qoriq-core-pll-2.0";
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2", "pll0-div4";
};
pll1: pll1@820 {
#clock-cells = <1>;
reg = <0x820 0x4>;
compatible = "fsl,qoriq-core-pll-2.0";
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2", "pll1-div4";
};
mux0: mux0@0 {
#clock-cells = <0>;
......
......@@ -124,33 +124,9 @@ guts: global-utilities@e0000 {
compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";
};
clockgen: global-utilities@e1000 {
/include/ "qoriq-clockgen2.dtsi"
global-utilities@e1000 {
compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";
ranges = <0x0 0xe1000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fsl,qoriq-sysclk-2.0";
clock-output-names = "sysclk";
};
pll0: pll0@800 {
#clock-cells = <1>;
reg = <0x800 0x4>;
compatible = "fsl,qoriq-core-pll-2.0";
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2", "pll0-div4";
};
pll1: pll1@820 {
#clock-cells = <1>;
reg = <0x820 0x4>;
compatible = "fsl,qoriq-core-pll-2.0";
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2", "pll1-div4";
};
mux0: mux0@0 {
#clock-cells = <0>;
......
......@@ -305,53 +305,9 @@ pins: global-utilities@e0e00 {
#sleep-cells = <2>;
};
clockgen: global-utilities@e1000 {
/include/ "qoriq-clockgen1.dtsi"
global-utilities@e1000 {
compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
ranges = <0x0 0xe1000 0x1000>;
reg = <0xe1000 0x1000>;
clock-frequency = <0>;
#address-cells = <1>;
#size-cells = <1>;
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fsl,qoriq-sysclk-1.0";
clock-output-names = "sysclk";
};
pll0: pll0@800 {
#clock-cells = <1>;
reg = <0x800 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2";
};
pll1: pll1@820 {
#clock-cells = <1>;
reg = <0x820 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2";
};
mux0: mux0@0 {
#clock-cells = <0>;
reg = <0x0 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux0";
};
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux1";
};
mux2: mux2@40 {
#clock-cells = <0>;
......
......@@ -332,53 +332,9 @@ pins: global-utilities@e0e00 {
#sleep-cells = <2>;
};
clockgen: global-utilities@e1000 {
/include/ "qoriq-clockgen1.dtsi"
global-utilities@e1000 {
compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
ranges = <0x0 0xe1000 0x1000>;
reg = <0xe1000 0x1000>;
clock-frequency = <0>;
#address-cells = <1>;
#size-cells = <1>;
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fsl,qoriq-sysclk-1.0";
clock-output-names = "sysclk";
};
pll0: pll0@800 {
#clock-cells = <1>;
reg = <0x800 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2";
};
pll1: pll1@820 {
#clock-cells = <1>;
reg = <0x820 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2";
};
mux0: mux0@0 {
#clock-cells = <0>;
reg = <0x0 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux0";
};
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux1";
};
mux2: mux2@40 {
#clock-cells = <0>;
......
......@@ -352,35 +352,9 @@ pins: global-utilities@e0e00 {
#sleep-cells = <2>;
};
clockgen: global-utilities@e1000 {
/include/ "qoriq-clockgen1.dtsi"
global-utilities@e1000 {
compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
ranges = <0x0 0xe1000 0x1000>;
reg = <0xe1000 0x1000>;
clock-frequency = <0>;
#address-cells = <1>;
#size-cells = <1>;
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fsl,qoriq-sysclk-1.0";
clock-output-names = "sysclk";
};
pll0: pll0@800 {
#clock-cells = <1>;
reg = <0x800 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2";
};
pll1: pll1@820 {
#clock-cells = <1>;
reg = <0x820 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2";
};
pll2: pll2@840 {
#clock-cells = <1>;
......@@ -398,24 +372,6 @@ pll3: pll3@860 {
clock-output-names = "pll3", "pll3-div2";
};
mux0: mux0@0 {
#clock-cells = <0>;
reg = <0x0 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux0";
};
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux1";
};
mux2: mux2@40 {
#clock-cells = <0>;
reg = <0x40 0x4>;
......
......@@ -337,53 +337,9 @@ pins: global-utilities@e0e00 {
#sleep-cells = <2>;
};
clockgen: global-utilities@e1000 {
/include/ "qoriq-clockgen1.dtsi"
global-utilities@e1000 {
compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
ranges = <0x0 0xe1000 0x1000>;
reg = <0xe1000 0x1000>;
clock-frequency = <0>;
#address-cells = <1>;
#size-cells = <1>;
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fsl,qoriq-sysclk-1.0";
clock-output-names = "sysclk";
};
pll0: pll0@800 {
#clock-cells = <1>;
reg = <0x800 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2";
};
pll1: pll1@820 {
#clock-cells = <1>;
reg = <0x820 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2";
};
mux0: mux0@0 {
#clock-cells = <0>;
reg = <0x0 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux0";
};
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux1";
};
};
rcpm: global-utilities@e2000 {
......
......@@ -297,53 +297,9 @@ pins: global-utilities@e0e00 {
#sleep-cells = <2>;
};
clockgen: global-utilities@e1000 {
/include/ "qoriq-clockgen1.dtsi"
global-utilities@e1000 {
compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
ranges = <0x0 0xe1000 0x1000>;
reg = <0xe1000 0x1000>;
clock-frequency = <0>;
#address-cells = <1>;
#size-cells = <1>;
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fsl,qoriq-sysclk-1.0";
clock-output-names = "sysclk";
};
pll0: pll0@800 {
#clock-cells = <1>;
reg = <0x800 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2";
};
pll1: pll1@820 {
#clock-cells = <1>;
reg = <0x820 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2";
};
mux0: mux0@0 {
#clock-cells = <0>;
reg = <0x0 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux0";
};
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux1";
};
mux2: mux2@40 {
#clock-cells = <0>;
......
/*
* QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
*
* Copyright 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
global-utilities@e1000 {
compatible = "fsl,qoriq-clockgen-1.0";
ranges = <0x0 0xe1000 0x1000>;
reg = <0xe1000 0x1000>;
clock-frequency = <0>;
#address-cells = <1>;
#size-cells = <1>;
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock";
clock-output-names = "sysclk";
};
pll0: pll0@800 {
#clock-cells = <1>;
reg = <0x800 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2";
};
pll1: pll1@820 {
#clock-cells = <1>;
reg = <0x820 0x4>;
compatible = "fsl,qoriq-core-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2";
};
mux0: mux0@0 {
#clock-cells = <0>;
reg = <0x0 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux0";
};
mux1: mux1@20 {
#clock-cells = <0>;
reg = <0x20 0x4>;
compatible = "fsl,qoriq-core-mux-1.0";
clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
clock-output-names = "cmux1";
};
platform_pll: platform-pll@c00 {
#clock-cells = <1>;
reg = <0xc00 0x4>;
compatible = "fsl,qoriq-platform-pll-1.0";
clocks = <&sysclk>;
clock-output-names = "platform-pll", "platform-pll-div2";
};
};
/*
* QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
*
* Copyright 2014 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
global-utilities@e1000 {
compatible = "fsl,qoriq-clockgen-2.0";
ranges = <0x0 0xe1000 0x1000>;
reg = <0xe1000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fsl,qoriq-sysclk-2.0", "fixed-clock";
clock-output-names = "sysclk";
};
pll0: pll0@800 {
#clock-cells = <1>;
reg = <0x800 0x4>;
compatible = "fsl,qoriq-core-pll-2.0";
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2", "pll0-div4";
};
pll1: pll1@820 {
#clock-cells = <1>;
reg = <0x820 0x4>;
compatible = "fsl,qoriq-core-pll-2.0";
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2", "pll1-div4";
};
platform_pll: platform-pll@c00 {
#clock-cells = <1>;
reg = <0xc00 0x4>;
compatible = "fsl,qoriq-platform-pll-2.0";
clocks = <&sysclk>;
clock-output-names = "platform-pll", "platform-pll-div2";
};
};
......@@ -281,35 +281,9 @@ guts: global-utilities@e0000 {
fsl,liodn-bits = <12>;
};
clockgen: global-utilities@e1000 {
/include/ "qoriq-clockgen2.dtsi"
global-utilities@e1000 {
compatible = "fsl,t1040-clockgen", "fsl,qoriq-clockgen-2.0";
ranges = <0x0 0xe1000 0x1000>;
reg = <0xe1000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fsl,qoriq-sysclk-2.0";
clock-output-names = "sysclk", "fixed-clock";
};
pll0: pll0@800 {
#clock-cells = <1>;
reg = <0x800 4>;
compatible = "fsl,qoriq-core-pll-2.0";
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2", "pll0-div4";
};
pll1: pll1@820 {
#clock-cells = <1>;
reg = <0x820 4>;
compatible = "fsl,qoriq-core-pll-2.0";
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2", "pll1-div4";
};
mux0: mux0@0 {
#clock-cells = <0>;
......
......@@ -305,34 +305,9 @@ guts: global-utilities@e0000 {
fsl,liodn-bits = <12>;
};
clockgen: global-utilities@e1000 {
/include/ "qoriq-clockgen2.dtsi"
global-utilities@e1000 {
compatible = "fsl,t2080-clockgen", "fsl,qoriq-clockgen-2.0";
ranges = <0x0 0xe1000 0x1000>;
reg = <0xe1000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fsl,qoriq-sysclk-2.0";
clock-output-names = "sysclk", "fixed-clock";
};
pll0: pll0@800 {
#clock-cells = <1>;
reg = <0x800 4>;
compatible = "fsl,qoriq-core-pll-2.0";
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2", "pll0-div4";
};
pll1: pll1@820 {
#clock-cells = <1>;
reg = <0x820 4>;
compatible = "fsl,qoriq-core-pll-2.0";
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2", "pll1-div4";
};
mux0: mux0@0 {
#clock-cells = <0>;
......
......@@ -368,34 +368,9 @@ guts: global-utilities@e0000 {
fsl,liodn-bits = <12>;
};
clockgen: global-utilities@e1000 {
/include/ "qoriq-clockgen2.dtsi"
global-utilities@e1000 {
compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
ranges = <0x0 0xe1000 0x1000>;
reg = <0xe1000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
sysclk: sysclk {
#clock-cells = <0>;
compatible = "fsl,qoriq-sysclk-2.0";
clock-output-names = "sysclk";
};
pll0: pll0@800 {
#clock-cells = <1>;
reg = <0x800 0x4>;
compatible = "fsl,qoriq-core-pll-2.0";
clocks = <&sysclk>;
clock-output-names = "pll0", "pll0-div2", "pll0-div4";
};
pll1: pll1@820 {
#clock-cells = <1>;
reg = <0x820 0x4>;
compatible = "fsl,qoriq-core-pll-2.0";
clocks = <&sysclk>;
clock-output-names = "pll1", "pll1-div2", "pll1-div4";
};
pll2: pll2@840 {
#clock-cells = <1>;
......
......@@ -98,6 +98,26 @@ rtc@68 {
reg = <0x68>;
interrupts = <0x1 0x1 0 0>;
};
ina220@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <1000>;
};
ina220@41 {
compatible = "ti,ina220";
reg = <0x41>;
shunt-resistor = <1000>;
};
ina220@44 {
compatible = "ti,ina220";
reg = <0x44>;
shunt-resistor = <1000>;
};
ina220@45 {
compatible = "ti,ina220";
reg = <0x45>;
shunt-resistor = <1000>;
};
adt7461@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
......
......@@ -98,6 +98,26 @@ rtc@68 {
reg = <0x68>;
interrupts = <0x1 0x1 0 0>;
};
ina220@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <1000>;
};
ina220@41 {
compatible = "ti,ina220";
reg = <0x41>;
shunt-resistor = <1000>;
};
ina220@44 {
compatible = "ti,ina220";
reg = <0x44>;
shunt-resistor = <1000>;
};
ina220@45 {
compatible = "ti,ina220";
reg = <0x45>;
shunt-resistor = <1000>;
};
adt7461@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
......
......@@ -95,6 +95,26 @@ rtc@68 {
reg = <0x68>;
interrupts = <0x1 0x1 0 0>;
};
ina220@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <1000>;
};
ina220@41 {
compatible = "ti,ina220";
reg = <0x41>;
shunt-resistor = <1000>;
};
ina220@44 {
compatible = "ti,ina220";
reg = <0x44>;
shunt-resistor = <1000>;
};
ina220@45 {
compatible = "ti,ina220";
reg = <0x45>;
shunt-resistor = <1000>;
};
adt7461@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
......
......@@ -83,6 +83,13 @@ flash@0 {
};
};
i2c@118000 {
adt7461@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
};
i2c@118100 {
pca9546@77 {
compatible = "nxp,pca9546";
......
......@@ -169,6 +169,17 @@ ina220@41 {
shunt-resistor = <1000>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
adt7461@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
};
};
};
};
......
......@@ -250,9 +250,9 @@ guts: global-utilities@e0000 {
fsl,liodn-bits = <12>;
};
clockgen: global-utilities@e1000 {
/include/ "fsl/qoriq-clockgen2.dtsi"
global-utilities@e1000 {
compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
reg = <0xe1000 0x1000>;
};
/include/ "fsl/qoriq-dma-0.dtsi"
......
......@@ -144,6 +144,7 @@ CONFIG_RTC_DRV_DS1374=y
CONFIG_RTC_DRV_DS3232=y
CONFIG_UIO=y
CONFIG_STAGING=y
CONFIG_MEMORY=y
CONFIG_VIRT_DRIVERS=y
CONFIG_FSL_HV_MANAGER=y
CONFIG_EXT2_FS=y
......
......@@ -118,6 +118,7 @@ CONFIG_FSL_DMA=y
CONFIG_VIRT_DRIVERS=y
CONFIG_FSL_HV_MANAGER=y
CONFIG_FSL_CORENET_CF=y
CONFIG_MEMORY=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
CONFIG_ISO9660_FS=m
......
......@@ -215,6 +215,7 @@ CONFIG_RTC_DRV_DS3232=y
CONFIG_RTC_DRV_CMOS=y
CONFIG_DMADEVICES=y
CONFIG_FSL_DMA=y
CONFIG_MEMORY=y
# CONFIG_NET_DMA is not set
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
......
......@@ -216,6 +216,7 @@ CONFIG_RTC_DRV_DS3232=y
CONFIG_RTC_DRV_CMOS=y
CONFIG_DMADEVICES=y
CONFIG_FSL_DMA=y
CONFIG_MEMORY=y
# CONFIG_NET_DMA is not set
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
......
......@@ -68,7 +68,10 @@ struct ccsr_guts {
u8 res0b4[0xc0 - 0xb4];
__be32 iovselsr; /* 0x.00c0 - I/O voltage select status register
Called 'elbcvselcr' on 86xx SOCs */
u8 res0c4[0x224 - 0xc4];
u8 res0c4[0x100 - 0xc4];
__be32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
There are 16 registers */
u8 res140[0x224 - 0x140];
__be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
__be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
u8 res22c[0x604 - 0x22c];
......
......@@ -56,6 +56,7 @@
* additional information from the MI_EPN, and MI_TWC registers.
*/
#define SPRN_MI_RPN 790
#define MI_SPS16K 0x00000008 /* Small page size (0 = 4k, 1 = 16k) */
/* Define an RPN value for mapping kernel memory to large virtual
* pages for boot initialization. This has real page number of 0,
......@@ -129,6 +130,7 @@
* additional information from the MD_EPN, and MD_TWC registers.
*/
#define SPRN_MD_RPN 798
#define MD_SPS16K 0x00000008 /* Small page size (0 = 4k, 1 = 16k) */
/* This is a temporary storage register that could be used to save
* a processor working register during a tablewalk.
......
......@@ -170,6 +170,25 @@ static inline unsigned long pte_update(pte_t *p,
#ifdef PTE_ATOMIC_UPDATES
unsigned long old, tmp;
#ifdef CONFIG_PPC_8xx
unsigned long tmp2;
__asm__ __volatile__("\
1: lwarx %0,0,%4\n\
andc %1,%0,%5\n\
or %1,%1,%6\n\
/* 0x200 == Extended encoding, bit 22 */ \
/* Bit 22 has to be 1 if neither _PAGE_USER nor _PAGE_RW are set */ \
rlwimi %1,%1,32-2,0x200\n /* get _PAGE_USER */ \
rlwinm %3,%1,32-1,0x200\n /* get _PAGE_RW */ \
or %1,%3,%1\n\
xori %1,%1,0x200\n"
" stwcx. %1,0,%4\n\
bne- 1b"
: "=&r" (old), "=&r" (tmp), "=m" (*p), "=&r" (tmp2)
: "r" (p), "r" (clr), "r" (set), "m" (*p)
: "cc" );
#else /* CONFIG_PPC_8xx */
__asm__ __volatile__("\
1: lwarx %0,0,%3\n\
andc %1,%0,%4\n\
......@@ -180,6 +199,7 @@ static inline unsigned long pte_update(pte_t *p,
: "=&r" (old), "=&r" (tmp), "=m" (*p)
: "r" (p), "r" (clr), "r" (set), "m" (*p)
: "cc" );
#endif /* CONFIG_PPC_8xx */
#else /* PTE_ATOMIC_UPDATES */
unsigned long old = pte_val(*p);
*p = __pte((old & ~clr) | set);
......
......@@ -48,19 +48,22 @@
*/
#define _PAGE_RW 0x0400 /* lsb PP bits, inverted in HW */
#define _PAGE_USER 0x0800 /* msb PP bits */
/* set when neither _PAGE_USER nor _PAGE_RW are set */
#define _PAGE_KNLRO 0x0200
#define _PMD_PRESENT 0x0001
#define _PMD_BAD 0x0ff0
#define _PMD_PAGE_MASK 0x000c
#define _PMD_PAGE_8M 0x000c
#define _PTE_NONE_MASK _PAGE_ACCESSED
#define _PTE_NONE_MASK _PAGE_KNLRO
/* Until my rework is finished, 8xx still needs atomic PTE updates */
#define PTE_ATOMIC_UPDATES 1
/* We need to add _PAGE_SHARED to kernel pages */
#define _PAGE_KERNEL_RO (_PAGE_SHARED)
#define _PAGE_KERNEL_RO (_PAGE_SHARED | _PAGE_KNLRO)
#define _PAGE_KERNEL_ROX (_PAGE_EXEC | _PAGE_KNLRO)
#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE)
#endif /* __KERNEL__ */
......
......@@ -33,13 +33,31 @@
/* Macro to make the code more readable. */
#ifdef CONFIG_8xx_CPU6
#define DO_8xx_CPU6(val, reg) \
li reg, val; \
stw reg, 12(r0); \
lwz reg, 12(r0);
#define SPRN_MI_TWC_ADDR 0x2b80
#define SPRN_MI_RPN_ADDR 0x2d80
#define SPRN_MD_TWC_ADDR 0x3b80
#define SPRN_MD_RPN_ADDR 0x3d80
#define MTSPR_CPU6(spr, reg, treg) \
li treg, spr##_ADDR; \
stw treg, 12(r0); \
lwz treg, 12(r0); \
mtspr spr, reg
#else
#define DO_8xx_CPU6(val, reg)
#define MTSPR_CPU6(spr, reg, treg) \
mtspr spr, reg
#endif
/*
* Value for the bits that have fixed value in RPN entries.
* Also used for tagging DAR for DTLBerror.
*/
#ifdef CONFIG_PPC_16K_PAGES
#define RPN_PATTERN (0x00f0 | MD_SPS16K)
#else
#define RPN_PATTERN 0x00f0
#endif
__HEAD
_ENTRY(_stext);
_ENTRY(_start);
......@@ -65,13 +83,6 @@ _ENTRY(_start);
* 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
* the "internal" processor registers before MMU_init is called.
*
* The TLB code currently contains a major hack. Since I use the condition
* code register, I have to save and restore it. I am out of registers, so
* I just store it in memory location 0 (the TLB handlers are not reentrant).
* To avoid making any decisions, I need to use the "segment" valid bit
* in the first level table, but that would require many changes to the
* Linux page directory/table functions that I don't want to do right now.
*
* -- Dan
*/
.globl __start
......@@ -211,7 +222,7 @@ MachineCheck:
EXCEPTION_PROLOG
mfspr r4,SPRN_DAR
stw r4,_DAR(r11)
li r5,0x00f0
li r5,RPN_PATTERN
mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
mfspr r5,SPRN_DSISR
stw r5,_DSISR(r11)
......@@ -219,30 +230,16 @@ MachineCheck:
EXC_XFER_STD(0x200, machine_check_exception)
/* Data access exception.
* This is "never generated" by the MPC8xx. We jump to it for other
* translation errors.
* This is "never generated" by the MPC8xx.
*/
. = 0x300
DataAccess:
EXCEPTION_PROLOG
mfspr r10,SPRN_DSISR
stw r10,_DSISR(r11)
mr r5,r10
mfspr r4,SPRN_DAR
li r10,0x00f0
mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
EXC_XFER_LITE(0x300, handle_page_fault)
/* Instruction access exception.
* This is "never generated" by the MPC8xx. We jump to it for other
* translation errors.
* This is "never generated" by the MPC8xx.
*/
. = 0x400
InstructionAccess:
EXCEPTION_PROLOG
mr r4,r12
mr r5,r9
EXC_XFER_LITE(0x400, handle_page_fault)
/* External interrupt */
EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
......@@ -253,7 +250,7 @@ Alignment:
EXCEPTION_PROLOG
mfspr r4,SPRN_DAR
stw r4,_DAR(r11)
li r5,0x00f0
li r5,RPN_PATTERN
mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
mfspr r5,SPRN_DSISR
stw r5,_DSISR(r11)
......@@ -292,8 +289,8 @@ SystemCall:
. = 0x1100
/*
* For the MPC8xx, this is a software tablewalk to load the instruction
* TLB. It is modelled after the example in the Motorola manual. The task
* switch loads the M_TWB register with the pointer to the first level table.
* TLB. The task switch loads the M_TW register with the pointer to the first
* level table.
* If we discover there is no second level table (value is zero) or if there
* is an invalid pte, we load that into the TLB, which causes another fault
* into the TLB Error interrupt where we can handle such problems.
......@@ -302,20 +299,17 @@ SystemCall:
*/
InstructionTLBMiss:
#ifdef CONFIG_8xx_CPU6
stw r3, 8(r0)
mtspr SPRN_DAR, r3
#endif
EXCEPTION_PROLOG_0
mtspr SPRN_SPRG_SCRATCH2, r10
mfspr r10, SPRN_SRR0 /* Get effective address of fault */
#ifdef CONFIG_8xx_CPU15
addi r11, r10, 0x1000
addi r11, r10, PAGE_SIZE
tlbie r11
addi r11, r10, -0x1000
addi r11, r10, -PAGE_SIZE
tlbie r11
#endif
DO_8xx_CPU6(0x3780, r3)
mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */
mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
......@@ -323,32 +317,37 @@ InstructionTLBMiss:
#ifdef CONFIG_MODULES
/* Only modules will cause ITLB Misses as we always
* pin the first 8MB of kernel memory */
andi. r11, r10, 0x0800 /* Address >= 0x80000000 */
andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
#endif
mfspr r11, SPRN_M_TW /* Get level 1 table base address */
#ifdef CONFIG_MODULES
beq 3f
lis r11, swapper_pg_dir@h
ori r11, r11, swapper_pg_dir@l
rlwimi r10, r11, 0, 2, 19
lis r11, (swapper_pg_dir-PAGE_OFFSET)@h
ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
3:
#endif
lwz r11, 0(r10) /* Get the level 1 entry */
/* Extract level 1 index */
rlwinm r10, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
lwzx r11, r10, r11 /* Get the level 1 entry */
rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
beq 2f /* If zero, don't try to find a pte */
/* We have a pte table, so load the MI_TWC with the attributes
* for this "segment."
*/
ori r11,r11,1 /* Set valid bit */
DO_8xx_CPU6(0x2b80, r3)
mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
DO_8xx_CPU6(0x3b80, r3)
mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
lwz r10, 0(r11) /* Get the pte */
MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */
mfspr r11, SPRN_SRR0 /* Get effective address of fault */
/* Extract level 2 index */
rlwinm r11, r11, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
lwzx r10, r10, r11 /* Get the pte */
#ifdef CONFIG_SWAP
andi. r11, r10, _PAGE_ACCESSED | _PAGE_PRESENT
cmpwi cr0, r11, _PAGE_ACCESSED | _PAGE_PRESENT
li r11, RPN_PATTERN
bne- cr0, 2f
#else
li r11, RPN_PATTERN
#endif
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 21 and 28 must be clear.
......@@ -356,62 +355,63 @@ InstructionTLBMiss:
* set. All other Linux PTE bits control the behavior
* of the MMU.
*/
li r11, 0x00f0
rlwimi r10, r11, 0, 0x07f8 /* Set 24-27, clear 21-23,28 */
DO_8xx_CPU6(0x2d80, r3)
mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */
/* Restore registers */
#ifdef CONFIG_8xx_CPU6
lwz r3, 8(r0)
mfspr r3, SPRN_DAR
mtspr SPRN_DAR, r11 /* Tag DAR */
#endif
mfspr r10, SPRN_SPRG_SCRATCH2
EXCEPTION_EPILOG_0
rfi
2:
mfspr r11, SPRN_SRR1
mfspr r10, SPRN_SRR1
/* clear all error bits as TLB Miss
* sets a few unconditionally
*/
rlwinm r11, r11, 0, 0xffff
mtspr SPRN_SRR1, r11
rlwinm r10, r10, 0, 0xffff
mtspr SPRN_SRR1, r10
/* Restore registers */
#ifdef CONFIG_8xx_CPU6
lwz r3, 8(r0)
mfspr r3, SPRN_DAR
mtspr SPRN_DAR, r11 /* Tag DAR */
#endif
mfspr r10, SPRN_SPRG_SCRATCH2
EXCEPTION_EPILOG_0
b InstructionAccess
b InstructionTLBError1
. = 0x1200
DataStoreTLBMiss:
#ifdef CONFIG_8xx_CPU6
stw r3, 8(r0)
mtspr SPRN_DAR, r3
#endif
EXCEPTION_PROLOG_0
mtspr SPRN_SPRG_SCRATCH2, r10
mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
mfspr r10, SPRN_MD_EPN
/* If we are faulting a kernel address, we have to use the
* kernel page tables.
*/
andi. r11, r10, 0x0800
andis. r11, r10, 0x8000
mfspr r11, SPRN_M_TW /* Get level 1 table base address */
beq 3f
lis r11, swapper_pg_dir@h
ori r11, r11, swapper_pg_dir@l
rlwimi r10, r11, 0, 2, 19
lis r11, (swapper_pg_dir-PAGE_OFFSET)@h
ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
3:
lwz r11, 0(r10) /* Get the level 1 entry */
/* Extract level 1 index */
rlwinm r10, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
lwzx r11, r10, r11 /* Get the level 1 entry */
rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
beq 2f /* If zero, don't try to find a pte */
/* We have a pte table, so load fetch the pte from the table.
*/
ori r11, r11, 1 /* Set valid bit in physical L2 page */
DO_8xx_CPU6(0x3b80, r3)
mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
mfspr r10, SPRN_MD_TWC /* ....and get the pte address */
mfspr r10, SPRN_MD_EPN /* Get address of fault */
/* Extract level 2 index */
rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
lwz r10, 0(r10) /* Get the pte */
/* Insert the Guarded flag into the TWC from the Linux PTE.
......@@ -425,8 +425,7 @@ DataStoreTLBMiss:
* It is bit 25 in the Linux PTE and bit 30 in the TWC
*/
rlwimi r11, r10, 32-5, 30, 30
DO_8xx_CPU6(0x3b80, r3)
mtspr SPRN_MD_TWC, r11
MTSPR_CPU6(SPRN_MD_TWC, r11, r3)
/* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
* We also need to know if the insn is a load/store, so:
......@@ -442,14 +441,8 @@ DataStoreTLBMiss:
and r11, r11, r10
rlwimi r10, r11, 0, _PAGE_PRESENT
#endif
/* Honour kernel RO, User NA */
/* 0x200 == Extended encoding, bit 22 */
rlwimi r10, r10, 32-2, 0x200 /* Copy USER to bit 22, 0x200 */
/* r11 = (r10 & _PAGE_RW) >> 1 */
rlwinm r11, r10, 32-1, 0x200
or r10, r11, r10
/* invert RW and 0x200 bits */
xori r10, r10, _PAGE_RW | 0x200
/* invert RW */
xori r10, r10, _PAGE_RW
/* The Linux PTE won't go exactly into the MMU TLB.
* Software indicator bits 22 and 28 must be clear.
......@@ -457,14 +450,13 @@ DataStoreTLBMiss:
* set. All other Linux PTE bits control the behavior
* of the MMU.
*/
2: li r11, 0x00f0
2: li r11, RPN_PATTERN
rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
DO_8xx_CPU6(0x3d80, r3)
mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */
/* Restore registers */
#ifdef CONFIG_8xx_CPU6
lwz r3, 8(r0)
mfspr r3, SPRN_DAR
#endif
mtspr SPRN_DAR, r11 /* Tag DAR */
mfspr r10, SPRN_SPRG_SCRATCH2
......@@ -477,7 +469,17 @@ DataStoreTLBMiss:
*/
. = 0x1300
InstructionTLBError:
b InstructionAccess
EXCEPTION_PROLOG_0
InstructionTLBError1:
EXCEPTION_PROLOG_1
EXCEPTION_PROLOG_2
mr r4,r12
mr r5,r9
andis. r10,r5,0x4000
beq+ 1f
tlbie r4
/* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
1: EXC_XFER_LITE(0x400, handle_page_fault)
/* This is the data TLB error on the MPC8xx. This could be due to
* many reasons, including a dirty update to a pte. We bail out to
......@@ -488,11 +490,21 @@ DataTLBError:
EXCEPTION_PROLOG_0
mfspr r11, SPRN_DAR
cmpwi cr0, r11, 0x00f0
cmpwi cr0, r11, RPN_PATTERN
beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
DARFixed:/* Return from dcbx instruction bug workaround */
EXCEPTION_EPILOG_0
b DataAccess
EXCEPTION_PROLOG_1
EXCEPTION_PROLOG_2
mfspr r5,SPRN_DSISR
stw r5,_DSISR(r11)
mfspr r4,SPRN_DAR
andis. r10,r5,0x4000
beq+ 1f
tlbie r4
1: li r10,RPN_PATTERN
mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
/* 0x300 is DataAccess exception, needed by bad_page_fault() */
EXC_XFER_LITE(0x300, handle_page_fault)
EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
......@@ -521,29 +533,30 @@ DARFixed:/* Return from dcbx instruction bug workaround */
#define NO_SELF_MODIFYING_CODE
FixupDAR:/* Entry point for dcbx workaround. */
#ifdef CONFIG_8xx_CPU6
stw r3, 8(r0)
mtspr SPRN_DAR, r3
#endif
mtspr SPRN_SPRG_SCRATCH2, r10
/* fetch instruction from memory. */
mfspr r10, SPRN_SRR0
andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
DO_8xx_CPU6(0x3780, r3)
mtspr SPRN_MD_EPN, r10
mfspr r11, SPRN_M_TWB /* Get level 1 table entry address */
mfspr r11, SPRN_M_TW /* Get level 1 table base address */
beq- 3f /* Branch if user space */
lis r11, (swapper_pg_dir-PAGE_OFFSET)@h
ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
rlwimi r11, r10, 32-20, 0xffc /* r11 = r11&~0xffc|(r10>>20)&0xffc */
3: lwz r11, 0(r11) /* Get the level 1 entry */
DO_8xx_CPU6(0x3b80, r3)
mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
lwz r11, 0(r11) /* Get the pte */
/* Extract level 1 index */
3: rlwinm r10, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
lwzx r11, r10, r11 /* Get the level 1 entry */
rlwinm r10, r11,0,0,19 /* Extract page descriptor page address */
mfspr r11, SPRN_SRR0 /* Get effective address of fault */
/* Extract level 2 index */
rlwinm r11, r11, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
lwzx r11, r10, r11 /* Get the pte */
#ifdef CONFIG_8xx_CPU6
lwz r3, 8(r0) /* restore r3 from memory */
mfspr r3, SPRN_DAR
#endif
/* concat physical page address(r11) and page offset(r10) */
rlwimi r11, r10, 0, 20, 31
mfspr r10, SPRN_SRR0
rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
lwz r11,0(r11)
/* Check if it really is a dcbx instruction. */
/* dcbt and dcbtst does not generate DTLB Misses/Errors,
......@@ -698,11 +711,11 @@ start_here:
#ifdef CONFIG_8xx_CPU6
lis r4, cpu6_errata_word@h
ori r4, r4, cpu6_errata_word@l
li r3, 0x3980
li r3, 0x3f80
stw r3, 12(r4)
lwz r3, 12(r4)
#endif
mtspr SPRN_M_TWB, r6
mtspr SPRN_M_TW, r6
lis r4,2f@h
ori r4,r4,2f@l
tophys(r4,r4)
......@@ -876,10 +889,10 @@ _GLOBAL(set_context)
lis r6, cpu6_errata_word@h
ori r6, r6, cpu6_errata_word@l
tophys (r4, r4)
li r7, 0x3980
li r7, 0x3f80
stw r7, 12(r6)
lwz r7, 12(r6)
mtspr SPRN_M_TWB, r4 /* Update MMU base address */
mtspr SPRN_M_TW, r4 /* Update MMU base address */
li r7, 0x3380
stw r7, 12(r6)
lwz r7, 12(r6)
......@@ -887,7 +900,7 @@ _GLOBAL(set_context)
#else
mtspr SPRN_M_CASID,r3 /* Update context */
tophys (r4, r4)
mtspr SPRN_M_TWB, r4 /* and pgd */
mtspr SPRN_M_TW, r4 /* and pgd */
#endif
SYNC
blr
......@@ -919,12 +932,13 @@ set_dec_cpu6:
.globl sdata
sdata:
.globl empty_zero_page
.align PAGE_SHIFT
empty_zero_page:
.space 4096
.space PAGE_SIZE
.globl swapper_pg_dir
swapper_pg_dir:
.space 4096
.space PGD_TABLE_SIZE
/* Room for two PTE table poiners, usually the kernel and current user
* pointer to their respective root page table (pgdir).
......
......@@ -43,7 +43,6 @@
#include <asm/tlbflush.h>
#include <asm/siginfo.h>
#include <asm/debug.h>
#include <mm/mmu_decl.h>
#include "icswx.h"
......@@ -380,12 +379,6 @@ int __kprobes do_page_fault(struct pt_regs *regs, unsigned long address,
goto bad_area;
#endif /* CONFIG_6xx */
#if defined(CONFIG_8xx)
/* 8xx sometimes need to load a invalid/non-present TLBs.
* These must be invalidated separately as linux mm don't.
*/
if (error_code & 0x40000000) /* no translation? */
_tlbil_va(address, 0, 0, 0);
/* The MPC8xx seems to always set 0x80000000, which is
* "undefined". Of those that can be set, this is the only
* one which seems bad.
......
config FADS
bool
config CPM1
bool
select CPM
......@@ -13,7 +10,6 @@ choice
config MPC8XXFADS
bool "FADS"
select FADS
config MPC86XADS
bool "MPC86XADS"
......
......@@ -58,6 +58,19 @@
#define RIO_ISR_AACR 0x10120
#define RIO_ISR_AACR_AA 0x1 /* Accept All ID */
#define RIWTAR_TRAD_VAL_SHIFT 12
#define RIWTAR_TRAD_MASK 0x00FFFFFF
#define RIWBAR_BADD_VAL_SHIFT 12
#define RIWBAR_BADD_MASK 0x003FFFFF
#define RIWAR_ENABLE 0x80000000
#define RIWAR_TGINT_LOCAL 0x00F00000
#define RIWAR_RDTYP_NO_SNOOP 0x00040000
#define RIWAR_RDTYP_SNOOP 0x00050000
#define RIWAR_WRTYP_NO_SNOOP 0x00004000
#define RIWAR_WRTYP_SNOOP 0x00005000
#define RIWAR_WRTYP_ALLOC 0x00006000
#define RIWAR_SIZE_MASK 0x0000003F
#define __fsl_read_rio_config(x, addr, err, op) \
__asm__ __volatile__( \
"1: "op" %1,0(%2)\n" \
......@@ -266,6 +279,89 @@ fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
return 0;
}
static void fsl_rio_inbound_mem_init(struct rio_priv *priv)
{
int i;
/* close inbound windows */
for (i = 0; i < RIO_INB_ATMU_COUNT; i++)
out_be32(&priv->inb_atmu_regs[i].riwar, 0);
}
int fsl_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart,
u64 rstart, u32 size, u32 flags)
{
struct rio_priv *priv = mport->priv;
u32 base_size;
unsigned int base_size_log;
u64 win_start, win_end;
u32 riwar;
int i;
if ((size & (size - 1)) != 0)
return -EINVAL;
base_size_log = ilog2(size);
base_size = 1 << base_size_log;
/* check if addresses are aligned with the window size */
if (lstart & (base_size - 1))
return -EINVAL;
if (rstart & (base_size - 1))
return -EINVAL;
/* check for conflicting ranges */
for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
if ((riwar & RIWAR_ENABLE) == 0)
continue;
win_start = ((u64)(in_be32(&priv->inb_atmu_regs[i].riwbar) & RIWBAR_BADD_MASK))
<< RIWBAR_BADD_VAL_SHIFT;
win_end = win_start + ((1 << ((riwar & RIWAR_SIZE_MASK) + 1)) - 1);
if (rstart < win_end && (rstart + size) > win_start)
return -EINVAL;
}
/* find unused atmu */
for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
if ((riwar & RIWAR_ENABLE) == 0)
break;
}
if (i >= RIO_INB_ATMU_COUNT)
return -ENOMEM;
out_be32(&priv->inb_atmu_regs[i].riwtar, lstart >> RIWTAR_TRAD_VAL_SHIFT);
out_be32(&priv->inb_atmu_regs[i].riwbar, rstart >> RIWBAR_BADD_VAL_SHIFT);
out_be32(&priv->inb_atmu_regs[i].riwar, RIWAR_ENABLE | RIWAR_TGINT_LOCAL |
RIWAR_RDTYP_SNOOP | RIWAR_WRTYP_SNOOP | (base_size_log - 1));
return 0;
}
void fsl_unmap_inb_mem(struct rio_mport *mport, dma_addr_t lstart)
{
u32 win_start_shift, base_start_shift;
struct rio_priv *priv = mport->priv;
u32 riwar, riwtar;
int i;
/* skip default window */
base_start_shift = lstart >> RIWTAR_TRAD_VAL_SHIFT;
for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
if ((riwar & RIWAR_ENABLE) == 0)
continue;
riwtar = in_be32(&priv->inb_atmu_regs[i].riwtar);
win_start_shift = riwtar & RIWTAR_TRAD_MASK;
if (win_start_shift == base_start_shift) {
out_be32(&priv->inb_atmu_regs[i].riwar, riwar & ~RIWAR_ENABLE);
return;
}
}
}
void fsl_rio_port_error_handler(int offset)
{
/*XXX: Error recovery is not implemented, we just clear errors */
......@@ -389,6 +485,8 @@ int fsl_rio_setup(struct platform_device *dev)
ops->add_outb_message = fsl_add_outb_message;
ops->add_inb_buffer = fsl_add_inb_buffer;
ops->get_inb_message = fsl_get_inb_message;
ops->map_inb = fsl_map_inb_mem;
ops->unmap_inb = fsl_unmap_inb_mem;
rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
if (!rmu_node) {
......@@ -602,6 +700,11 @@ int fsl_rio_setup(struct platform_device *dev)
RIO_ATMU_REGS_PORT2_OFFSET));
priv->maint_atmu_regs = priv->atmu_regs + 1;
priv->inb_atmu_regs = (struct rio_inb_atmu_regs __iomem *)
(priv->regs_win +
((i == 0) ? RIO_INB_ATMU_REGS_PORT1_OFFSET :
RIO_INB_ATMU_REGS_PORT2_OFFSET));
/* Set to receive any dist ID for serial RapidIO controller. */
if (port->phy_type == RIO_PHY_SERIAL)
......@@ -620,6 +723,7 @@ int fsl_rio_setup(struct platform_device *dev)
rio_law_start = range_start;
fsl_rio_setup_rmu(port, rmu_np[i]);
fsl_rio_inbound_mem_init(priv);
dbell->mport[i] = port;
......
......@@ -50,9 +50,12 @@
#define RIO_S_DBELL_REGS_OFFSET 0x13400
#define RIO_S_PW_REGS_OFFSET 0x134e0
#define RIO_ATMU_REGS_DBELL_OFFSET 0x10C40
#define RIO_INB_ATMU_REGS_PORT1_OFFSET 0x10d60
#define RIO_INB_ATMU_REGS_PORT2_OFFSET 0x10f60
#define MAX_MSG_UNIT_NUM 2
#define MAX_PORT_NUM 4
#define RIO_INB_ATMU_COUNT 4
struct rio_atmu_regs {
u32 rowtar;
......@@ -63,6 +66,15 @@ struct rio_atmu_regs {
u32 pad2[3];
};
struct rio_inb_atmu_regs {
u32 riwtar;
u32 pad1;
u32 riwbar;
u32 pad2;
u32 riwar;
u32 pad3[3];
};
struct rio_dbell_ring {
void *virt;
dma_addr_t phys;
......@@ -99,6 +111,7 @@ struct rio_priv {
void __iomem *regs_win;
struct rio_atmu_regs __iomem *atmu_regs;
struct rio_atmu_regs __iomem *maint_atmu_regs;
struct rio_inb_atmu_regs __iomem *inb_atmu_regs;
void __iomem *maint_win;
void *rmm_handle; /* RapidIO message manager(unit) Handle */
};
......
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