Skip to content

L
linux
Commit 3886edbb authored by Olof Johansson's avatar Olof Johansson
Browse files
Options

Merge tag 'v5.6-rockchip-dts32-1' of... 

Merge tag 'v5.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/dt

Pin-name corrections for Veyron-Fievel, bluetooth for a number of veyron boards and
additional operating points for rk3288-tinker.

* tag 'v5.6-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: Use ABI name for recovery mode pin on veyron fievel/tiger
  ARM: dts: rockchip: Use ABI name for write protect pin on veyron fievel/tiger
  ARM: dts: rockchip: Add missing cpu operating points for rk3288-tinker
  ARM: dts: rockchip: Add brcm bluetooth for rk3288-veyron

Link: https://lore.kernel.org/r/8215452.dU6eVM2tAM@philSigned-off-by: default avatarOlof Johansson <olof@lixom.net>
parents afa7f6eb a950c4c6
Show whitespace changes
Inline Side-by-side
Showing with 177 additions and 78 deletions
arch/arm/boot/dts/rk3288-tinker.dtsi
View file @ 3886edbb
...@@ -113,6 +113,17 @@ &cpu0 { ...@@ -113,6 +113,17 @@ &cpu0 {
cpu0-supply = <&vdd_cpu>; cpu0-supply = <&vdd_cpu>;
}; };
&cpu_opp_table {
opp-1704000000 {
opp-hz = /bits/ 64 <1704000000>;
opp-microvolt = <1350000>;
};
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
opp-microvolt = <1400000>;
};
};
&gmac { &gmac {
assigned-clocks = <&cru SCLK_MAC>; assigned-clocks = <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>; assigned-clock-parents = <&ext_gmac>;
...@@ -175,7 +186,7 @@ vdd_cpu: DCDC_REG1 { ...@@ -175,7 +186,7 @@ vdd_cpu: DCDC_REG1 {
regulator-always-on; regulator-always-on;
regulator-boot-on; regulator-boot-on;
regulator-min-microvolt = <750000>; regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>; regulator-max-microvolt = <1400000>;
regulator-name = "vdd_arm"; regulator-name = "vdd_arm";
regulator-ramp-delay = <6000>; regulator-ramp-delay = <6000>;
regulator-state-mem { regulator-state-mem {
......
arch/arm/boot/dts/rk3288-veyron-brain.dts
View file @ 3886edbb
...@@ -7,6 +7,7 @@ ...@@ -7,6 +7,7 @@
/dts-v1/; /dts-v1/;
#include "rk3288-veyron.dtsi" #include "rk3288-veyron.dtsi"
#include "rk3288-veyron-broadcom-bluetooth.dtsi"
/ { / {
model = "Google Brain"; model = "Google Brain";
...@@ -40,6 +41,14 @@ vcc5_host2: vcc5-host2-regulator { ...@@ -40,6 +41,14 @@ vcc5_host2: vcc5-host2-regulator {
}; };
&pinctrl { &pinctrl {
pinctrl-names = "default";
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
>;
hdmi { hdmi {
vcc50_hdmi_en: vcc50-hdmi-en { vcc50_hdmi_en: vcc50-hdmi-en {
rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
......
arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi 0 → 100644
View file @ 3886edbb
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Veyron (and derivatives) fragment for the Broadcom 43450 bluetooth
* chip.
*
* Copyright 2019 Google, Inc
*/
&uart0 {
bluetooth {
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l>, <&bt_enable_l>,
<&bt_dev_wake>;
compatible = "brcm,bcm43540-bt";
host-wakeup-gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
max-speed = <3000000>;
brcm,bt-pcm-int-params = [01 02 00 01 01];
};
};
arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
View file @ 3886edbb
...@@ -136,27 +136,6 @@ trackpad@15 { ...@@ -136,27 +136,6 @@ trackpad@15 {
}; };
&pinctrl { &pinctrl {
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Wake only */
&suspend_l_wake
&bt_dev_wake_awake
>;
pinctrl-1 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Sleep only */
&suspend_l_sleep
&bt_dev_wake_sleep
>;
buttons { buttons {
ap_lid_int_l: ap-lid-int-l { ap_lid_int_l: ap-lid-int-l {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
......
arch/arm/boot/dts/rk3288-veyron-fievel.dts
View file @ 3886edbb
...@@ -18,8 +18,6 @@ / { ...@@ -18,8 +18,6 @@ / {
"google,veyron-fievel-rev0", "google,veyron-fievel", "google,veyron-fievel-rev0", "google,veyron-fievel",
"google,veyron", "rockchip,rk3288"; "google,veyron", "rockchip,rk3288";
/delete-node/ bt-activity;
vccsys: vccsys { vccsys: vccsys {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "vccsys"; regulator-name = "vccsys";
...@@ -215,7 +213,11 @@ &gpio0 { ...@@ -215,7 +213,11 @@ &gpio0 {
"PHY_PMEB", "PHY_PMEB",
"PHY_INT", "PHY_INT",
"REC_MODE_L", /*
* RECOVERY_SW_L is Chrome OS ABI. Schematics call
* it REC_MODE_L.
*/
"RECOVERY_SW_L",
"OTP_OUT", "OTP_OUT",
"", "",
"USB_OTG_POWER_EN", "USB_OTG_POWER_EN",
...@@ -382,7 +384,11 @@ &gpio7 { ...@@ -382,7 +384,11 @@ &gpio7 {
"PWR_LED1", "PWR_LED1",
"TPM_INT_H", "TPM_INT_H",
"SPK_ON", "SPK_ON",
"FW_WP_AP", /*
* AP_FLASH_WP_L is Chrome OS ABI. Schematics call
* it FW_WP_AP.
*/
"AP_FLASH_WP_L",
"", "",
"CPU_NMI", "CPU_NMI",
......
arch/arm/boot/dts/rk3288-veyron-jaq.dts
View file @ 3886edbb
...@@ -273,6 +273,28 @@ &gpio8 { ...@@ -273,6 +273,28 @@ &gpio8 {
}; };
&pinctrl { &pinctrl {
pinctrl-names = "default", "sleep";
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Wake only */
&suspend_l_wake
&bt_dev_wake_awake
>;
pinctrl-1 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Sleep only */
&suspend_l_sleep
&bt_dev_wake_sleep
>;
buck-5v { buck-5v {
drv_5v: drv-5v { drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
......
arch/arm/boot/dts/rk3288-veyron-jerry.dts
View file @ 3886edbb
...@@ -418,6 +418,28 @@ &gpio8 { ...@@ -418,6 +418,28 @@ &gpio8 {
}; };
&pinctrl { &pinctrl {
pinctrl-names = "default", "sleep";
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Wake only */
&suspend_l_wake
&bt_dev_wake_awake
>;
pinctrl-1 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Sleep only */
&suspend_l_sleep
&bt_dev_wake_sleep
>;
buck-5v { buck-5v {
drv_5v: drv-5v { drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
......
arch/arm/boot/dts/rk3288-veyron-mickey.dts
View file @ 3886edbb
...@@ -7,6 +7,7 @@ ...@@ -7,6 +7,7 @@
/dts-v1/; /dts-v1/;
#include "rk3288-veyron.dtsi" #include "rk3288-veyron.dtsi"
#include "rk3288-veyron-broadcom-bluetooth.dtsi"
/ { / {
model = "Google Mickey"; model = "Google Mickey";
...@@ -411,6 +412,14 @@ &gpio8 { ...@@ -411,6 +412,14 @@ &gpio8 {
}; };
&pinctrl { &pinctrl {
pinctrl-names = "default";
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
>;
hdmi { hdmi {
power_hdmi_on: power-hdmi-on { power_hdmi_on: power-hdmi-on {
rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
......
arch/arm/boot/dts/rk3288-veyron-minnie.dts
View file @ 3886edbb
...@@ -7,6 +7,7 @@ ...@@ -7,6 +7,7 @@
/dts-v1/; /dts-v1/;
#include "rk3288-veyron-chromebook.dtsi" #include "rk3288-veyron-chromebook.dtsi"
#include "rk3288-veyron-broadcom-bluetooth.dtsi"
/ { / {
model = "Google Minnie"; model = "Google Minnie";
...@@ -344,6 +345,26 @@ &gpio8 { ...@@ -344,6 +345,26 @@ &gpio8 {
}; };
&pinctrl { &pinctrl {
pinctrl-names = "default", "sleep";
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Wake only */
&suspend_l_wake
>;
pinctrl-1 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Sleep only */
&suspend_l_sleep
>;
buck-5v { buck-5v {
drv_5v: drv-5v { drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
......
arch/arm/boot/dts/rk3288-veyron-pinky.dts
View file @ 3886edbb
...@@ -64,6 +64,28 @@ &panel { ...@@ -64,6 +64,28 @@ &panel {
}; };
&pinctrl { &pinctrl {
pinctrl-names = "default", "sleep";
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Wake only */
&suspend_l_wake
&bt_dev_wake_awake
>;
pinctrl-1 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Sleep only */
&suspend_l_sleep
&bt_dev_wake_sleep
>;
/delete-node/ lcd; /delete-node/ lcd;
backlight { backlight {
......
arch/arm/boot/dts/rk3288-veyron-speedy.dts
View file @ 3886edbb
...@@ -7,6 +7,7 @@ ...@@ -7,6 +7,7 @@
/dts-v1/; /dts-v1/;
#include "rk3288-veyron-chromebook.dtsi" #include "rk3288-veyron-chromebook.dtsi"
#include "rk3288-veyron-broadcom-bluetooth.dtsi"
#include "cros-ec-sbs.dtsi" #include "cros-ec-sbs.dtsi"
/ { / {
...@@ -279,6 +280,26 @@ &gpio8 { ...@@ -279,6 +280,26 @@ &gpio8 {
}; };
&pinctrl { &pinctrl {
pinctrl-names = "default", "sleep";
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Wake only */
&suspend_l_wake
>;
pinctrl-1 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Sleep only */
&suspend_l_sleep
>;
buck-5v { buck-5v {
drv_5v: drv-5v { drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
......
arch/arm/boot/dts/rk3288-veyron.dtsi
View file @ 3886edbb
...@@ -23,30 +23,6 @@ memory { ...@@ -23,30 +23,6 @@ memory {
reg = <0x0 0x0 0x0 0x80000000>; reg = <0x0 0x0 0x0 0x80000000>;
}; };
bt_activity: bt-activity {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake>;
/*
* HACK: until we have an LPM driver, we'll use an
* ugly GPIO key to allow Bluetooth to wake from S3.
* This is expected to only be used by BT modules that
* use UART for comms. For BT modules that talk over
* SDIO we should use a wakeup mechanism related to SDIO.
*
* Use KEY_RESERVED here since that will work as a wakeup but
* doesn't get reported to higher levels (so doesn't confuse
* Chrome).
*/
bt-wake {
label = "BT Wakeup";
gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_RESERVED>;
wakeup-source;
};
};
power_button: power-button { power_button: power-button {
compatible = "gpio-keys"; compatible = "gpio-keys";
...@@ -82,22 +58,17 @@ sdio_pwrseq: sdio-pwrseq { ...@@ -82,22 +58,17 @@ sdio_pwrseq: sdio-pwrseq {
clocks = <&rk808 RK808_CLKOUT1>; clocks = <&rk808 RK808_CLKOUT1>;
clock-names = "ext_clock"; clock-names = "ext_clock";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>; pinctrl-0 = <&wifi_enable_h>;
/* /*
* Depending on the actual card populated GPIO4 D4 and D5 * Depending on the actual card populated GPIO4 D4
* correspond to one of these signals on the module: * correspond to one of these signals on the module:
* *
* D4: * D4:
* - SDIO_RESET_L_WL_REG_ON * - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low) * - PDN (power down when low)
*
* D5:
* - BT_I2S_WS_BT_RFDISABLE_L
* - No connect
*/ */
reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>, reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
<&gpio4 RK_PD5 GPIO_ACTIVE_LOW>;
}; };
vcc_5v: vcc-5v { vcc_5v: vcc-5v {
...@@ -481,26 +452,6 @@ &wdt { ...@@ -481,26 +452,6 @@ &wdt {
}; };
&pinctrl { &pinctrl {
pinctrl-names = "default", "sleep";
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Wake only */
&bt_dev_wake_awake
>;
pinctrl-1 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Sleep only */
&bt_dev_wake_sleep
>;
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
bias-disable; bias-disable;
drive-strength = <8>; drive-strength = <8>;
...@@ -622,6 +573,10 @@ bt_dev_wake_sleep: bt-dev-wake-sleep { ...@@ -622,6 +573,10 @@ bt_dev_wake_sleep: bt-dev-wake-sleep {
bt_dev_wake_awake: bt-dev-wake-awake { bt_dev_wake_awake: bt-dev-wake-awake {
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>; rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;
}; };
bt_dev_wake: bt-dev-wake {
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
}; };
tpm { tpm {
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7