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Commit 398abaab authored by William Breathitt Gray's avatar William Breathitt Gray
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counter: 104-quad-8: Utilize bitfield access macros 

The 104-QUAD-8 features several registers with various bitfields.
Utilize bitfield access macros such as u8_get_bits() and
u8_encode_bits() to make the code easier to read and the intent clearer.
Suggested-by: default avatarJonathan Cameron <jic23@kernel.org>
Link: https://lore.kernel.org/r/7cea5ad049c75d8d1c6f25e288aa743a8d2a25d8.1681753140.git.william.gray@linaro.org/Signed-off-by: default avatarWilliam Breathitt Gray <william.gray@linaro.org>
parent 228354ed
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drivers/counter/104-quad-8.c
View file @ 398abaab
...@@ -5,7 +5,8 @@ ...@@ -5,7 +5,8 @@
* *
* This driver supports the ACCES 104-QUAD-8 and ACCES 104-QUAD-4. * This driver supports the ACCES 104-QUAD-8 and ACCES 104-QUAD-4.
*/ */
#include <linux/bitops.h> #include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/counter.h> #include <linux/counter.h>
#include <linux/device.h> #include <linux/device.h>
#include <linux/errno.h> #include <linux/errno.h>
...@@ -98,36 +99,108 @@ struct quad8 { ...@@ -98,36 +99,108 @@ struct quad8 {
}; };
/* Error flag */ /* Error flag */
#define QUAD8_FLAG_E BIT(4) #define FLAG_E BIT(4)
/* Up/Down flag */ /* Up/Down flag */
#define QUAD8_FLAG_UD BIT(5) #define FLAG_UD BIT(5)
#define REGISTER_SELECTION GENMASK(6, 5)
/* Reset and Load Signal Decoders */ /* Reset and Load Signal Decoders */
#define QUAD8_CTR_RLD 0x00 #define SELECT_RLD u8_encode_bits(0x0, REGISTER_SELECTION)
/* Counter Mode Register */ /* Counter Mode Register */
#define QUAD8_CTR_CMR 0x20 #define SELECT_CMR u8_encode_bits(0x1, REGISTER_SELECTION)
/* Input / Output Control Register */ /* Input / Output Control Register */
#define QUAD8_CTR_IOR 0x40 #define SELECT_IOR u8_encode_bits(0x2, REGISTER_SELECTION)
/* Index Control Register */ /* Index Control Register */
#define QUAD8_CTR_IDR 0x60 #define SELECT_IDR u8_encode_bits(0x3, REGISTER_SELECTION)
/*
* Reset and Load Signal Decoders
*/
#define RESETS GENMASK(2, 1)
#define LOADS GENMASK(4, 3)
/* Reset Byte Pointer (three byte data pointer) */ /* Reset Byte Pointer (three byte data pointer) */
#define QUAD8_RLD_RESET_BP 0x01 #define RESET_BP BIT(0)
/* Reset Counter */ /* Reset Borrow Toggle, Carry toggle, Compare toggle, Sign, and Index flags */
#define QUAD8_RLD_RESET_CNTR 0x02 #define RESET_BT_CT_CPT_S_IDX u8_encode_bits(0x2, RESETS)
/* Reset Borrow Toggle, Carry Toggle, Compare Toggle, and Sign flags */
#define QUAD8_RLD_RESET_FLAGS 0x04
/* Reset Error flag */ /* Reset Error flag */
#define QUAD8_RLD_RESET_E 0x06 #define RESET_E u8_encode_bits(0x3, RESETS)
/* Preset Register to Counter */ /* Preset Register to Counter */
#define QUAD8_RLD_PRESET_CNTR 0x08 #define TRANSFER_PR_TO_CNTR u8_encode_bits(0x1, LOADS)
/* Transfer Counter to Output Latch */ /* Transfer Counter to Output Latch */
#define QUAD8_RLD_CNTR_OUT 0x10 #define TRANSFER_CNTR_TO_OL u8_encode_bits(0x2, LOADS)
/* Transfer Preset Register LSB to FCK Prescaler */ /* Transfer Preset Register LSB to FCK Prescaler */
#define QUAD8_RLD_PRESET_PSC 0x18 #define TRANSFER_PR0_TO_PSC u8_encode_bits(0x3, LOADS)
#define QUAD8_CHAN_OP_RESET_COUNTERS 0x01
#define QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC 0x04 /*
#define QUAD8_CMR_QUADRATURE_X1 0x08 * Counter Mode Registers
#define QUAD8_CMR_QUADRATURE_X2 0x10 */
#define QUAD8_CMR_QUADRATURE_X4 0x18 #define COUNT_ENCODING BIT(0)
#define COUNT_MODE GENMASK(2, 1)
#define QUADRATURE_MODE GENMASK(4, 3)
/* Binary count */
#define BINARY u8_encode_bits(0x0, COUNT_ENCODING)
/* Normal count */
#define NORMAL_COUNT 0x0
/* Range Limit */
#define RANGE_LIMIT 0x1
/* Non-recycle count */
#define NON_RECYCLE_COUNT 0x2
/* Modulo-N */
#define MODULO_N 0x3
/* Non-quadrature */
#define NON_QUADRATURE 0x0
/* Quadrature X1 */
#define QUADRATURE_X1 0x1
/* Quadrature X2 */
#define QUADRATURE_X2 0x2
/* Quadrature X4 */
#define QUADRATURE_X4 0x3
/*
* Input/Output Control Register
*/
#define AB_GATE BIT(0)
#define LOAD_PIN BIT(1)
#define FLG_PINS GENMASK(4, 3)
/* Disable inputs A and B */
#define DISABLE_AB u8_encode_bits(0x0, AB_GATE)
/* Load Counter input */
#define LOAD_CNTR 0x0
/* FLG1 = CARRY(active low); FLG2 = BORROW(active low) */
#define FLG1_CARRY_FLG2_BORROW 0x0
/* FLG1 = COMPARE(active low); FLG2 = BORROW(active low) */
#define FLG1_COMPARE_FLG2_BORROW 0x1
/* FLG1 = Carry(active low)/Borrow(active low); FLG2 = U/D(active low) flag */
#define FLG1_CARRYBORROW_FLG2_UD 0x2
/* FLG1 = INDX (low pulse at INDEX pin active level); FLG2 = E flag */
#define FLG1_INDX_FLG2_E 0x3
/*
* INDEX CONTROL REGISTERS
*/
#define INDEX_MODE BIT(0)
#define INDEX_POLARITY BIT(1)
/* Disable Index mode */
#define DISABLE_INDEX_MODE 0x0
/* Negative Index Polarity */
#define NEGATIVE_INDEX_POLARITY 0x0
/*
* Channel Operation Register
*/
#define COUNTERS_OPERATION BIT(0)
#define INTERRUPT_FUNCTION BIT(2)
/* Enable all Counters */
#define ENABLE_COUNTERS u8_encode_bits(0x0, COUNTERS_OPERATION)
/* Reset all Counters */
#define RESET_COUNTERS u8_encode_bits(0x1, COUNTERS_OPERATION)
/* Disable the interrupt function */
#define DISABLE_INTERRUPT_FUNCTION u8_encode_bits(0x0, INTERRUPT_FUNCTION)
/* Enable the interrupt function */
#define ENABLE_INTERRUPT_FUNCTION u8_encode_bits(0x1, INTERRUPT_FUNCTION)
/* Any write to the Channel Operation register clears any pending interrupts */
#define CLEAR_PENDING_INTERRUPTS (ENABLE_COUNTERS | ENABLE_INTERRUPT_FUNCTION)
/* Each Counter is 24 bits wide */ /* Each Counter is 24 bits wide */
#define LS7267_CNTR_MAX GENMASK(23, 0) #define LS7267_CNTR_MAX GENMASK(23, 0)
...@@ -162,9 +235,7 @@ static int quad8_count_read(struct counter_device *counter, ...@@ -162,9 +235,7 @@ static int quad8_count_read(struct counter_device *counter,
spin_lock_irqsave(&priv->lock, irqflags); spin_lock_irqsave(&priv->lock, irqflags);
/* Reset Byte Pointer; transfer Counter to Output Latch */ iowrite8(SELECT_RLD | RESET_BP | TRANSFER_CNTR_TO_OL, &chan->control);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT,
&chan->control);
for (i = 0; i < 3; i++) for (i = 0; i < 3; i++)
*val |= (unsigned long)ioread8(&chan->data) << (8 * i); *val |= (unsigned long)ioread8(&chan->data) << (8 * i);
...@@ -187,28 +258,23 @@ static int quad8_count_write(struct counter_device *counter, ...@@ -187,28 +258,23 @@ static int quad8_count_write(struct counter_device *counter,
spin_lock_irqsave(&priv->lock, irqflags); spin_lock_irqsave(&priv->lock, irqflags);
/* Reset Byte Pointer */ iowrite8(SELECT_RLD | RESET_BP, &chan->control);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
/* Counter can only be set via Preset Register */ /* Counter can only be set via Preset Register */
for (i = 0; i < 3; i++) for (i = 0; i < 3; i++)
iowrite8(val >> (8 * i), &chan->data); iowrite8(val >> (8 * i), &chan->data);
/* Transfer Preset Register to Counter */ iowrite8(SELECT_RLD | TRANSFER_PR_TO_CNTR, &chan->control);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_PRESET_CNTR, &chan->control);
/* Reset Byte Pointer */ iowrite8(SELECT_RLD | RESET_BP, &chan->control);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
/* Set Preset Register back to original value */ /* Set Preset Register back to original value */
val = priv->preset[count->id]; val = priv->preset[count->id];
for (i = 0; i < 3; i++) for (i = 0; i < 3; i++)
iowrite8(val >> (8 * i), &chan->data); iowrite8(val >> (8 * i), &chan->data);
/* Reset Borrow, Carry, Compare, and Sign flags */ iowrite8(SELECT_RLD | RESET_BT_CT_CPT_S_IDX, &chan->control);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, &chan->control); iowrite8(SELECT_RLD | RESET_E, &chan->control);
/* Reset Error flag */
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, &chan->control);
spin_unlock_irqrestore(&priv->lock, irqflags); spin_unlock_irqrestore(&priv->lock, irqflags);
...@@ -279,8 +345,8 @@ static int quad8_function_write(struct counter_device *counter, ...@@ -279,8 +345,8 @@ static int quad8_function_write(struct counter_device *counter,
spin_lock_irqsave(&priv->lock, irqflags); spin_lock_irqsave(&priv->lock, irqflags);
mode_cfg = priv->count_mode[id] << 1; mode_cfg = u8_encode_bits(priv->count_mode[id], COUNT_MODE);
idr_cfg = priv->index_polarity[id] << 1; idr_cfg = u8_encode_bits(priv->index_polarity[id], INDEX_POLARITY);
if (function == COUNTER_FUNCTION_PULSE_DIRECTION) { if (function == COUNTER_FUNCTION_PULSE_DIRECTION) {
*quadrature_mode = 0; *quadrature_mode = 0;
...@@ -288,11 +354,14 @@ static int quad8_function_write(struct counter_device *counter, ...@@ -288,11 +354,14 @@ static int quad8_function_write(struct counter_device *counter,
/* Quadrature scaling only available in quadrature mode */ /* Quadrature scaling only available in quadrature mode */
*scale = 0; *scale = 0;
mode_cfg |= u8_encode_bits(NON_QUADRATURE, QUADRATURE_MODE);
/* Synchronous function not supported in non-quadrature mode */ /* Synchronous function not supported in non-quadrature mode */
if (*synchronous_mode) { if (*synchronous_mode) {
*synchronous_mode = 0; *synchronous_mode = 0;
/* Disable synchronous function mode */ /* Disable synchronous function mode */
iowrite8(QUAD8_CTR_IDR | idr_cfg, control); idr_cfg |= u8_encode_bits(*synchronous_mode, INDEX_MODE);
iowrite8(SELECT_IDR | idr_cfg, control);
} }
} else { } else {
*quadrature_mode = 1; *quadrature_mode = 1;
...@@ -300,15 +369,15 @@ static int quad8_function_write(struct counter_device *counter, ...@@ -300,15 +369,15 @@ static int quad8_function_write(struct counter_device *counter,
switch (function) { switch (function) {
case COUNTER_FUNCTION_QUADRATURE_X1_A: case COUNTER_FUNCTION_QUADRATURE_X1_A:
*scale = 0; *scale = 0;
mode_cfg |= QUAD8_CMR_QUADRATURE_X1; mode_cfg |= u8_encode_bits(QUADRATURE_X1, QUADRATURE_MODE);
break; break;
case COUNTER_FUNCTION_QUADRATURE_X2_A: case COUNTER_FUNCTION_QUADRATURE_X2_A:
*scale = 1; *scale = 1;
mode_cfg |= QUAD8_CMR_QUADRATURE_X2; mode_cfg |= u8_encode_bits(QUADRATURE_X2, QUADRATURE_MODE);
break; break;
case COUNTER_FUNCTION_QUADRATURE_X4: case COUNTER_FUNCTION_QUADRATURE_X4:
*scale = 2; *scale = 2;
mode_cfg |= QUAD8_CMR_QUADRATURE_X4; mode_cfg |= u8_encode_bits(QUADRATURE_X4, QUADRATURE_MODE);
break; break;
default: default:
/* should never reach this path */ /* should never reach this path */
...@@ -318,7 +387,7 @@ static int quad8_function_write(struct counter_device *counter, ...@@ -318,7 +387,7 @@ static int quad8_function_write(struct counter_device *counter,
} }
/* Load mode configuration to Counter Mode Register */ /* Load mode configuration to Counter Mode Register */
iowrite8(QUAD8_CTR_CMR | mode_cfg, control); iowrite8(SELECT_CMR | mode_cfg, control);
spin_unlock_irqrestore(&priv->lock, irqflags); spin_unlock_irqrestore(&priv->lock, irqflags);
...@@ -332,9 +401,11 @@ static int quad8_direction_read(struct counter_device *counter, ...@@ -332,9 +401,11 @@ static int quad8_direction_read(struct counter_device *counter,
const struct quad8 *const priv = counter_priv(counter); const struct quad8 *const priv = counter_priv(counter);
unsigned int ud_flag; unsigned int ud_flag;
u8 __iomem *const flag_addr = &priv->reg->channel[count->id].control; u8 __iomem *const flag_addr = &priv->reg->channel[count->id].control;
u8 flag;
flag = ioread8(flag_addr);
/* U/D flag: nonzero = up, zero = down */ /* U/D flag: nonzero = up, zero = down */
ud_flag = ioread8(flag_addr) & QUAD8_FLAG_UD; ud_flag = u8_get_bits(flag, FLAG_UD);
*direction = (ud_flag) ? COUNTER_COUNT_DIRECTION_FORWARD : *direction = (ud_flag) ? COUNTER_COUNT_DIRECTION_FORWARD :
COUNTER_COUNT_DIRECTION_BACKWARD; COUNTER_COUNT_DIRECTION_BACKWARD;
...@@ -423,10 +494,10 @@ static int quad8_action_read(struct counter_device *counter, ...@@ -423,10 +494,10 @@ static int quad8_action_read(struct counter_device *counter,
} }
enum { enum {
QUAD8_EVENT_CARRY = 0, QUAD8_EVENT_CARRY = FLG1_CARRY_FLG2_BORROW,
QUAD8_EVENT_COMPARE = 1, QUAD8_EVENT_COMPARE = FLG1_COMPARE_FLG2_BORROW,
QUAD8_EVENT_CARRY_BORROW = 2, QUAD8_EVENT_CARRY_BORROW = FLG1_CARRYBORROW_FLG2_UD,
QUAD8_EVENT_INDEX = 3, QUAD8_EVENT_INDEX = FLG1_INDX_FLG2_E,
}; };
static int quad8_events_configure(struct counter_device *counter) static int quad8_events_configure(struct counter_device *counter)
...@@ -471,10 +542,10 @@ static int quad8_events_configure(struct counter_device *counter) ...@@ -471,10 +542,10 @@ static int quad8_events_configure(struct counter_device *counter)
priv->irq_trigger[event_node->channel] = next_irq_trigger; priv->irq_trigger[event_node->channel] = next_irq_trigger;
/* Load configuration to I/O Control Register */ /* Load configuration to I/O Control Register */
ior_cfg = priv->ab_enable[event_node->channel] | ior_cfg = u8_encode_bits(priv->ab_enable[event_node->channel], AB_GATE) |
priv->preset_enable[event_node->channel] << 1 | u8_encode_bits(priv->preset_enable[event_node->channel], LOAD_PIN) |
priv->irq_trigger[event_node->channel] << 3; u8_encode_bits(priv->irq_trigger[event_node->channel], FLG_PINS);
iowrite8(QUAD8_CTR_IOR | ior_cfg, iowrite8(SELECT_IOR | ior_cfg,
&priv->reg->channel[event_node->channel].control); &priv->reg->channel[event_node->channel].control);
} }
...@@ -544,16 +615,16 @@ static int quad8_index_polarity_set(struct counter_device *counter, ...@@ -544,16 +615,16 @@ static int quad8_index_polarity_set(struct counter_device *counter,
const size_t channel_id = signal->id - 16; const size_t channel_id = signal->id - 16;
u8 __iomem *const control = &priv->reg->channel[channel_id].control; u8 __iomem *const control = &priv->reg->channel[channel_id].control;
unsigned long irqflags; unsigned long irqflags;
unsigned int idr_cfg = index_polarity << 1; unsigned int idr_cfg = u8_encode_bits(index_polarity, INDEX_POLARITY);
spin_lock_irqsave(&priv->lock, irqflags); spin_lock_irqsave(&priv->lock, irqflags);
idr_cfg |= priv->synchronous_mode[channel_id]; idr_cfg |= u8_encode_bits(priv->synchronous_mode[channel_id], INDEX_MODE);
priv->index_polarity[channel_id] = index_polarity; priv->index_polarity[channel_id] = index_polarity;
/* Load Index Control configuration to Index Control Register */ /* Load Index Control configuration to Index Control Register */
iowrite8(QUAD8_CTR_IDR | idr_cfg, control); iowrite8(SELECT_IDR | idr_cfg, control);
spin_unlock_irqrestore(&priv->lock, irqflags); spin_unlock_irqrestore(&priv->lock, irqflags);
...@@ -611,11 +682,11 @@ static int quad8_synchronous_mode_set(struct counter_device *counter, ...@@ -611,11 +682,11 @@ static int quad8_synchronous_mode_set(struct counter_device *counter,
const size_t channel_id = signal->id - 16; const size_t channel_id = signal->id - 16;
u8 __iomem *const control = &priv->reg->channel[channel_id].control; u8 __iomem *const control = &priv->reg->channel[channel_id].control;
unsigned long irqflags; unsigned long irqflags;
unsigned int idr_cfg = synchronous_mode; unsigned int idr_cfg = u8_encode_bits(synchronous_mode, INDEX_MODE);
spin_lock_irqsave(&priv->lock, irqflags); spin_lock_irqsave(&priv->lock, irqflags);
idr_cfg |= priv->index_polarity[channel_id] << 1; idr_cfg |= u8_encode_bits(priv->index_polarity[channel_id], INDEX_POLARITY);
/* Index function must be non-synchronous in non-quadrature mode */ /* Index function must be non-synchronous in non-quadrature mode */
if (synchronous_mode && !priv->quadrature_mode[channel_id]) { if (synchronous_mode && !priv->quadrature_mode[channel_id]) {
...@@ -626,7 +697,7 @@ static int quad8_synchronous_mode_set(struct counter_device *counter, ...@@ -626,7 +697,7 @@ static int quad8_synchronous_mode_set(struct counter_device *counter,
priv->synchronous_mode[channel_id] = synchronous_mode; priv->synchronous_mode[channel_id] = synchronous_mode;
/* Load Index Control configuration to Index Control Register */ /* Load Index Control configuration to Index Control Register */
iowrite8(QUAD8_CTR_IDR | idr_cfg, control); iowrite8(SELECT_IDR | idr_cfg, control);
spin_unlock_irqrestore(&priv->lock, irqflags); spin_unlock_irqrestore(&priv->lock, irqflags);
...@@ -648,18 +719,17 @@ static int quad8_count_mode_read(struct counter_device *counter, ...@@ -648,18 +719,17 @@ static int quad8_count_mode_read(struct counter_device *counter,
{ {
const struct quad8 *const priv = counter_priv(counter); const struct quad8 *const priv = counter_priv(counter);
/* Map 104-QUAD-8 count mode to Generic Counter count mode */
switch (priv->count_mode[count->id]) { switch (priv->count_mode[count->id]) {
case 0: case NORMAL_COUNT:
*cnt_mode = COUNTER_COUNT_MODE_NORMAL; *cnt_mode = COUNTER_COUNT_MODE_NORMAL;
break; break;
case 1: case RANGE_LIMIT:
*cnt_mode = COUNTER_COUNT_MODE_RANGE_LIMIT; *cnt_mode = COUNTER_COUNT_MODE_RANGE_LIMIT;
break; break;
case 2: case NON_RECYCLE_COUNT:
*cnt_mode = COUNTER_COUNT_MODE_NON_RECYCLE; *cnt_mode = COUNTER_COUNT_MODE_NON_RECYCLE;
break; break;
case 3: case MODULO_N:
*cnt_mode = COUNTER_COUNT_MODE_MODULO_N; *cnt_mode = COUNTER_COUNT_MODE_MODULO_N;
break; break;
} }
...@@ -677,19 +747,18 @@ static int quad8_count_mode_write(struct counter_device *counter, ...@@ -677,19 +747,18 @@ static int quad8_count_mode_write(struct counter_device *counter,
u8 __iomem *const control = &priv->reg->channel[count->id].control; u8 __iomem *const control = &priv->reg->channel[count->id].control;
unsigned long irqflags; unsigned long irqflags;
/* Map Generic Counter count mode to 104-QUAD-8 count mode */
switch (cnt_mode) { switch (cnt_mode) {
case COUNTER_COUNT_MODE_NORMAL: case COUNTER_COUNT_MODE_NORMAL:
count_mode = 0; count_mode = NORMAL_COUNT;
break; break;
case COUNTER_COUNT_MODE_RANGE_LIMIT: case COUNTER_COUNT_MODE_RANGE_LIMIT:
count_mode = 1; count_mode = RANGE_LIMIT;
break; break;
case COUNTER_COUNT_MODE_NON_RECYCLE: case COUNTER_COUNT_MODE_NON_RECYCLE:
count_mode = 2; count_mode = NON_RECYCLE_COUNT;
break; break;
case COUNTER_COUNT_MODE_MODULO_N: case COUNTER_COUNT_MODE_MODULO_N:
count_mode = 3; count_mode = MODULO_N;
break; break;
default: default:
/* should never reach this path */ /* should never reach this path */
...@@ -701,14 +770,16 @@ static int quad8_count_mode_write(struct counter_device *counter, ...@@ -701,14 +770,16 @@ static int quad8_count_mode_write(struct counter_device *counter,
priv->count_mode[count->id] = count_mode; priv->count_mode[count->id] = count_mode;
/* Set count mode configuration value */ /* Set count mode configuration value */
mode_cfg = count_mode << 1; mode_cfg = u8_encode_bits(count_mode, COUNT_MODE);
/* Add quadrature mode configuration */ /* Add quadrature mode configuration */
if (priv->quadrature_mode[count->id]) if (priv->quadrature_mode[count->id])
mode_cfg |= (priv->quadrature_scale[count->id] + 1) << 3; mode_cfg |= u8_encode_bits(priv->quadrature_scale[count->id] + 1, QUADRATURE_MODE);
else
mode_cfg |= u8_encode_bits(NON_QUADRATURE, QUADRATURE_MODE);
/* Load mode configuration to Counter Mode Register */ /* Load mode configuration to Counter Mode Register */
iowrite8(QUAD8_CTR_CMR | mode_cfg, control); iowrite8(SELECT_CMR | mode_cfg, control);
spin_unlock_irqrestore(&priv->lock, irqflags); spin_unlock_irqrestore(&priv->lock, irqflags);
...@@ -737,11 +808,12 @@ static int quad8_count_enable_write(struct counter_device *counter, ...@@ -737,11 +808,12 @@ static int quad8_count_enable_write(struct counter_device *counter,
priv->ab_enable[count->id] = enable; priv->ab_enable[count->id] = enable;
ior_cfg = enable | priv->preset_enable[count->id] << 1 | ior_cfg = u8_encode_bits(enable, AB_GATE) |
priv->irq_trigger[count->id] << 3; u8_encode_bits(priv->preset_enable[count->id], LOAD_PIN) |
u8_encode_bits(priv->irq_trigger[count->id], FLG_PINS);
/* Load I/O control configuration */ /* Load I/O control configuration */
iowrite8(QUAD8_CTR_IOR | ior_cfg, control); iowrite8(SELECT_IOR | ior_cfg, control);
spin_unlock_irqrestore(&priv->lock, irqflags); spin_unlock_irqrestore(&priv->lock, irqflags);
...@@ -758,8 +830,10 @@ static int quad8_error_noise_get(struct counter_device *counter, ...@@ -758,8 +830,10 @@ static int quad8_error_noise_get(struct counter_device *counter,
{ {
const struct quad8 *const priv = counter_priv(counter); const struct quad8 *const priv = counter_priv(counter);
u8 __iomem *const flag_addr = &priv->reg->channel[count->id].control; u8 __iomem *const flag_addr = &priv->reg->channel[count->id].control;
u8 flag;
*noise_error = !!(ioread8(flag_addr) & QUAD8_FLAG_E); flag = ioread8(flag_addr);
*noise_error = u8_get_bits(flag, FLAG_E);
return 0; return 0;
} }
...@@ -782,8 +856,7 @@ static void quad8_preset_register_set(struct quad8 *const priv, const int id, ...@@ -782,8 +856,7 @@ static void quad8_preset_register_set(struct quad8 *const priv, const int id,
priv->preset[id] = preset; priv->preset[id] = preset;
/* Reset Byte Pointer */ iowrite8(SELECT_RLD | RESET_BP, &chan->control);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
/* Set Preset Register */ /* Set Preset Register */
for (i = 0; i < 3; i++) for (i = 0; i < 3; i++)
...@@ -818,8 +891,8 @@ static int quad8_count_ceiling_read(struct counter_device *counter, ...@@ -818,8 +891,8 @@ static int quad8_count_ceiling_read(struct counter_device *counter,
/* Range Limit and Modulo-N count modes use preset value as ceiling */ /* Range Limit and Modulo-N count modes use preset value as ceiling */
switch (priv->count_mode[count->id]) { switch (priv->count_mode[count->id]) {
case 1: case RANGE_LIMIT:
case 3: case MODULO_N:
*ceiling = priv->preset[count->id]; *ceiling = priv->preset[count->id];
break; break;
default: default:
...@@ -845,8 +918,8 @@ static int quad8_count_ceiling_write(struct counter_device *counter, ...@@ -845,8 +918,8 @@ static int quad8_count_ceiling_write(struct counter_device *counter,
/* Range Limit and Modulo-N count modes use preset value as ceiling */ /* Range Limit and Modulo-N count modes use preset value as ceiling */
switch (priv->count_mode[count->id]) { switch (priv->count_mode[count->id]) {
case 1: case RANGE_LIMIT:
case 3: case MODULO_N:
quad8_preset_register_set(priv, count->id, ceiling); quad8_preset_register_set(priv, count->id, ceiling);
spin_unlock_irqrestore(&priv->lock, irqflags); spin_unlock_irqrestore(&priv->lock, irqflags);
return 0; return 0;
...@@ -884,11 +957,12 @@ static int quad8_count_preset_enable_write(struct counter_device *counter, ...@@ -884,11 +957,12 @@ static int quad8_count_preset_enable_write(struct counter_device *counter,
priv->preset_enable[count->id] = preset_enable; priv->preset_enable[count->id] = preset_enable;
ior_cfg = priv->ab_enable[count->id] | preset_enable << 1 | ior_cfg = u8_encode_bits(priv->ab_enable[count->id], AB_GATE) |
priv->irq_trigger[count->id] << 3; u8_encode_bits(preset_enable, LOAD_PIN) |
u8_encode_bits(priv->irq_trigger[count->id], FLG_PINS);
/* Load I/O control configuration to Input / Output Control Register */ /* Load I/O control configuration to Input / Output Control Register */
iowrite8(QUAD8_CTR_IOR | ior_cfg, control); iowrite8(SELECT_IOR | ior_cfg, control);
spin_unlock_irqrestore(&priv->lock, irqflags); spin_unlock_irqrestore(&priv->lock, irqflags);
...@@ -987,13 +1061,11 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter, ...@@ -987,13 +1061,11 @@ static int quad8_signal_fck_prescaler_write(struct counter_device *counter,
priv->fck_prescaler[channel_id] = prescaler; priv->fck_prescaler[channel_id] = prescaler;
/* Reset Byte Pointer */ iowrite8(SELECT_RLD | RESET_BP, &chan->control);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
/* Set filter clock factor */ /* Set filter clock factor */
iowrite8(prescaler, &chan->data); iowrite8(prescaler, &chan->data);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, iowrite8(SELECT_RLD | RESET_BP | TRANSFER_PR0_TO_PSC, &chan->control);
&chan->control);
spin_unlock_irqrestore(&priv->lock, irqflags); spin_unlock_irqrestore(&priv->lock, irqflags);
...@@ -1183,7 +1255,7 @@ static irqreturn_t quad8_irq_handler(int irq, void *private) ...@@ -1183,7 +1255,7 @@ static irqreturn_t quad8_irq_handler(int irq, void *private)
} }
/* Clear pending interrupts on device */ /* Clear pending interrupts on device */
iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, &priv->reg->channel_oper); iowrite8(CLEAR_PENDING_INTERRUPTS, &priv->reg->channel_oper);
return IRQ_HANDLED; return IRQ_HANDLED;
} }
...@@ -1192,27 +1264,25 @@ static void quad8_init_counter(struct channel_reg __iomem *const chan) ...@@ -1192,27 +1264,25 @@ static void quad8_init_counter(struct channel_reg __iomem *const chan)
{ {
unsigned long i; unsigned long i;
/* Reset Byte Pointer */ iowrite8(SELECT_RLD | RESET_BP, &chan->control);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
/* Reset filter clock factor */ /* Reset filter clock factor */
iowrite8(0, &chan->data); iowrite8(0, &chan->data);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_PRESET_PSC, iowrite8(SELECT_RLD | RESET_BP | TRANSFER_PR0_TO_PSC, &chan->control);
&chan->control); iowrite8(SELECT_RLD | RESET_BP, &chan->control);
/* Reset Byte Pointer */
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP, &chan->control);
/* Reset Preset Register */ /* Reset Preset Register */
for (i = 0; i < 3; i++) for (i = 0; i < 3; i++)
iowrite8(0x00, &chan->data); iowrite8(0x00, &chan->data);
/* Reset Borrow, Carry, Compare, and Sign flags */ iowrite8(SELECT_RLD | RESET_BT_CT_CPT_S_IDX, &chan->control);
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_FLAGS, &chan->control); iowrite8(SELECT_RLD | RESET_E, &chan->control);
/* Reset Error flag */
iowrite8(QUAD8_CTR_RLD | QUAD8_RLD_RESET_E, &chan->control);
/* Binary encoding; Normal count; non-quadrature mode */ /* Binary encoding; Normal count; non-quadrature mode */
iowrite8(QUAD8_CTR_CMR, &chan->control); iowrite8(SELECT_CMR | BINARY | u8_encode_bits(NORMAL_COUNT, COUNT_MODE) |
u8_encode_bits(NON_QUADRATURE, QUADRATURE_MODE), &chan->control);
/* Disable A and B inputs; preset on index; FLG1 as Carry */ /* Disable A and B inputs; preset on index; FLG1 as Carry */
iowrite8(QUAD8_CTR_IOR, &chan->control); iowrite8(SELECT_IOR | DISABLE_AB | u8_encode_bits(LOAD_CNTR, LOAD_PIN) |
u8_encode_bits(FLG1_CARRY_FLG2_BORROW, FLG_PINS), &chan->control);
/* Disable index function; negative index polarity */ /* Disable index function; negative index polarity */
iowrite8(QUAD8_CTR_IDR, &chan->control); iowrite8(SELECT_IDR | u8_encode_bits(DISABLE_INDEX_MODE, INDEX_MODE) |
u8_encode_bits(NEGATIVE_INDEX_POLARITY, INDEX_POLARITY), &chan->control);
} }
static int quad8_probe(struct device *dev, unsigned int id) static int quad8_probe(struct device *dev, unsigned int id)
...@@ -1251,14 +1321,14 @@ static int quad8_probe(struct device *dev, unsigned int id) ...@@ -1251,14 +1321,14 @@ static int quad8_probe(struct device *dev, unsigned int id)
/* Reset Index/Interrupt Register */ /* Reset Index/Interrupt Register */
iowrite8(0x00, &priv->reg->index_interrupt); iowrite8(0x00, &priv->reg->index_interrupt);
/* Reset all counters and disable interrupt function */ /* Reset all counters and disable interrupt function */
iowrite8(QUAD8_CHAN_OP_RESET_COUNTERS, &priv->reg->channel_oper); iowrite8(RESET_COUNTERS | DISABLE_INTERRUPT_FUNCTION, &priv->reg->channel_oper);
/* Set initial configuration for all counters */ /* Set initial configuration for all counters */
for (i = 0; i < QUAD8_NUM_COUNTERS; i++) for (i = 0; i < QUAD8_NUM_COUNTERS; i++)
quad8_init_counter(priv->reg->channel + i); quad8_init_counter(priv->reg->channel + i);
/* Disable Differential Encoder Cable Status for all channels */ /* Disable Differential Encoder Cable Status for all channels */
iowrite8(0xFF, &priv->reg->cable_status); iowrite8(0xFF, &priv->reg->cable_status);
/* Enable all counters and enable interrupt function */ /* Enable all counters and enable interrupt function */
iowrite8(QUAD8_CHAN_OP_ENABLE_INTERRUPT_FUNC, &priv->reg->channel_oper); iowrite8(ENABLE_COUNTERS | ENABLE_INTERRUPT_FUNCTION, &priv->reg->channel_oper);
err = devm_request_irq(&counter->dev, irq[id], quad8_irq_handler, err = devm_request_irq(&counter->dev, irq[id], quad8_irq_handler,
IRQF_SHARED, counter->name, counter); IRQF_SHARED, counter->name, counter);
......
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