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Commit 3c22ba52 authored by Sukadev Bhattiprolu's avatar Sukadev Bhattiprolu Committed by Arnaldo Carvalho de Melo
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perf vendor events powerpc: Update POWER9 events 

Update and cleanup POWER9 PMU events.
Signed-off-by: default avatarSukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Cc: Anton Blanchard <anton@au1.ibm.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Link: http://lkml.kernel.org/r/20170802174617.GA32545@us.ibm.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 2862a168
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tools/perf/pmu-events/arch/powerpc/power9/cache.json
View file @ 3c22ba52
[
{,
"EventCode": "0x1002A",
"EventName": "PM_CMPLU_STALL_LARX",
"BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied",
"PublicDescription": ""
"EventCode": "0x300F4",
"EventName": "PM_THRD_CONC_RUN_INST",
"BriefDescription": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set"
},
{,
"EventCode": "0x1003C",
"EventName": "PM_CMPLU_STALL_DMISS_L2L3",
"BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3",
"PublicDescription": ""
"EventCode": "0x1E056",
"EventName": "PM_CMPLU_STALL_FLUSH_ANY_THREAD",
"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion"
},
{,
"EventCode": "0x14048",
"EventName": "PM_INST_FROM_ON_CHIP_CACHE",
"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x4D016",
"EventName": "PM_CMPLU_STALL_FXLONG",
"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (division, square root)"
},
{,
"EventCode": "0x3E054",
"EventName": "PM_LD_MISS_L1",
"BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load.",
"PublicDescription": ""
"EventCode": "0x2D016",
"EventName": "PM_CMPLU_STALL_FXU",
"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes"
},
{,
"EventCode": "0x400F0",
"EventName": "PM_LD_MISS_L1",
"BriefDescription": "Load Missed L1, at execution time (not gated by finish, which means this counter can be greater than loads finished)",
"PublicDescription": ""
"EventCode": "0x1D15C",
"EventName": "PM_MRK_DTLB_MISS_1G",
"BriefDescription": "Marked Data TLB reload (after a miss) page size 2M. Implies radix translation was used"
},
{,
"EventCode": "0x1404A",
"EventName": "PM_INST_FROM_RL2L3_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x4D12A",
"EventName": "PM_MRK_DATA_FROM_RL4_CYC",
"BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load"
},
{,
"EventCode": "0x1C058",
"EventName": "PM_DTLB_MISS_16G",
"BriefDescription": "Data TLB Miss page size 16G",
"PublicDescription": ""
"EventCode": "0x1003C",
"EventName": "PM_CMPLU_STALL_DMISS_L2L3",
"BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3"
},
{,
"EventCode": "0x1D15C",
"EventName": "PM_MRK_DTLB_MISS_1G",
"BriefDescription": "Marked Data TLB reload (after a miss) page size 2M. Implies radix translation was used",
"PublicDescription": ""
"EventCode": "0x4C014",
"EventName": "PM_CMPLU_STALL_LMQ_FULL",
"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full"
},
{,
"EventCode": "0x1E056",
"EventName": "PM_CMPLU_STALL_FLUSH_ANY_THREAD",
"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion",
"PublicDescription": ""
"EventCode": "0x14048",
"EventName": "PM_INST_FROM_ON_CHIP_CACHE",
"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x101E6",
"EventName": "PM_THRESH_EXC_4096",
"BriefDescription": "Threshold counter exceed a count of 4096",
"PublicDescription": ""
"EventCode": "0x4D014",
"EventName": "PM_CMPLU_STALL_LOAD_FINISH",
"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish"
},
{,
"EventCode": "0x2C01A",
"EventName": "PM_CMPLU_STALL_LHS",
"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data",
"PublicDescription": ""
"EventCode": "0x2404A",
"EventName": "PM_INST_FROM_RL4",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x2D016",
"EventName": "PM_CMPLU_STALL_FXU",
"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes",
"PublicDescription": ""
"EventCode": "0x1404A",
"EventName": "PM_INST_FROM_RL2L3_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x24046",
"EventName": "PM_INST_FROM_RL2L3_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x401EA",
"EventName": "PM_THRESH_EXC_128",
"BriefDescription": "Threshold counter exceeded a value of 128"
},
{,
"EventCode": "0x2404A",
"EventName": "PM_INST_FROM_RL4",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x400F6",
"EventName": "PM_BR_MPRED_CMPL",
"BriefDescription": "Number of Branch Mispredicts"
},
{,
"EventCode": "0x2F140",
"EventName": "PM_MRK_DPTEG_FROM_L2_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x2D15E",
"EventName": "PM_MRK_DTLB_MISS_16G",
"BriefDescription": "Marked Data TLB Miss page size 16G",
"PublicDescription": ""
},
{,
"EventCode": "0x3F14A",
"EventName": "PM_MRK_DPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x101E6",
"EventName": "PM_THRESH_EXC_4096",
"BriefDescription": "Threshold counter exceed a count of 4096"
},
{,
"EventCode": "0x3D156",
"EventName": "PM_MRK_DTLB_MISS_64K",
"BriefDescription": "Marked Data TLB Miss page size 64K",
"PublicDescription": ""
"BriefDescription": "Marked Data TLB Miss page size 64K"
},
{,
"EventCode": "0x3006C",
"EventName": "PM_RUN_CYC_SMT2_MODE",
"BriefDescription": "Cycles in which this thread's run latch is set and the core is in SMT2 mode",
"PublicDescription": ""
"EventCode": "0x4C15E",
"EventName": "PM_MRK_DTLB_MISS_16M",
"BriefDescription": "Marked Data TLB Miss page size 16M"
},
{,
"EventCode": "0x300F4",
"EventName": "PM_THRD_CONC_RUN_INST",
"BriefDescription": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set",
"PublicDescription": ""
"EventCode": "0x2D15E",
"EventName": "PM_MRK_DTLB_MISS_16G",
"BriefDescription": "Marked Data TLB Miss page size 16G"
},
{,
"EventCode": "0x4C014",
"EventName": "PM_CMPLU_STALL_LMQ_FULL",
"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full",
"PublicDescription": ""
"EventCode": "0x3F14A",
"EventName": "PM_MRK_DPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x4C016",
"EventName": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT",
"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict",
"PublicDescription": ""
},
{,
"EventCode": "0x4D014",
"EventName": "PM_CMPLU_STALL_LOAD_FINISH",
"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish",
"PublicDescription": ""
"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict"
},
{,
"EventCode": "0x4D016",
"EventName": "PM_CMPLU_STALL_FXLONG",
"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (division, square root)",
"PublicDescription": ""
"EventCode": "0x2C01A",
"EventName": "PM_CMPLU_STALL_LHS",
"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data"
},
{,
"EventCode": "0x4D12A",
"EventName": "PM_MRK_DATA_FROM_RL4_CYC",
"BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
"PublicDescription": ""
"EventCode": "0x401E4",
"EventName": "PM_MRK_DTLB_MISS",
"BriefDescription": "Marked dtlb miss"
},
{,
"EventCode": "0x4C15E",
"EventName": "PM_MRK_DTLB_MISS_16M",
"BriefDescription": "Marked Data TLB Miss page size 16M",
"PublicDescription": ""
"EventCode": "0x24046",
"EventName": "PM_INST_FROM_RL2L3_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x401E4",
"EventName": "PM_MRK_DTLB_MISS",
"BriefDescription": "Marked dtlb miss",
"PublicDescription": ""
"EventCode": "0x1002A",
"EventName": "PM_CMPLU_STALL_LARX",
"BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied"
},
{,
"EventCode": "0x401EA",
"EventName": "PM_THRESH_EXC_128",
"BriefDescription": "Threshold counter exceeded a value of 128",
"PublicDescription": ""
"EventCode": "0x3006C",
"EventName": "PM_RUN_CYC_SMT2_MODE",
"BriefDescription": "Cycles in which this thread's run latch is set and the core is in SMT2 mode"
},
{,
"EventCode": "0x400F6",
"EventName": "PM_BR_MPRED_CMPL",
"BriefDescription": "Number of Branch Mispredicts",
"PublicDescription": ""
"EventCode": "0x1C058",
"EventName": "PM_DTLB_MISS_16G",
"BriefDescription": "Data TLB Miss page size 16G"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/powerpc/power9/floating-point.json
View file @ 3c22ba52
[
{,
"EventCode": "0x10058",
"EventName": "PM_MEM_LOC_THRESH_IFU",
"BriefDescription": "Local Memory above threshold for IFU speculation control",
"PublicDescription": ""
},
{,
"EventCode": "0x4505E",
"EventName": "PM_FLOP_CMPL",
"BriefDescription": "Floating Point Operation Finished",
"PublicDescription": ""
},
{,
"EventCode": "0x1415A",
"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load",
"PublicDescription": ""
"BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load"
},
{,
"EventCode": "0x2D028",
"EventName": "PM_RADIX_PWC_L2_PDE_FROM_L2",
"BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache",
"PublicDescription": ""
"EventCode": "0x10058",
"EventName": "PM_MEM_LOC_THRESH_IFU",
"BriefDescription": "Local Memory above threshold for IFU speculation control"
},
{,
"EventCode": "0x2D154",
"EventName": "PM_MRK_DERAT_MISS_64K",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K",
"PublicDescription": ""
"EventCode": "0x2D028",
"EventName": "PM_RADIX_PWC_L2_PDE_FROM_L2",
"BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache"
},
{,
"EventCode": "0x30012",
"EventName": "PM_FLUSH_COMPLETION",
"BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush",
"PublicDescription": ""
"BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush"
},
{,
"EventCode": "0x2D154",
"EventName": "PM_MRK_DERAT_MISS_64K",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K"
},
{,
"EventCode": "0x4016E",
"EventName": "PM_THRESH_NOT_MET",
"BriefDescription": "Threshold counter did not meet threshold",
"PublicDescription": ""
"BriefDescription": "Threshold counter did not meet threshold"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/powerpc/power9/frontend.json
View file @ 3c22ba52
[
{,
"EventCode": "0x20036",
"EventName": "PM_BR_2PATH",
"BriefDescription": "Branches that are not strongly biased",
"PublicDescription": ""
"EventCode": "0x3E15C",
"EventName": "PM_MRK_L2_TM_ST_ABORT_SISTER",
"BriefDescription": "TM marked store abort for this thread"
},
{,
"EventCode": "0x40036",
"EventName": "PM_BR_2PATH",
"BriefDescription": "Branches that are not strongly biased",
"PublicDescription": ""
"EventCode": "0x25044",
"EventName": "PM_IPTEG_FROM_L31_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request"
},
{,
"EventCode": "0x10004",
"EventName": "PM_CMPLU_STALL_LRQ_OTHER",
"BriefDescription": "Finish stall due to LRQ miscellaneous reasons, lost arbitration to LMQ slot, bank collisions, set prediction cleanup, set prediction multihit and others",
"PublicDescription": ""
"EventCode": "0x101E8",
"EventName": "PM_THRESH_EXC_256",
"BriefDescription": "Threshold counter exceed a count of 256"
},
{,
"EventCode": "0x10010",
"EventName": "PM_PMC4_OVERFLOW",
"BriefDescription": "Overflow from counter 4",
"PublicDescription": ""
"EventCode": "0x4504E",
"EventName": "PM_IPTEG_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a instruction side request"
},
{,
"EventCode": "0x1006A",
"EventName": "PM_NTC_ISSUE_HELD_DARQ_FULL",
"BriefDescription": "The NTC instruction is being held at dispatch because there are no slots in the DARQ for it"
},
{,
"EventCode": "0x4E016",
"EventName": "PM_CMPLU_STALL_LSAQ_ARB",
"BriefDescription": "Finish stall because the NTF instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ won arbitration to the LSU pipe when this instruction tried to launch"
},
{,
"EventCode": "0x1001A",
"EventName": "PM_LSU_SRQ_FULL_CYC",
"BriefDescription": "Cycles in which the Store Queue is full on all 4 slices. This is event is not per thread. All the threads will see the same count for this core resource",
"PublicDescription": ""
"BriefDescription": "Cycles in which the Store Queue is full on all 4 slices. This is event is not per thread. All the threads will see the same count for this core resource"
},
{,
"EventCode": "0x10020",
"EventName": "PM_PMC4_REWIND",
"BriefDescription": "PMC4 Rewind Event",
"PublicDescription": ""
"EventCode": "0x1E15E",
"EventName": "PM_MRK_L2_TM_REQ_ABORT",
"BriefDescription": "TM abort"
},
{,
"EventCode": "0x1003A",
"EventName": "PM_CMPLU_STALL_LSU_FIN",
"BriefDescription": "Finish stall because the NTF instruction was an LSU op (other than a load or a store) with all its dependencies met and just going through the LSU pipe to finish",
"PublicDescription": ""
"EventCode": "0x34052",
"EventName": "PM_INST_SYS_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch"
},
{,
"EventCode": "0x1013E",
"EventName": "PM_MRK_LD_MISS_EXPOSED_CYC",
"BriefDescription": "Marked Load exposed Miss (use edge detect to count #)",
"PublicDescription": ""
"EventCode": "0x20114",
"EventName": "PM_MRK_L2_RC_DISP",
"BriefDescription": "Marked Instruction RC dispatched in L2"
},
{,
"EventCode": "0x4C044",
"EventName": "PM_DATA_FROM_L31_ECO_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load"
},
{,
"EventCode": "0x1C044",
"EventName": "PM_DATA_FROM_L3_NO_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load",
"PublicDescription": ""
"BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a demand load"
},
{,
"EventCode": "0x15044",
"EventName": "PM_IPTEG_FROM_L3_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request",
"PublicDescription": ""
"EventCode": "0x44050",
"EventName": "PM_INST_SYS_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch"
},
{,
"EventCode": "0x15046",
"EventName": "PM_IPTEG_FROM_L3.1_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request",
"PublicDescription": ""
"EventCode": "0x30154",
"EventName": "PM_MRK_FAB_RSP_DCLAIM",
"BriefDescription": "Marked store had to do a dclaim"
},
{,
"EventCode": "0x1015E",
"EventName": "PM_MRK_FAB_RSP_RD_T_INTV",
"BriefDescription": "Sampled Read got a T intervention",
"PublicDescription": ""
"EventCode": "0x30014",
"EventName": "PM_CMPLU_STALL_STORE_FIN_ARB",
"BriefDescription": "Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. This means the instruction is ready to finish but there are instructions ahead of it, using the finish pipe"
},
{,
"EventCode": "0x14054",
"EventName": "PM_INST_PUMP_CPRED",
"BriefDescription": "Pump prediction correct. Counts across all types of pumps for an instruction fetch",
"PublicDescription": ""
"EventCode": "0x3E054",
"EventName": "PM_LD_MISS_L1",
"BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load."
},
{,
"EventCode": "0x15152",
"EventName": "PM_SYNC_MRK_BR_LINK",
"BriefDescription": "Marked Branch and link branch that can cause a synchronous interrupt",
"PublicDescription": ""
"EventCode": "0x400F0",
"EventName": "PM_LD_MISS_L1",
"BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load."
},
{,
"EventCode": "0x1515C",
"EventName": "PM_SYNC_MRK_BR_MPRED",
"BriefDescription": "Marked Branch mispredict that can cause a synchronous interrupt",
"PublicDescription": ""
"EventCode": "0x2E01A",
"EventName": "PM_CMPLU_STALL_LSU_FLUSH_NEXT",
"BriefDescription": "Completion stall of one cycle because the LSU requested to flush the next iop in the sequence. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to complete"
},
{,
"EventCode": "0x1E050",
"EventName": "PM_CMPLU_STALL_TEND",
"BriefDescription": "Finish stall because the NTF instruction was a tend instruction awaiting response from L2",
"PublicDescription": ""
"EventCode": "0x2D01C",
"EventName": "PM_CMPLU_STALL_STCX",
"BriefDescription": "Finish stall because the NTF instruction was a stcx waiting for response from L2"
},
{,
"EventCode": "0x1E15E",
"EventName": "PM_MRK_L2_TM_REQ_ABORT",
"BriefDescription": "TM abort",
"PublicDescription": ""
"EventCode": "0x2C010",
"EventName": "PM_CMPLU_STALL_LSU",
"BriefDescription": "Completion stall by LSU instruction"
},
{,
"EventCode": "0x1F054",
"EventName": "PM_TLB_HIT",
"BriefDescription": "Number of times the TLB had the data required by the instruction. Applies to both HPT and RPT",
"PublicDescription": ""
"EventCode": "0x2C042",
"EventName": "PM_DATA_FROM_L3_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load"
},
{,
"EventCode": "0x1006A",
"EventName": "PM_NTC_ISSUE_HELD_DARQ_FULL",
"BriefDescription": "The NTC instruction is being held at dispatch because there are no slots in the DARQ for it",
"PublicDescription": ""
"EventCode": "0x4E012",
"EventName": "PM_CMPLU_STALL_MTFPSCR",
"BriefDescription": "Completion stall because the ISU is updating the register and notifying the Effective Address Table (EAT)"
},
{,
"EventCode": "0x101E8",
"EventName": "PM_THRESH_EXC_256",
"BriefDescription": "Threshold counter exceed a count of 256",
"PublicDescription": ""
"EventCode": "0x100F2",
"EventName": "PM_1PLUS_PPC_CMPL",
"BriefDescription": "1 or more ppc insts finished"
},
{,
"EventCode": "0x101EC",
"EventName": "PM_THRESH_MET",
"BriefDescription": "threshold exceeded",
"PublicDescription": ""
"EventCode": "0x3001C",
"EventName": "PM_LSU_REJECT_LMQ_FULL",
"BriefDescription": "LSU Reject due to LMQ full (up to 4 per cycles)"
},
{,
"EventCode": "0x100F2",
"EventName": "PM_1PLUS_PPC_CMPL",
"BriefDescription": "1 or more ppc insts finished",
"PublicDescription": ""
"EventCode": "0x15046",
"EventName": "PM_IPTEG_FROM_L31_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request"
},
{,
"EventCode": "0x20114",
"EventName": "PM_MRK_L2_RC_DISP",
"BriefDescription": "Marked Instruction RC dispatched in L2",
"PublicDescription": ""
"EventCode": "0x1015E",
"EventName": "PM_MRK_FAB_RSP_RD_T_INTV",
"BriefDescription": "Sampled Read got a T intervention"
},
{,
"EventCode": "0x2C010",
"EventName": "PM_CMPLU_STALL_LSU",
"BriefDescription": "Completion stall by LSU instruction",
"PublicDescription": ""
"EventCode": "0x101EC",
"EventName": "PM_THRESH_MET",
"BriefDescription": "threshold exceeded"
},
{,
"EventCode": "0x2C014",
"EventName": "PM_CMPLU_STALL_STORE_FINISH",
"BriefDescription": "Finish stall because the NTF instruction was a store with all its dependencies met, just waiting to go through the LSU pipe to finish",
"PublicDescription": ""
"EventCode": "0x10020",
"EventName": "PM_PMC4_REWIND",
"BriefDescription": "PMC4 Rewind Event"
},
{,
"EventCode": "0x2C01E",
"EventName": "PM_CMPLU_STALL_SYNC_PMU_INT",
"BriefDescription": "Cycles in which the NTC instruction is waiting for a synchronous PMU interrupt",
"PublicDescription": ""
"EventCode": "0x301EA",
"EventName": "PM_THRESH_EXC_1024",
"BriefDescription": "Threshold counter exceeded a value of 1024"
},
{,
"EventCode": "0x2D01C",
"EventName": "PM_CMPLU_STALL_STCX",
"BriefDescription": "Finish stall because the NTF instruction was a stcx waiting for response from L2",
"PublicDescription": ""
"EventCode": "0x34056",
"EventName": "PM_CMPLU_STALL_LSU_MFSPR",
"BriefDescription": "Finish stall because the NTF instruction was a mfspr instruction targeting an LSU SPR and it was waiting for the register data to be returned"
},
{,
"EventCode": "0x2E01A",
"EventName": "PM_CMPLU_STALL_LSU_FLUSH_NEXT",
"BriefDescription": "Completion stall of one cycle because the LSU requested to flush the next iop in the sequence. It takes 1 cycle for the ISU to process this request before the LSU instruction is allowed to complete",
"PublicDescription": ""
"EventCode": "0x44056",
"EventName": "PM_VECTOR_ST_CMPL",
"BriefDescription": "Number of vector store instructions completed"
},
{,
"EventCode": "0x2C124",
"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load",
"PublicDescription": ""
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load"
},
{,
"EventCode": "0x2C042",
"EventName": "PM_DATA_FROM_L3_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to a demand load",
"PublicDescription": ""
},
{,
"EventCode": "0x2D14C",
"EventName": "PM_MRK_DATA_FROM_L3.1_ECO_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load",
"PublicDescription": ""
"EventCode": "0x4C12A",
"EventName": "PM_MRK_DATA_FROM_RL2L3_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load"
},
{,
"EventCode": "0x25042",
"EventName": "PM_IPTEG_FROM_L3_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request",
"PublicDescription": ""
"EventCode": "0x3C056",
"EventName": "PM_DTLB_MISS_64K",
"BriefDescription": "Data TLB Miss page size 64K"
},
{,
"EventCode": "0x25044",
"EventName": "PM_IPTEG_FROM_L3.1_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request",
"PublicDescription": ""
"EventCode": "0x30060",
"EventName": "PM_TM_TRANS_RUN_INST",
"BriefDescription": "Run instructions completed in transactional state (gated by the run latch)"
},
{,
"EventCode": "0x2015E",
"EventName": "PM_MRK_FAB_RSP_RWITM_RTY",
"BriefDescription": "Sampled store did a rwitm and got a rty",
"PublicDescription": ""
"EventCode": "0x2C014",
"EventName": "PM_CMPLU_STALL_STORE_FINISH",
"BriefDescription": "Finish stall because the NTF instruction was a store with all its dependencies met, just waiting to go through the LSU pipe to finish"
},
{,
"EventCode": "0x24050",
"EventName": "PM_IOPS_CMPL",
"BriefDescription": "Internal Operations completed",
"PublicDescription": ""
"EventCode": "0x3515A",
"EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC",
"BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load"
},
{,
"EventCode": "0x24154",
"EventName": "PM_THRESH_ACC",
"BriefDescription": "This event increments every time the threshold event counter ticks. Thresholding must be enabled (via MMCRA) and the thresholding start event must occur for this counter to increment. It will stop incrementing when the thresholding stop event occurs or when thresholding is disabled, until the next time a configured thresholding start event occurs.",
"PublicDescription": ""
"EventCode": "0x34050",
"EventName": "PM_INST_SYS_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch"
},
{,
"EventCode": "0x2F152",
"EventName": "PM_MRK_FAB_RSP_DCLAIM_CYC",
"BriefDescription": "cycles L2 RC took for a dclaim",
"PublicDescription": ""
"EventCode": "0x3015E",
"EventName": "PM_MRK_FAB_RSP_CLAIM_RTY",
"BriefDescription": "Sampled store did a rwitm and got a rty"
},
{,
"EventCode": "0x200FA",
"EventName": "PM_BR_TAKEN_CMPL",
"BriefDescription": "New event for Branch Taken",
"PublicDescription": ""
"EventCode": "0x0",
"EventName": "PM_SUSPENDED",
"BriefDescription": "Counter OFF"
},
{,
"EventCode": "0x30014",
"EventName": "PM_CMPLU_STALL_STORE_FIN_ARB",
"BriefDescription": "Finish stall because the NTF instruction was a store waiting for a slot in the store finish pipe. This means the instruction is ready to finish but there are instructions ahead of it, using the finish pipe",
"PublicDescription": ""
"EventCode": "0x10010",
"EventName": "PM_PMC4_OVERFLOW",
"BriefDescription": "Overflow from counter 4"
},
{,
"EventCode": "0x3001C",
"EventName": "PM_LSU_REJECT_LMQ_FULL",
"BriefDescription": "LSU Reject due to LMQ full (up to 4 per cycles)",
"PublicDescription": ""
"EventCode": "0x3E04A",
"EventName": "PM_DPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x30026",
"EventName": "PM_CMPLU_STALL_STORE_DATA",
"BriefDescription": "Finish stall because the next to finish instruction was a store waiting on data",
"PublicDescription": ""
"EventCode": "0x2F152",
"EventName": "PM_MRK_FAB_RSP_DCLAIM_CYC",
"BriefDescription": "cycles L2 RC took for a dclaim"
},
{,
"EventCode": "0x3012A",
"EventName": "PM_MRK_L2_RC_DONE",
"BriefDescription": "Marked RC done",
"PublicDescription": ""
"EventCode": "0x10004",
"EventName": "PM_CMPLU_STALL_LRQ_OTHER",
"BriefDescription": "Finish stall due to LRQ miscellaneous reasons, lost arbitration to LMQ slot, bank collisions, set prediction cleanup, set prediction multihit and others"
},
{,
"EventCode": "0x35044",
"EventName": "PM_IPTEG_FROM_L3.1_ECO_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request",
"PublicDescription": ""
"EventCode": "0x4F150",
"EventName": "PM_MRK_FAB_RSP_RWITM_CYC",
"BriefDescription": "cycles L2 RC took for a rwitm"
},
{,
"EventCode": "0x3E04A",
"EventName": "PM_DPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x4E042",
"EventName": "PM_DPTEG_FROM_L3",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x30154",
"EventName": "PM_MRK_FAB_RSP_DCLAIM",
"BriefDescription": "Marked store had to do a dclaim",
"PublicDescription": ""
"EventCode": "0x1F054",
"EventName": "PM_TLB_HIT",
"BriefDescription": "Number of times the TLB had the data required by the instruction. Applies to both HPT and RPT"
},
{,
"EventCode": "0x3015E",
"EventName": "PM_MRK_FAB_RSP_CLAIM_RTY",
"BriefDescription": "Sampled store did a rwitm and got a rty",
"PublicDescription": ""
"EventCode": "0x2C01E",
"EventName": "PM_CMPLU_STALL_SYNC_PMU_INT",
"BriefDescription": "Cycles in which the NTC instruction is waiting for a synchronous PMU interrupt"
},
{,
"EventCode": "0x3C056",
"EventName": "PM_DTLB_MISS_64K",
"BriefDescription": "Data TLB Miss page size 64K",
"PublicDescription": ""
"EventCode": "0x24050",
"EventName": "PM_IOPS_CMPL",
"BriefDescription": "Internal Operations completed"
},
{,
"EventCode": "0x34050",
"EventName": "PM_INST_SYS_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for an instruction fetch",
"PublicDescription": ""
"EventCode": "0x1515C",
"EventName": "PM_SYNC_MRK_BR_MPRED",
"BriefDescription": "Marked Branch mispredict that can cause a synchronous interrupt"
},
{,
"EventCode": "0x34052",
"EventName": "PM_INST_SYS_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for an instruction fetch",
"PublicDescription": ""
"EventCode": "0x300FA",
"EventName": "PM_INST_FROM_L3MISS",
"BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet"
},
{,
"EventCode": "0x34056",
"EventName": "PM_CMPLU_STALL_LSU_MFSPR",
"BriefDescription": "Finish stall because the NTF instruction was a mfspr instruction targeting an LSU SPR and it was waiting for the register data to be returned",
"PublicDescription": ""
"EventCode": "0x15044",
"EventName": "PM_IPTEG_FROM_L3_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request"
},
{,
"EventCode": "0x3515A",
"EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC",
"BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
"PublicDescription": ""
"EventCode": "0x15152",
"EventName": "PM_SYNC_MRK_BR_LINK",
"BriefDescription": "Marked Branch and link branch that can cause a synchronous interrupt"
},
{,
"EventCode": "0x3515C",
"EventName": "PM_MRK_DATA_FROM_RL4",
"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
"PublicDescription": ""
"EventCode": "0x1E050",
"EventName": "PM_CMPLU_STALL_TEND",
"BriefDescription": "Finish stall because the NTF instruction was a tend instruction awaiting response from L2"
},
{,
"EventCode": "0x3E15C",
"EventName": "PM_MRK_L2_TM_ST_ABORT_SISTER",
"BriefDescription": "TM marked store abort for this thread",
"PublicDescription": ""
"EventCode": "0x1013E",
"EventName": "PM_MRK_LD_MISS_EXPOSED_CYC",
"BriefDescription": "Marked Load exposed Miss (use edge detect to count #)"
},
{,
"EventCode": "0x30060",
"EventName": "PM_TM_TRANS_RUN_INST",
"BriefDescription": "Run instructions completed in transactional state (gated by the run latch)",
"PublicDescription": ""
"EventCode": "0x25042",
"EventName": "PM_IPTEG_FROM_L3_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request"
},
{,
"EventCode": "0x301E6",
"EventName": "PM_MRK_DERAT_MISS",
"BriefDescription": "Erat Miss (TLB Access) All page sizes",
"PublicDescription": ""
"EventCode": "0x14054",
"EventName": "PM_INST_PUMP_CPRED",
"BriefDescription": "Pump prediction correct. Counts across all types of pumps for an instruction fetch"
},
{,
"EventCode": "0x301EA",
"EventName": "PM_THRESH_EXC_1024",
"BriefDescription": "Threshold counter exceeded a value of 1024",
"PublicDescription": ""
"EventCode": "0x4015E",
"EventName": "PM_MRK_FAB_RSP_RD_RTY",
"BriefDescription": "Sampled L2 reads retry count"
},
{,
"EventCode": "0x300FA",
"EventName": "PM_INST_FROM_L3MISS",
"BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet",
"PublicDescription": ""
"EventCode": "0x45048",
"EventName": "PM_IPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request"
},
{,
"EventCode": "0x40116",
"EventName": "PM_MRK_LARX_FIN",
"BriefDescription": "Larx finished",
"PublicDescription": ""
"EventCode": "0x44052",
"EventName": "PM_INST_PUMP_MPRED",
"BriefDescription": "Pump misprediction. Counts across all types of pumps for an instruction fetch"
},
{,
"EventCode": "0x4C010",
"EventName": "PM_CMPLU_STALL_STORE_PIPE_ARB",
"BriefDescription": "Finish stall because the NTF instruction was a store waiting for the next relaunch opportunity after an internal reject. This means the instruction is ready to relaunch and tried once but lost arbitration",
"PublicDescription": ""
"EventCode": "0x30026",
"EventName": "PM_CMPLU_STALL_STORE_DATA",
"BriefDescription": "Finish stall because the next to finish instruction was a store waiting on data"
},
{,
"EventCode": "0x4C01C",
"EventName": "PM_CMPLU_STALL_ST_FWD",
"BriefDescription": "Completion stall due to store forward",
"PublicDescription": ""
"EventCode": "0x301E6",
"EventName": "PM_MRK_DERAT_MISS",
"BriefDescription": "Erat Miss (TLB Access) All page sizes"
},
{,
"EventCode": "0x4E012",
"EventName": "PM_CMPLU_STALL_MTFPSCR",
"BriefDescription": "Completion stall because the ISU is updating the register and notifying the Effective Address Table (EAT)",
"PublicDescription": ""
"EventCode": "0x24154",
"EventName": "PM_THRESH_ACC",
"BriefDescription": "This event increments every time the threshold event counter ticks. Thresholding must be enabled (via MMCRA) and the thresholding start event must occur for this counter to increment. It will stop incrementing when the thresholding stop event occurs or when thresholding is disabled, until the next time a configured thresholding start event occurs."
},
{,
"EventCode": "0x4E016",
"EventName": "PM_CMPLU_STALL_LSAQ_ARB",
"BriefDescription": "Finish stall because the NTF instruction was a load or store that was held in LSAQ because an older instruction from SRQ or LRQ won arbitration to the LSU pipe when this instruction tried to launch",
"PublicDescription": ""
"EventCode": "0x2015E",
"EventName": "PM_MRK_FAB_RSP_RWITM_RTY",
"BriefDescription": "Sampled store did a rwitm and got a rty"
},
{,
"EventCode": "0x4C12A",
"EventName": "PM_MRK_DATA_FROM_RL2L3_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
"PublicDescription": ""
"EventCode": "0x200FA",
"EventName": "PM_BR_TAKEN_CMPL",
"BriefDescription": "New event for Branch Taken"
},
{,
"EventCode": "0x4C044",
"EventName": "PM_DATA_FROM_L3.1_ECO_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a demand load",
"PublicDescription": ""
"EventCode": "0x35044",
"EventName": "PM_IPTEG_FROM_L31_ECO_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request"
},
{,
"EventCode": "0x45044",
"EventName": "PM_IPTEG_FROM_L3.1_ECO_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request",
"PublicDescription": ""
"EventCode": "0x4C010",
"EventName": "PM_CMPLU_STALL_STORE_PIPE_ARB",
"BriefDescription": "Finish stall because the NTF instruction was a store waiting for the next relaunch opportunity after an internal reject. This means the instruction is ready to relaunch and tried once but lost arbitration"
},
{,
"EventCode": "0x45048",
"EventName": "PM_IPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
"PublicDescription": ""
"EventCode": "0x4C01C",
"EventName": "PM_CMPLU_STALL_ST_FWD",
"BriefDescription": "Completion stall due to store forward"
},
{,
"EventCode": "0x4504E",
"EventName": "PM_IPTEG_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a instruction side request",
"PublicDescription": ""
"EventCode": "0x3515C",
"EventName": "PM_MRK_DATA_FROM_RL4",
"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load"
},
{,
"EventCode": "0x4E042",
"EventName": "PM_DPTEG_FROM_L3",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x2D14C",
"EventName": "PM_MRK_DATA_FROM_L31_ECO_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load"
},
{,
"EventCode": "0x4015E",
"EventName": "PM_MRK_FAB_RSP_RD_RTY",
"BriefDescription": "Sampled L2 reads retry count",
"PublicDescription": ""
"EventCode": "0x40116",
"EventName": "PM_MRK_LARX_FIN",
"BriefDescription": "Larx finished"
},
{,
"EventCode": "0x4C056",
"EventName": "PM_DTLB_MISS_16M",
"BriefDescription": "Data TLB Miss page size 16M",
"PublicDescription": ""
},
{,
"EventCode": "0x44050",
"EventName": "PM_INST_SYS_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for an instruction fetch",
"PublicDescription": ""
"BriefDescription": "Data TLB Miss page size 16M"
},
{,
"EventCode": "0x44052",
"EventName": "PM_INST_PUMP_MPRED",
"BriefDescription": "Pump misprediction. Counts across all types of pumps for an instruction fetch",
"PublicDescription": ""
"EventCode": "0x1003A",
"EventName": "PM_CMPLU_STALL_LSU_FIN",
"BriefDescription": "Finish stall because the NTF instruction was an LSU op (other than a load or a store) with all its dependencies met and just going through the LSU pipe to finish"
},
{,
"EventCode": "0x44056",
"EventName": "PM_VECTOR_ST_CMPL",
"BriefDescription": "Number of vector store instructions completed",
"PublicDescription": ""
"EventCode": "0x3012A",
"EventName": "PM_MRK_L2_RC_DONE",
"BriefDescription": "Marked RC done"
},
{,
"EventCode": "0x4F150",
"EventName": "PM_MRK_FAB_RSP_RWITM_CYC",
"BriefDescription": "cycles L2 RC took for a rwitm",
"PublicDescription": ""
"EventCode": "0x45044",
"EventName": "PM_IPTEG_FROM_L31_ECO_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/powerpc/power9/marked.json
View file @ 3c22ba52
[
{,
"EventCode": "0x1002C",
"EventName": "PM_L1_DCACHE_RELOADED_ALL",
"BriefDescription": "L1 data cache reloaded for demand. If MMCR1[16] is 1, prefetches will be included as well",
"PublicDescription": ""
},
{,
"EventCode": "0x10132",
"EventName": "PM_MRK_INST_ISSUED",
"BriefDescription": "Marked instruction issued",
"PublicDescription": ""
"EventCode": "0x3C052",
"EventName": "PM_DATA_SYS_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load"
},
{,
"EventCode": "0x1C042",
"EventName": "PM_DATA_FROM_L2",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand load",
"PublicDescription": ""
"EventCode": "0x3013E",
"EventName": "PM_MRK_STALL_CMPLU_CYC",
"BriefDescription": "Number of cycles the marked instruction is experiencing a stall while it is next to complete (NTC)"
},
{,
"EventCode": "0x1C046",
"EventName": "PM_DATA_FROM_L3.1_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a demand load",
"PublicDescription": ""
"EventCode": "0x4F056",
"EventName": "PM_RADIX_PWC_L1_PDE_FROM_L3MISS",
"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond the core's L3 data cache. The source could be local/remote/distant memory or another core's cache"
},
{,
"EventCode": "0x1C048",
"EventName": "PM_DATA_FROM_ON_CHIP_CACHE",
"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load",
"PublicDescription": ""
"EventCode": "0x24158",
"EventName": "PM_MRK_INST",
"BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at decode time and Random Event Sampling (RES) at the time the configured event happens"
},
{,
"EventCode": "0x14040",
"EventName": "PM_INST_FROM_L2_NO_CONFLICT",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x1E046",
"EventName": "PM_DPTEG_FROM_L31_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x14042",
"EventName": "PM_INST_FROM_L2",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x3C04A",
"EventName": "PM_DATA_FROM_RMEM",
"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load"
},
{,
"EventCode": "0x14046",
"EventName": "PM_INST_FROM_L3.1_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x2C01C",
"EventName": "PM_CMPLU_STALL_DMISS_REMOTE",
"BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or memory)"
},
{,
"EventCode": "0x1404C",
"EventName": "PM_INST_FROM_LL4",
"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x44040",
"EventName": "PM_INST_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x1D14C",
"EventName": "PM_MRK_DATA_FROM_LL4",
"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load",
"PublicDescription": ""
"EventCode": "0x2E050",
"EventName": "PM_DARQ0_7_9_ENTRIES",
"BriefDescription": "Cycles in which 7,8, or 9 DARQ entries (out of 12) are in use"
},
{,
"EventCode": "0x15042",
"EventName": "PM_IPTEG_FROM_L2",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request",
"PublicDescription": ""
"EventCode": "0x2D02E",
"EventName": "PM_RADIX_PWC_L3_PTE_FROM_L2",
"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache. This implies that a level 4 PWC access was not necessary for this translation"
},
{,
"EventCode": "0x1504E",
"EventName": "PM_IPTEG_FROM_L2MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a instruction side request",
"PublicDescription": ""
"EventCode": "0x3F05E",
"EventName": "PM_RADIX_PWC_L3_PTE_FROM_L3",
"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This implies that a level 4 PWC access was not necessary for this translation"
},
{,
"EventCode": "0x1E042",
"EventName": "PM_DPTEG_FROM_L2",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x2E01E",
"EventName": "PM_CMPLU_STALL_NTC_FLUSH",
"BriefDescription": "Completion stall due to ntc flush"
},
{,
"EventCode": "0x1E044",
"EventName": "PM_DPTEG_FROM_L3_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x1F14C",
"EventName": "PM_MRK_DPTEG_FROM_LL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x1E046",
"EventName": "PM_DPTEG_FROM_L3.1_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x20130",
"EventName": "PM_MRK_INST_DECODED",
"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) only"
},
{,
"EventCode": "0x1F14A",
"EventName": "PM_MRK_DPTEG_FROM_RL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x3F144",
"EventName": "PM_MRK_DPTEG_FROM_L31_ECO_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x1F14C",
"EventName": "PM_MRK_DPTEG_FROM_LL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x4D058",
"EventName": "PM_VECTOR_FLOP_CMPL",
"BriefDescription": "Vector FP instruction completed"
},
{,
"EventCode": "0x1005C",
"EventName": "PM_CMPLU_STALL_DP",
"BriefDescription": "Finish stall because the NTF instruction was a scalar instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by NOT vector",
"PublicDescription": ""
"EventCode": "0x14040",
"EventName": "PM_INST_FROM_L2_NO_CONFLICT",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x1C052",
"EventName": "PM_DATA_GRP_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load",
"PublicDescription": ""
"EventCode": "0x4404E",
"EventName": "PM_INST_FROM_L3MISS_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L3 due to a instruction fetch"
},
{,
"EventCode": "0x1C054",
"EventName": "PM_DATA_PUMP_CPRED",
"BriefDescription": "Pump prediction correct. Counts across all types of pumps for a demand load",
"PublicDescription": ""
"EventCode": "0x3003A",
"EventName": "PM_CMPLU_STALL_EXCEPTION",
"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete"
},
{,
"EventCode": "0x1C05E",
"EventName": "PM_MEM_LOC_THRESH_LSU_MED",
"BriefDescription": "Local memory above threshold for data prefetch",
"PublicDescription": ""
"EventCode": "0x4F144",
"EventName": "PM_MRK_DPTEG_FROM_L31_ECO_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x1415E",
"EventName": "PM_MRK_DATA_FROM_L3MISS_CYC",
"BriefDescription": "Duration in cycles to reload from a location other than the local core's L3 due to a marked load",
"PublicDescription": ""
"EventCode": "0x3E044",
"EventName": "PM_DPTEG_FROM_L31_ECO_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x1D058",
"EventName": "PM_DARQ0_10_12_ENTRIES",
"BriefDescription": "Cycles in which 10 or more DARQ entries (out of 12) are in use",
"PublicDescription": ""
"EventCode": "0x300F6",
"EventName": "PM_L1_DCACHE_RELOAD_VALID",
"BriefDescription": "DL1 reloaded due to Demand Load"
},
{,
"EventCode": "0x15150",
"EventName": "PM_SYNC_MRK_PROBE_NOP",
"BriefDescription": "Marked probeNops which can cause synchronous interrupts",
"PublicDescription": ""
"EventCode": "0x1415E",
"EventName": "PM_MRK_DATA_FROM_L3MISS_CYC",
"BriefDescription": "Duration in cycles to reload from a location other than the local core's L3 due to a marked load"
},
{,
"EventCode": "0x1E052",
"EventName": "PM_CMPLU_STALL_SLB",
"BriefDescription": "Finish stall because the NTF instruction was awaiting L2 response for an SLB",
"PublicDescription": ""
"BriefDescription": "Finish stall because the NTF instruction was awaiting L2 response for an SLB"
},
{,
"EventCode": "0x1F150",
"EventName": "PM_MRK_ST_L2DISP_TO_CMPL_CYC",
"BriefDescription": "cycles from L2 rc disp to l2 rc completion",
"PublicDescription": ""
"EventCode": "0x4404C",
"EventName": "PM_INST_FROM_DMEM",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x1F05A",
"EventName": "PM_RADIX_PWC_L4_PTE_FROM_L2",
"BriefDescription": "A Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 data cache. This is the deepest level of PWC possible for a translation",
"PublicDescription": ""
"EventCode": "0x3000E",
"EventName": "PM_FXU_1PLUS_BUSY",
"BriefDescription": "At least one of the 4 FXU units is busy"
},
{,
"EventCode": "0x1F05C",
"EventName": "PM_RADIX_PWC_L3_PDE_FROM_L3",
"BriefDescription": "A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 data cache",
"PublicDescription": ""
"EventCode": "0x2C048",
"EventName": "PM_DATA_FROM_LMEM",
"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a demand load"
},
{,
"EventCode": "0x1006C",
"EventName": "PM_RUN_CYC_ST_MODE",
"BriefDescription": "Cycles run latch is set and core is in ST mode",
"PublicDescription": ""
"EventCode": "0x3000A",
"EventName": "PM_CMPLU_STALL_PM",
"BriefDescription": "Finish stall because the NTF instruction was issued to the Permute execution pipe and waiting to finish. Includes permute and decimal fixed point instructions (128 bit BCD arithmetic) + a few 128 bit fixpoint add/subtract instructions with carry. Not qualified by vector or multicycle"
},
{,
"EventCode": "0x1016E",
"EventName": "PM_MRK_BR_CMPL",
"BriefDescription": "Branch Instruction completed",
"PublicDescription": ""
"EventCode": "0x1504E",
"EventName": "PM_IPTEG_FROM_L2MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a instruction side request"
},
{,
"EventCode": "0x101E0",
"EventName": "PM_MRK_INST_DISP",
"BriefDescription": "The thread has dispatched a randomly sampled marked instruction",
"PublicDescription": ""
"EventCode": "0x1C052",
"EventName": "PM_DATA_GRP_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for a demand load"
},
{,
"EventCode": "0x101E2",
"EventName": "PM_MRK_BR_TAKEN_CMPL",
"BriefDescription": "Marked Branch Taken completed",
"PublicDescription": ""
"EventCode": "0x30008",
"EventName": "PM_DISP_STARVED",
"BriefDescription": "Dispatched Starved"
},
{,
"EventCode": "0x2C016",
"EventName": "PM_CMPLU_STALL_PASTE",
"BriefDescription": "Finish stall because the NTF instruction was a paste waiting for response from L2",
"PublicDescription": ""
"EventCode": "0x14042",
"EventName": "PM_INST_FROM_L2",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x2C01C",
"EventName": "PM_CMPLU_STALL_DMISS_REMOTE",
"BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or memory)",
"PublicDescription": ""
"EventCode": "0x4000C",
"EventName": "PM_FREQ_UP",
"BriefDescription": "Power Management: Above Threshold A"
},
{,
"EventCode": "0x2E01E",
"EventName": "PM_CMPLU_STALL_NTC_FLUSH",
"BriefDescription": "Completion stall due to ntc flush",
"PublicDescription": ""
"EventCode": "0x3C050",
"EventName": "PM_DATA_SYS_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for a demand load"
},
{,
"EventCode": "0x2C128",
"EventName": "PM_MRK_DATA_FROM_DL2L3_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
"PublicDescription": ""
"EventCode": "0x25040",
"EventName": "PM_IPTEG_FROM_L2_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request"
},
{,
"EventCode": "0x2C12E",
"EventName": "PM_MRK_DATA_FROM_LL4_CYC",
"BriefDescription": "Duration in cycles to reload from the local chip's L4 cache due to a marked load",
"PublicDescription": ""
"EventCode": "0x10132",
"EventName": "PM_MRK_INST_ISSUED",
"BriefDescription": "Marked instruction issued"
},
{,
"EventCode": "0x2D024",
"EventName": "PM_RADIX_PWC_L2_HIT",
"BriefDescription": "A radix translation attempt missed in the TLB but hit on both the first and second levels of page walk cache.",
"PublicDescription": ""
"EventCode": "0x1C046",
"EventName": "PM_DATA_FROM_L31_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a demand load"
},
{,
"EventCode": "0x2D02A",
"EventName": "PM_RADIX_PWC_L3_PDE_FROM_L2",
"BriefDescription": "A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L2 data cache",
"PublicDescription": ""
"EventCode": "0x2C044",
"EventName": "PM_DATA_FROM_L31_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a demand load"
},
{,
"EventCode": "0x2D02E",
"EventName": "PM_RADIX_PWC_L3_PTE_FROM_L2",
"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 data cache. This implies that a level 4 PWC access was not necessary for this translation",
"PublicDescription": ""
"EventCode": "0x2C04A",
"EventName": "PM_DATA_FROM_RL4",
"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load"
},
{,
"EventCode": "0x20130",
"EventName": "PM_MRK_INST_DECODED",
"BriefDescription": "An instruction was marked at decode time. Random Instruction Sampling (RIS) only",
"PublicDescription": ""
"EventCode": "0x24044",
"EventName": "PM_INST_FROM_L31_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x20138",
"EventName": "PM_MRK_ST_NEST",
"BriefDescription": "Marked store sent to nest",
"PublicDescription": ""
"EventCode": "0x4C050",
"EventName": "PM_DATA_SYS_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load"
},
{,
"EventCode": "0x2013A",
"EventName": "PM_MRK_BRU_FIN",
"BriefDescription": "bru marked instr finish",
"PublicDescription": ""
"EventCode": "0x2C052",
"EventName": "PM_DATA_GRP_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load"
},
{,
"EventCode": "0x2C044",
"EventName": "PM_DATA_FROM_L3.1_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a demand load",
"PublicDescription": ""
"EventCode": "0x2F148",
"EventName": "PM_MRK_DPTEG_FROM_LMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x2C048",
"EventName": "PM_DATA_FROM_LMEM",
"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a demand load",
"PublicDescription": ""
"EventCode": "0x4D01A",
"EventName": "PM_CMPLU_STALL_EIEIO",
"BriefDescription": "Finish stall because the NTF instruction is an EIEIO waiting for response from L2"
},
{,
"EventCode": "0x2C04A",
"EventName": "PM_DATA_FROM_RL4",
"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a demand load",
"PublicDescription": ""
"EventCode": "0x4F14E",
"EventName": "PM_MRK_DPTEG_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x24044",
"EventName": "PM_INST_FROM_L3.1_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x4F05A",
"EventName": "PM_RADIX_PWC_L4_PTE_FROM_L3",
"BriefDescription": "A Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 data cache. This is the deepest level of PWC possible for a translation"
},
{,
"EventCode": "0x25040",
"EventName": "PM_IPTEG_FROM_L2_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request",
"PublicDescription": ""
"EventCode": "0x1F05A",
"EventName": "PM_RADIX_PWC_L4_PTE_FROM_L2",
"BriefDescription": "A Page Table Entry was reloaded to a level 4 page walk cache from the core's L2 data cache. This is the deepest level of PWC possible for a translation"
},
{,
"EventCode": "0x2E044",
"EventName": "PM_DPTEG_FROM_L3.1_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x30068",
"EventName": "PM_L1_ICACHE_RELOADED_PREF",
"BriefDescription": "Counts all Icache prefetch reloads ( includes demand turned into prefetch)"
},
{,
"EventCode": "0x2E048",
"EventName": "PM_DPTEG_FROM_LMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x4C04A",
"EventName": "PM_DATA_FROM_OFF_CHIP_CACHE",
"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load"
},
{,
"EventCode": "0x2F148",
"EventName": "PM_MRK_DPTEG_FROM_LMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x400FE",
"EventName": "PM_DATA_FROM_MEMORY",
"BriefDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load"
},
{,
"EventCode": "0x20050",
"EventName": "PM_GRP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": ""
"EventCode": "0x3F058",
"EventName": "PM_RADIX_PWC_L1_PDE_FROM_L3",
"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L3 data cache"
},
{,
"EventCode": "0x2C052",
"EventName": "PM_DATA_GRP_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for a demand load",
"PublicDescription": ""
"EventCode": "0x4D142",
"EventName": "PM_MRK_DATA_FROM_L3",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a marked load"
},
{,
"EventCode": "0x2C058",
"EventName": "PM_MEM_PREF",
"BriefDescription": "Memory prefetch for this thread. Includes L4",
"PublicDescription": ""
"EventCode": "0x30050",
"EventName": "PM_SYS_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
"EventCode": "0x24156",
"EventName": "PM_MRK_STCX_FIN",
"BriefDescription": "Number of marked stcx instructions finished. This includes instructions in the speculative path of a branch that may be flushed",
"PublicDescription": ""
"EventCode": "0x30028",
"EventName": "PM_CMPLU_STALL_SPEC_FINISH",
"BriefDescription": "Finish stall while waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECC"
},
{,
"EventCode": "0x24158",
"EventName": "PM_MRK_INST",
"BriefDescription": "An instruction was marked. Includes both Random Instruction Sampling (RIS) at decode time and Random Event Sampling (RES) at the time the configured event happens",
"PublicDescription": ""
"EventCode": "0x400F4",
"EventName": "PM_RUN_PURR",
"BriefDescription": "Run_PURR"
},
{,
"EventCode": "0x2E050",
"EventName": "PM_DARQ0_7_9_ENTRIES",
"BriefDescription": "Cycles in which 7,8, or 9 DARQ entries (out of 12) are in use",
"PublicDescription": ""
"EventCode": "0x3404C",
"EventName": "PM_INST_FROM_DL4",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x2E05E",
"EventName": "PM_LMQ_EMPTY_CYC",
"BriefDescription": "Cycles in which the LMQ has no pending load misses for this thread",
"PublicDescription": ""
"EventCode": "0x3D05A",
"EventName": "PM_NTC_ISSUE_HELD_OTHER",
"BriefDescription": "The NTC instruction is being held at dispatch during regular pipeline cycles, or because the VSU is busy with multi-cycle instructions, or because of a write-back collision with VSU"
},
{,
"EventCode": "0x200FD",
"EventName": "PM_L1_ICACHE_MISS",
"BriefDescription": "Demand iCache Miss",
"PublicDescription": ""
"EventCode": "0x2E048",
"EventName": "PM_DPTEG_FROM_LMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x30006",
"EventName": "PM_CMPLU_STALL_OTHER_CMPL",
"BriefDescription": "Instructions the core completed while this tread was stalled",
"PublicDescription": ""
"EventCode": "0x2D02A",
"EventName": "PM_RADIX_PWC_L3_PDE_FROM_L2",
"BriefDescription": "A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L2 data cache"
},
{,
"EventCode": "0x30008",
"EventName": "PM_DISP_STARVED",
"BriefDescription": "Dispatched Starved",
"PublicDescription": ""
"EventCode": "0x1F05C",
"EventName": "PM_RADIX_PWC_L3_PDE_FROM_L3",
"BriefDescription": "A Page Directory Entry was reloaded to a level 3 page walk cache from the core's L3 data cache"
},
{,
"EventCode": "0x3000A",
"EventName": "PM_CMPLU_STALL_PM",
"BriefDescription": "Finish stall because the NTF instruction was issued to the Permute execution pipe and waiting to finish. Includes permute and decimal fixed point instructions (128 bit BCD arithmetic) + a few 128 bit fixpoint add/subtract instructions with carry. Not qualified by vector or multicycle",
"PublicDescription": ""
"EventCode": "0x4D04A",
"EventName": "PM_DARQ0_0_3_ENTRIES",
"BriefDescription": "Cycles in which 3 or less DARQ entries (out of 12) are in use"
},
{,
"EventCode": "0x3000E",
"EventName": "PM_FXU_1PLUS_BUSY",
"BriefDescription": "At least one of the 4 FXU units is busy",
"PublicDescription": ""
"EventCode": "0x1404C",
"EventName": "PM_INST_FROM_LL4",
"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's L4 cache due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x30028",
"EventName": "PM_CMPLU_STALL_SPEC_FINISH",
"BriefDescription": "Finish stall while waiting for the non-speculative finish of either a stcx waiting for its result or a load waiting for non-critical sectors of data and ECC",
"PublicDescription": ""
"EventCode": "0x200FD",
"EventName": "PM_L1_ICACHE_MISS",
"BriefDescription": "Demand iCache Miss"
},
{,
"EventCode": "0x3012C",
"EventName": "PM_MRK_ST_FWD",
"BriefDescription": "Marked st forwards",
"PublicDescription": ""
"EventCode": "0x34040",
"EventName": "PM_INST_FROM_L2_DISP_CONFLICT_LDHITST",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x30130",
"EventName": "PM_MRK_INST_FIN",
"BriefDescription": "marked instruction finished",
"PublicDescription": ""
"EventCode": "0x20138",
"EventName": "PM_MRK_ST_NEST",
"BriefDescription": "Marked store sent to nest"
},
{,
"EventCode": "0x3003A",
"EventName": "PM_CMPLU_STALL_EXCEPTION",
"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because it was interrupted by ANY exception, which has to be serviced before the instruction can complete",
"PublicDescription": ""
"EventCode": "0x44048",
"EventName": "PM_INST_FROM_DL2L3_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x3003C",
"EventName": "PM_CMPLU_STALL_NESTED_TEND",
"BriefDescription": "Completion stall because the ISU is updating the TEXASR to keep track of the nested tend and decrement the TEXASR nested level. This is a short delay",
"PublicDescription": ""
"EventCode": "0x35046",
"EventName": "PM_IPTEG_FROM_L21_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request"
},
{,
"EventCode": "0x3013E",
"EventName": "PM_MRK_STALL_CMPLU_CYC",
"BriefDescription": "Number of cycles the marked instruction is experiencing a stall while it is next to complete (NTC)",
"PublicDescription": ""
"EventCode": "0x4C04E",
"EventName": "PM_DATA_FROM_L3MISS_MOD",
"BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L3 due to a demand load"
},
{,
"EventCode": "0x3C044",
"EventName": "PM_DATA_FROM_L3.1_ECO_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a demand load",
"PublicDescription": ""
"EventCode": "0x401E0",
"EventName": "PM_MRK_INST_CMPL",
"BriefDescription": "marked instruction completed"
},
{,
"EventCode": "0x3C04A",
"EventName": "PM_DATA_FROM_RMEM",
"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load",
"PublicDescription": ""
"EventCode": "0x2C128",
"EventName": "PM_MRK_DATA_FROM_DL2L3_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load"
},
{,
"EventCode": "0x34040",
"EventName": "PM_INST_FROM_L2_DISP_CONFLICT_LDHITST",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x34044",
"EventName": "PM_INST_FROM_L31_ECO_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x34044",
"EventName": "PM_INST_FROM_L3.1_ECO_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x4E018",
"EventName": "PM_CMPLU_STALL_NTC_DISP_FIN",
"BriefDescription": "Finish stall because the NTF instruction was one that must finish at dispatch."
},
{,
"EventCode": "0x34048",
"EventName": "PM_INST_FROM_DL2L3_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x2E05E",
"EventName": "PM_LMQ_EMPTY_CYC",
"BriefDescription": "Cycles in which the LMQ has no pending load misses for this thread"
},
{,
"EventCode": "0x3404C",
"EventName": "PM_INST_FROM_DL4",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x4C122",
"EventName": "PM_DARQ1_0_3_ENTRIES",
"BriefDescription": "Cycles in which 3 or fewer DARQ1 entries (out of 12) are in use"
},
{,
"EventCode": "0x35046",
"EventName": "PM_IPTEG_FROM_L2.1_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request",
"PublicDescription": ""
"EventCode": "0x4F058",
"EventName": "PM_RADIX_PWC_L2_PTE_FROM_L3",
"BriefDescription": "A Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation"
},
{,
"EventCode": "0x3504E",
"EventName": "PM_DARQ0_4_6_ENTRIES",
"BriefDescription": "Cycles in which 4, 5, or 6 DARQ entries (out of 12) are in use",
"PublicDescription": ""
"EventCode": "0x14046",
"EventName": "PM_INST_FROM_L31_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x3E044",
"EventName": "PM_DPTEG_FROM_L3.1_ECO_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x3012C",
"EventName": "PM_MRK_ST_FWD",
"BriefDescription": "Marked st forwards"
},
{,
"EventCode": "0x3F144",
"EventName": "PM_MRK_DPTEG_FROM_L3.1_ECO_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x101E0",
"EventName": "PM_MRK_INST_DISP",
"BriefDescription": "The thread has dispatched a randomly sampled marked instruction"
},
{,
"EventCode": "0x30050",
"EventName": "PM_SYS_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": ""
"EventCode": "0x1D058",
"EventName": "PM_DARQ0_10_12_ENTRIES",
"BriefDescription": "Cycles in which 10 or more DARQ entries (out of 12) are in use"
},
{,
"EventCode": "0x30052",
"EventName": "PM_SYS_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": ""
"EventCode": "0x300FE",
"EventName": "PM_DATA_FROM_L3MISS",
"BriefDescription": "Demand LD - L3 Miss (not L2 hit and not L3 hit)"
},
{,
"EventCode": "0x3C050",
"EventName": "PM_DATA_SYS_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was system pump (prediction=correct) for a demand load",
"PublicDescription": ""
"EventCode": "0x30006",
"EventName": "PM_CMPLU_STALL_OTHER_CMPL",
"BriefDescription": "Instructions the core completed while this tread was stalled"
},
{,
"EventCode": "0x3C052",
"EventName": "PM_DATA_SYS_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for a demand load",
"PublicDescription": ""
"EventCode": "0x1005C",
"EventName": "PM_CMPLU_STALL_DP",
"BriefDescription": "Finish stall because the NTF instruction was a scalar instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by NOT vector"
},
{,
"EventCode": "0x3D05A",
"EventName": "PM_NTC_ISSUE_HELD_OTHER",
"BriefDescription": "The NTC instruction is being held at dispatch during regular pipeline cycles, or because the VSU is busy with multi-cycle instructions, or because of a write-back collision with VSU",
"PublicDescription": ""
"EventCode": "0x1E042",
"EventName": "PM_DPTEG_FROM_L2",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x3D05C",
"EventName": "PM_DISP_HELD_HB_FULL",
"BriefDescription": "Dispatch held due to History Buffer full. Could be GPR/VSR/VMR/FPR/CR/XVF; CR; XVF (XER/VSCR/FPSCR)",
"PublicDescription": ""
"EventCode": "0x1016E",
"EventName": "PM_MRK_BR_CMPL",
"BriefDescription": "Branch Instruction completed"
},
{,
"EventCode": "0x3E158",
"EventName": "PM_MRK_STCX_FAIL",
"BriefDescription": "marked stcx failed",
"PublicDescription": ""
"EventCode": "0x2013A",
"EventName": "PM_MRK_BRU_FIN",
"BriefDescription": "bru marked instr finish"
},
{,
"EventCode": "0x3F056",
"EventName": "PM_RADIX_PWC_L3_HIT",
"BriefDescription": "A radix translation attempt missed in the TLB but hit on the first, second, and third levels of page walk cache.",
"PublicDescription": ""
"EventCode": "0x4F05E",
"EventName": "PM_RADIX_PWC_L3_PTE_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from beyond the core's L3 data cache. This implies that a level 4 PWC access was not necessary for this translation. The source could be local/remote/distant memory or another core's cache"
},
{,
"EventCode": "0x3F058",
"EventName": "PM_RADIX_PWC_L1_PDE_FROM_L3",
"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from the core's L3 data cache",
"PublicDescription": ""
"EventCode": "0x400FC",
"EventName": "PM_ITLB_MISS",
"BriefDescription": "ITLB Reloaded. Counts 1 per ITLB miss for HPT but multiple for radix depending on number of levels traveresed"
},
{,
"EventCode": "0x3F05E",
"EventName": "PM_RADIX_PWC_L3_PTE_FROM_L3",
"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 data cache. This implies that a level 4 PWC access was not necessary for this translation",
"PublicDescription": ""
"EventCode": "0x2D024",
"EventName": "PM_RADIX_PWC_L2_HIT",
"BriefDescription": "A radix translation attempt missed in the TLB but hit on both the first and second levels of page walk cache."
},
{,
"EventCode": "0x30064",
"EventName": "PM_DARQ_STORE_XMIT",
"BriefDescription": "The DARQ attempted to transmit a store into an LSAQ or SRQ entry. Includes rejects. Not qualified by thread, so it includes counts for the whole core",
"PublicDescription": ""
"EventCode": "0x3F056",
"EventName": "PM_RADIX_PWC_L3_HIT",
"BriefDescription": "A radix translation attempt missed in the TLB but hit on the first, second, and third levels of page walk cache."
},
{,
"EventCode": "0x30068",
"EventName": "PM_L1_ICACHE_RELOADED_PREF",
"BriefDescription": "Counts all Icache prefetch reloads ( includes demand turned into prefetch)",
"PublicDescription": ""
"EventCode": "0x4E014",
"EventName": "PM_TM_TX_PASS_RUN_INST",
"BriefDescription": "Run instructions spent in successful transactions"
},
{,
"EventCode": "0x301E4",
"EventName": "PM_MRK_BR_MPRED_CMPL",
"BriefDescription": "Marked Branch Mispredicted",
"PublicDescription": ""
"EventCode": "0x1E044",
"EventName": "PM_DPTEG_FROM_L3_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x300F2",
"EventName": "PM_INST_DISP",
"BriefDescription": "# PPC Dispatched",
"PublicDescription": ""
"EventCode": "0x4D05A",
"EventName": "PM_NON_MATH_FLOP_CMPL",
"BriefDescription": "Non FLOP operation completed"
},
{,
"EventCode": "0x300F6",
"EventName": "PM_L1_DCACHE_RELOAD_VALID",
"BriefDescription": "DL1 reloaded due to Demand Load",
"PublicDescription": ""
"EventCode": "0x101E2",
"EventName": "PM_MRK_BR_TAKEN_CMPL",
"BriefDescription": "Marked Branch Taken completed"
},
{,
"EventCode": "0x300FE",
"EventName": "PM_DATA_FROM_L3MISS",
"BriefDescription": "Demand LD - L3 Miss (not L2 hit and not L3 hit)",
"PublicDescription": ""
"EventCode": "0x3E158",
"EventName": "PM_MRK_STCX_FAIL",
"BriefDescription": "marked stcx failed"
},
{,
"EventCode": "0x4000A",
"EventName": "PM_ISQ_36_44_ENTRIES",
"BriefDescription": "Cycles in which 36 or more Issue Queue entries are in use. This is a shared event, not per thread. There are 44 issue queue entries across 4 slices in the whole core",
"PublicDescription": ""
"EventCode": "0x1C048",
"EventName": "PM_DATA_FROM_ON_CHIP_CACHE",
"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a demand load"
},
{,
"EventCode": "0x4000C",
"EventName": "PM_FREQ_UP",
"BriefDescription": "Power Management: Above Threshold A",
"PublicDescription": ""
"EventCode": "0x1C054",
"EventName": "PM_DATA_PUMP_CPRED",
"BriefDescription": "Pump prediction correct. Counts across all types of pumps for a demand load"
},
{,
"EventCode": "0x40012",
"EventName": "PM_L1_ICACHE_RELOADED_ALL",
"BriefDescription": "Counts all Icache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch",
"PublicDescription": ""
"EventCode": "0x4405E",
"EventName": "PM_DARQ_STORE_REJECT",
"BriefDescription": "The DARQ attempted to transmit a store into an LSAQ or SRQ entry but It was rejected. Divide by PM_DARQ_STORE_XMIT to get reject ratio"
},
{,
"EventCode": "0x4D01A",
"EventName": "PM_CMPLU_STALL_EIEIO",
"BriefDescription": "Finish stall because the NTF instruction is an EIEIO waiting for response from L2",
"PublicDescription": ""
"EventCode": "0x1C042",
"EventName": "PM_DATA_FROM_L2",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand load"
},
{,
"EventCode": "0x4E014",
"EventName": "PM_TM_TX_PASS_RUN_INST",
"BriefDescription": "Run instructions spent in successful transactions",
"PublicDescription": ""
"EventCode": "0x1D14C",
"EventName": "PM_MRK_DATA_FROM_LL4",
"BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load"
},
{,
"EventCode": "0x4E018",
"EventName": "PM_CMPLU_STALL_NTC_DISP_FIN",
"BriefDescription": "Finish stall because the NTF instruction was one that must finish at dispatch.",
"PublicDescription": ""
"EventCode": "0x1006C",
"EventName": "PM_RUN_CYC_ST_MODE",
"BriefDescription": "Cycles run latch is set and core is in ST mode"
},
{,
"EventCode": "0x4C122",
"EventName": "PM_DARQ1_0_3_ENTRIES",
"BriefDescription": "Cycles in which 3 or fewer DARQ1 entries (out of 12) are in use",
"PublicDescription": ""
"EventCode": "0x3C044",
"EventName": "PM_DATA_FROM_L31_ECO_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a demand load"
},
{,
"EventCode": "0x40134",
"EventName": "PM_MRK_INST_TIMEO",
"BriefDescription": "marked Instruction finish timeout (instruction lost)",
"PublicDescription": ""
"EventCode": "0x4C052",
"EventName": "PM_DATA_PUMP_MPRED",
"BriefDescription": "Pump misprediction. Counts across all types of pumps for a demand load"
},
{,
"EventCode": "0x4003C",
"EventName": "PM_DISP_HELD_SYNC_HOLD",
"BriefDescription": "Cycles in which dispatch is held because of a synchronizing instruction in the pipeline",
"PublicDescription": ""
"EventCode": "0x20050",
"EventName": "PM_GRP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
"EventCode": "0x4C04A",
"EventName": "PM_DATA_FROM_OFF_CHIP_CACHE",
"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a demand load",
"PublicDescription": ""
"EventCode": "0x1F150",
"EventName": "PM_MRK_ST_L2DISP_TO_CMPL_CYC",
"BriefDescription": "cycles from L2 rc disp to l2 rc completion"
},
{,
"EventCode": "0x4C04E",
"EventName": "PM_DATA_FROM_L3MISS_MOD",
"BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L3 due to a demand load",
"PublicDescription": ""
"EventCode": "0x4505A",
"EventName": "PM_SP_FLOP_CMPL",
"BriefDescription": "SP instruction completed"
},
{,
"EventCode": "0x44040",
"EventName": "PM_INST_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x4000A",
"EventName": "PM_ISQ_36_44_ENTRIES",
"BriefDescription": "Cycles in which 36 or more Issue Queue entries are in use. This is a shared event, not per thread. There are 44 issue queue entries across 4 slices in the whole core"
},
{,
"EventCode": "0x44048",
"EventName": "PM_INST_FROM_DL2L3_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x2C12E",
"EventName": "PM_MRK_DATA_FROM_LL4_CYC",
"BriefDescription": "Duration in cycles to reload from the local chip's L4 cache due to a marked load"
},
{,
"EventCode": "0x4404C",
"EventName": "PM_INST_FROM_DMEM",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x2C058",
"EventName": "PM_MEM_PREF",
"BriefDescription": "Memory prefetch for this thread. Includes L4"
},
{,
"EventCode": "0x4404E",
"EventName": "PM_INST_FROM_L3MISS_MOD",
"BriefDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L3 due to a instruction fetch",
"PublicDescription": ""
"EventCode": "0x40012",
"EventName": "PM_L1_ICACHE_RELOADED_ALL",
"BriefDescription": "Counts all Icache reloads includes demand, prefetch, prefetch turned into demand and demand turned into prefetch"
},
{,
"EventCode": "0x4D142",
"EventName": "PM_MRK_DATA_FROM_L3",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a marked load",
"PublicDescription": ""
"EventCode": "0x4003C",
"EventName": "PM_DISP_HELD_SYNC_HOLD",
"BriefDescription": "Cycles in which dispatch is held because of a synchronizing instruction in the pipeline"
},
{,
"EventCode": "0x4D04A",
"EventName": "PM_DARQ0_0_3_ENTRIES",
"BriefDescription": "Cycles in which 3 or less DARQ entries (out of 12) are in use",
"PublicDescription": ""
"EventCode": "0x3003C",
"EventName": "PM_CMPLU_STALL_NESTED_TEND",
"BriefDescription": "Completion stall because the ISU is updating the TEXASR to keep track of the nested tend and decrement the TEXASR nested level. This is a short delay"
},
{,
"EventCode": "0x45042",
"EventName": "PM_IPTEG_FROM_L3",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request",
"PublicDescription": ""
"EventCode": "0x3D05C",
"EventName": "PM_DISP_HELD_HB_FULL",
"BriefDescription": "Dispatch held due to History Buffer full. Could be GPR/VSR/VMR/FPR/CR/XVF; CR; XVF (XER/VSCR/FPSCR)"
},
{,
"EventCode": "0x45046",
"EventName": "PM_IPTEG_FROM_L2.1_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request",
"PublicDescription": ""
"EventCode": "0x30052",
"EventName": "PM_SYS_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (system) mispredicted. Either the original scope was too small (Chip/Group) or the original scope was System and it should have been smaller. Counts for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
"EventCode": "0x4F144",
"EventName": "PM_MRK_DPTEG_FROM_L3.1_ECO_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x2E044",
"EventName": "PM_DPTEG_FROM_L31_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x4F14E",
"EventName": "PM_MRK_DPTEG_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x34048",
"EventName": "PM_INST_FROM_DL2L3_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x4C050",
"EventName": "PM_DATA_SYS_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for a demand load",
"PublicDescription": ""
"EventCode": "0x45042",
"EventName": "PM_IPTEG_FROM_L3",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request"
},
{,
"EventCode": "0x4C052",
"EventName": "PM_DATA_PUMP_MPRED",
"BriefDescription": "Pump misprediction. Counts across all types of pumps for a demand load",
"PublicDescription": ""
"EventCode": "0x15042",
"EventName": "PM_IPTEG_FROM_L2",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request"
},
{,
"EventCode": "0x4405E",
"EventName": "PM_DARQ_STORE_REJECT",
"BriefDescription": "The DARQ attempted to transmit a store into an LSAQ or SRQ entry but It was rejected. Divide by PM_DARQ_STORE_XMIT to get reject ratio",
"PublicDescription": ""
"EventCode": "0x1C05E",
"EventName": "PM_MEM_LOC_THRESH_LSU_MED",
"BriefDescription": "Local memory above threshold for data prefetch"
},
{,
"EventCode": "0x4D058",
"EventName": "PM_VECTOR_FLOP_CMPL",
"BriefDescription": "Vector FP instruction completed",
"PublicDescription": ""
"EventCode": "0x40134",
"EventName": "PM_MRK_INST_TIMEO",
"BriefDescription": "marked Instruction finish timeout (instruction lost)"
},
{,
"EventCode": "0x4D05A",
"EventName": "PM_NON_MATH_FLOP_CMPL",
"BriefDescription": "Non FLOP operation completed",
"PublicDescription": ""
"EventCode": "0x1002C",
"EventName": "PM_L1_DCACHE_RELOADED_ALL",
"BriefDescription": "L1 data cache reloaded for demand. If MMCR1[16] is 1, prefetches will be included as well"
},
{,
"EventCode": "0x4505A",
"EventName": "PM_SP_FLOP_CMPL",
"BriefDescription": "SP instruction completed",
"PublicDescription": ""
"EventCode": "0x30130",
"EventName": "PM_MRK_INST_FIN",
"BriefDescription": "marked instruction finished"
},
{,
"EventCode": "0x4F056",
"EventName": "PM_RADIX_PWC_L1_PDE_FROM_L3MISS",
"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond the core's L3 data cache. The source could be local/remote/distant memory or another core's cache",
"PublicDescription": ""
"EventCode": "0x1F14A",
"EventName": "PM_MRK_DPTEG_FROM_RL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x4F058",
"EventName": "PM_RADIX_PWC_L2_PTE_FROM_L3",
"BriefDescription": "A Page Table Entry was reloaded to a level 2 page walk cache from the core's L3 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation",
"PublicDescription": ""
"EventCode": "0x3504E",
"EventName": "PM_DARQ0_4_6_ENTRIES",
"BriefDescription": "Cycles in which 4, 5, or 6 DARQ entries (out of 12) are in use"
},
{,
"EventCode": "0x4F05A",
"EventName": "PM_RADIX_PWC_L4_PTE_FROM_L3",
"BriefDescription": "A Page Table Entry was reloaded to a level 4 page walk cache from the core's L3 data cache. This is the deepest level of PWC possible for a translation",
"PublicDescription": ""
"EventCode": "0x30064",
"EventName": "PM_DARQ_STORE_XMIT",
"BriefDescription": "The DARQ attempted to transmit a store into an LSAQ or SRQ entry. Includes rejects. Not qualified by thread, so it includes counts for the whole core"
},
{,
"EventCode": "0x4F05E",
"EventName": "PM_RADIX_PWC_L3_PTE_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from beyond the core's L3 data cache. This implies that a level 4 PWC access was not necessary for this translation. The source could be local/remote/distant memory or another core's cache",
"PublicDescription": ""
"EventCode": "0x45046",
"EventName": "PM_IPTEG_FROM_L21_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request"
},
{,
"EventCode": "0x401E0",
"EventName": "PM_MRK_INST_CMPL",
"BriefDescription": "marked instruction completed",
"PublicDescription": ""
"EventCode": "0x2C016",
"EventName": "PM_CMPLU_STALL_PASTE",
"BriefDescription": "Finish stall because the NTF instruction was a paste waiting for response from L2"
},
{,
"EventCode": "0x400F4",
"EventName": "PM_RUN_PURR",
"BriefDescription": "Run_PURR",
"PublicDescription": ""
"EventCode": "0x24156",
"EventName": "PM_MRK_STCX_FIN",
"BriefDescription": "Number of marked stcx instructions finished. This includes instructions in the speculative path of a branch that may be flushed"
},
{,
"EventCode": "0x400FC",
"EventName": "PM_ITLB_MISS",
"BriefDescription": "ITLB Reloaded. Counts 1 per ITLB miss for HPT but multiple for radix depending on number of levels traveresed",
"PublicDescription": ""
"EventCode": "0x15150",
"EventName": "PM_SYNC_MRK_PROBE_NOP",
"BriefDescription": "Marked probeNops which can cause synchronous interrupts"
},
{,
"EventCode": "0x400FE",
"EventName": "PM_DATA_FROM_MEMORY",
"BriefDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a demand load",
"PublicDescription": ""
"EventCode": "0x301E4",
"EventName": "PM_MRK_BR_MPRED_CMPL",
"BriefDescription": "Marked Branch Mispredicted"
}
]
tools/perf/pmu-events/arch/powerpc/power9/memory.json
View file @ 3c22ba52
[
{,
"EventCode": "0x10008",
"EventName": "PM_RUN_SPURR",
"BriefDescription": "Run SPURR",
"PublicDescription": ""
},
{,
"EventCode": "0x1000A",
"EventName": "PM_PMC3_REWIND",
"BriefDescription": "PMC3 rewind event. A rewind happens when a speculative event (such as latency or CPI stack) is selected on PMC3 and the stall reason or reload source did not match the one programmed in PMC3. When this occurs, the count in PMC3 will not change.",
"PublicDescription": ""
"EventCode": "0x3006E",
"EventName": "PM_NEST_REF_CLK",
"BriefDescription": "Multiply by 4 to obtain the number of PB cycles"
},
{,
"EventCode": "0x1C040",
"EventName": "PM_DATA_FROM_L2_NO_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load",
"PublicDescription": ""
"EventCode": "0x20010",
"EventName": "PM_PMC1_OVERFLOW",
"BriefDescription": "Overflow from counter 1"
},
{,
"EventCode": "0x1C050",
"EventName": "PM_DATA_CHIP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load",
"PublicDescription": ""
"EventCode": "0x2005A",
"EventName": "PM_DARQ1_7_9_ENTRIES",
"BriefDescription": "Cycles in which 7 to 9 DARQ1 entries (out of 12) are in use"
},
{,
"EventCode": "0x1D15E",
"EventName": "PM_MRK_RUN_CYC",
"BriefDescription": "Run cycles in which a marked instruction is in the pipeline",
"PublicDescription": ""
"EventCode": "0x3C048",
"EventName": "PM_DATA_FROM_DL2L3_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load"
},
{,
"EventCode": "0x15158",
"EventName": "PM_SYNC_MRK_L2HIT",
"BriefDescription": "Marked L2 Hits that can throw a synchronous interrupt",
"PublicDescription": ""
"EventCode": "0x10008",
"EventName": "PM_RUN_SPURR",
"BriefDescription": "Run SPURR"
},
{,
"EventCode": "0x20010",
"EventName": "PM_PMC1_OVERFLOW",
"BriefDescription": "Overflow from counter 1",
"PublicDescription": ""
"EventCode": "0x200F6",
"EventName": "PM_LSU_DERAT_MISS",
"BriefDescription": "DERAT Reloaded due to a DERAT miss"
},
{,
"EventCode": "0x2C040",
"EventName": "PM_DATA_FROM_L2_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load",
"PublicDescription": ""
"EventCode": "0x4C048",
"EventName": "PM_DATA_FROM_DL2L3_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load"
},
{,
"EventCode": "0x2005A",
"EventName": "PM_DARQ1_7_9_ENTRIES",
"BriefDescription": "Cycles in which 7 to 9 DARQ1 entries (out of 12) are in use",
"PublicDescription": ""
"EventCode": "0x1D15E",
"EventName": "PM_MRK_RUN_CYC",
"BriefDescription": "Run cycles in which a marked instruction is in the pipeline"
},
{,
"EventCode": "0x2C05C",
"EventName": "PM_INST_GRP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only)",
"PublicDescription": ""
"EventCode": "0x4003E",
"EventName": "PM_LD_CMPL",
"BriefDescription": "count of Loads completed"
},
{,
"EventCode": "0x2D156",
"EventName": "PM_MRK_DTLB_MISS_4K",
"BriefDescription": "Marked Data TLB Miss page size 4k",
"PublicDescription": ""
},
{,
"EventCode": "0x2E05A",
"EventName": "PM_LRQ_REJECT",
"BriefDescription": "Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued. This event counts the number of times the LRQ attempts to relaunch an instruction after a reject. Any load can suffer multiple rejects",
"PublicDescription": ""
"BriefDescription": "Marked Data TLB Miss page size 4k"
},
{,
"EventCode": "0x2E05C",
"EventName": "PM_LSU_REJECT_ERAT_MISS",
"BriefDescription": "LSU Reject due to ERAT (up to 4 per cycles)",
"PublicDescription": ""
"EventCode": "0x4C042",
"EventName": "PM_DATA_FROM_L3",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand load"
},
{,
"EventCode": "0x200F6",
"EventName": "PM_LSU_DERAT_MISS",
"BriefDescription": "DERAT Reloaded due to a DERAT miss",
"PublicDescription": ""
"EventCode": "0x4D02C",
"EventName": "PM_PMC1_REWIND",
"BriefDescription": ""
},
{,
"EventCode": "0x3C048",
"EventName": "PM_DATA_FROM_DL2L3_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
"PublicDescription": ""
"EventCode": "0x15158",
"EventName": "PM_SYNC_MRK_L2HIT",
"BriefDescription": "Marked L2 Hits that can throw a synchronous interrupt"
},
{,
"EventCode": "0x3404A",
"EventName": "PM_INST_FROM_RMEM",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x3C058",
"EventName": "PM_LARX_FIN",
"BriefDescription": "Larx finished",
"PublicDescription": ""
"EventCode": "0x301E2",
"EventName": "PM_MRK_ST_CMPL",
"BriefDescription": "Marked store completed and sent to nest"
},
{,
"EventCode": "0x3E050",
"EventName": "PM_DARQ1_4_6_ENTRIES",
"BriefDescription": "Cycles in which 4, 5, or 6 DARQ1 entries (out of 12) are in use",
"PublicDescription": ""
"EventCode": "0x1C050",
"EventName": "PM_DATA_CHIP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load"
},
{,
"EventCode": "0x3006E",
"EventName": "PM_NEST_REF_CLK",
"BriefDescription": "Multiply by 4 to obtain the number of PB cycles",
"PublicDescription": ""
"EventCode": "0x4C040",
"EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load"
},
{,
"EventCode": "0x301E2",
"EventName": "PM_MRK_ST_CMPL",
"BriefDescription": "Marked store completed and sent to nest",
"PublicDescription": ""
"EventCode": "0x2E05C",
"EventName": "PM_LSU_REJECT_ERAT_MISS",
"BriefDescription": "LSU Reject due to ERAT (up to 4 per cycles)"
},
{,
"EventCode": "0x4D02C",
"EventName": "PM_PMC1_REWIND",
"BriefDescription": "",
"PublicDescription": ""
"EventCode": "0x1000A",
"EventName": "PM_PMC3_REWIND",
"BriefDescription": "PMC3 rewind event. A rewind happens when a speculative event (such as latency or CPI stack) is selected on PMC3 and the stall reason or reload source did not match the one programmed in PMC3. When this occurs, the count in PMC3 will not change."
},
{,
"EventCode": "0x4003E",
"EventName": "PM_LD_CMPL",
"BriefDescription": "count of Loads completed",
"PublicDescription": ""
"EventCode": "0x3C058",
"EventName": "PM_LARX_FIN",
"BriefDescription": "Larx finished"
},
{,
"EventCode": "0x4C040",
"EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load",
"PublicDescription": ""
"EventCode": "0x1C040",
"EventName": "PM_DATA_FROM_L2_NO_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load"
},
{,
"EventCode": "0x4C042",
"EventName": "PM_DATA_FROM_L3",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand load",
"PublicDescription": ""
"EventCode": "0x2C040",
"EventName": "PM_DATA_FROM_L2_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load"
},
{,
"EventCode": "0x4C048",
"EventName": "PM_DATA_FROM_DL2L3_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
"PublicDescription": ""
"EventCode": "0x2E05A",
"EventName": "PM_LRQ_REJECT",
"BriefDescription": "Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued. This event counts the number of times the LRQ attempts to relaunch an instruction after a reject. Any load can suffer multiple rejects"
},
{,
"EventCode": "0x2C05C",
"EventName": "PM_INST_GRP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only)"
},
{,
"EventCode": "0x4D056",
"EventName": "PM_NON_FMA_FLOP_CMPL",
"BriefDescription": "Non FMA instruction completed",
"PublicDescription": ""
"BriefDescription": "Non FMA instruction completed"
},
{,
"EventCode": "0x3E050",
"EventName": "PM_DARQ1_4_6_ENTRIES",
"BriefDescription": "Cycles in which 4, 5, or 6 DARQ1 entries (out of 12) are in use"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/powerpc/power9/other.json
View file @ 3c22ba52
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tools/perf/pmu-events/arch/powerpc/power9/pipeline.json
View file @ 3c22ba52
[
{,
"EventCode": "0x1E",
"EventName": "PM_CYC",
"BriefDescription": "Cycles",
"PublicDescription": ""
},
{,
"EventCode": "0x100F0",
"EventName": "PM_CYC",
"BriefDescription": "Cycles",
"PublicDescription": ""
"EventCode": "0x4D04C",
"EventName": "PM_DFU_BUSY",
"BriefDescription": "Cycles in which all 4 Decimal Floating Point units are busy. The DFU is running at capacity"
},
{,
"EventCode": "0x2",
"EventName": "PM_INST_CMPL",
"BriefDescription": "Number of PowerPC Instructions that completed.",
"PublicDescription": ""
"EventCode": "0x100F6",
"EventName": "PM_IERAT_RELOAD",
"BriefDescription": "Number of I-ERAT reloads"
},
{,
"EventCode": "0x100FE",
"EventName": "PM_INST_CMPL",
"BriefDescription": "# PPC instructions completed",
"PublicDescription": ""
"EventCode": "0x201E2",
"EventName": "PM_MRK_LD_MISS_L1",
"BriefDescription": "Marked DL1 Demand Miss counted at exec time. Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load."
},
{,
"EventCode": "0x10006",
"EventName": "PM_DISP_HELD",
"BriefDescription": "Dispatch Held",
"PublicDescription": ""
"EventCode": "0x40010",
"EventName": "PM_PMC3_OVERFLOW",
"BriefDescription": "Overflow from counter 3"
},
{,
"EventCode": "0x10016",
"EventName": "PM_DSLB_MISS",
"BriefDescription": "Data SLB Miss - Total of all segment sizes",
"PublicDescription": ""
"EventCode": "0x1005A",
"EventName": "PM_CMPLU_STALL_DFLONG",
"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued to the Decimal Floating Point execution pipe and waiting to finish. Includes decimal floating point instructions + 128 bit binary floating point instructions. Qualified by multicycle"
},
{,
"EventCode": "0x10018",
"EventName": "PM_IC_DEMAND_CYC",
"BriefDescription": "Icache miss demand cycles",
"PublicDescription": ""
"EventCode": "0x4D140",
"EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE",
"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load"
},
{,
"EventCode": "0x10022",
"EventName": "PM_PMC2_SAVED",
"BriefDescription": "PMC2 Rewind Value saved",
"PublicDescription": ""
"EventCode": "0x3F14C",
"EventName": "PM_MRK_DPTEG_FROM_DL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x10024",
"EventName": "PM_PMC5_OVERFLOW",
"BriefDescription": "Overflow from counter 5",
"PublicDescription": ""
"EventCode": "0x1E040",
"EventName": "PM_DPTEG_FROM_L2_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x1D14A",
"EventName": "PM_MRK_DATA_FROM_RL2L3_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
"PublicDescription": ""
"EventCode": "0x24052",
"EventName": "PM_FXU_IDLE",
"BriefDescription": "Cycles in which FXU0, FXU1, FXU2, and FXU3 are all idle"
},
{,
"EventCode": "0x1E040",
"EventName": "PM_DPTEG_FROM_L2_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x1E054",
"EventName": "PM_CMPLU_STALL",
"BriefDescription": "Nothing completed and ICT not empty"
},
{,
"EventCode": "0x1E04A",
"EventName": "PM_DPTEG_FROM_RL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x2",
"EventName": "PM_INST_CMPL",
"BriefDescription": "Number of PowerPC Instructions that completed."
},
{,
"EventCode": "0x1F140",
"EventName": "PM_MRK_DPTEG_FROM_L2_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x3D058",
"EventName": "PM_VSU_DP_FSQRT_FDIV",
"BriefDescription": "vector versions of fdiv,fsqrt"
},
{,
"EventCode": "0x1F142",
"EventName": "PM_MRK_DPTEG_FROM_L2",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x10006",
"EventName": "PM_DISP_HELD",
"BriefDescription": "Dispatch Held"
},
{,
"EventCode": "0x1F144",
"EventName": "PM_MRK_DPTEG_FROM_L3_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x3D154",
"EventName": "PM_MRK_DERAT_MISS_16M",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16M"
},
{,
"EventCode": "0x1F148",
"EventName": "PM_MRK_DPTEG_FROM_ON_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x200F8",
"EventName": "PM_EXT_INT",
"BriefDescription": "external interrupt"
},
{,
"EventCode": "0x10050",
"EventName": "PM_CHIP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": ""
"EventCode": "0x20008",
"EventName": "PM_ICT_EMPTY_CYC",
"BriefDescription": "Cycles in which the ICT is completely empty. No itags are assigned to any thread"
},
{,
"EventCode": "0x10054",
"EventName": "PM_PUMP_CPRED",
"BriefDescription": "Pump prediction correct. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": ""
"EventCode": "0x4F146",
"EventName": "PM_MRK_DPTEG_FROM_L21_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x10056",
"EventName": "PM_MEM_READ",
"BriefDescription": "Reads from Memory from this thread (includes data/inst/xlate/l1prefetch/inst prefetch). Includes L4",
"PublicDescription": ""
"BriefDescription": "Reads from Memory from this thread (includes data/inst/xlate/l1prefetch/inst prefetch). Includes L4"
},
{,
"EventCode": "0x1005A",
"EventName": "PM_CMPLU_STALL_DFLONG",
"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued to the Decimal Floating Point execution pipe and waiting to finish. Includes decimal floating point instructions + 128 bit binary floating point instructions. Qualified by multicycle",
"PublicDescription": ""
"EventCode": "0x3C04C",
"EventName": "PM_DATA_FROM_DL4",
"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load"
},
{,
"EventCode": "0x1C056",
"EventName": "PM_DERAT_MISS_4K",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K",
"PublicDescription": ""
"EventCode": "0x4E046",
"EventName": "PM_DPTEG_FROM_L21_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x1C05A",
"EventName": "PM_DERAT_MISS_2M",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation",
"PublicDescription": ""
"EventCode": "0x2E016",
"EventName": "PM_NTC_ISSUE_HELD_ARB",
"BriefDescription": "The NTC instruction is being held at dispatch because it lost arbitration onto the issue pipe to another instruction (from the same thread or a different thread)"
},
{,
"EventCode": "0x14050",
"EventName": "PM_INST_CHIP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch",
"PublicDescription": ""
"EventCode": "0x15156",
"EventName": "PM_SYNC_MRK_FX_DIVIDE",
"BriefDescription": "Marked fixed point divide that can cause a synchronous interrupt"
},
{,
"EventCode": "0x14052",
"EventName": "PM_INST_GRP_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch",
"PublicDescription": ""
"EventCode": "0x1C056",
"EventName": "PM_DERAT_MISS_4K",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K"
},
{,
"EventCode": "0x1D154",
"EventName": "PM_MRK_DATA_FROM_L2.1_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load",
"PublicDescription": ""
"EventCode": "0x2F142",
"EventName": "PM_MRK_DPTEG_FROM_L3_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x15156",
"EventName": "PM_SYNC_MRK_FX_DIVIDE",
"BriefDescription": "Marked fixed point divide that can cause a synchronous interrupt",
"PublicDescription": ""
"EventCode": "0x10024",
"EventName": "PM_PMC5_OVERFLOW",
"BriefDescription": "Overflow from counter 5"
},
{,
"EventCode": "0x1E054",
"EventName": "PM_CMPLU_STALL",
"BriefDescription": "Nothing completed and ICT not empty",
"PublicDescription": ""
"EventCode": "0x2C018",
"EventName": "PM_CMPLU_STALL_DMISS_L21_L31",
"BriefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)"
},
{,
"EventCode": "0x1F058",
"EventName": "PM_RADIX_PWC_L2_PTE_FROM_L2",
"BriefDescription": "A Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation",
"PublicDescription": ""
"EventCode": "0x4006A",
"EventName": "PM_IERAT_RELOAD_16M",
"BriefDescription": "IERAT Reloaded (Miss) for a 16M page"
},
{,
"EventCode": "0x10062",
"EventName": "PM_LD_L3MISS_PEND_CYC",
"BriefDescription": "Cycles L3 miss was pending for this thread",
"PublicDescription": ""
"EventCode": "0x4E010",
"EventName": "PM_ICT_NOSLOT_IC_L3MISS",
"BriefDescription": "Ict empty for this thread due to icache misses that were sourced from beyond the local L3. The source could be local/remote/distant memory or another core's cache"
},
{,
"EventCode": "0x10064",
"EventName": "PM_ICT_NOSLOT_DISP_HELD_TBEGIN",
"BriefDescription": "the NTC instruction is being held at dispatch because it is a tbegin instruction and there is an older tbegin in the pipeline that must complete before the younger tbegin can dispatch",
"PublicDescription": ""
"EventCode": "0x4D01C",
"EventName": "PM_ICT_NOSLOT_DISP_HELD_SYNC",
"BriefDescription": "Dispatch held due to a synchronizing instruction at dispatch"
},
{,
"EventCode": "0x10068",
"EventName": "PM_BRU_FIN",
"BriefDescription": "Branch Instruction Finished",
"PublicDescription": ""
"EventCode": "0x2D01A",
"EventName": "PM_ICT_NOSLOT_IC_MISS",
"BriefDescription": "Ict empty for this thread due to Icache Miss"
},
{,
"EventCode": "0x100F6",
"EventName": "PM_IERAT_RELOAD",
"BriefDescription": "Number of I-ERAT reloads",
"PublicDescription": ""
"EventCode": "0x3D152",
"EventName": "PM_MRK_DERAT_MISS_1G",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 1G. Implies radix translation"
},
{,
"EventCode": "0x100F8",
"EventName": "PM_ICT_NOSLOT_CYC",
"BriefDescription": "Number of cycles the ICT has no itags assigned to this thread",
"PublicDescription": ""
"EventCode": "0x4F14A",
"EventName": "PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x20008",
"EventName": "PM_ICT_EMPTY_CYC",
"BriefDescription": "Cycles in which the ICT is completely empty. No itags are assigned to any thread",
"PublicDescription": ""
"EventCode": "0x30058",
"EventName": "PM_TLBIE_FIN",
"BriefDescription": "tlbie finished"
},
{,
"EventCode": "0x2000A",
"EventName": "PM_HV_CYC",
"BriefDescription": "Cycles in which msr_hv is high. Note that this event does not take msr_pr into consideration",
"PublicDescription": ""
"EventCode": "0x100F8",
"EventName": "PM_ICT_NOSLOT_CYC",
"BriefDescription": "Number of cycles the ICT has no itags assigned to this thread"
},
{,
"EventCode": "0x2000E",
"EventName": "PM_FXU_BUSY",
"BriefDescription": "Cycles in which all 4 FXUs are busy. The FXU is running at capacity",
"PublicDescription": ""
"EventCode": "0x3E042",
"EventName": "PM_DPTEG_FROM_L3_DISP_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x2C018",
"EventName": "PM_CMPLU_STALL_DMISS_L21_L31",
"BriefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)",
"PublicDescription": ""
"EventCode": "0x1F140",
"EventName": "PM_MRK_DPTEG_FROM_L2_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x2D012",
"EventName": "PM_CMPLU_STALL_DFU",
"BriefDescription": "Finish stall because the NTF instruction was issued to the Decimal Floating Point execution pipe and waiting to finish. Includes decimal floating point instructions + 128 bit binary floating point instructions. Not qualified by multicycle",
"PublicDescription": ""
"EventCode": "0x2C05A",
"EventName": "PM_DERAT_MISS_1G",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 1G. Implies radix translation"
},
{,
"EventCode": "0x2D01A",
"EventName": "PM_ICT_NOSLOT_IC_MISS",
"BriefDescription": "Ict empty for this thread due to Icache Miss",
"PublicDescription": ""
"EventCode": "0x1F058",
"EventName": "PM_RADIX_PWC_L2_PTE_FROM_L2",
"BriefDescription": "A Page Table Entry was reloaded to a level 2 page walk cache from the core's L2 data cache. This implies that level 3 and level 4 PWC accesses were not necessary for this translation"
},
{,
"EventCode": "0x2E012",
"EventName": "PM_TM_TX_PASS_RUN_CYC",
"BriefDescription": "cycles spent in successful transactions",
"PublicDescription": ""
"EventCode": "0x1D14A",
"EventName": "PM_MRK_DATA_FROM_RL2L3_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load"
},
{,
"EventCode": "0x2E016",
"EventName": "PM_NTC_ISSUE_HELD_ARB",
"BriefDescription": "The NTC instruction is being held at dispatch because it lost arbitration onto the issue pipe to another instruction (from the same thread or a different thread)",
"PublicDescription": ""
"EventCode": "0x10050",
"EventName": "PM_CHIP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
"EventCode": "0x2C046",
"EventName": "PM_DATA_FROM_RL2L3_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load",
"PublicDescription": ""
"EventCode": "0x45058",
"EventName": "PM_IC_MISS_CMPL",
"BriefDescription": "Non-speculative icache miss, counted at completion"
},
{,
"EventCode": "0x2404C",
"EventName": "PM_INST_FROM_MEMORY",
"BriefDescription": "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x2D150",
"EventName": "PM_MRK_DERAT_MISS_4K",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 4K"
},
{,
"EventCode": "0x2D14E",
"EventName": "PM_MRK_DATA_FROM_L2.1_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load",
"PublicDescription": ""
"EventCode": "0x34058",
"EventName": "PM_ICT_NOSLOT_BR_MPRED_ICMISS",
"BriefDescription": "Ict empty for this thread due to Icache Miss and branch mispred"
},
{,
"EventCode": "0x2E042",
"EventName": "PM_DPTEG_FROM_L3_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x10022",
"EventName": "PM_PMC2_SAVED",
"BriefDescription": "PMC2 Rewind Value saved"
},
{,
"EventCode": "0x2E046",
"EventName": "PM_DPTEG_FROM_RL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x2000A",
"EventName": "PM_HV_CYC",
"BriefDescription": "Cycles in which msr_hv is high. Note that this event does not take msr_pr into consideration"
},
{,
"EventCode": "0x2F142",
"EventName": "PM_MRK_DPTEG_FROM_L3_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x1F144",
"EventName": "PM_MRK_DPTEG_FROM_L3_NO_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x2F144",
"EventName": "PM_MRK_DPTEG_FROM_L3.1_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x300FC",
"EventName": "PM_DTLB_MISS",
"BriefDescription": "Data PTEG reload"
},
{,
"EventCode": "0x2F146",
"EventName": "PM_MRK_DPTEG_FROM_RL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x2D152",
"EventName": "PM_MRK_DERAT_MISS_2M",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation"
},
{,
"EventCode": "0x2F14C",
"EventName": "PM_MRK_DPTEG_FROM_MEMORY",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x2C046",
"EventName": "PM_DATA_FROM_RL2L3_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a demand load"
},
{,
"EventCode": "0x20052",
"EventName": "PM_GRP_PUMP_MPRED",
"BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": ""
},
{,
"EventCode": "0x2C054",
"EventName": "PM_DERAT_MISS_64K",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K",
"PublicDescription": ""
"BriefDescription": "Final Pump Scope (Group) ended up either larger or smaller than Initial Pump Scope for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
"EventCode": "0x2C05A",
"EventName": "PM_DERAT_MISS_1G",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 1G. Implies radix translation",
"PublicDescription": ""
"EventCode": "0x3F05A",
"EventName": "PM_RADIX_PWC_L2_PDE_FROM_L3",
"BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache"
},
{,
"EventCode": "0x24052",
"EventName": "PM_FXU_IDLE",
"BriefDescription": "Cycles in which FXU0, FXU1, FXU2, and FXU3 are all idle",
"PublicDescription": ""
"EventCode": "0x1E04A",
"EventName": "PM_DPTEG_FROM_RL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x2405A",
"EventName": "PM_NTC_FIN",
"BriefDescription": "Cycles in which the oldest instruction in the pipeline (NTC) finishes. This event is used to account for cycles in which work is being completed in the CPI stack",
"PublicDescription": ""
"EventCode": "0x10064",
"EventName": "PM_ICT_NOSLOT_DISP_HELD_TBEGIN",
"BriefDescription": "the NTC instruction is being held at dispatch because it is a tbegin instruction and there is an older tbegin in the pipeline that must complete before the younger tbegin can dispatch"
},
{,
"EventCode": "0x2D150",
"EventName": "PM_MRK_DERAT_MISS_4K",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 4K",
"PublicDescription": ""
"EventCode": "0x2E046",
"EventName": "PM_DPTEG_FROM_RL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x2D152",
"EventName": "PM_MRK_DERAT_MISS_2M",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation",
"PublicDescription": ""
"EventCode": "0x4F14C",
"EventName": "PM_MRK_DPTEG_FROM_DMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x20066",
"EventName": "PM_TLB_MISS",
"BriefDescription": "TLB Miss (I + D)",
"PublicDescription": ""
"EventCode": "0x2E042",
"EventName": "PM_DPTEG_FROM_L3_MEPF",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x201E2",
"EventName": "PM_MRK_LD_MISS_L1",
"BriefDescription": "Marked DL1 Demand Miss counted at exec time. Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load.",
"PublicDescription": ""
"EventCode": "0x2D012",
"EventName": "PM_CMPLU_STALL_DFU",
"BriefDescription": "Finish stall because the NTF instruction was issued to the Decimal Floating Point execution pipe and waiting to finish. Includes decimal floating point instructions + 128 bit binary floating point instructions. Not qualified by multicycle"
},
{,
"EventCode": "0x200F4",
"EventName": "PM_RUN_CYC",
"BriefDescription": "Run_cycles",
"PublicDescription": ""
"EventCode": "0x4C04C",
"EventName": "PM_DATA_FROM_DMEM",
"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load"
},
{,
"EventCode": "0x200F8",
"EventName": "PM_EXT_INT",
"BriefDescription": "external interrupt",
"PublicDescription": ""
"EventCode": "0x30022",
"EventName": "PM_PMC4_SAVED",
"BriefDescription": "PMC4 Rewind Value saved (matched condition)"
},
{,
"EventCode": "0x30004",
"EventName": "PM_CMPLU_STALL_EMQ_FULL",
"BriefDescription": "Finish stall because the next to finish instruction suffered an ERAT miss and the EMQ was full",
"PublicDescription": ""
"EventCode": "0x200F4",
"EventName": "PM_RUN_CYC",
"BriefDescription": "Run_cycles"
},
{,
"EventCode": "0x30020",
"EventName": "PM_PMC2_REWIND",
"BriefDescription": "PMC2 Rewind Event (did not match condition)",
"PublicDescription": ""
"EventCode": "0x400F2",
"EventName": "PM_1PLUS_PPC_DISP",
"BriefDescription": "Cycles at least one Instr Dispatched"
},
{,
"EventCode": "0x30022",
"EventName": "PM_PMC4_SAVED",
"BriefDescription": "PMC4 Rewind Value saved (matched condition)",
"PublicDescription": ""
"EventCode": "0x3D148",
"EventName": "PM_MRK_DATA_FROM_L21_MOD_CYC",
"BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load"
},
{,
"EventCode": "0x30024",
"EventName": "PM_PMC6_OVERFLOW",
"BriefDescription": "Overflow from counter 6",
"PublicDescription": ""
"EventCode": "0x2F146",
"EventName": "PM_MRK_DPTEG_FROM_RL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x3C04C",
"EventName": "PM_DATA_FROM_DL4",
"BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load",
"PublicDescription": ""
"EventCode": "0x4E01A",
"EventName": "PM_ICT_NOSLOT_DISP_HELD",
"BriefDescription": "Cycles in which the NTC instruction is held at dispatch for any reason"
},
{,
"EventCode": "0x3D148",
"EventName": "PM_MRK_DATA_FROM_L2.1_MOD_CYC",
"BriefDescription": "Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load",
"PublicDescription": ""
"EventCode": "0x401EC",
"EventName": "PM_THRESH_EXC_2048",
"BriefDescription": "Threshold counter exceeded a value of 2048"
},
{,
"EventCode": "0x3E042",
"EventName": "PM_DPTEG_FROM_L3_DISP_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x35150",
"EventName": "PM_MRK_DATA_FROM_RL2L3_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load"
},
{,
"EventCode": "0x3E046",
"EventName": "PM_DPTEG_FROM_L2.1_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x3E052",
"EventName": "PM_ICT_NOSLOT_IC_L3",
"BriefDescription": "Ict empty for this thread due to icache misses that were sourced from the local L3"
},
{,
"EventCode": "0x3F148",
"EventName": "PM_MRK_DPTEG_FROM_DL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x2405A",
"EventName": "PM_NTC_FIN",
"BriefDescription": "Cycles in which the oldest instruction in the pipeline (NTC) finishes. This event is used to account for cycles in which work is being completed in the CPI stack"
},
{,
"EventCode": "0x3F14C",
"EventName": "PM_MRK_DPTEG_FROM_DL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x40052",
"EventName": "PM_PUMP_MPRED",
"BriefDescription": "Pump misprediction. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
"EventCode": "0x30056",
"EventName": "PM_TM_ABORTS",
"BriefDescription": "Number of TM transactions aborted",
"PublicDescription": ""
"BriefDescription": "Number of TM transactions aborted"
},
{,
"EventCode": "0x30058",
"EventName": "PM_TLBIE_FIN",
"BriefDescription": "tlbie finished",
"PublicDescription": ""
"EventCode": "0x2404C",
"EventName": "PM_INST_FROM_MEMORY",
"BriefDescription": "The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x3C054",
"EventName": "PM_DERAT_MISS_16M",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M",
"PublicDescription": ""
"EventCode": "0x1C05A",
"EventName": "PM_DERAT_MISS_2M",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 2M. Implies radix translation"
},
{,
"EventCode": "0x34058",
"EventName": "PM_ICT_NOSLOT_BR_MPRED_ICMISS",
"BriefDescription": "Ict empty for this thread due to Icache Miss and branch mispred",
"PublicDescription": ""
"EventCode": "0x30024",
"EventName": "PM_PMC6_OVERFLOW",
"BriefDescription": "Overflow from counter 6"
},
{,
"EventCode": "0x3405C",
"EventName": "PM_CMPLU_STALL_DPLONG",
"BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle",
"PublicDescription": ""
"EventCode": "0x10068",
"EventName": "PM_BRU_FIN",
"BriefDescription": "Branch Instruction Finished"
},
{,
"EventCode": "0x3405E",
"EventName": "PM_IFETCH_THROTTLE",
"BriefDescription": "Cycles in which Instruction fetch throttle was active.",
"PublicDescription": ""
"EventCode": "0x30020",
"EventName": "PM_PMC2_REWIND",
"BriefDescription": "PMC2 Rewind Event (did not match condition)"
},
{,
"EventCode": "0x3D152",
"EventName": "PM_MRK_DERAT_MISS_1G",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 1G. Implies radix translation",
"PublicDescription": ""
"EventCode": "0x40064",
"EventName": "PM_DUMMY2_REMOVE_ME",
"BriefDescription": "Space holder for LS_PC_RELOAD_RA"
},
{,
"EventCode": "0x3D154",
"EventName": "PM_MRK_DERAT_MISS_16M",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16M",
"PublicDescription": ""
"EventCode": "0x3F148",
"EventName": "PM_MRK_DPTEG_FROM_DL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x3D058",
"EventName": "PM_VSU_DP_FSQRT_FDIV",
"BriefDescription": "vector versions of fdiv,fsqrt",
"PublicDescription": ""
"EventCode": "0x4D01E",
"EventName": "PM_ICT_NOSLOT_BR_MPRED",
"BriefDescription": "Ict empty for this thread due to branch mispred"
},
{,
"EventCode": "0x35150",
"EventName": "PM_MRK_DATA_FROM_RL2L3_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
"PublicDescription": ""
"EventCode": "0x3405E",
"EventName": "PM_IFETCH_THROTTLE",
"BriefDescription": "Cycles in which Instruction fetch throttle was active."
},
{,
"EventCode": "0x3E052",
"EventName": "PM_ICT_NOSLOT_IC_L3",
"BriefDescription": "Ict empty for this thread due to icache misses that were sourced from the local L3",
"PublicDescription": ""
"EventCode": "0x1F148",
"EventName": "PM_MRK_DPTEG_FROM_ON_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x3F05A",
"EventName": "PM_RADIX_PWC_L2_PDE_FROM_L3",
"BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L3 data cache",
"PublicDescription": ""
"EventCode": "0x3E046",
"EventName": "PM_DPTEG_FROM_L21_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x300FC",
"EventName": "PM_DTLB_MISS",
"BriefDescription": "Data PTEG reload",
"PublicDescription": ""
"EventCode": "0x2F144",
"EventName": "PM_MRK_DPTEG_FROM_L31_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x40004",
"EventName": "PM_FXU_FIN",
"BriefDescription": "The fixed point unit Unit finished an instruction. Instructions that finish may not necessary complete.",
"PublicDescription": ""
"EventCode": "0x4C15C",
"EventName": "PM_MRK_DERAT_MISS_16G",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16G"
},
{,
"EventCode": "0x40010",
"EventName": "PM_PMC3_OVERFLOW",
"BriefDescription": "Overflow from counter 3",
"PublicDescription": ""
"EventCode": "0x14052",
"EventName": "PM_INST_GRP_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (Group) ended up larger than Initial Pump Scope (Chip) for an instruction fetch"
},
{,
"EventCode": "0x4C012",
"EventName": "PM_CMPLU_STALL_ERAT_MISS",
"BriefDescription": "Finish stall because the NTF instruction was a load or store that suffered a translation miss",
"PublicDescription": ""
"EventCode": "0x10016",
"EventName": "PM_DSLB_MISS",
"BriefDescription": "Data SLB Miss - Total of all segment sizes"
},
{,
"EventCode": "0x4D01C",
"EventName": "PM_ICT_NOSLOT_DISP_HELD_SYNC",
"BriefDescription": "Dispatch held due to a synchronizing instruction at dispatch",
"PublicDescription": ""
"EventCode": "0xD0A8",
"EventName": "PM_DSLB_MISS",
"BriefDescription": "Data SLB Miss - Total of all segment sizes"
},
{,
"EventCode": "0x4D01E",
"EventName": "PM_ICT_NOSLOT_BR_MPRED",
"BriefDescription": "Ict empty for this thread due to branch mispred",
"PublicDescription": ""
"EventCode": "0x4C058",
"EventName": "PM_MEM_CO",
"BriefDescription": "Memory castouts from this thread"
},
{,
"EventCode": "0x4E010",
"EventName": "PM_ICT_NOSLOT_IC_L3MISS",
"BriefDescription": "Ict empty for this thread due to icache misses that were sourced from beyond the local L3. The source could be local/remote/distant memory or another core's cache",
"PublicDescription": ""
"EventCode": "0x40004",
"EventName": "PM_FXU_FIN",
"BriefDescription": "The fixed point unit Unit finished an instruction. Instructions that finish may not necessary complete."
},
{,
"EventCode": "0x4E01A",
"EventName": "PM_ICT_NOSLOT_DISP_HELD",
"BriefDescription": "Cycles in which the NTC instruction is held at dispatch for any reason",
"PublicDescription": ""
"EventCode": "0x2C054",
"EventName": "PM_DERAT_MISS_64K",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K"
},
{,
"EventCode": "0x4C120",
"EventName": "PM_MRK_DATA_FROM_L2_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load",
"PublicDescription": ""
"EventCode": "0x10018",
"EventName": "PM_IC_DEMAND_CYC",
"BriefDescription": "Icache miss demand cycles"
},
{,
"EventCode": "0x4D124",
"EventName": "PM_MRK_DATA_FROM_L3.1_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load",
"PublicDescription": ""
"EventCode": "0x3C054",
"EventName": "PM_DERAT_MISS_16M",
"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M"
},
{,
"EventCode": "0x4C04C",
"EventName": "PM_DATA_FROM_DMEM",
"BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a demand load",
"PublicDescription": ""
"EventCode": "0x2D14E",
"EventName": "PM_MRK_DATA_FROM_L21_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load"
},
{,
"EventCode": "0x4D140",
"EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE",
"BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
"PublicDescription": ""
"EventCode": "0x3405C",
"EventName": "PM_CMPLU_STALL_DPLONG",
"BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle"
},
{,
"EventCode": "0x4D04C",
"EventName": "PM_DFU_BUSY",
"BriefDescription": "Cycles in which all 4 Decimal Floating Point units are busy. The DFU is running at capacity",
"PublicDescription": ""
"EventCode": "0x4D052",
"EventName": "PM_2FLOP_CMPL",
"BriefDescription": "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg "
},
{,
"EventCode": "0x4D04E",
"EventName": "PM_VSU_FSQRT_FDIV",
"BriefDescription": "four flops operation (fdiv,fsqrt) Scalar Instructions only",
"PublicDescription": ""
"EventCode": "0x1F142",
"EventName": "PM_MRK_DPTEG_FROM_L2",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x4E046",
"EventName": "PM_DPTEG_FROM_L2.1_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x40062",
"EventName": "PM_DUMMY1_REMOVE_ME",
"BriefDescription": "Space holder for L2_PC_PM_MK_LDST_SCOPE_PRED_STATUS"
},
{,
"EventCode": "0x4F146",
"EventName": "PM_MRK_DPTEG_FROM_L2.1_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x4C012",
"EventName": "PM_CMPLU_STALL_ERAT_MISS",
"BriefDescription": "Finish stall because the NTF instruction was a load or store that suffered a translation miss"
},
{,
"EventCode": "0x4F14A",
"EventName": "PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x4D050",
"EventName": "PM_VSU_NON_FLOP_CMPL",
"BriefDescription": "Non FLOP operation completed"
},
{,
"EventCode": "0x4F14C",
"EventName": "PM_MRK_DPTEG_FROM_DMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x2E012",
"EventName": "PM_TM_TX_PASS_RUN_CYC",
"BriefDescription": "cycles spent in successful transactions"
},
{,
"EventCode": "0x40052",
"EventName": "PM_PUMP_MPRED",
"BriefDescription": "Pump misprediction. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": ""
"EventCode": "0x4D04E",
"EventName": "PM_VSU_FSQRT_FDIV",
"BriefDescription": "four flops operation (fdiv,fsqrt) Scalar Instructions only"
},
{,
"EventCode": "0x4C058",
"EventName": "PM_MEM_CO",
"BriefDescription": "Memory castouts from this thread",
"PublicDescription": ""
"EventCode": "0x4C120",
"EventName": "PM_MRK_DATA_FROM_L2_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load"
},
{,
"EventCode": "0x4C15C",
"EventName": "PM_MRK_DERAT_MISS_16G",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16G",
"PublicDescription": ""
"EventCode": "0x10062",
"EventName": "PM_LD_L3MISS_PEND_CYC",
"BriefDescription": "Cycles L3 miss was pending for this thread"
},
{,
"EventCode": "0x4D050",
"EventName": "PM_VSU_NON_FLOP_CMPL",
"BriefDescription": "Non FLOP operation completed",
"PublicDescription": ""
"EventCode": "0x2F14C",
"EventName": "PM_MRK_DPTEG_FROM_MEMORY",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x4D052",
"EventName": "PM_2FLOP_CMPL",
"BriefDescription": "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg ",
"PublicDescription": ""
"EventCode": "0x14050",
"EventName": "PM_INST_CHIP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch"
},
{,
"EventCode": "0x45058",
"EventName": "PM_IC_MISS_CMPL",
"BriefDescription": "Non-speculative icache miss, counted at completion",
"PublicDescription": ""
"EventCode": "0x2000E",
"EventName": "PM_FXU_BUSY",
"BriefDescription": "Cycles in which all 4 FXUs are busy. The FXU is running at capacity"
},
{,
"EventCode": "0x40062",
"EventName": "PM_DUMMY1_REMOVE_ME",
"BriefDescription": "Space holder for L2_PC_PM_MK_LDST_SCOPE_PRED_STATUS",
"PublicDescription": ""
"EventCode": "0x20066",
"EventName": "PM_TLB_MISS",
"BriefDescription": "TLB Miss (I + D)"
},
{,
"EventCode": "0x40064",
"EventName": "PM_DUMMY2_REMOVE_ME",
"BriefDescription": "Space holder for LS_PC_RELOAD_RA",
"PublicDescription": ""
"EventCode": "0x10054",
"EventName": "PM_PUMP_CPRED",
"BriefDescription": "Pump prediction correct. Counts across all types of pumps for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
"EventCode": "0x4006A",
"EventName": "PM_IERAT_RELOAD_16M",
"BriefDescription": "IERAT Reloaded (Miss) for a 16M page",
"PublicDescription": ""
"EventCode": "0x4D124",
"EventName": "PM_MRK_DATA_FROM_L31_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load"
},
{,
"EventCode": "0x401EC",
"EventName": "PM_THRESH_EXC_2048",
"BriefDescription": "Threshold counter exceeded a value of 2048",
"PublicDescription": ""
"EventCode": "0x400F8",
"EventName": "PM_FLUSH",
"BriefDescription": "Flush (any type)"
},
{,
"EventCode": "0x400F2",
"EventName": "PM_1PLUS_PPC_DISP",
"BriefDescription": "Cycles at least one Instr Dispatched",
"PublicDescription": ""
"EventCode": "0x30004",
"EventName": "PM_CMPLU_STALL_EMQ_FULL",
"BriefDescription": "Finish stall because the next to finish instruction suffered an ERAT miss and the EMQ was full"
},
{,
"EventCode": "0x400F8",
"EventName": "PM_FLUSH",
"BriefDescription": "Flush (any type)",
"PublicDescription": ""
"EventCode": "0x1D154",
"EventName": "PM_MRK_DATA_FROM_L21_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/powerpc/power9/pmc.json
View file @ 3c22ba52
[
{,
"EventCode": "0x0",
"EventName": "PM_SUSPENDED",
"BriefDescription": "Counter OFF",
"PublicDescription": ""
"EventCode": "0x20036",
"EventName": "PM_BR_2PATH",
"BriefDescription": "Branches that are not strongly biased"
},
{,
"EventCode": "0x10026",
"EventName": "PM_TABLEWALK_CYC",
"BriefDescription": "Cycles when an instruction tablewalk is active",
"PublicDescription": ""
"EventCode": "0x40036",
"EventName": "PM_BR_2PATH",
"BriefDescription": "Branches that are not strongly biased"
},
{,
"EventCode": "0x1E04C",
"EventName": "PM_DPTEG_FROM_LL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x40056",
"EventName": "PM_MEM_LOC_THRESH_LSU_HIGH",
"BriefDescription": "Local memory above threshold for LSU medium"
},
{,
"EventCode": "0x1F14E",
"EventName": "PM_MRK_DPTEG_FROM_L2MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x2C056",
"EventName": "PM_DTLB_MISS_4K",
"BriefDescription": "Data TLB Miss page size 4k"
},
{,
"EventCode": "0x10060",
"EventName": "PM_TM_TRANS_RUN_CYC",
"BriefDescription": "run cycles in transactional state",
"PublicDescription": ""
"EventCode": "0x40118",
"EventName": "PM_MRK_DCACHE_RELOAD_INTV",
"BriefDescription": "Combined Intervention event"
},
{,
"EventCode": "0x2C012",
"EventName": "PM_CMPLU_STALL_DCACHE_MISS",
"BriefDescription": "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest",
"PublicDescription": ""
"EventCode": "0x4F148",
"EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x2E04C",
"EventName": "PM_DPTEG_FROM_MEMORY",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x301E8",
"EventName": "PM_THRESH_EXC_64",
"BriefDescription": "Threshold counter exceeded a value of 64"
},
{,
"EventCode": "0x2C056",
"EventName": "PM_DTLB_MISS_4K",
"BriefDescription": "Data TLB Miss page size 4k",
"PublicDescription": ""
"EventCode": "0x4E04E",
"EventName": "PM_DPTEG_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x3000C",
"EventName": "PM_FREQ_DOWN",
"BriefDescription": "Power Management: Below Threshold B",
"PublicDescription": ""
"EventCode": "0x40050",
"EventName": "PM_SYS_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
},
{,
"EventCode": "0x3D142",
"EventName": "PM_MRK_DATA_FROM_LMEM",
"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load",
"PublicDescription": ""
"EventCode": "0x1F14E",
"EventName": "PM_MRK_DPTEG_FROM_L2MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x3F142",
"EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x4D018",
"EventName": "PM_CMPLU_STALL_BRU",
"BriefDescription": "Completion stall due to a Branch Unit"
},
{,
"EventCode": "0x301E8",
"EventName": "PM_THRESH_EXC_64",
"BriefDescription": "Threshold counter exceeded a value of 64",
"PublicDescription": ""
"EventCode": "0x45052",
"EventName": "PM_4FLOP_CMPL",
"BriefDescription": "4 FLOP instruction completed"
},
{,
"EventCode": "0x40118",
"EventName": "PM_MRK_DCACHE_RELOAD_INTV",
"BriefDescription": "Combined Intervention event",
"PublicDescription": ""
"EventCode": "0x3D142",
"EventName": "PM_MRK_DATA_FROM_LMEM",
"BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load"
},
{,
"EventCode": "0x4C01E",
"EventName": "PM_CMPLU_STALL_CRYPTO",
"BriefDescription": "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish",
"PublicDescription": ""
"BriefDescription": "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish"
},
{,
"EventCode": "0x4D018",
"EventName": "PM_CMPLU_STALL_BRU",
"BriefDescription": "Completion stall due to a Branch Unit",
"PublicDescription": ""
"EventCode": "0x3000C",
"EventName": "PM_FREQ_DOWN",
"BriefDescription": "Power Management: Below Threshold B"
},
{,
"EventCode": "0x4D128",
"EventName": "PM_MRK_DATA_FROM_LMEM_CYC",
"BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load",
"PublicDescription": ""
"BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load"
},
{,
"EventCode": "0x4E04E",
"EventName": "PM_DPTEG_FROM_L3MISS",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x4D054",
"EventName": "PM_8FLOP_CMPL",
"BriefDescription": "8 FLOP instruction completed"
},
{,
"EventCode": "0x4F142",
"EventName": "PM_MRK_DPTEG_FROM_L3",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x10026",
"EventName": "PM_TABLEWALK_CYC",
"BriefDescription": "Cycles when an instruction tablewalk is active"
},
{,
"EventCode": "0x4F148",
"EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x2C012",
"EventName": "PM_CMPLU_STALL_DCACHE_MISS",
"BriefDescription": "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest"
},
{,
"EventCode": "0x40050",
"EventName": "PM_SYS_PUMP_MPRED_RTY",
"BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)",
"PublicDescription": ""
"EventCode": "0x2E04C",
"EventName": "PM_DPTEG_FROM_MEMORY",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x40056",
"EventName": "PM_MEM_LOC_THRESH_LSU_HIGH",
"BriefDescription": "Local memory above threshold for LSU medium",
"PublicDescription": ""
"EventCode": "0x3F142",
"EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x4D054",
"EventName": "PM_8FLOP_CMPL",
"BriefDescription": "8 FLOP instruction completed",
"PublicDescription": ""
"EventCode": "0x4F142",
"EventName": "PM_MRK_DPTEG_FROM_L3",
"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x45050",
"EventName": "PM_1FLOP_CMPL",
"BriefDescription": "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed",
"PublicDescription": ""
"EventCode": "0x10060",
"EventName": "PM_TM_TRANS_RUN_CYC",
"BriefDescription": "run cycles in transactional state"
},
{,
"EventCode": "0x45052",
"EventName": "PM_4FLOP_CMPL",
"BriefDescription": "4 FLOP instruction completed",
"PublicDescription": ""
"EventCode": "0x1E04C",
"EventName": "PM_DPTEG_FROM_LL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x45050",
"EventName": "PM_1FLOP_CMPL",
"BriefDescription": "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/powerpc/power9/translation.json
View file @ 3c22ba52
[
{,
"EventCode": "0x10028",
"EventName": "PM_STALL_END_ICT_EMPTY",
"BriefDescription": "The number a times the core transitioned from a stall to ICT-empty for this thread",
"PublicDescription": ""
},
{,
"EventCode": "0x1C04E",
"EventName": "PM_DATA_FROM_L2MISS_MOD",
"BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load",
"PublicDescription": ""
"EventCode": "0x1E",
"EventName": "PM_CYC",
"BriefDescription": "Processor cycles"
},
{,
"EventCode": "0x14044",
"EventName": "PM_INST_FROM_L3_NO_CONFLICT",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x30010",
"EventName": "PM_PMC2_OVERFLOW",
"BriefDescription": "Overflow from counter 2"
},
{,
"EventCode": "0x1404E",
"EventName": "PM_INST_FROM_L2MISS",
"BriefDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x3C046",
"EventName": "PM_DATA_FROM_L21_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load"
},
{,
"EventCode": "0x1D142",
"EventName": "PM_MRK_DATA_FROM_L3.1_ECO_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load",
"PublicDescription": ""
"EventCode": "0x4D05C",
"EventName": "PM_DP_QP_FLOP_CMPL",
"BriefDescription": "Double-Precion or Quad-Precision instruction completed"
},
{,
"EventCode": "0x15048",
"EventName": "PM_IPTEG_FROM_ON_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request",
"PublicDescription": ""
"EventCode": "0x4E04C",
"EventName": "PM_DPTEG_FROM_DMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x1504A",
"EventName": "PM_IPTEG_FROM_RL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
"PublicDescription": ""
"EventCode": "0x20016",
"EventName": "PM_ST_FIN",
"BriefDescription": "Store finish count. Includes speculative activity"
},
{,
"EventCode": "0x1E058",
"EventName": "PM_STCX_FAIL",
"BriefDescription": "stcx failed",
"PublicDescription": ""
"EventCode": "0x44042",
"EventName": "PM_INST_FROM_L3",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x1F15E",
"EventName": "PM_MRK_PROBE_NOP_CMPL",
"BriefDescription": "Marked probeNops completed",
"PublicDescription": ""
"EventCode": "0x1504A",
"EventName": "PM_IPTEG_FROM_RL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
},
{,
"EventCode": "0x20112",
"EventName": "PM_MRK_NTF_FIN",
"BriefDescription": "Marked next to finish instruction finished",
"PublicDescription": ""
"EventCode": "0x40132",
"EventName": "PM_MRK_LSU_FIN",
"BriefDescription": "lsu marked instr PPC finish"
},
{,
"EventCode": "0x20016",
"EventName": "PM_ST_FIN",
"BriefDescription": "Store finish count. Includes speculative activity",
"PublicDescription": ""
"EventCode": "0x3C05C",
"EventName": "PM_CMPLU_STALL_VFXU",
"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes"
},
{,
"EventCode": "0x20018",
"EventName": "PM_ST_FWD",
"BriefDescription": "Store forwards that finished",
"PublicDescription": ""
"EventCode": "0x30066",
"EventName": "PM_LSU_FIN",
"BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)"
},
{,
"EventCode": "0x2011C",
"EventName": "PM_MRK_NTC_CYC",
"BriefDescription": "Cycles during which the marked instruction is next to complete (completion is held up because the marked instruction hasn't completed yet)",
"PublicDescription": ""
"BriefDescription": "Cycles during which the marked instruction is next to complete (completion is held up because the marked instruction hasn't completed yet)"
},
{,
"EventCode": "0x3E048",
"EventName": "PM_DPTEG_FROM_DL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x2E018",
"EventName": "PM_CMPLU_STALL_VFXLONG",
"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (division, square root)",
"PublicDescription": ""
"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (division, square root)"
},
{,
"EventCode": "0x2E01C",
"EventName": "PM_CMPLU_STALL_TLBIE",
"BriefDescription": "Finish stall because the NTF instruction was a tlbie waiting for response from L2",
"PublicDescription": ""
"EventCode": "0x1C04E",
"EventName": "PM_DATA_FROM_L2MISS_MOD",
"BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L2 due to a demand load"
},
{,
"EventCode": "0x2003E",
"EventName": "PM_LSU_LMQ_SRQ_EMPTY_CYC",
"BriefDescription": "Cycles in which the LSU is empty for all threads (lmq and srq are completely empty)",
"PublicDescription": ""
"EventCode": "0x15048",
"EventName": "PM_IPTEG_FROM_ON_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request"
},
{,
"EventCode": "0x24042",
"EventName": "PM_INST_FROM_L3_MEPF",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x34046",
"EventName": "PM_INST_FROM_L21_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x2D14A",
"EventName": "PM_MRK_DATA_FROM_RL2L3_MOD_CYC",
"BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
"PublicDescription": ""
"EventCode": "0x1E058",
"EventName": "PM_STCX_FAIL",
"BriefDescription": "stcx failed"
},
{,
"EventCode": "0x25046",
"EventName": "PM_IPTEG_FROM_RL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request",
"PublicDescription": ""
"EventCode": "0x20112",
"EventName": "PM_MRK_NTF_FIN",
"BriefDescription": "Marked next to finish instruction finished"
},
{,
"EventCode": "0x300F0",
"EventName": "PM_ST_MISS_L1",
"BriefDescription": "Store Missed L1"
},
{,
"EventCode": "0x4C046",
"EventName": "PM_DATA_FROM_L21_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load"
},
{,
"EventCode": "0x2504A",
"EventName": "PM_IPTEG_FROM_RL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request",
"PublicDescription": ""
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request"
},
{,
"EventCode": "0x2504C",
"EventName": "PM_IPTEG_FROM_MEMORY",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request",
"PublicDescription": ""
"EventCode": "0x2003E",
"EventName": "PM_LSU_LMQ_SRQ_EMPTY_CYC",
"BriefDescription": "Cycles in which the LSU is empty for all threads (lmq and srq are completely empty)"
},
{,
"EventCode": "0x201E6",
"EventName": "PM_THRESH_EXC_32",
"BriefDescription": "Threshold counter exceeded a value of 32",
"PublicDescription": ""
"BriefDescription": "Threshold counter exceeded a value of 32"
},
{,
"EventCode": "0x200F0",
"EventName": "PM_ST_CMPL",
"BriefDescription": "Stores completed from S2Q (2nd-level store queue).",
"PublicDescription": ""
},
{,
"EventCode": "0x200FE",
"EventName": "PM_DATA_FROM_L2MISS",
"BriefDescription": "Demand LD - L2 Miss (not L2 hit)",
"PublicDescription": ""
"EventCode": "0x4405C",
"EventName": "PM_CMPLU_STALL_VDP",
"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by vector"
},
{,
"EventCode": "0x30010",
"EventName": "PM_PMC2_OVERFLOW",
"BriefDescription": "Overflow from counter 2",
"PublicDescription": ""
"EventCode": "0x4D010",
"EventName": "PM_PMC1_SAVED",
"BriefDescription": "PMC1 Rewind Value saved"
},
{,
"EventCode": "0x3C046",
"EventName": "PM_DATA_FROM_L2.1_SHR",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load",
"PublicDescription": ""
"EventCode": "0x200FE",
"EventName": "PM_DATA_FROM_L2MISS",
"BriefDescription": "Demand LD - L2 Miss (not L2 hit)"
},
{,
"EventCode": "0x34042",
"EventName": "PM_INST_FROM_L3_DISP_CONFLICT",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x2D14A",
"EventName": "PM_MRK_DATA_FROM_RL2L3_MOD_CYC",
"BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load"
},
{,
"EventCode": "0x34046",
"EventName": "PM_INST_FROM_L2.1_SHR",
"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x10028",
"EventName": "PM_STALL_END_ICT_EMPTY",
"BriefDescription": "The number a times the core transitioned from a stall to ICT-empty for this thread"
},
{,
"EventCode": "0x3504A",
"EventName": "PM_IPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request",
"PublicDescription": ""
"EventCode": "0x2504C",
"EventName": "PM_IPTEG_FROM_MEMORY",
"BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request"
},
{,
"EventCode": "0x3E048",
"EventName": "PM_DPTEG_FROM_DL2L3_SHR",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x4504A",
"EventName": "PM_IPTEG_FROM_OFF_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request"
},
{,
"EventCode": "0x3E04C",
"EventName": "PM_DPTEG_FROM_DL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x1404E",
"EventName": "PM_INST_FROM_L2MISS",
"BriefDescription": "The processor's Instruction cache was reloaded from a location other than the local core's L2 due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x3C05A",
"EventName": "PM_CMPLU_STALL_VDPLONG",
"BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle",
"PublicDescription": ""
"EventCode": "0x34042",
"EventName": "PM_INST_FROM_L3_DISP_CONFLICT",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x3C05C",
"EventName": "PM_CMPLU_STALL_VFXU",
"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes",
"PublicDescription": ""
"EventCode": "0x4E048",
"EventName": "PM_DPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x30066",
"EventName": "PM_LSU_FIN",
"BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)",
"PublicDescription": ""
"EventCode": "0x200F0",
"EventName": "PM_ST_CMPL",
"BriefDescription": "Stores completed from S2Q (2nd-level store queue)."
},
{,
"EventCode": "0x300F0",
"EventName": "PM_ST_MISS_L1",
"BriefDescription": "Store Missed L1",
"PublicDescription": ""
"EventCode": "0x4E05C",
"EventName": "PM_LSU_REJECT_LHS",
"BriefDescription": "LSU Reject due to LHS (up to 4 per cycle)"
},
{,
"EventCode": "0x4D010",
"EventName": "PM_PMC1_SAVED",
"BriefDescription": "PMC1 Rewind Value saved",
"PublicDescription": ""
"EventCode": "0x14044",
"EventName": "PM_INST_FROM_L3_NO_CONFLICT",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without conflict due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x40132",
"EventName": "PM_MRK_LSU_FIN",
"BriefDescription": "lsu marked instr PPC finish",
"PublicDescription": ""
"EventCode": "0x3E04C",
"EventName": "PM_DPTEG_FROM_DL4",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
},
{,
"EventCode": "0x4C046",
"EventName": "PM_DATA_FROM_L2.1_MOD",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load",
"PublicDescription": ""
"EventCode": "0x1F15E",
"EventName": "PM_MRK_PROBE_NOP_CMPL",
"BriefDescription": "Marked probeNops completed"
},
{,
"EventCode": "0x44042",
"EventName": "PM_INST_FROM_L3",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 due to an instruction fetch (not prefetch)",
"PublicDescription": ""
"EventCode": "0x20018",
"EventName": "PM_ST_FWD",
"BriefDescription": "Store forwards that finished"
},
{,
"EventCode": "0x4504A",
"EventName": "PM_IPTEG_FROM_OFF_CHIP_CACHE",
"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request",
"PublicDescription": ""
"EventCode": "0x1D142",
"EventName": "PM_MRK_DATA_FROM_L31_ECO_SHR_CYC",
"BriefDescription": "Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load"
},
{,
"EventCode": "0x4E048",
"EventName": "PM_DPTEG_FROM_DL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x24042",
"EventName": "PM_INST_FROM_L3_MEPF",
"BriefDescription": "The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to an instruction fetch (not prefetch)"
},
{,
"EventCode": "0x4E04C",
"EventName": "PM_DPTEG_FROM_DMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
"PublicDescription": ""
"EventCode": "0x25046",
"EventName": "PM_IPTEG_FROM_RL2L3_MOD",
"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
},
{,
"EventCode": "0x4405C",
"EventName": "PM_CMPLU_STALL_VDP",
"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Not qualified multicycle. Qualified by vector",
"PublicDescription": ""
"EventCode": "0x3504A",
"EventName": "PM_IPTEG_FROM_RMEM",
"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request"
},
{,
"EventCode": "0x4D05C",
"EventName": "PM_DP_QP_FLOP_CMPL",
"BriefDescription": "Double-Precion or Quad-Precision instruction completed",
"PublicDescription": ""
"EventCode": "0x3C05A",
"EventName": "PM_CMPLU_STALL_VDPLONG",
"BriefDescription": "Finish stall because the NTF instruction was a scalar multi-cycle instruction issued to the Double Precision execution pipe and waiting to finish. Includes binary floating point instructions in 32 and 64 bit binary floating point format. Qualified by NOT vector AND multicycle"
},
{,
"EventCode": "0x4E05C",
"EventName": "PM_LSU_REJECT_LHS",
"BriefDescription": "LSU Reject due to LHS (up to 4 per cycle)",
"PublicDescription": ""
"EventCode": "0x2E01C",
"EventName": "PM_CMPLU_STALL_TLBIE",
"BriefDescription": "Finish stall because the NTF instruction was a tlbie waiting for response from L2"
}
]
\ No newline at end of file
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