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Commit 3c22ba52 authored by Sukadev Bhattiprolu's avatar Sukadev Bhattiprolu Committed by Arnaldo Carvalho de Melo
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perf vendor events powerpc: Update POWER9 events 

Update and cleanup POWER9 PMU events.
Signed-off-by: default avatarSukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Cc: Anton Blanchard <anton@au1.ibm.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Link: http://lkml.kernel.org/r/20170802174617.GA32545@us.ibm.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 2862a168
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tools/perf/pmu-events/arch/powerpc/power9/floating-point.json
View file @ 3c22ba52
[ [
{,
"EventCode": "0x10058",
"EventName": "PM_MEM_LOC_THRESH_IFU",
"BriefDescription": "Local Memory above threshold for IFU speculation control",
"PublicDescription": ""
},
{,
"EventCode": "0x4505E",
"EventName": "PM_FLOP_CMPL",
"BriefDescription": "Floating Point Operation Finished",
"PublicDescription": ""
},
{, {,
"EventCode": "0x1415A", "EventCode": "0x1415A",
"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC", "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC",
"BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load", "BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x2D028", "EventCode": "0x10058",
"EventName": "PM_RADIX_PWC_L2_PDE_FROM_L2", "EventName": "PM_MEM_LOC_THRESH_IFU",
"BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache", "BriefDescription": "Local Memory above threshold for IFU speculation control"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x2D154", "EventCode": "0x2D028",
"EventName": "PM_MRK_DERAT_MISS_64K", "EventName": "PM_RADIX_PWC_L2_PDE_FROM_L2",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K", "BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x30012", "EventCode": "0x30012",
"EventName": "PM_FLUSH_COMPLETION", "EventName": "PM_FLUSH_COMPLETION",
"BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush", "BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush"
"PublicDescription": "" },
{,
"EventCode": "0x2D154",
"EventName": "PM_MRK_DERAT_MISS_64K",
"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K"
}, },
{, {,
"EventCode": "0x4016E", "EventCode": "0x4016E",
"EventName": "PM_THRESH_NOT_MET", "EventName": "PM_THRESH_NOT_MET",
"BriefDescription": "Threshold counter did not meet threshold", "BriefDescription": "Threshold counter did not meet threshold"
"PublicDescription": ""
} }
] ]
\ No newline at end of file
tools/perf/pmu-events/arch/powerpc/power9/memory.json
View file @ 3c22ba52
[ [
{, {,
"EventCode": "0x10008", "EventCode": "0x3006E",
"EventName": "PM_RUN_SPURR", "EventName": "PM_NEST_REF_CLK",
"BriefDescription": "Run SPURR", "BriefDescription": "Multiply by 4 to obtain the number of PB cycles"
"PublicDescription": ""
},
{,
"EventCode": "0x1000A",
"EventName": "PM_PMC3_REWIND",
"BriefDescription": "PMC3 rewind event. A rewind happens when a speculative event (such as latency or CPI stack) is selected on PMC3 and the stall reason or reload source did not match the one programmed in PMC3. When this occurs, the count in PMC3 will not change.",
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x1C040", "EventCode": "0x20010",
"EventName": "PM_DATA_FROM_L2_NO_CONFLICT", "EventName": "PM_PMC1_OVERFLOW",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load", "BriefDescription": "Overflow from counter 1"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x1C050", "EventCode": "0x2005A",
"EventName": "PM_DATA_CHIP_PUMP_CPRED", "EventName": "PM_DARQ1_7_9_ENTRIES",
"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load", "BriefDescription": "Cycles in which 7 to 9 DARQ1 entries (out of 12) are in use"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x1D15E", "EventCode": "0x3C048",
"EventName": "PM_MRK_RUN_CYC", "EventName": "PM_DATA_FROM_DL2L3_SHR",
"BriefDescription": "Run cycles in which a marked instruction is in the pipeline", "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x15158", "EventCode": "0x10008",
"EventName": "PM_SYNC_MRK_L2HIT", "EventName": "PM_RUN_SPURR",
"BriefDescription": "Marked L2 Hits that can throw a synchronous interrupt", "BriefDescription": "Run SPURR"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x20010", "EventCode": "0x200F6",
"EventName": "PM_PMC1_OVERFLOW", "EventName": "PM_LSU_DERAT_MISS",
"BriefDescription": "Overflow from counter 1", "BriefDescription": "DERAT Reloaded due to a DERAT miss"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x2C040", "EventCode": "0x4C048",
"EventName": "PM_DATA_FROM_L2_MEPF", "EventName": "PM_DATA_FROM_DL2L3_MOD",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load", "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x2005A", "EventCode": "0x1D15E",
"EventName": "PM_DARQ1_7_9_ENTRIES", "EventName": "PM_MRK_RUN_CYC",
"BriefDescription": "Cycles in which 7 to 9 DARQ1 entries (out of 12) are in use", "BriefDescription": "Run cycles in which a marked instruction is in the pipeline"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x2C05C", "EventCode": "0x4003E",
"EventName": "PM_INST_GRP_PUMP_CPRED", "EventName": "PM_LD_CMPL",
"BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only)", "BriefDescription": "count of Loads completed"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x2D156", "EventCode": "0x2D156",
"EventName": "PM_MRK_DTLB_MISS_4K", "EventName": "PM_MRK_DTLB_MISS_4K",
"BriefDescription": "Marked Data TLB Miss page size 4k", "BriefDescription": "Marked Data TLB Miss page size 4k"
"PublicDescription": ""
},
{,
"EventCode": "0x2E05A",
"EventName": "PM_LRQ_REJECT",
"BriefDescription": "Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued. This event counts the number of times the LRQ attempts to relaunch an instruction after a reject. Any load can suffer multiple rejects",
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x2E05C", "EventCode": "0x4C042",
"EventName": "PM_LSU_REJECT_ERAT_MISS", "EventName": "PM_DATA_FROM_L3",
"BriefDescription": "LSU Reject due to ERAT (up to 4 per cycles)", "BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand load"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x200F6", "EventCode": "0x4D02C",
"EventName": "PM_LSU_DERAT_MISS", "EventName": "PM_PMC1_REWIND",
"BriefDescription": "DERAT Reloaded due to a DERAT miss", "BriefDescription": ""
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x3C048", "EventCode": "0x15158",
"EventName": "PM_DATA_FROM_DL2L3_SHR", "EventName": "PM_SYNC_MRK_L2HIT",
"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load", "BriefDescription": "Marked L2 Hits that can throw a synchronous interrupt"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x3404A", "EventCode": "0x3404A",
"EventName": "PM_INST_FROM_RMEM", "EventName": "PM_INST_FROM_RMEM",
"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)", "BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x3C058", "EventCode": "0x301E2",
"EventName": "PM_LARX_FIN", "EventName": "PM_MRK_ST_CMPL",
"BriefDescription": "Larx finished", "BriefDescription": "Marked store completed and sent to nest"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x3E050", "EventCode": "0x1C050",
"EventName": "PM_DARQ1_4_6_ENTRIES", "EventName": "PM_DATA_CHIP_PUMP_CPRED",
"BriefDescription": "Cycles in which 4, 5, or 6 DARQ1 entries (out of 12) are in use", "BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x3006E", "EventCode": "0x4C040",
"EventName": "PM_NEST_REF_CLK", "EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER",
"BriefDescription": "Multiply by 4 to obtain the number of PB cycles", "BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x301E2", "EventCode": "0x2E05C",
"EventName": "PM_MRK_ST_CMPL", "EventName": "PM_LSU_REJECT_ERAT_MISS",
"BriefDescription": "Marked store completed and sent to nest", "BriefDescription": "LSU Reject due to ERAT (up to 4 per cycles)"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x4D02C", "EventCode": "0x1000A",
"EventName": "PM_PMC1_REWIND", "EventName": "PM_PMC3_REWIND",
"BriefDescription": "", "BriefDescription": "PMC3 rewind event. A rewind happens when a speculative event (such as latency or CPI stack) is selected on PMC3 and the stall reason or reload source did not match the one programmed in PMC3. When this occurs, the count in PMC3 will not change."
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x4003E", "EventCode": "0x3C058",
"EventName": "PM_LD_CMPL", "EventName": "PM_LARX_FIN",
"BriefDescription": "count of Loads completed", "BriefDescription": "Larx finished"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x4C040", "EventCode": "0x1C040",
"EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER", "EventName": "PM_DATA_FROM_L2_NO_CONFLICT",
"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load", "BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x4C042", "EventCode": "0x2C040",
"EventName": "PM_DATA_FROM_L3", "EventName": "PM_DATA_FROM_L2_MEPF",
"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand load", "BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load"
"PublicDescription": ""
}, },
{, {,
"EventCode": "0x4C048", "EventCode": "0x2E05A",
"EventName": "PM_DATA_FROM_DL2L3_MOD", "EventName": "PM_LRQ_REJECT",
"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load", "BriefDescription": "Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued. This event counts the number of times the LRQ attempts to relaunch an instruction after a reject. Any load can suffer multiple rejects"
"PublicDescription": "" },
{,
"EventCode": "0x2C05C",
"EventName": "PM_INST_GRP_PUMP_CPRED",
"BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only)"
}, },
{, {,
"EventCode": "0x4D056", "EventCode": "0x4D056",
"EventName": "PM_NON_FMA_FLOP_CMPL", "EventName": "PM_NON_FMA_FLOP_CMPL",
"BriefDescription": "Non FMA instruction completed", "BriefDescription": "Non FMA instruction completed"
"PublicDescription": "" },
{,
"EventCode": "0x3E050",
"EventName": "PM_DARQ1_4_6_ENTRIES",
"BriefDescription": "Cycles in which 4, 5, or 6 DARQ1 entries (out of 12) are in use"
} }
] ]
\ No newline at end of file
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