Skip to content

L
linux
Commit 3c51f78e authored by Jeff Garzik's avatar Jeff Garzik
Browse files
Options

[netdrvr sis190] Lindent sis190. zero code changes.

parent e2e096b5
Show whitespace changes
Inline Side-by-side
Showing with 281 additions and 269 deletions
drivers/net/sis190.c
View file @ 3c51f78e
...@@ -149,36 +149,36 @@ MODULE_DEVICE_TABLE(pci, sis190_pci_tbl); ...@@ -149,36 +149,36 @@ MODULE_DEVICE_TABLE(pci, sis190_pci_tbl);
enum SiS190_registers { enum SiS190_registers {
TxControl=0x0, TxControl = 0x0,
TxDescStartAddr =0x4, TxDescStartAddr = 0x4,
TxNextDescAddr =0x0c, TxNextDescAddr = 0x0c,
RxControl=0x10, RxControl = 0x10,
RxDescStartAddr =0x14, RxDescStartAddr = 0x14,
RxNextDescAddr =0x1c, RxNextDescAddr = 0x1c,
IntrStatus = 0x20, IntrStatus = 0x20,
IntrMask = 0x24, IntrMask = 0x24,
IntrControl = 0x28, IntrControl = 0x28,
IntrTimer = 0x2c, IntrTimer = 0x2c,
PMControl = 0x30, PMControl = 0x30,
ROMControl=0x38, ROMControl = 0x38,
ROMInterface=0x3c, ROMInterface = 0x3c,
StationControl=0x40, StationControl = 0x40,
GMIIControl=0x44, GMIIControl = 0x44,
TxMacControl=0x50, TxMacControl = 0x50,
RxMacControl=0x60, RxMacControl = 0x60,
RxMacAddr=0x62, RxMacAddr = 0x62,
RxHashTable=0x68, RxHashTable = 0x68,
RxWakeOnLan=0x70, RxWakeOnLan = 0x70,
RxMPSControl=0x78, RxMPSControl = 0x78,
}; };
enum sis190_register_content { enum sis190_register_content {
/*InterruptStatusBits */ /*InterruptStatusBits */
SoftInt=0x40000000, SoftInt = 0x40000000,
Timeup=0x20000000, Timeup = 0x20000000,
PauseFrame = 0x80000, PauseFrame = 0x80000,
MagicPacket=0x40000, MagicPacket = 0x40000,
WakeupFrame = 0x20000, WakeupFrame = 0x20000,
LinkChange = 0x10000, LinkChange = 0x10000,
RxQEmpty = 0x80, RxQEmpty = 0x80,
...@@ -188,7 +188,7 @@ enum sis190_register_content { ...@@ -188,7 +188,7 @@ enum sis190_register_content {
TxQ0Empty = 0x08, TxQ0Empty = 0x08,
TxQ0Int = 0x04, TxQ0Int = 0x04,
RxHalt = 0x02, RxHalt = 0x02,
TxHalt=0x01, TxHalt = 0x01,
/*RxStatusDesc */ /*RxStatusDesc */
RxRES = 0x00200000, RxRES = 0x00200000,
...@@ -285,8 +285,8 @@ enum _DescStatusBit { ...@@ -285,8 +285,8 @@ enum _DescStatusBit {
INTbit = 0x40000000, INTbit = 0x40000000,
DEFbit = 0x200000, DEFbit = 0x200000,
CRCbit = 0x20000, CRCbit = 0x20000,
PADbit=0x10000, PADbit = 0x10000,
ENDbit=0x80000000, ENDbit = 0x80000000,
}; };
struct TxDesc { struct TxDesc {
...@@ -338,7 +338,8 @@ static void SiS190_tx_timeout(struct net_device *dev); ...@@ -338,7 +338,8 @@ static void SiS190_tx_timeout(struct net_device *dev);
static struct net_device_stats *SiS190_get_stats(struct net_device *netdev); static struct net_device_stats *SiS190_get_stats(struct net_device *netdev);
static const u32 sis190_intr_mask = static const u32 sis190_intr_mask =
RxQEmpty | RxQInt |TxQ1Empty | TxQ1Int | TxQ0Empty | TxQ0Int |RxHalt | TxHalt; RxQEmpty | RxQInt | TxQ1Empty | TxQ1Int | TxQ0Empty | TxQ0Int | RxHalt |
TxHalt;
void void
smdio_write(void *ioaddr, int RegAddr, int value) smdio_write(void *ioaddr, int RegAddr, int value)
...@@ -348,24 +349,27 @@ smdio_write(void *ioaddr, int RegAddr, int value) ...@@ -348,24 +349,27 @@ smdio_write(void *ioaddr, int RegAddr, int value)
u16 i; u16 i;
u32 pmd; u32 pmd;
pmd=1; pmd = 1;
l=0; l = 0;
l = EhnMIIwrite |(((u32)RegAddr)<<EhnMIIregShift) |EhnMIIreq | (((u32)value)<<EhnMIIdataShift)|(((u32)pmd)<<EhnMIIpmdShift); l = EhnMIIwrite | (((u32) RegAddr) << EhnMIIregShift) | EhnMIIreq |
(((u32) value) << EhnMIIdataShift) | (((u32) pmd) <<
EhnMIIpmdShift);
SiS_W32(GMIIControl, l ); SiS_W32(GMIIControl, l);
udelay(1000); udelay(1000);
for ( i=0; i<1000; i++) { for (i = 0; i < 1000; i++) {
if ( SiS_R32( GMIIControl ) & EhnMIInotDone ) { if (SiS_R32(GMIIControl) & EhnMIInotDone) {
udelay(100); udelay(100);
} else { } else {
break; break;
} }
} }
if(i>999) printk(KERN_ERR PFX "Phy write Error!!!\n"); if (i > 999)
printk(KERN_ERR PFX "Phy write Error!!!\n");
} }
...@@ -377,26 +381,28 @@ smdio_read(void *ioaddr, int RegAddr) ...@@ -377,26 +381,28 @@ smdio_read(void *ioaddr, int RegAddr)
u16 i; u16 i;
u32 pmd; u32 pmd;
pmd=1; pmd = 1;
l=0; l = 0;
l = EhnMIIread |EhnMIIreq | (((u32)RegAddr)<<EhnMIIregShift) |(((u32)pmd)<<EhnMIIpmdShift); l = EhnMIIread | EhnMIIreq | (((u32) RegAddr) << EhnMIIregShift) |
(((u32) pmd) << EhnMIIpmdShift);
SiS_W32(GMIIControl, l ); SiS_W32(GMIIControl, l);
udelay(1000); udelay(1000);
for ( i=0; i<1000; i++) { for (i = 0; i < 1000; i++) {
if ((l == SiS_R32(GMIIControl)) & EhnMIInotDone) { if ((l == SiS_R32(GMIIControl)) & EhnMIInotDone) {
udelay(100); udelay(100);
} else { } else {
break; break;
} }
if(i>999) printk(KERN_ERR PFX "Phy Read Error!!!\n"); if (i > 999)
printk(KERN_ERR PFX "Phy Read Error!!!\n");
} }
l=SiS_R32(GMIIControl); l = SiS_R32(GMIIControl);
return( (u16) ( l>>EhnMIIdataShift ) ); return ((u16) (l >> EhnMIIdataShift));
} }
...@@ -407,8 +413,7 @@ ReadEEprom(void *ioaddr, u32 RegAddr) ...@@ -407,8 +413,7 @@ ReadEEprom(void *ioaddr, u32 RegAddr)
u32 i; u32 i;
u32 ulValue; u32 ulValue;
if(!(SiS_R32(ROMControl)&BIT_1)) if (!(SiS_R32(ROMControl) & BIT_1)) {
{
return 0; return 0;
} }
...@@ -416,16 +421,15 @@ ReadEEprom(void *ioaddr, u32 RegAddr) ...@@ -416,16 +421,15 @@ ReadEEprom(void *ioaddr, u32 RegAddr)
SiS_W32(ROMInterface, ulValue); SiS_W32(ROMInterface, ulValue);
for(i=0 ; i < 200; i++) for (i = 0; i < 200; i++) {
{
if(!(SiS_R32(ROMInterface)& BIT_7)) if (!(SiS_R32(ROMInterface) & BIT_7))
break; break;
udelay(1000); udelay(1000);
} }
data = (u16)((SiS_R32(ROMInterface) & 0xffff0000) >> 16); data = (u16) ((SiS_R32(ROMInterface) & 0xffff0000) >> 16);
return data; return data;
} }
...@@ -496,24 +500,23 @@ SiS190_init_board(struct pci_dev *pdev, struct net_device **dev_out, ...@@ -496,24 +500,23 @@ SiS190_init_board(struct pci_dev *pdev, struct net_device **dev_out,
rc = -EIO; rc = -EIO;
goto err_out_free_res; goto err_out_free_res;
} }
// Soft reset the chip. // Soft reset the chip.
SiS_W32(IntrControl,0x8000); SiS_W32(IntrControl, 0x8000);
udelay(1000); udelay(1000);
SiS_W32(IntrControl,0x0); SiS_W32(IntrControl, 0x0);
SiS_W32(TxControl,0x1a00); SiS_W32(TxControl, 0x1a00);
SiS_W32(RxControl,0x1a00); SiS_W32(RxControl, 0x1a00);
udelay(1000); udelay(1000);
*ioaddr_out = ioaddr; *ioaddr_out = ioaddr;
*dev_out = dev; *dev_out = dev;
return 0; return 0;
err_out_free_res: err_out_free_res:
pci_release_regions(pdev); pci_release_regions(pdev);
err_out: err_out:
pci_disable_device(pdev); pci_disable_device(pdev);
unregister_netdev(dev); unregister_netdev(dev);
kfree(dev); kfree(dev);
...@@ -528,7 +531,7 @@ SiS190_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) ...@@ -528,7 +531,7 @@ SiS190_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
void *ioaddr = NULL; void *ioaddr = NULL;
static int board_idx = -1; static int board_idx = -1;
static int printed_version = 0; static int printed_version = 0;
int i,rc; int i, rc;
u16 reg31; u16 reg31;
assert(pdev != NULL); assert(pdev != NULL);
...@@ -554,21 +557,21 @@ SiS190_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) ...@@ -554,21 +557,21 @@ SiS190_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
// Get MAC address // // Get MAC address //
// Read node address from the EEPROM // Read node address from the EEPROM
if(SiS_R32(ROMControl)&0x2){ if (SiS_R32(ROMControl) & 0x2) {
for (i=0; i< 6; i += 2){ for (i = 0; i < 6; i += 2) {
SiS_W16(RxMacAddr+i,ReadEEprom(ioaddr, 3 + (i/2))); SiS_W16(RxMacAddr + i, ReadEEprom(ioaddr, 3 + (i / 2)));
} }
}else{ } else {
SiS_W32(RxMacAddr,0x11111100); //If 9346 does not exist SiS_W32(RxMacAddr, 0x11111100); //If 9346 does not exist
SiS_W32(RxMacAddr+2,0x00111111); SiS_W32(RxMacAddr + 2, 0x00111111);
} }
for (i = 0; i < MAC_ADDR_LEN; i++) { for (i = 0; i < MAC_ADDR_LEN; i++) {
dev->dev_addr[i] = SiS_R8(RxMacAddr+i); dev->dev_addr[i] = SiS_R8(RxMacAddr + i);
printk("SiS_R8(RxMacAddr+%x)= %x ",i,SiS_R8(RxMacAddr+i)); printk("SiS_R8(RxMacAddr+%x)= %x ", i, SiS_R8(RxMacAddr + i));
} }
dev->open = SiS190_open; dev->open = SiS190_open;
...@@ -616,18 +619,15 @@ SiS190_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) ...@@ -616,18 +619,15 @@ SiS190_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
int val = smdio_read(ioaddr, PHY_AUTO_NEGO_REG); int val = smdio_read(ioaddr, PHY_AUTO_NEGO_REG);
printk(KERN_INFO "%s: Auto-negotiation Enabled.\n", printk(KERN_INFO "%s: Auto-negotiation Enabled.\n", dev->name);
dev->name);
// enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged // enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged
smdio_write(ioaddr, PHY_AUTO_NEGO_REG, smdio_write(ioaddr, PHY_AUTO_NEGO_REG,
PHY_Cap_10_Half | PHY_Cap_10_Full | PHY_Cap_10_Half | PHY_Cap_10_Full |
PHY_Cap_100_Half | PHY_Cap_100_Full | (val & PHY_Cap_100_Half | PHY_Cap_100_Full | (val & 0x1F));
0x1F));
// enable 1000 Full Mode // enable 1000 Full Mode
smdio_write(ioaddr, PHY_1000_CTRL_REG, smdio_write(ioaddr, PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
PHY_Cap_1000_Full);
// Enable auto-negotiation and restart auto-nigotiation // Enable auto-negotiation and restart auto-nigotiation
smdio_write(ioaddr, PHY_CTRL_REG, smdio_write(ioaddr, PHY_CTRL_REG,
...@@ -637,38 +637,44 @@ SiS190_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) ...@@ -637,38 +637,44 @@ SiS190_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
// wait for auto-negotiation process // wait for auto-negotiation process
for (i = 10000; i > 0; i--) { for (i = 10000; i > 0; i--) {
//check if auto-negotiation complete //check if auto-negotiation complete
if (smdio_read(ioaddr, PHY_STAT_REG) & if (smdio_read(ioaddr, PHY_STAT_REG) & PHY_Auto_Neco_Comp) {
PHY_Auto_Neco_Comp) {
udelay(100); udelay(100);
reg31=smdio_read(ioaddr,31); reg31 = smdio_read(ioaddr, 31);
reg31 &= 0x1c; //bit 4:2 reg31 &= 0x1c; //bit 4:2
switch(reg31){ switch (reg31) {
case _1000bpsF: case _1000bpsF:
SiS_W16( 0x40, 0x1c01); SiS_W16(0x40, 0x1c01);
printk("SiS190 Link on 1000 bps Full Duplex mode. \n"); printk
("SiS190 Link on 1000 bps Full Duplex mode. \n");
break; break;
case _1000bpsH: case _1000bpsH:
SiS_W16( 0x40, 0x0c01); SiS_W16(0x40, 0x0c01);
printk("SiS190 Link on 1000 bps Half Duplex mode. \n"); printk
("SiS190 Link on 1000 bps Half Duplex mode. \n");
break; break;
case _100bpsF: case _100bpsF:
SiS_W16( 0x40, 0x1801); SiS_W16(0x40, 0x1801);
printk("SiS190 Link on 100 bps Full Duplex mode. \n"); printk
("SiS190 Link on 100 bps Full Duplex mode. \n");
break; break;
case _100bpsH: case _100bpsH:
SiS_W16( 0x40, 0x0801); SiS_W16(0x40, 0x0801);
printk("SiS190 Link on 100 bps Half Duplex mode. \n"); printk
("SiS190 Link on 100 bps Half Duplex mode. \n");
break; break;
case _10bpsF: case _10bpsF:
SiS_W16( 0x40, 0x1401); SiS_W16(0x40, 0x1401);
printk("SiS190 Link on 10 bps Full Duplex mode. \n"); printk
("SiS190 Link on 10 bps Full Duplex mode. \n");
break; break;
case _10bpsH: case _10bpsH:
SiS_W16( 0x40, 0x0401); SiS_W16(0x40, 0x0401);
printk("SiS190 Link on 10 bps Half Duplex mode. \n"); printk
("SiS190 Link on 10 bps Half Duplex mode. \n");
break; break;
default: default:
printk(KERN_ERR PFX "Error! SiS190 Can not detect mode !!! \n"); printk(KERN_ERR PFX
"Error! SiS190 Can not detect mode !!! \n");
break; break;
} }
...@@ -761,26 +767,26 @@ SiS190_hw_start(struct net_device *dev) ...@@ -761,26 +767,26 @@ SiS190_hw_start(struct net_device *dev)
/* Soft reset the chip. */ /* Soft reset the chip. */
SiS_W32(IntrControl,0x8000); SiS_W32(IntrControl, 0x8000);
udelay(1000); udelay(1000);
SiS_W32(IntrControl,0x0); SiS_W32(IntrControl, 0x0);
SiS_W32( 0x0, 0x01a00); SiS_W32(0x0, 0x01a00);
SiS_W32( 0x4, virt_to_bus(tp->TxDescArray)); SiS_W32(0x4, virt_to_bus(tp->TxDescArray));
SiS_W32( 0x10, 0x1a00); SiS_W32(0x10, 0x1a00);
SiS_W32( 0x14, virt_to_bus(tp->RxDescArray)); SiS_W32(0x14, virt_to_bus(tp->RxDescArray));
SiS_W32( 0x20, 0xffffffff); SiS_W32(0x20, 0xffffffff);
SiS_W32( 0x24, 0x0); SiS_W32(0x24, 0x0);
SiS_W16( 0x40, 0x1901); //default is 100Mbps SiS_W16(0x40, 0x1901); //default is 100Mbps
SiS_W32( 0x44, 0x0); SiS_W32(0x44, 0x0);
SiS_W32( 0x50, 0x60); SiS_W32(0x50, 0x60);
SiS_W16( 0x60, 0x02); SiS_W16(0x60, 0x02);
SiS_W32( 0x68, 0x0); SiS_W32(0x68, 0x0);
SiS_W32( 0x6c, 0x0); SiS_W32(0x6c, 0x0);
SiS_W32( 0x70, 0x0); SiS_W32(0x70, 0x0);
SiS_W32( 0x74, 0x0); SiS_W32(0x74, 0x0);
// Set Rx Config register // Set Rx Config register
...@@ -793,8 +799,8 @@ SiS190_hw_start(struct net_device *dev) ...@@ -793,8 +799,8 @@ SiS190_hw_start(struct net_device *dev)
/* Enable all known interrupts by setting the interrupt mask. */ /* Enable all known interrupts by setting the interrupt mask. */
SiS_W32(IntrMask, sis190_intr_mask); SiS_W32(IntrMask, sis190_intr_mask);
SiS_W32( 0x0, 0x1a01); SiS_W32(0x0, 0x1a01);
SiS_W32( 0x10, 0x1a1d); SiS_W32(0x10, 0x1a1d);
netif_start_queue(dev); netif_start_queue(dev);
...@@ -820,8 +826,7 @@ SiS190_init_ring(struct net_device *dev) ...@@ -820,8 +826,7 @@ SiS190_init_ring(struct net_device *dev)
tp->RxDescArray[i].PSize = 0x0; tp->RxDescArray[i].PSize = 0x0;
if (i == (NUM_RX_DESC - 1)) if (i == (NUM_RX_DESC - 1))
tp->RxDescArray[i].buf_Len = tp->RxDescArray[i].buf_Len = BIT_31 + RX_BUF_SIZE; //bit 31 is End bit
BIT_31 + RX_BUF_SIZE; //bit 31 is End bit
else else
tp->RxDescArray[i].buf_Len = RX_BUF_SIZE; tp->RxDescArray[i].buf_Len = RX_BUF_SIZE;
...@@ -892,17 +897,21 @@ SiS190_start_xmit(struct sk_buff *skb, struct net_device *dev) ...@@ -892,17 +897,21 @@ SiS190_start_xmit(struct sk_buff *skb, struct net_device *dev)
if ((tp->TxDescArray[entry].status & OWNbit) == 0) { if ((tp->TxDescArray[entry].status & OWNbit) == 0) {
tp->Tx_skbuff[entry] = skb; tp->Tx_skbuff[entry] = skb;
tp->TxDescArray[entry].buf_addr = virt_to_bus(skb->data); tp->TxDescArray[entry].buf_addr = virt_to_bus(skb->data);
tp->TxDescArray[entry].PSize = ((skb->len > ETH_ZLEN) ? skb->len : ETH_ZLEN); tp->TxDescArray[entry].PSize =
((skb->len > ETH_ZLEN) ? skb->len : ETH_ZLEN);
if (entry != (NUM_TX_DESC - 1)){ if (entry != (NUM_TX_DESC - 1)) {
tp->TxDescArray[entry].buf_Len = tp->TxDescArray[entry].PSize; tp->TxDescArray[entry].buf_Len =
}else{ tp->TxDescArray[entry].PSize;
tp->TxDescArray[entry].buf_Len = tp->TxDescArray[entry].PSize|ENDbit; } else {
tp->TxDescArray[entry].buf_Len =
tp->TxDescArray[entry].PSize | ENDbit;
} }
tp->TxDescArray[entry].status |= (OWNbit | INTbit | DEFbit |CRCbit |PADbit); tp->TxDescArray[entry].status |=
(OWNbit | INTbit | DEFbit | CRCbit | PADbit);
SiS_W32(TxControl,0x1a11); //Start Send SiS_W32(TxControl, 0x1a11); //Start Send
dev->trans_start = jiffies; dev->trans_start = jiffies;
...@@ -970,7 +979,7 @@ SiS190_rx_interrupt(struct net_device *dev, struct sis190_private *tp, ...@@ -970,7 +979,7 @@ SiS190_rx_interrupt(struct net_device *dev, struct sis190_private *tp,
printk(KERN_INFO "%s: Rx ERROR!!!\n", dev->name); printk(KERN_INFO "%s: Rx ERROR!!!\n", dev->name);
tp->stats.rx_errors++; tp->stats.rx_errors++;
tp->stats.rx_length_errors++; tp->stats.rx_length_errors++;
}else if(!(tp->RxDescArray[cur_rx].PSize & 0x0010000)){ } else if (!(tp->RxDescArray[cur_rx].PSize & 0x0010000)) {
printk(KERN_INFO "%s: Rx ERROR!!!\n", dev->name); printk(KERN_INFO "%s: Rx ERROR!!!\n", dev->name);
tp->stats.rx_errors++; tp->stats.rx_errors++;
tp->stats.rx_crc_errors++; tp->stats.rx_crc_errors++;
...@@ -988,12 +997,14 @@ SiS190_rx_interrupt(struct net_device *dev, struct sis190_private *tp, ...@@ -988,12 +997,14 @@ SiS190_rx_interrupt(struct net_device *dev, struct sis190_private *tp,
skb->protocol = eth_type_trans(skb, dev); skb->protocol = eth_type_trans(skb, dev);
netif_rx(skb); netif_rx(skb);
tp->RxDescArray[cur_rx].PSize =0x0; tp->RxDescArray[cur_rx].PSize = 0x0;
if (cur_rx == (NUM_RX_DESC - 1)) if (cur_rx == (NUM_RX_DESC - 1))
tp->RxDescArray[cur_rx].buf_Len = ENDbit+RX_BUF_SIZE; tp->RxDescArray[cur_rx].buf_Len =
ENDbit + RX_BUF_SIZE;
else else
tp->RxDescArray[cur_rx].buf_Len = RX_BUF_SIZE; tp->RxDescArray[cur_rx].buf_Len =
RX_BUF_SIZE;
tp->RxDescArray[cur_rx].buf_addr = tp->RxDescArray[cur_rx].buf_addr =
virt_to_bus(tp->RxBufferRing[cur_rx]); virt_to_bus(tp->RxBufferRing[cur_rx]);
...@@ -1001,7 +1012,8 @@ SiS190_rx_interrupt(struct net_device *dev, struct sis190_private *tp, ...@@ -1001,7 +1012,8 @@ SiS190_rx_interrupt(struct net_device *dev, struct sis190_private *tp,
tp->stats.rx_bytes += pkt_size; tp->stats.rx_bytes += pkt_size;
tp->stats.rx_packets++; tp->stats.rx_packets++;
tp->RxDescArray[cur_rx].status = OWNbit|INTbit; tp->RxDescArray[cur_rx].status =
OWNbit | INTbit;
} else { } else {
printk(KERN_WARNING printk(KERN_WARNING
"%s: Memory squeeze, deferring packet.\n", "%s: Memory squeeze, deferring packet.\n",
...@@ -1035,10 +1047,9 @@ SiS190_interrupt(int irq, void *dev_instance, struct pt_regs *regs) ...@@ -1035,10 +1047,9 @@ SiS190_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
/* h/w no longer present (hotplug?) or major error, bail */ /* h/w no longer present (hotplug?) or major error, bail */
SiS_W32(IntrStatus,status); SiS_W32(IntrStatus, status);
if ((status & if ((status & (TxQ0Int | RxQInt)) == 0)
(TxQ0Int | RxQInt)) == 0)
break; break;
// Rx interrupt // Rx interrupt
...@@ -1078,8 +1089,8 @@ SiS190_close(struct net_device *dev) ...@@ -1078,8 +1089,8 @@ SiS190_close(struct net_device *dev)
/* Stop the chip's Tx and Rx DMA processes. */ /* Stop the chip's Tx and Rx DMA processes. */
SiS_W32(TxControl,0x1a00); SiS_W32(TxControl, 0x1a00);
SiS_W32(RxControl,0x1a00); SiS_W32(RxControl, 0x1a00);
/* Disable interrupts by clearing the interrupt mask. */ /* Disable interrupts by clearing the interrupt mask. */
SiS_W32(IntrMask, 0x0000); SiS_W32(IntrMask, 0x0000);
...@@ -1136,7 +1147,8 @@ SiS190_set_rx_mode(struct net_device *dev) ...@@ -1136,7 +1147,8 @@ SiS190_set_rx_mode(struct net_device *dev)
mc_filter[1] = mc_filter[0] = 0; mc_filter[1] = mc_filter[0] = 0;
for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
i++, mclist = mclist->next) { i++, mclist = mclist->next) {
int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26; int bit_nr =
ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
rx_mode |= AcceptMulticast; rx_mode |= AcceptMulticast;
} }
...@@ -1147,7 +1159,7 @@ SiS190_set_rx_mode(struct net_device *dev) ...@@ -1147,7 +1159,7 @@ SiS190_set_rx_mode(struct net_device *dev)
tmp = rx_mode | 0x2; tmp = rx_mode | 0x2;
SiS_W16(RxMacControl, tmp); SiS_W16(RxMacControl, tmp);
SiS_W32(RxHashTable , mc_filter[0]); SiS_W32(RxHashTable, mc_filter[0]);
SiS_W32(RxHashTable + 4, mc_filter[1]); SiS_W32(RxHashTable + 4, mc_filter[1]);
spin_unlock_irqrestore(&tp->lock, flags); spin_unlock_irqrestore(&tp->lock, flags);
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7