Commit 3eb12bce authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Linus Walleij

pinctrl: samsung: do not use bindings header with constants

The Samsung SoC pin controller driver uses only three defines from the
bindings header with pin configuration register values, which proves
the point that this header is not a proper bindings-type abstraction
layer with IDs.

Define the needed register values directly in the driver and stop using
the bindings header.
Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarChanho Park <chanho61.park@samsung.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220605160508.134075-8-krzysztof.kozlowski@linaro.org
Link: https://lore.kernel.org/r/20220624081022.32384-1-krzysztof.kozlowski@linaro.orgSigned-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent d1e7bb90
...@@ -27,8 +27,6 @@ ...@@ -27,8 +27,6 @@
#include <linux/soc/samsung/exynos-pmu.h> #include <linux/soc/samsung/exynos-pmu.h>
#include <linux/soc/samsung/exynos-regs-pmu.h> #include <linux/soc/samsung/exynos-regs-pmu.h>
#include <dt-bindings/pinctrl/samsung.h>
#include "pinctrl-samsung.h" #include "pinctrl-samsung.h"
#include "pinctrl-exynos.h" #include "pinctrl-exynos.h"
...@@ -173,7 +171,7 @@ static int exynos_irq_request_resources(struct irq_data *irqd) ...@@ -173,7 +171,7 @@ static int exynos_irq_request_resources(struct irq_data *irqd)
con = readl(bank->pctl_base + reg_con); con = readl(bank->pctl_base + reg_con);
con &= ~(mask << shift); con &= ~(mask << shift);
con |= EXYNOS_PIN_FUNC_EINT << shift; con |= EXYNOS_PIN_CON_FUNC_EINT << shift;
writel(con, bank->pctl_base + reg_con); writel(con, bank->pctl_base + reg_con);
raw_spin_unlock_irqrestore(&bank->slock, flags); raw_spin_unlock_irqrestore(&bank->slock, flags);
...@@ -196,7 +194,7 @@ static void exynos_irq_release_resources(struct irq_data *irqd) ...@@ -196,7 +194,7 @@ static void exynos_irq_release_resources(struct irq_data *irqd)
con = readl(bank->pctl_base + reg_con); con = readl(bank->pctl_base + reg_con);
con &= ~(mask << shift); con &= ~(mask << shift);
con |= EXYNOS_PIN_FUNC_INPUT << shift; con |= PIN_CON_FUNC_INPUT << shift;
writel(con, bank->pctl_base + reg_con); writel(con, bank->pctl_base + reg_con);
raw_spin_unlock_irqrestore(&bank->slock, flags); raw_spin_unlock_irqrestore(&bank->slock, flags);
......
...@@ -16,6 +16,9 @@ ...@@ -16,6 +16,9 @@
#ifndef __PINCTRL_SAMSUNG_EXYNOS_H #ifndef __PINCTRL_SAMSUNG_EXYNOS_H
#define __PINCTRL_SAMSUNG_EXYNOS_H #define __PINCTRL_SAMSUNG_EXYNOS_H
/* Values for the pin CON register */
#define EXYNOS_PIN_CON_FUNC_EINT 0xf
/* External GPIO and wakeup interrupt related definitions */ /* External GPIO and wakeup interrupt related definitions */
#define EXYNOS_GPIO_ECON_OFFSET 0x700 #define EXYNOS_GPIO_ECON_OFFSET 0x700
#define EXYNOS_GPIO_EFLTCON_OFFSET 0x800 #define EXYNOS_GPIO_EFLTCON_OFFSET 0x800
......
...@@ -26,8 +26,6 @@ ...@@ -26,8 +26,6 @@
#include <linux/of_device.h> #include <linux/of_device.h>
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include <dt-bindings/pinctrl/samsung.h>
#include "../core.h" #include "../core.h"
#include "pinctrl-samsung.h" #include "pinctrl-samsung.h"
...@@ -614,7 +612,7 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc, ...@@ -614,7 +612,7 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc,
data = readl(reg); data = readl(reg);
data &= ~(mask << shift); data &= ~(mask << shift);
if (!input) if (!input)
data |= EXYNOS_PIN_FUNC_OUTPUT << shift; data |= PIN_CON_FUNC_OUTPUT << shift;
writel(data, reg); writel(data, reg);
return 0; return 0;
......
...@@ -53,6 +53,14 @@ enum pincfg_type { ...@@ -53,6 +53,14 @@ enum pincfg_type {
#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK) #define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \ #define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
PINCFG_VALUE_SHIFT) PINCFG_VALUE_SHIFT)
/*
* Values for the pin CON register, choosing pin function.
* The basic set (input and output) are same between: S3C24xx, S3C64xx, S5PV210,
* Exynos ARMv7, Exynos ARMv8, Tesla FSD.
*/
#define PIN_CON_FUNC_INPUT 0x0
#define PIN_CON_FUNC_OUTPUT 0x1
/** /**
* enum eint_type - possible external interrupt types. * enum eint_type - possible external interrupt types.
* @EINT_TYPE_NONE: bank does not support external interrupts * @EINT_TYPE_NONE: bank does not support external interrupts
......
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