Commit 3f95ecf2 authored by David E. Box's avatar David E. Box Committed by Hans de Goede

platform/x86/intel: vsec: Explicitly enable capabilities

Discovered Intel VSEC/DVSEC capabilities are enabled by default and only
get disabled by quirk. Instead, remove such quirks and only enable support
for capabilities that have been explicitly added to a new capabilities
field. While here, also reorder the device info structures alphabetically.
Signed-off-by: default avatarDavid E. Box <david.e.box@linux.intel.com>
Reviewed-by: default avatarAndy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20230316224628.2855884-1-david.e.box@linux.intel.comReviewed-by: default avatarHans de Goede <hdegoede@redhat.com>
Signed-off-by: default avatarHans de Goede <hdegoede@redhat.com>
parent d7b2b938
...@@ -67,14 +67,6 @@ enum intel_vsec_id { ...@@ -67,14 +67,6 @@ enum intel_vsec_id {
VSEC_ID_TPMI = 66, VSEC_ID_TPMI = 66,
}; };
static enum intel_vsec_id intel_vsec_allow_list[] = {
VSEC_ID_TELEMETRY,
VSEC_ID_WATCHER,
VSEC_ID_CRASHLOG,
VSEC_ID_SDSI,
VSEC_ID_TPMI,
};
static const char *intel_vsec_name(enum intel_vsec_id id) static const char *intel_vsec_name(enum intel_vsec_id id)
{ {
switch (id) { switch (id) {
...@@ -98,26 +90,19 @@ static const char *intel_vsec_name(enum intel_vsec_id id) ...@@ -98,26 +90,19 @@ static const char *intel_vsec_name(enum intel_vsec_id id)
} }
} }
static bool intel_vsec_allowed(u16 id) static bool intel_vsec_supported(u16 id, unsigned long caps)
{
int i;
for (i = 0; i < ARRAY_SIZE(intel_vsec_allow_list); i++)
if (intel_vsec_allow_list[i] == id)
return true;
return false;
}
static bool intel_vsec_disabled(u16 id, unsigned long quirks)
{ {
switch (id) { switch (id) {
case VSEC_ID_TELEMETRY:
return !!(caps & VSEC_CAP_TELEMETRY);
case VSEC_ID_WATCHER: case VSEC_ID_WATCHER:
return !!(quirks & VSEC_QUIRK_NO_WATCHER); return !!(caps & VSEC_CAP_WATCHER);
case VSEC_ID_CRASHLOG: case VSEC_ID_CRASHLOG:
return !!(quirks & VSEC_QUIRK_NO_CRASHLOG); return !!(caps & VSEC_CAP_CRASHLOG);
case VSEC_ID_SDSI:
return !!(caps & VSEC_CAP_SDSI);
case VSEC_ID_TPMI:
return !!(caps & VSEC_CAP_TPMI);
default: default:
return false; return false;
} }
...@@ -205,7 +190,7 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he ...@@ -205,7 +190,7 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he
unsigned long quirks = info->quirks; unsigned long quirks = info->quirks;
int i; int i;
if (!intel_vsec_allowed(header->id) || intel_vsec_disabled(header->id, quirks)) if (!intel_vsec_supported(header->id, info->caps))
return -EINVAL; return -EINVAL;
if (!header->num_entries) { if (!header->num_entries) {
...@@ -260,14 +245,14 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he ...@@ -260,14 +245,14 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, struct intel_vsec_header *he
static bool intel_vsec_walk_header(struct pci_dev *pdev, static bool intel_vsec_walk_header(struct pci_dev *pdev,
struct intel_vsec_platform_info *info) struct intel_vsec_platform_info *info)
{ {
struct intel_vsec_header **header = info->capabilities; struct intel_vsec_header **header = info->headers;
bool have_devices = false; bool have_devices = false;
int ret; int ret;
for ( ; *header; header++) { for ( ; *header; header++) {
ret = intel_vsec_add_dev(pdev, *header, info); ret = intel_vsec_add_dev(pdev, *header, info);
if (ret) if (ret)
dev_info(&pdev->dev, "Could not add device for DVSEC id %d\n", dev_info(&pdev->dev, "Could not add device for VSEC id %d\n",
(*header)->id); (*header)->id);
else else
have_devices = true; have_devices = true;
...@@ -402,14 +387,8 @@ static int intel_vsec_pci_probe(struct pci_dev *pdev, const struct pci_device_id ...@@ -402,14 +387,8 @@ static int intel_vsec_pci_probe(struct pci_dev *pdev, const struct pci_device_id
return 0; return 0;
} }
/* TGL info */
static const struct intel_vsec_platform_info tgl_info = {
.quirks = VSEC_QUIRK_NO_WATCHER | VSEC_QUIRK_NO_CRASHLOG |
VSEC_QUIRK_TABLE_SHIFT | VSEC_QUIRK_EARLY_HW,
};
/* DG1 info */ /* DG1 info */
static struct intel_vsec_header dg1_telemetry = { static struct intel_vsec_header dg1_header = {
.length = 0x10, .length = 0x10,
.id = 2, .id = 2,
.num_entries = 1, .num_entries = 1,
...@@ -418,19 +397,31 @@ static struct intel_vsec_header dg1_telemetry = { ...@@ -418,19 +397,31 @@ static struct intel_vsec_header dg1_telemetry = {
.offset = 0x466000, .offset = 0x466000,
}; };
static struct intel_vsec_header *dg1_capabilities[] = { static struct intel_vsec_header *dg1_headers[] = {
&dg1_telemetry, &dg1_header,
NULL NULL
}; };
static const struct intel_vsec_platform_info dg1_info = { static const struct intel_vsec_platform_info dg1_info = {
.capabilities = dg1_capabilities, .caps = VSEC_CAP_TELEMETRY,
.headers = dg1_headers,
.quirks = VSEC_QUIRK_NO_DVSEC | VSEC_QUIRK_EARLY_HW, .quirks = VSEC_QUIRK_NO_DVSEC | VSEC_QUIRK_EARLY_HW,
}; };
/* MTL info */ /* MTL info */
static const struct intel_vsec_platform_info mtl_info = { static const struct intel_vsec_platform_info mtl_info = {
.quirks = VSEC_QUIRK_NO_WATCHER | VSEC_QUIRK_NO_CRASHLOG, .caps = VSEC_CAP_TELEMETRY,
};
/* OOBMSM info */
static const struct intel_vsec_platform_info oobmsm_info = {
.caps = VSEC_CAP_TELEMETRY | VSEC_CAP_SDSI | VSEC_CAP_TPMI,
};
/* TGL info */
static const struct intel_vsec_platform_info tgl_info = {
.caps = VSEC_CAP_TELEMETRY,
.quirks = VSEC_QUIRK_TABLE_SHIFT | VSEC_QUIRK_EARLY_HW,
}; };
#define PCI_DEVICE_ID_INTEL_VSEC_ADL 0x467d #define PCI_DEVICE_ID_INTEL_VSEC_ADL 0x467d
...@@ -445,7 +436,7 @@ static const struct pci_device_id intel_vsec_pci_ids[] = { ...@@ -445,7 +436,7 @@ static const struct pci_device_id intel_vsec_pci_ids[] = {
{ PCI_DEVICE_DATA(INTEL, VSEC_DG1, &dg1_info) }, { PCI_DEVICE_DATA(INTEL, VSEC_DG1, &dg1_info) },
{ PCI_DEVICE_DATA(INTEL, VSEC_MTL_M, &mtl_info) }, { PCI_DEVICE_DATA(INTEL, VSEC_MTL_M, &mtl_info) },
{ PCI_DEVICE_DATA(INTEL, VSEC_MTL_S, &mtl_info) }, { PCI_DEVICE_DATA(INTEL, VSEC_MTL_S, &mtl_info) },
{ PCI_DEVICE_DATA(INTEL, VSEC_OOBMSM, &(struct intel_vsec_platform_info) {}) }, { PCI_DEVICE_DATA(INTEL, VSEC_OOBMSM, &oobmsm_info) },
{ PCI_DEVICE_DATA(INTEL, VSEC_RPL, &tgl_info) }, { PCI_DEVICE_DATA(INTEL, VSEC_RPL, &tgl_info) },
{ PCI_DEVICE_DATA(INTEL, VSEC_TGL, &tgl_info) }, { PCI_DEVICE_DATA(INTEL, VSEC_TGL, &tgl_info) },
{ } { }
......
...@@ -5,6 +5,12 @@ ...@@ -5,6 +5,12 @@
#include <linux/auxiliary_bus.h> #include <linux/auxiliary_bus.h>
#include <linux/bits.h> #include <linux/bits.h>
#define VSEC_CAP_TELEMETRY BIT(0)
#define VSEC_CAP_WATCHER BIT(1)
#define VSEC_CAP_CRASHLOG BIT(2)
#define VSEC_CAP_SDSI BIT(3)
#define VSEC_CAP_TPMI BIT(4)
struct pci_dev; struct pci_dev;
struct resource; struct resource;
...@@ -27,7 +33,8 @@ enum intel_vsec_quirks { ...@@ -27,7 +33,8 @@ enum intel_vsec_quirks {
/* Platform specific data */ /* Platform specific data */
struct intel_vsec_platform_info { struct intel_vsec_platform_info {
struct intel_vsec_header **capabilities; struct intel_vsec_header **headers;
unsigned long caps;
unsigned long quirks; unsigned long quirks;
}; };
......
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