Commit 40baba56 authored by Jonatas Esteves's avatar Jonatas Esteves Committed by Alex Deucher

drm/amd/pm: Fix output of pp_od_clk_voltage

Printing the other clock types should not be conditioned on being able
to print OD_SCLK. Some GPUs currently have limited capability of only
printing a subset of these.

Since this condition was introduced in v5.18-rc1, reading from
`pp_od_clk_voltage` has been returning empty on the Asus ROG Strix G15
(2021).

Fixes: 79c65f3f ("drm/amd/pm: do not expose power implementation details to amdgpu_pm.c")
Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarJonatas Esteves <jntesteves@gmail.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 0d2dd02d
...@@ -871,14 +871,12 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, ...@@ -871,14 +871,12 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
} }
if (ret == -ENOENT) { if (ret == -ENOENT) {
size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf); size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
if (size > 0) {
size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size); size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size);
size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size); size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size);
size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size); size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size);
size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size); size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size);
size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size); size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size);
} }
}
if (size == 0) if (size == 0)
size = sysfs_emit(buf, "\n"); size = sysfs_emit(buf, "\n");
......
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