Commit 41797f75 authored by Phil Edworthy's avatar Phil Edworthy Committed by Paul Mundt

sh: Add pinmux for sh7264

Signed-off-by: default avatarPhil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent d584e204
......@@ -15,6 +15,7 @@ config SH_RSK7203
config SH_RSK7264
bool "RSK2+SH7264"
select ARCH_REQUIRE_GPIOLIB
depends on CPU_SUBTYPE_SH7264
endchoice
......
#ifndef __ASM_SH7264_H__
#define __ASM_SH7264_H__
enum {
/* Port A */
GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,
/* Port B */
GPIO_PB22, GPIO_PB21, GPIO_PB20,
GPIO_PB19, GPIO_PB18, GPIO_PB17, GPIO_PB16,
GPIO_PB15, GPIO_PB14, GPIO_PB13, GPIO_PB12,
GPIO_PB11, GPIO_PB10, GPIO_PB9, GPIO_PB8,
GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
GPIO_PB3, GPIO_PB2, GPIO_PB1,
/* Port C */
GPIO_PC10, GPIO_PC9, GPIO_PC8,
GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
/* Port D */
GPIO_PD15, GPIO_PD14, GPIO_PD13, GPIO_PD12,
GPIO_PD11, GPIO_PD10, GPIO_PD9, GPIO_PD8,
GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
/* Port E */
GPIO_PE5, GPIO_PE4,
GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0,
/* Port F */
GPIO_PF12,
GPIO_PF11, GPIO_PF10, GPIO_PF9, GPIO_PF8,
GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
/* Port G */
GPIO_PG24,
GPIO_PG23, GPIO_PG22, GPIO_PG21, GPIO_PG20,
GPIO_PG19, GPIO_PG18, GPIO_PG17, GPIO_PG16,
GPIO_PG15, GPIO_PG14, GPIO_PG13, GPIO_PG12,
GPIO_PG11, GPIO_PG10, GPIO_PG9, GPIO_PG8,
GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
/* Port H */
GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
/* Port I - not on device */
/* Port J */
GPIO_PJ11, GPIO_PJ10, GPIO_PJ9, GPIO_PJ8,
GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0,
/* Port K */
GPIO_PK11, GPIO_PK10, GPIO_PK9, GPIO_PK8,
GPIO_PK7, GPIO_PK6, GPIO_PK5, GPIO_PK4,
GPIO_PK3, GPIO_PK2, GPIO_PK1, GPIO_PK0,
/* INTC: IRQ and PINT on PB/PD/PE */
GPIO_FN_PINT7_PG, GPIO_FN_PINT6_PG, GPIO_FN_PINT5_PG, GPIO_FN_PINT4_PG,
GPIO_FN_PINT3_PG, GPIO_FN_PINT2_PG, GPIO_FN_PINT1_PG,
GPIO_FN_IRQ7_PC, GPIO_FN_IRQ6_PC, GPIO_FN_IRQ5_PC, GPIO_FN_IRQ4_PC,
GPIO_FN_IRQ3_PG, GPIO_FN_IRQ2_PG, GPIO_FN_IRQ1_PJ, GPIO_FN_IRQ0_PJ,
GPIO_FN_IRQ3_PE, GPIO_FN_IRQ2_PE, GPIO_FN_IRQ1_PE, GPIO_FN_IRQ0_PE,
/* WDT */
GPIO_FN_WDTOVF,
/* CAN */
GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1,
GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1,
/* DMAC */
GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0,
GPIO_FN_TEND1, GPIO_FN_DACK1, GPIO_FN_DREQ1,
/* ADC */
GPIO_FN_ADTRG,
/* BSC */
GPIO_FN_A25, GPIO_FN_A24,
GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20,
GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16,
GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12,
GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8,
GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4,
GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0,
GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8,
GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4,
GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0,
GPIO_FN_BS,
GPIO_FN_CS4, GPIO_FN_CS3, GPIO_FN_CS2, GPIO_FN_CS1, GPIO_FN_CS0,
GPIO_FN_CS6CE1B, GPIO_FN_CS5CE1A,
GPIO_FN_CE2A, GPIO_FN_CE2B,
GPIO_FN_RD, GPIO_FN_RDWR,
GPIO_FN_ICIOWRAH, GPIO_FN_ICIORD,
GPIO_FN_WE1DQMUWE, GPIO_FN_WE0DQML,
GPIO_FN_RAS, GPIO_FN_CAS, GPIO_FN_CKE,
GPIO_FN_WAIT, GPIO_FN_BREQ, GPIO_FN_BACK,
GPIO_FN_IOIS16,
/* TMU */
GPIO_FN_TIOC4D, GPIO_FN_TIOC4C, GPIO_FN_TIOC4B, GPIO_FN_TIOC4A,
GPIO_FN_TIOC3D, GPIO_FN_TIOC3C, GPIO_FN_TIOC3B, GPIO_FN_TIOC3A,
GPIO_FN_TIOC2B, GPIO_FN_TIOC1B, GPIO_FN_TIOC2A, GPIO_FN_TIOC1A,
GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A,
GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA,
/* SSU */
GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD,
GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF,
GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD,
GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF,
/* SCIF */
GPIO_FN_SCK0, GPIO_FN_SCK1, GPIO_FN_SCK2, GPIO_FN_SCK3,
GPIO_FN_RXD0, GPIO_FN_RXD1, GPIO_FN_RXD2, GPIO_FN_RXD3,
GPIO_FN_TXD0, GPIO_FN_TXD1, GPIO_FN_TXD2, GPIO_FN_TXD3,
GPIO_FN_RXD4, GPIO_FN_RXD5, GPIO_FN_RXD6, GPIO_FN_RXD7,
GPIO_FN_TXD4, GPIO_FN_TXD5, GPIO_FN_TXD6, GPIO_FN_TXD7,
GPIO_FN_RTS1, GPIO_FN_RTS3, GPIO_FN_CTS1, GPIO_FN_CTS3,
/* RSPI */
GPIO_FN_RSPCK0, GPIO_FN_MOSI0,
GPIO_FN_MISO0_PF12, GPIO_FN_MISO1,
GPIO_FN_SSL00,
GPIO_FN_RSPCK1, GPIO_FN_MOSI1,
GPIO_FN_MISO1_PG19, GPIO_FN_SSL10,
/* IIC3 */
GPIO_FN_SCL0, GPIO_FN_SCL1, GPIO_FN_SCL2,
GPIO_FN_SDA2, GPIO_FN_SDA1, GPIO_FN_SDA0,
/* SSI */
GPIO_FN_SSISCK0, GPIO_FN_SSIWS0, GPIO_FN_SSITXD0, GPIO_FN_SSIRXD0,
GPIO_FN_SSIWS1, GPIO_FN_SSIWS2, GPIO_FN_SSIWS3,
GPIO_FN_SSISCK1, GPIO_FN_SSISCK2, GPIO_FN_SSISCK3,
GPIO_FN_SSIDATA1, GPIO_FN_SSIDATA2, GPIO_FN_SSIDATA3,
GPIO_FN_AUDIO_CLK,
/* SIOF */
GPIO_FN_SIOFTXD, GPIO_FN_SIOFRXD, GPIO_FN_SIOFSYNC, GPIO_FN_SIOFSCK,
/* SPDIF */
GPIO_FN_SPDIF_IN,
GPIO_FN_SPDIF_OUT,
/* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
GPIO_FN_FCE,
GPIO_FN_FRB,
/* VDC3 */
GPIO_FN_DV_CLK, GPIO_FN_DV_VSYNC, GPIO_FN_DV_HSYNC,
GPIO_FN_DV_DATA7, GPIO_FN_DV_DATA6, GPIO_FN_DV_DATA5, GPIO_FN_DV_DATA4,
GPIO_FN_DV_DATA3, GPIO_FN_DV_DATA2, GPIO_FN_DV_DATA1, GPIO_FN_DV_DATA0,
GPIO_FN_LCD_CLK, GPIO_FN_LCD_EXTCLK,
GPIO_FN_LCD_VSYNC, GPIO_FN_LCD_HSYNC, GPIO_FN_LCD_DE,
GPIO_FN_LCD_DATA15, GPIO_FN_LCD_DATA14,
GPIO_FN_LCD_DATA13, GPIO_FN_LCD_DATA12,
GPIO_FN_LCD_DATA11, GPIO_FN_LCD_DATA10,
GPIO_FN_LCD_DATA9, GPIO_FN_LCD_DATA8,
GPIO_FN_LCD_DATA7, GPIO_FN_LCD_DATA6,
GPIO_FN_LCD_DATA5, GPIO_FN_LCD_DATA4,
GPIO_FN_LCD_DATA3, GPIO_FN_LCD_DATA2,
GPIO_FN_LCD_DATA1, GPIO_FN_LCD_DATA0,
GPIO_FN_LCD_M_DISP,
};
#endif /* __ASM_SH7264_H__ */
......@@ -17,5 +17,6 @@ obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o
# Pinmux setup
pinmux-$(CONFIG_CPU_SUBTYPE_SH7203) := pinmux-sh7203.o
pinmux-$(CONFIG_CPU_SUBTYPE_SH7264) := pinmux-sh7264.o
obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y)
/*
* SH7264 Pinmux
*
* Copyright (C) 2012 Renesas Electronics Europe Ltd
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <cpu/sh7264.h>
enum {
PINMUX_RESERVED = 0,
PINMUX_DATA_BEGIN,
/* Port A */
PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
/* Port B */
PB22_DATA, PB21_DATA, PB20_DATA,
PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA,
PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA,
PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
PB3_DATA, PB2_DATA, PB1_DATA,
/* Port C */
PC10_DATA, PC9_DATA, PC8_DATA,
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
/* Port D */
PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
/* Port E */
PE5_DATA, PE4_DATA,
PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
/* Port F */
PF12_DATA,
PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
/* Port G */
PG24_DATA,
PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA,
PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA,
PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA,
PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA,
PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
/* Port H */
/* NOTE - Port H does not have a Data Register, but PH Data is
connected to PH Port Register */
PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
/* Port I - not on device */
/* Port J */
PJ12_DATA,
PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA,
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA,
/* Port K */
PK12_DATA,
PK11_DATA, PK10_DATA, PK9_DATA, PK8_DATA,
PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA,
PINMUX_DATA_END,
PINMUX_INPUT_BEGIN,
FORCE_IN,
/* Port A */
PA3_IN, PA2_IN, PA1_IN, PA0_IN,
/* Port B */
PB22_IN, PB21_IN, PB20_IN,
PB19_IN, PB18_IN, PB17_IN, PB16_IN,
PB15_IN, PB14_IN, PB13_IN, PB12_IN,
PB11_IN, PB10_IN, PB9_IN, PB8_IN,
PB7_IN, PB6_IN, PB5_IN, PB4_IN,
PB3_IN, PB2_IN, PB1_IN,
/* Port C */
PC10_IN, PC9_IN, PC8_IN,
PC7_IN, PC6_IN, PC5_IN, PC4_IN,
PC3_IN, PC2_IN, PC1_IN, PC0_IN,
/* Port D */
PD15_IN, PD14_IN, PD13_IN, PD12_IN,
PD11_IN, PD10_IN, PD9_IN, PD8_IN,
PD7_IN, PD6_IN, PD5_IN, PD4_IN,
PD3_IN, PD2_IN, PD1_IN, PD0_IN,
/* Port E */
PE5_IN, PE4_IN,
PE3_IN, PE2_IN, PE1_IN, PE0_IN,
/* Port F */
PF12_IN,
PF11_IN, PF10_IN, PF9_IN, PF8_IN,
PF7_IN, PF6_IN, PF5_IN, PF4_IN,
PF3_IN, PF2_IN, PF1_IN, PF0_IN,
/* Port G */
PG24_IN,
PG23_IN, PG22_IN, PG21_IN, PG20_IN,
PG19_IN, PG18_IN, PG17_IN, PG16_IN,
PG15_IN, PG14_IN, PG13_IN, PG12_IN,
PG11_IN, PG10_IN, PG9_IN, PG8_IN,
PG7_IN, PG6_IN, PG5_IN, PG4_IN,
PG3_IN, PG2_IN, PG1_IN, PG0_IN,
/* Port H - Port H does not have a Data Register */
/* Port I - not on device */
/* Port J */
PJ12_IN,
PJ11_IN, PJ10_IN, PJ9_IN, PJ8_IN,
PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
PJ3_IN, PJ2_IN, PJ1_IN, PJ0_IN,
/* Port K */
PK12_IN,
PK11_IN, PK10_IN, PK9_IN, PK8_IN,
PK7_IN, PK6_IN, PK5_IN, PK4_IN,
PK3_IN, PK2_IN, PK1_IN, PK0_IN,
PINMUX_INPUT_END,
PINMUX_OUTPUT_BEGIN,
FORCE_OUT,
/* Port A */
PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
/* Port B */
PB22_OUT, PB21_OUT, PB20_OUT,
PB19_OUT, PB18_OUT, PB17_OUT, PB16_OUT,
PB15_OUT, PB14_OUT, PB13_OUT, PB12_OUT,
PB11_OUT, PB10_OUT, PB9_OUT, PB8_OUT,
PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
PB3_OUT, PB2_OUT, PB1_OUT,
/* Port C */
PC10_OUT, PC9_OUT, PC8_OUT,
PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
/* Port D */
PD15_OUT, PD14_OUT, PD13_OUT, PD12_OUT,
PD11_OUT, PD10_OUT, PD9_OUT, PD8_OUT,
PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
/* Port E */
PE5_OUT, PE4_OUT,
PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
/* Port F */
PF12_OUT,
PF11_OUT, PF10_OUT, PF9_OUT, PF8_OUT,
PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
/* Port G */
PG24_OUT,
PG23_OUT, PG22_OUT, PG21_OUT, PG20_OUT,
PG19_OUT, PG18_OUT, PG17_OUT, PG16_OUT,
PG15_OUT, PG14_OUT, PG13_OUT, PG12_OUT,
PG11_OUT, PG10_OUT, PG9_OUT, PG8_OUT,
PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT,
PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT,
/* Port H - Port H does not have a Data Register */
/* Port I - not on device */
/* Port J */
PJ12_OUT,
PJ11_OUT, PJ10_OUT, PJ9_OUT, PJ8_OUT,
PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
PJ3_OUT, PJ2_OUT, PJ1_OUT, PJ0_OUT,
/* Port K */
PK12_OUT,
PK11_OUT, PK10_OUT, PK9_OUT, PK8_OUT,
PK7_OUT, PK6_OUT, PK5_OUT, PK4_OUT,
PK3_OUT, PK2_OUT, PK1_OUT, PK0_OUT,
PINMUX_OUTPUT_END,
PINMUX_FUNCTION_BEGIN,
/* Port A */
PA3_IOR_IN, PA3_IOR_OUT,
PA2_IOR_IN, PA2_IOR_OUT,
PA1_IOR_IN, PA1_IOR_OUT,
PA0_IOR_IN, PA0_IOR_OUT,
/* Port B */
PB11_IOR_IN, PB11_IOR_OUT,
PB10_IOR_IN, PB10_IOR_OUT,
PB9_IOR_IN, PB9_IOR_OUT,
PB8_IOR_IN, PB8_IOR_OUT,
PB22MD_00, PB22MD_01, PB22MD_10,
PB21MD_0, PB21MD_1,
PB20MD_0, PB20MD_1,
PB19MD_00, PB19MD_01, PB19MD_10, PB19MD_11,
PB18MD_00, PB18MD_01, PB18MD_10, PB18MD_11,
PB17MD_00, PB17MD_01, PB17MD_10, PB17MD_11,
PB16MD_00, PB16MD_01, PB16MD_10, PB16MD_11,
PB15MD_00, PB15MD_01, PB15MD_10, PB15MD_11,
PB14MD_00, PB14MD_01, PB14MD_10, PB14MD_11,
PB13MD_00, PB13MD_01, PB13MD_10, PB13MD_11,
PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11,
PB11MD_00, PB11MD_01, PB11MD_10, PB11MD_11,
PB10MD_00, PB10MD_01, PB10MD_10, PB10MD_11,
PB9MD_00, PB9MD_01, PB9MD_10, PB9MD_11,
PB8MD_00, PB8MD_01, PB8MD_10, PB8MD_11,
PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11,
PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11,
PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11,
PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11,
PB3MD_0, PB3MD_1,
PB2MD_0, PB2MD_1,
PB1MD_0, PB1MD_1,
/* Port C */
PC14_IOR_IN, PC14_IOR_OUT,
PC13_IOR_IN, PC13_IOR_OUT,
PC12_IOR_IN, PC12_IOR_OUT,
PC11_IOR_IN, PC11_IOR_OUT,
PC10_IOR_IN, PC10_IOR_OUT,
PC9_IOR_IN, PC9_IOR_OUT,
PC8_IOR_IN, PC8_IOR_OUT,
PC7_IOR_IN, PC7_IOR_OUT,
PC6_IOR_IN, PC6_IOR_OUT,
PC5_IOR_IN, PC5_IOR_OUT,
PC4_IOR_IN, PC4_IOR_OUT,
PC3_IOR_IN, PC3_IOR_OUT,
PC2_IOR_IN, PC2_IOR_OUT,
PC1_IOR_IN, PC1_IOR_OUT,
PC0_IOR_IN, PC0_IOR_OUT,
PC10MD_0, PC10MD_1,
PC9MD_0, PC9MD_1,
PC8MD_00, PC8MD_01, PC8MD_10, PC8MD_11,
PC7MD_00, PC7MD_01, PC7MD_10, PC7MD_11,
PC6MD_00, PC6MD_01, PC6MD_10, PC6MD_11,
PC5MD_00, PC5MD_01, PC5MD_10, PC5MD_11,
PC4MD_0, PC4MD_1,
PC3MD_0, PC3MD_1,
PC2MD_0, PC2MD_1,
PC1MD_0, PC1MD_1,
PC0MD_0, PC0MD_1,
/* Port D */
PD15_IOR_IN, PD15_IOR_OUT,
PD14_IOR_IN, PD14_IOR_OUT,
PD13_IOR_IN, PD13_IOR_OUT,
PD12_IOR_IN, PD12_IOR_OUT,
PD11_IOR_IN, PD11_IOR_OUT,
PD10_IOR_IN, PD10_IOR_OUT,
PD9_IOR_IN, PD9_IOR_OUT,
PD8_IOR_IN, PD8_IOR_OUT,
PD7_IOR_IN, PD7_IOR_OUT,
PD6_IOR_IN, PD6_IOR_OUT,
PD5_IOR_IN, PD5_IOR_OUT,
PD4_IOR_IN, PD4_IOR_OUT,
PD3_IOR_IN, PD3_IOR_OUT,
PD2_IOR_IN, PD2_IOR_OUT,
PD1_IOR_IN, PD1_IOR_OUT,
PD0_IOR_IN, PD0_IOR_OUT,
PD15MD_00, PD15MD_01, PD15MD_10, PD15MD_11,
PD14MD_00, PD14MD_01, PD14MD_10, PD14MD_11,
PD13MD_00, PD13MD_01, PD13MD_10, PD13MD_11,
PD12MD_00, PD12MD_01, PD12MD_10, PD12MD_11,
PD11MD_00, PD11MD_01, PD11MD_10, PD11MD_11,
PD10MD_00, PD10MD_01, PD10MD_10, PD10MD_11,
PD9MD_00, PD9MD_01, PD9MD_10, PD9MD_11,
PD8MD_00, PD8MD_01, PD8MD_10, PD8MD_11,
PD7MD_00, PD7MD_01, PD7MD_10, PD7MD_11,
PD6MD_00, PD6MD_01, PD6MD_10, PD6MD_11,
PD5MD_00, PD5MD_01, PD5MD_10, PD5MD_11,
PD4MD_00, PD4MD_01, PD4MD_10, PD4MD_11,
PD3MD_00, PD3MD_01, PD3MD_10, PD3MD_11,
PD2MD_00, PD2MD_01, PD2MD_10, PD2MD_11,
PD1MD_00, PD1MD_01, PD1MD_10, PD1MD_11,
PD0MD_00, PD0MD_01, PD0MD_10, PD0MD_11,
/* Port E */
PE5_IOR_IN, PE5_IOR_OUT,
PE4_IOR_IN, PE4_IOR_OUT,
PE3_IOR_IN, PE3_IOR_OUT,
PE2_IOR_IN, PE2_IOR_OUT,
PE1_IOR_IN, PE1_IOR_OUT,
PE0_IOR_IN, PE0_IOR_OUT,
PE5MD_00, PE5MD_01, PE5MD_10, PE5MD_11,
PE4MD_00, PE4MD_01, PE4MD_10, PE4MD_11,
PE3MD_00, PE3MD_01, PE3MD_10, PE3MD_11,
PE2MD_00, PE2MD_01, PE2MD_10, PE2MD_11,
PE1MD_000, PE1MD_001, PE1MD_010, PE1MD_011,
PE1MD_100, PE1MD_101, PE1MD_110, PE1MD_111,
PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11,
/* Port F */
PF12_IOR_IN, PF12_IOR_OUT,
PF11_IOR_IN, PF11_IOR_OUT,
PF10_IOR_IN, PF10_IOR_OUT,
PF9_IOR_IN, PF9_IOR_OUT,
PF8_IOR_IN, PF8_IOR_OUT,
PF7_IOR_IN, PF7_IOR_OUT,
PF6_IOR_IN, PF6_IOR_OUT,
PF5_IOR_IN, PF5_IOR_OUT,
PF4_IOR_IN, PF4_IOR_OUT,
PF3_IOR_IN, PF3_IOR_OUT,
PF2_IOR_IN, PF2_IOR_OUT,
PF1_IOR_IN, PF1_IOR_OUT,
PF0_IOR_IN, PF0_IOR_OUT,
PF12MD_000, PF12MD_001, PF12MD_010, PF12MD_011,
PF12MD_100, PF12MD_101, PF12MD_110, PF12MD_111,
PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011,
PF11MD_100, PF11MD_101, PF11MD_110, PF11MD_111,
PF10MD_000, PF10MD_001, PF10MD_010, PF10MD_011,
PF10MD_100, PF10MD_101, PF10MD_110, PF10MD_111,
PF9MD_000, PF9MD_001, PF9MD_010, PF9MD_011,
PF9MD_100, PF9MD_101, PF9MD_110, PF9MD_111,
PF8MD_00, PF8MD_01, PF8MD_10, PF8MD_11,
PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011,
PF7MD_100, PF7MD_101, PF7MD_110, PF7MD_111,
PF6MD_000, PF6MD_001, PF6MD_010, PF6MD_011,
PF6MD_100, PF6MD_101, PF6MD_110, PF6MD_111,
PF5MD_000, PF5MD_001, PF5MD_010, PF5MD_011,
PF5MD_100, PF5MD_101, PF5MD_110, PF5MD_111,
PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011,
PF4MD_100, PF4MD_101, PF4MD_110, PF4MD_111,
PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011,
PF3MD_100, PF3MD_101, PF3MD_110, PF3MD_111,
PF2MD_000, PF2MD_001, PF2MD_010, PF2MD_011,
PF2MD_100, PF2MD_101, PF2MD_110, PF2MD_111,
PF1MD_000, PF1MD_001, PF1MD_010, PF1MD_011,
PF1MD_100, PF1MD_101, PF1MD_110, PF1MD_111,
PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011,
PF0MD_100, PF0MD_101, PF0MD_110, PF0MD_111,
/* Port G */
PG24_IOR_IN, PG24_IOR_OUT,
PG23_IOR_IN, PG23_IOR_OUT,
PG22_IOR_IN, PG22_IOR_OUT,
PG21_IOR_IN, PG21_IOR_OUT,
PG20_IOR_IN, PG20_IOR_OUT,
PG19_IOR_IN, PG19_IOR_OUT,
PG18_IOR_IN, PG18_IOR_OUT,
PG17_IOR_IN, PG17_IOR_OUT,
PG16_IOR_IN, PG16_IOR_OUT,
PG15_IOR_IN, PG15_IOR_OUT,
PG14_IOR_IN, PG14_IOR_OUT,
PG13_IOR_IN, PG13_IOR_OUT,
PG12_IOR_IN, PG12_IOR_OUT,
PG11_IOR_IN, PG11_IOR_OUT,
PG10_IOR_IN, PG10_IOR_OUT,
PG9_IOR_IN, PG9_IOR_OUT,
PG8_IOR_IN, PG8_IOR_OUT,
PG7_IOR_IN, PG7_IOR_OUT,
PG6_IOR_IN, PG6_IOR_OUT,
PG5_IOR_IN, PG5_IOR_OUT,
PG4_IOR_IN, PG4_IOR_OUT,
PG3_IOR_IN, PG3_IOR_OUT,
PG2_IOR_IN, PG2_IOR_OUT,
PG1_IOR_IN, PG1_IOR_OUT,
PG0_IOR_IN, PG0_IOR_OUT,
PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11,
PG23MD_00, PG23MD_01, PG23MD_10, PG23MD_11,
PG22MD_00, PG22MD_01, PG22MD_10, PG22MD_11,
PG21MD_00, PG21MD_01, PG21MD_10, PG21MD_11,
PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011,
PG20MD_100, PG20MD_101, PG20MD_110, PG20MD_111,
PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011,
PG19MD_100, PG19MD_101, PG19MD_110, PG19MD_111,
PG18MD_000, PG18MD_001, PG18MD_010, PG18MD_011,
PG18MD_100, PG18MD_101, PG18MD_110, PG18MD_111,
PG17MD_000, PG17MD_001, PG17MD_010, PG17MD_011,
PG17MD_100, PG17MD_101, PG17MD_110, PG17MD_111,
PG16MD_000, PG16MD_001, PG16MD_010, PG16MD_011,
PG16MD_100, PG16MD_101, PG16MD_110, PG16MD_111,
PG15MD_000, PG15MD_001, PG15MD_010, PG15MD_011,
PG15MD_100, PG15MD_101, PG15MD_110, PG15MD_111,
PG14MD_000, PG14MD_001, PG14MD_010, PG14MD_011,
PG14MD_100, PG14MD_101, PG14MD_110, PG14MD_111,
PG13MD_000, PG13MD_001, PG13MD_010, PG13MD_011,
PG13MD_100, PG13MD_101, PG13MD_110, PG13MD_111,
PG12MD_000, PG12MD_001, PG12MD_010, PG12MD_011,
PG12MD_100, PG12MD_101, PG12MD_110, PG12MD_111,
PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011,
PG11MD_100, PG11MD_101, PG11MD_110, PG11MD_111,
PG10MD_000, PG10MD_001, PG10MD_010, PG10MD_011,
PG10MD_100, PG10MD_101, PG10MD_110, PG10MD_111,
PG9MD_000, PG9MD_001, PG9MD_010, PG9MD_011,
PG9MD_100, PG9MD_101, PG9MD_110, PG9MD_111,
PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011,
PG8MD_100, PG8MD_101, PG8MD_110, PG8MD_111,
PG7MD_00, PG7MD_01, PG7MD_10, PG7MD_11,
PG6MD_00, PG6MD_01, PG6MD_10, PG6MD_11,
PG5MD_00, PG5MD_01, PG5MD_10, PG5MD_11,
PG4MD_00, PG4MD_01, PG4MD_10, PG4MD_11,
PG3MD_00, PG3MD_01, PG3MD_10, PG3MD_11,
PG2MD_00, PG2MD_01, PG2MD_10, PG2MD_11,
PG1MD_00, PG1MD_01, PG1MD_10, PG1MD_11,
PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011,
PG0MD_100, PG0MD_101, PG0MD_110, PG0MD_111,
/* Port H */
PH7MD_0, PH7MD_1,
PH6MD_0, PH6MD_1,
PH5MD_0, PH5MD_1,
PH4MD_0, PH4MD_1,
PH3MD_0, PH3MD_1,
PH2MD_0, PH2MD_1,
PH1MD_0, PH1MD_1,
PH0MD_0, PH0MD_1,
/* Port I - not on device */
/* Port J */
PJ11_IOR_IN, PJ11_IOR_OUT,
PJ10_IOR_IN, PJ10_IOR_OUT,
PJ9_IOR_IN, PJ9_IOR_OUT,
PJ8_IOR_IN, PJ8_IOR_OUT,
PJ7_IOR_IN, PJ7_IOR_OUT,
PJ6_IOR_IN, PJ6_IOR_OUT,
PJ5_IOR_IN, PJ5_IOR_OUT,
PJ4_IOR_IN, PJ4_IOR_OUT,
PJ3_IOR_IN, PJ3_IOR_OUT,
PJ2_IOR_IN, PJ2_IOR_OUT,
PJ1_IOR_IN, PJ1_IOR_OUT,
PJ0_IOR_IN, PJ0_IOR_OUT,
PJ11MD_00, PJ11MD_01, PJ11MD_10, PJ11MD_11,
PJ10MD_00, PJ10MD_01, PJ10MD_10, PJ10MD_11,
PJ9MD_00, PJ9MD_01, PJ9MD_10, PJ9MD_11,
PJ8MD_00, PJ8MD_01, PJ8MD_10, PJ8MD_11,
PJ7MD_00, PJ7MD_01, PJ7MD_10, PJ7MD_11,
PJ6MD_00, PJ6MD_01, PJ6MD_10, PJ6MD_11,
PJ5MD_00, PJ5MD_01, PJ5MD_10, PJ5MD_11,
PJ4MD_00, PJ4MD_01, PJ4MD_10, PJ4MD_11,
PJ3MD_00, PJ3MD_01, PJ3MD_10, PJ3MD_11,
PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011,
PJ2MD_100, PJ2MD_101, PJ2MD_110, PJ2MD_111,
PJ1MD_000, PJ1MD_001, PJ1MD_010, PJ1MD_011,
PJ1MD_100, PJ1MD_101, PJ1MD_110, PJ1MD_111,
PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011,
PJ0MD_100, PJ0MD_101, PJ0MD_110, PJ0MD_111,
/* Port K */
PK11_IOR_IN, PK11_IOR_OUT,
PK10_IOR_IN, PK10_IOR_OUT,
PK9_IOR_IN, PK9_IOR_OUT,
PK8_IOR_IN, PK8_IOR_OUT,
PK7_IOR_IN, PK7_IOR_OUT,
PK6_IOR_IN, PK6_IOR_OUT,
PK5_IOR_IN, PK5_IOR_OUT,
PK4_IOR_IN, PK4_IOR_OUT,
PK3_IOR_IN, PK3_IOR_OUT,
PK2_IOR_IN, PK2_IOR_OUT,
PK1_IOR_IN, PK1_IOR_OUT,
PK0_IOR_IN, PK0_IOR_OUT,
PK11MD_00, PK11MD_01, PK11MD_10, PK11MD_11,
PK10MD_00, PK10MD_01, PK10MD_10, PK10MD_11,
PK9MD_00, PK9MD_01, PK9MD_10, PK9MD_11,
PK8MD_00, PK8MD_01, PK8MD_10, PK8MD_11,
PK7MD_00, PK7MD_01, PK7MD_10, PK7MD_11,
PK6MD_00, PK6MD_01, PK6MD_10, PK6MD_11,
PK5MD_00, PK5MD_01, PK5MD_10, PK5MD_11,
PK4MD_00, PK4MD_01, PK4MD_10, PK4MD_11,
PK3MD_00, PK3MD_01, PK3MD_10, PK3MD_11,
PK2MD_00, PK2MD_01, PK2MD_10, PK2MD_11,
PK1MD_00, PK1MD_01, PK1MD_10, PK1MD_11,
PK0MD_00, PK0MD_01, PK0MD_10, PK0MD_11,
PINMUX_FUNCTION_END,
PINMUX_MARK_BEGIN,
/* Port A */
/* Port B */
/* Port C */
/* Port D */
/* Port E */
/* Port F */
/* Port G */
/* Port H */
PHAN7_MARK, PHAN6_MARK, PHAN5_MARK, PHAN4_MARK,
PHAN3_MARK, PHAN2_MARK, PHAN1_MARK, PHAN0_MARK,
/* Port I - not on device */
/* Port J */
/* Port K */
IRQ7_PC_MARK, IRQ6_PC_MARK, IRQ5_PC_MARK, IRQ4_PC_MARK,
IRQ3_PG_MARK, IRQ2_PG_MARK, IRQ1_PJ_MARK, IRQ0_PJ_MARK,
IRQ3_PE_MARK, IRQ2_PE_MARK, IRQ1_PE_MARK, IRQ0_PE_MARK,
PINT7_PG_MARK, PINT6_PG_MARK, PINT5_PG_MARK, PINT4_PG_MARK,
PINT3_PG_MARK, PINT2_PG_MARK, PINT1_PG_MARK, PINT0_PG_MARK,
SD_CD_MARK, SD_D0_MARK, SD_D1_MARK, SD_D2_MARK, SD_D3_MARK,
SD_WP_MARK, SD_CLK_MARK, SD_CMD_MARK,
CRX0_MARK, CRX1_MARK,
CTX0_MARK, CTX1_MARK,
PWM1A_MARK, PWM1B_MARK, PWM1C_MARK, PWM1D_MARK,
PWM1E_MARK, PWM1F_MARK, PWM1G_MARK, PWM1H_MARK,
PWM2A_MARK, PWM2B_MARK, PWM2C_MARK, PWM2D_MARK,
PWM2E_MARK, PWM2F_MARK, PWM2G_MARK, PWM2H_MARK,
IERXD_MARK, IETXD_MARK,
CRX0CRX1_MARK,
WDTOVF_MARK,
CRX0X1_MARK,
/* DMAC */
TEND0_MARK, DACK0_MARK, DREQ0_MARK,
TEND1_MARK, DACK1_MARK, DREQ1_MARK,
/* ADC */
ADTRG_MARK,
/* BSC */
A25_MARK, A24_MARK,
A23_MARK, A22_MARK, A21_MARK, A20_MARK,
A19_MARK, A18_MARK, A17_MARK, A16_MARK,
A15_MARK, A14_MARK, A13_MARK, A12_MARK,
A11_MARK, A10_MARK, A9_MARK, A8_MARK,
A7_MARK, A6_MARK, A5_MARK, A4_MARK,
A3_MARK, A2_MARK, A1_MARK, A0_MARK,
D15_MARK, D14_MARK, D13_MARK, D12_MARK,
D11_MARK, D10_MARK, D9_MARK, D8_MARK,
D7_MARK, D6_MARK, D5_MARK, D4_MARK,
D3_MARK, D2_MARK, D1_MARK, D0_MARK,
BS_MARK,
CS4_MARK, CS3_MARK, CS2_MARK, CS1_MARK, CS0_MARK,
CS6CE1B_MARK, CS5CE1A_MARK,
CE2A_MARK, CE2B_MARK,
RD_MARK, RDWR_MARK,
ICIOWRAH_MARK,
ICIORD_MARK,
WE1DQMUWE_MARK,
WE0DQML_MARK,
RAS_MARK, CAS_MARK, CKE_MARK,
WAIT_MARK, BREQ_MARK, BACK_MARK, IOIS16_MARK,
/* TMU */
TIOC0A_MARK, TIOC0B_MARK, TIOC0C_MARK, TIOC0D_MARK,
TIOC1A_MARK, TIOC1B_MARK,
TIOC2A_MARK, TIOC2B_MARK,
TIOC3A_MARK, TIOC3B_MARK, TIOC3C_MARK, TIOC3D_MARK,
TIOC4A_MARK, TIOC4B_MARK, TIOC4C_MARK, TIOC4D_MARK,
TCLKA_MARK, TCLKB_MARK, TCLKC_MARK, TCLKD_MARK,
/* SCIF */
SCK0_MARK, SCK1_MARK, SCK2_MARK, SCK3_MARK,
RXD0_MARK, RXD1_MARK, RXD2_MARK, RXD3_MARK,
TXD0_MARK, TXD1_MARK, TXD2_MARK, TXD3_MARK,
RXD4_MARK, RXD5_MARK, RXD6_MARK, RXD7_MARK,
TXD4_MARK, TXD5_MARK, TXD6_MARK, TXD7_MARK,
RTS1_MARK, RTS3_MARK,
CTS1_MARK, CTS3_MARK,
/* RSPI */
RSPCK0_MARK, RSPCK1_MARK,
MOSI0_MARK, MOSI1_MARK,
MISO0_PF12_MARK, MISO1_MARK, MISO1_PG19_MARK,
SSL00_MARK, SSL10_MARK,
/* IIC3 */
SCL0_MARK, SCL1_MARK, SCL2_MARK,
SDA0_MARK, SDA1_MARK, SDA2_MARK,
/* SSI */
SSISCK0_MARK,
SSIWS0_MARK,
SSITXD0_MARK,
SSIRXD0_MARK,
SSIWS1_MARK, SSIWS2_MARK, SSIWS3_MARK,
SSISCK1_MARK, SSISCK2_MARK, SSISCK3_MARK,
SSIDATA1_MARK, SSIDATA2_MARK, SSIDATA3_MARK,
AUDIO_CLK_MARK,
/* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
SIOFTXD_MARK, SIOFRXD_MARK, SIOFSYNC_MARK, SIOFSCK_MARK,
/* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
SPDIF_IN_MARK, SPDIF_OUT_MARK,
/* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
FCE_MARK,
FRB_MARK,
/* VDC3 */
DV_CLK_MARK,
DV_VSYNC_MARK, DV_HSYNC_MARK,
DV_DATA7_MARK, DV_DATA6_MARK, DV_DATA5_MARK, DV_DATA4_MARK,
DV_DATA3_MARK, DV_DATA2_MARK, DV_DATA1_MARK, DV_DATA0_MARK,
LCD_CLK_MARK, LCD_EXTCLK_MARK,
LCD_VSYNC_MARK, LCD_HSYNC_MARK, LCD_DE_MARK,
LCD_DATA15_MARK, LCD_DATA14_MARK, LCD_DATA13_MARK, LCD_DATA12_MARK,
LCD_DATA11_MARK, LCD_DATA10_MARK, LCD_DATA9_MARK, LCD_DATA8_MARK,
LCD_DATA7_MARK, LCD_DATA6_MARK, LCD_DATA5_MARK, LCD_DATA4_MARK,
LCD_DATA3_MARK, LCD_DATA2_MARK, LCD_DATA1_MARK, LCD_DATA0_MARK,
LCD_M_DISP_MARK,
PINMUX_MARK_END,
};
static pinmux_enum_t pinmux_data[] = {
/* Port A */
PINMUX_DATA(PA3_DATA, PA3_IN),
PINMUX_DATA(PA2_DATA, PA2_IN),
PINMUX_DATA(PA1_DATA, PA1_IN),
PINMUX_DATA(PA0_DATA, PA0_IN),
/* Port B */
PINMUX_DATA(PB22_DATA, PB22MD_00, PB22_IN, PB22_OUT),
PINMUX_DATA(A22_MARK, PB22MD_01),
PINMUX_DATA(CS4_MARK, PB22MD_10),
PINMUX_DATA(PB21_DATA, PB21MD_0, PB21_IN, PB21_OUT),
PINMUX_DATA(A21_MARK, PB21MD_1),
PINMUX_DATA(A20_MARK, PB20MD_1),
PINMUX_DATA(A19_MARK, PB19MD_01),
PINMUX_DATA(A18_MARK, PB18MD_01),
PINMUX_DATA(A17_MARK, PB17MD_01),
PINMUX_DATA(A16_MARK, PB16MD_01),
PINMUX_DATA(A15_MARK, PB15MD_01),
PINMUX_DATA(A14_MARK, PB14MD_01),
PINMUX_DATA(A13_MARK, PB13MD_01),
PINMUX_DATA(A12_MARK, PB12MD_01),
PINMUX_DATA(A11_MARK, PB11MD_01),
PINMUX_DATA(A10_MARK, PB10MD_01),
PINMUX_DATA(A9_MARK, PB9MD_01),
PINMUX_DATA(A8_MARK, PB8MD_01),
PINMUX_DATA(A7_MARK, PB7MD_01),
PINMUX_DATA(A6_MARK, PB6MD_01),
PINMUX_DATA(A5_MARK, PB5MD_01),
PINMUX_DATA(A4_MARK, PB4MD_01),
PINMUX_DATA(A3_MARK, PB3MD_1),
PINMUX_DATA(A2_MARK, PB2MD_1),
PINMUX_DATA(A1_MARK, PB1MD_1),
/* Port C */
PINMUX_DATA(PC10_DATA, PC10MD_0),
PINMUX_DATA(TIOC2B_MARK, PC1MD_1),
PINMUX_DATA(PC9_DATA, PC9MD_0),
PINMUX_DATA(TIOC2A_MARK, PC9MD_1),
PINMUX_DATA(PC8_DATA, PC8MD_00),
PINMUX_DATA(CS3_MARK, PC8MD_01),
PINMUX_DATA(TIOC4D_MARK, PC8MD_10),
PINMUX_DATA(IRQ7_PC_MARK, PC8MD_11),
PINMUX_DATA(PC7_DATA, PC7MD_00),
PINMUX_DATA(CKE_MARK, PC7MD_01),
PINMUX_DATA(TIOC4C_MARK, PC7MD_10),
PINMUX_DATA(IRQ6_PC_MARK, PC7MD_11),
PINMUX_DATA(PC6_DATA, PC6MD_00),
PINMUX_DATA(CAS_MARK, PC6MD_01),
PINMUX_DATA(TIOC4B_MARK, PC6MD_10),
PINMUX_DATA(IRQ5_PC_MARK, PC6MD_11),
PINMUX_DATA(PC5_DATA, PC5MD_00),
PINMUX_DATA(RAS_MARK, PC5MD_01),
PINMUX_DATA(TIOC4A_MARK, PC5MD_10),
PINMUX_DATA(IRQ4_PC_MARK, PC5MD_11),
PINMUX_DATA(PC4_DATA, PC4MD_0),
PINMUX_DATA(WE1DQMUWE_MARK, PC4MD_1),
PINMUX_DATA(PC3_DATA, PC3MD_0),
PINMUX_DATA(WE0DQML_MARK, PC3MD_1),
PINMUX_DATA(PC2_DATA, PC2MD_0),
PINMUX_DATA(RDWR_MARK, PC2MD_1),
PINMUX_DATA(PC1_DATA, PC1MD_0),
PINMUX_DATA(RD_MARK, PC1MD_1),
PINMUX_DATA(PC0_DATA, PC0MD_0),
PINMUX_DATA(CS0_MARK, PC0MD_1),
/* Port D */
PINMUX_DATA(D15_MARK, PD15MD_01),
PINMUX_DATA(D14_MARK, PD14MD_01),
PINMUX_DATA(D13_MARK, PD13MD_01),
PINMUX_DATA(D12_MARK, PD12MD_01),
PINMUX_DATA(D11_MARK, PD11MD_01),
PINMUX_DATA(D10_MARK, PD10MD_01),
PINMUX_DATA(D9_MARK, PD9MD_01),
PINMUX_DATA(D8_MARK, PD8MD_01),
PINMUX_DATA(D7_MARK, PD7MD_01),
PINMUX_DATA(D6_MARK, PD6MD_01),
PINMUX_DATA(D5_MARK, PD5MD_01),
PINMUX_DATA(D4_MARK, PD4MD_01),
PINMUX_DATA(D3_MARK, PD3MD_01),
PINMUX_DATA(D2_MARK, PD2MD_01),
PINMUX_DATA(D1_MARK, PD1MD_01),
PINMUX_DATA(D0_MARK, PD0MD_01),
/* Port E */
PINMUX_DATA(PE5_DATA, PE5MD_00),
PINMUX_DATA(SDA2_MARK, PE5MD_01),
PINMUX_DATA(DV_HSYNC_MARK, PE5MD_11),
PINMUX_DATA(PE4_DATA, PE4MD_00),
PINMUX_DATA(SCL2_MARK, PE4MD_01),
PINMUX_DATA(DV_VSYNC_MARK, PE4MD_11),
PINMUX_DATA(PE3_DATA, PE3MD_00),
PINMUX_DATA(SDA1_MARK, PE3MD_01),
PINMUX_DATA(IRQ3_PE_MARK, PE3MD_11),
PINMUX_DATA(PE2_DATA, PE2MD_00),
PINMUX_DATA(SCL1_MARK, PE2MD_01),
PINMUX_DATA(IRQ2_PE_MARK, PE2MD_11),
PINMUX_DATA(PE1_DATA, PE1MD_000),
PINMUX_DATA(SDA0_MARK, PE1MD_001),
PINMUX_DATA(IOIS16_MARK, PE1MD_010),
PINMUX_DATA(IRQ1_PE_MARK, PE1MD_011),
PINMUX_DATA(TCLKA_MARK, PE1MD_100),
PINMUX_DATA(ADTRG_MARK, PE1MD_101),
PINMUX_DATA(PE0_DATA, PE0MD_00),
PINMUX_DATA(SCL0_MARK, PE0MD_01),
PINMUX_DATA(AUDIO_CLK_MARK, PE0MD_10),
PINMUX_DATA(IRQ0_PE_MARK, PE0MD_11),
/* Port F */
PINMUX_DATA(PF12_DATA, PF12MD_000),
PINMUX_DATA(BS_MARK, PF12MD_001),
PINMUX_DATA(MISO0_PF12_MARK, PF12MD_011),
PINMUX_DATA(TIOC3D_MARK, PF12MD_100),
PINMUX_DATA(SPDIF_OUT_MARK, PF12MD_101),
PINMUX_DATA(PF11_DATA, PF11MD_000),
PINMUX_DATA(A25_MARK, PF11MD_001),
PINMUX_DATA(SSIDATA3_MARK, PF11MD_010),
PINMUX_DATA(MOSI0_MARK, PF11MD_011),
PINMUX_DATA(TIOC3C_MARK, PF11MD_100),
PINMUX_DATA(SPDIF_IN_MARK, PF11MD_101),
PINMUX_DATA(PF10_DATA, PF10MD_000),
PINMUX_DATA(A24_MARK, PF10MD_001),
PINMUX_DATA(SSIWS3_MARK, PF10MD_010),
PINMUX_DATA(SSL00_MARK, PF10MD_011),
PINMUX_DATA(TIOC3B_MARK, PF10MD_100),
PINMUX_DATA(FCE_MARK, PF10MD_101),
PINMUX_DATA(PF9_DATA, PF9MD_000),
PINMUX_DATA(A23_MARK, PF9MD_001),
PINMUX_DATA(SSISCK3_MARK, PF9MD_010),
PINMUX_DATA(RSPCK0_MARK, PF9MD_011),
PINMUX_DATA(TIOC3A_MARK, PF9MD_100),
PINMUX_DATA(FRB_MARK, PF9MD_101),
PINMUX_DATA(PF8_DATA, PF8MD_00),
PINMUX_DATA(CE2B_MARK, PF8MD_01),
PINMUX_DATA(SSIDATA3_MARK, PF8MD_10),
PINMUX_DATA(DV_CLK_MARK, PF8MD_11),
PINMUX_DATA(PF7_DATA, PF7MD_000),
PINMUX_DATA(CE2A_MARK, PF7MD_001),
PINMUX_DATA(SSIWS3_MARK, PF7MD_010),
PINMUX_DATA(DV_DATA7_MARK, PF7MD_011),
PINMUX_DATA(TCLKD_MARK, PF7MD_100),
PINMUX_DATA(PF6_DATA, PF6MD_000),
PINMUX_DATA(CS6CE1B_MARK, PF6MD_001),
PINMUX_DATA(SSISCK3_MARK, PF6MD_010),
PINMUX_DATA(DV_DATA6_MARK, PF6MD_011),
PINMUX_DATA(TCLKB_MARK, PF6MD_100),
PINMUX_DATA(PF5_DATA, PF5MD_000),
PINMUX_DATA(CS5CE1A_MARK, PF5MD_001),
PINMUX_DATA(SSIDATA2_MARK, PF5MD_010),
PINMUX_DATA(DV_DATA5_MARK, PF5MD_011),
PINMUX_DATA(TCLKC_MARK, PF5MD_100),
PINMUX_DATA(PF4_DATA, PF4MD_000),
PINMUX_DATA(ICIOWRAH_MARK, PF4MD_001),
PINMUX_DATA(SSIWS2_MARK, PF4MD_010),
PINMUX_DATA(DV_DATA4_MARK, PF4MD_011),
PINMUX_DATA(TXD3_MARK, PF4MD_100),
PINMUX_DATA(PF3_DATA, PF3MD_000),
PINMUX_DATA(ICIORD_MARK, PF3MD_001),
PINMUX_DATA(SSISCK2_MARK, PF3MD_010),
PINMUX_DATA(DV_DATA3_MARK, PF3MD_011),
PINMUX_DATA(RXD3_MARK, PF3MD_100),
PINMUX_DATA(PF2_DATA, PF2MD_000),
PINMUX_DATA(BACK_MARK, PF2MD_001),
PINMUX_DATA(SSIDATA1_MARK, PF2MD_010),
PINMUX_DATA(DV_DATA2_MARK, PF2MD_011),
PINMUX_DATA(TXD2_MARK, PF2MD_100),
PINMUX_DATA(DACK0_MARK, PF2MD_101),
PINMUX_DATA(PF1_DATA, PF1MD_000),
PINMUX_DATA(BREQ_MARK, PF1MD_001),
PINMUX_DATA(SSIWS1_MARK, PF1MD_010),
PINMUX_DATA(DV_DATA1_MARK, PF1MD_011),
PINMUX_DATA(RXD2_MARK, PF1MD_100),
PINMUX_DATA(DREQ0_MARK, PF1MD_101),
PINMUX_DATA(PF0_DATA, PF0MD_000),
PINMUX_DATA(WAIT_MARK, PF0MD_001),
PINMUX_DATA(SSISCK1_MARK, PF0MD_010),
PINMUX_DATA(DV_DATA0_MARK, PF0MD_011),
PINMUX_DATA(SCK2_MARK, PF0MD_100),
PINMUX_DATA(TEND0_MARK, PF0MD_101),
/* Port G */
PINMUX_DATA(PG24_DATA, PG24MD_00),
PINMUX_DATA(MOSI0_MARK, PG24MD_01),
PINMUX_DATA(TIOC0D_MARK, PG24MD_10),
PINMUX_DATA(PG23_DATA, PG23MD_00),
PINMUX_DATA(MOSI1_MARK, PG23MD_01),
PINMUX_DATA(TIOC0C_MARK, PG23MD_10),
PINMUX_DATA(PG22_DATA, PG22MD_00),
PINMUX_DATA(SSL10_MARK, PG22MD_01),
PINMUX_DATA(TIOC0B_MARK, PG22MD_10),
PINMUX_DATA(PG21_DATA, PG21MD_00),
PINMUX_DATA(RSPCK1_MARK, PG21MD_01),
PINMUX_DATA(TIOC0A_MARK, PG21MD_10),
PINMUX_DATA(PG20_DATA, PG20MD_000),
PINMUX_DATA(LCD_EXTCLK_MARK, PG20MD_001),
PINMUX_DATA(MISO1_MARK, PG20MD_011),
PINMUX_DATA(TXD7_MARK, PG20MD_100),
PINMUX_DATA(PG19_DATA, PG19MD_000),
PINMUX_DATA(LCD_CLK_MARK, PG19MD_001),
PINMUX_DATA(TIOC2B_MARK, PG19MD_010),
PINMUX_DATA(MISO1_PG19_MARK, PG19MD_011),
PINMUX_DATA(RXD7_MARK, PG19MD_100),
PINMUX_DATA(PG18_DATA, PG18MD_000),
PINMUX_DATA(LCD_DE_MARK, PG18MD_001),
PINMUX_DATA(TIOC2A_MARK, PG18MD_010),
PINMUX_DATA(SSL10_MARK, PG18MD_011),
PINMUX_DATA(TXD6_MARK, PG18MD_100),
PINMUX_DATA(PG17_DATA, PG17MD_000),
PINMUX_DATA(LCD_HSYNC_MARK, PG17MD_001),
PINMUX_DATA(TIOC1B_MARK, PG17MD_010),
PINMUX_DATA(RSPCK1_MARK, PG17MD_011),
PINMUX_DATA(RXD6_MARK, PG17MD_100),
PINMUX_DATA(PG16_DATA, PG16MD_000),
PINMUX_DATA(LCD_VSYNC_MARK, PG16MD_001),
PINMUX_DATA(TIOC1A_MARK, PG16MD_010),
PINMUX_DATA(TXD3_MARK, PG16MD_011),
PINMUX_DATA(CTS1_MARK, PG16MD_100),
PINMUX_DATA(PG15_DATA, PG15MD_000),
PINMUX_DATA(LCD_DATA15_MARK, PG15MD_001),
PINMUX_DATA(TIOC0D_MARK, PG15MD_010),
PINMUX_DATA(RXD3_MARK, PG15MD_011),
PINMUX_DATA(RTS1_MARK, PG15MD_100),
PINMUX_DATA(PG14_DATA, PG14MD_000),
PINMUX_DATA(LCD_DATA14_MARK, PG14MD_001),
PINMUX_DATA(TIOC0C_MARK, PG14MD_010),
PINMUX_DATA(SCK1_MARK, PG14MD_100),
PINMUX_DATA(PG13_DATA, PG13MD_000),
PINMUX_DATA(LCD_DATA13_MARK, PG13MD_001),
PINMUX_DATA(TIOC0B_MARK, PG13MD_010),
PINMUX_DATA(TXD1_MARK, PG13MD_100),
PINMUX_DATA(PG12_DATA, PG12MD_000),
PINMUX_DATA(LCD_DATA12_MARK, PG12MD_001),
PINMUX_DATA(TIOC0A_MARK, PG12MD_010),
PINMUX_DATA(RXD1_MARK, PG12MD_100),
PINMUX_DATA(PG11_DATA, PG11MD_000),
PINMUX_DATA(LCD_DATA11_MARK, PG11MD_001),
PINMUX_DATA(SSITXD0_MARK, PG11MD_010),
PINMUX_DATA(IRQ3_PG_MARK, PG11MD_011),
PINMUX_DATA(TXD5_MARK, PG11MD_100),
PINMUX_DATA(SIOFTXD_MARK, PG11MD_101),
PINMUX_DATA(PG10_DATA, PG10MD_000),
PINMUX_DATA(LCD_DATA10_MARK, PG10MD_001),
PINMUX_DATA(SSIRXD0_MARK, PG10MD_010),
PINMUX_DATA(IRQ2_PG_MARK, PG10MD_011),
PINMUX_DATA(RXD5_MARK, PG10MD_100),
PINMUX_DATA(SIOFRXD_MARK, PG10MD_101),
PINMUX_DATA(PG9_DATA, PG9MD_000),
PINMUX_DATA(LCD_DATA9_MARK, PG9MD_001),
PINMUX_DATA(SSIWS0_MARK, PG9MD_010),
PINMUX_DATA(TXD4_MARK, PG9MD_100),
PINMUX_DATA(SIOFSYNC_MARK, PG9MD_101),
PINMUX_DATA(PG8_DATA, PG8MD_000),
PINMUX_DATA(LCD_DATA8_MARK, PG8MD_001),
PINMUX_DATA(SSISCK0_MARK, PG8MD_010),
PINMUX_DATA(RXD4_MARK, PG8MD_100),
PINMUX_DATA(SIOFSCK_MARK, PG8MD_101),
PINMUX_DATA(PG7_DATA, PG7MD_00),
PINMUX_DATA(LCD_DATA7_MARK, PG7MD_01),
PINMUX_DATA(SD_CD_MARK, PG7MD_10),
PINMUX_DATA(PINT7_PG_MARK, PG7MD_11),
PINMUX_DATA(PG6_DATA, PG7MD_00),
PINMUX_DATA(LCD_DATA6_MARK, PG7MD_01),
PINMUX_DATA(SD_WP_MARK, PG7MD_10),
PINMUX_DATA(PINT6_PG_MARK, PG7MD_11),
PINMUX_DATA(PG5_DATA, PG5MD_00),
PINMUX_DATA(LCD_DATA5_MARK, PG5MD_01),
PINMUX_DATA(SD_D1_MARK, PG5MD_10),
PINMUX_DATA(PINT5_PG_MARK, PG5MD_11),
PINMUX_DATA(PG4_DATA, PG4MD_00),
PINMUX_DATA(LCD_DATA4_MARK, PG4MD_01),
PINMUX_DATA(SD_D0_MARK, PG4MD_10),
PINMUX_DATA(PINT4_PG_MARK, PG4MD_11),
PINMUX_DATA(PG3_DATA, PG3MD_00),
PINMUX_DATA(LCD_DATA3_MARK, PG3MD_01),
PINMUX_DATA(SD_CLK_MARK, PG3MD_10),
PINMUX_DATA(PINT3_PG_MARK, PG3MD_11),
PINMUX_DATA(PG2_DATA, PG2MD_00),
PINMUX_DATA(LCD_DATA2_MARK, PG2MD_01),
PINMUX_DATA(SD_CMD_MARK, PG2MD_10),
PINMUX_DATA(PINT2_PG_MARK, PG2MD_11),
PINMUX_DATA(PG1_DATA, PG1MD_00),
PINMUX_DATA(LCD_DATA1_MARK, PG1MD_01),
PINMUX_DATA(SD_D3_MARK, PG1MD_10),
PINMUX_DATA(PINT1_PG_MARK, PG1MD_11),
PINMUX_DATA(PG0_DATA, PG0MD_000),
PINMUX_DATA(LCD_DATA0_MARK, PG0MD_001),
PINMUX_DATA(SD_D2_MARK, PG0MD_010),
PINMUX_DATA(PINT0_PG_MARK, PG0MD_011),
PINMUX_DATA(WDTOVF_MARK, PG0MD_100),
/* Port H */
PINMUX_DATA(PH7_DATA, PH7MD_0),
PINMUX_DATA(PHAN7_MARK, PH7MD_1),
PINMUX_DATA(PH6_DATA, PH6MD_0),
PINMUX_DATA(PHAN6_MARK, PH6MD_1),
PINMUX_DATA(PH5_DATA, PH5MD_0),
PINMUX_DATA(PHAN5_MARK, PH5MD_1),
PINMUX_DATA(PH4_DATA, PH4MD_0),
PINMUX_DATA(PHAN4_MARK, PH4MD_1),
PINMUX_DATA(PH3_DATA, PH3MD_0),
PINMUX_DATA(PHAN3_MARK, PH3MD_1),
PINMUX_DATA(PH2_DATA, PH2MD_0),
PINMUX_DATA(PHAN2_MARK, PH2MD_1),
PINMUX_DATA(PH1_DATA, PH1MD_0),
PINMUX_DATA(PHAN1_MARK, PH1MD_1),
PINMUX_DATA(PH0_DATA, PH0MD_0),
PINMUX_DATA(PHAN0_MARK, PH0MD_1),
/* Port I - not on device */
/* Port J */
PINMUX_DATA(PJ11_DATA, PJ11MD_00),
PINMUX_DATA(PWM2H_MARK, PJ11MD_01),
PINMUX_DATA(DACK1_MARK, PJ11MD_10),
PINMUX_DATA(PJ10_DATA, PJ10MD_00),
PINMUX_DATA(PWM2G_MARK, PJ10MD_01),
PINMUX_DATA(DREQ1_MARK, PJ10MD_10),
PINMUX_DATA(PJ9_DATA, PJ9MD_00),
PINMUX_DATA(PWM2F_MARK, PJ9MD_01),
PINMUX_DATA(TEND1_MARK, PJ9MD_10),
PINMUX_DATA(PJ8_DATA, PJ8MD_00),
PINMUX_DATA(PWM2E_MARK, PJ8MD_01),
PINMUX_DATA(RTS3_MARK, PJ8MD_10),
PINMUX_DATA(PJ7_DATA, PJ7MD_00),
PINMUX_DATA(TIOC1B_MARK, PJ7MD_01),
PINMUX_DATA(CTS3_MARK, PJ7MD_10),
PINMUX_DATA(PJ6_DATA, PJ6MD_00),
PINMUX_DATA(TIOC1A_MARK, PJ6MD_01),
PINMUX_DATA(SCK3_MARK, PJ6MD_10),
PINMUX_DATA(PJ5_DATA, PJ5MD_00),
PINMUX_DATA(IERXD_MARK, PJ5MD_01),
PINMUX_DATA(TXD3_MARK, PJ5MD_10),
PINMUX_DATA(PJ4_DATA, PJ4MD_00),
PINMUX_DATA(IETXD_MARK, PJ4MD_01),
PINMUX_DATA(RXD3_MARK, PJ4MD_10),
PINMUX_DATA(PJ3_DATA, PJ3MD_00),
PINMUX_DATA(CRX1_MARK, PJ3MD_01),
PINMUX_DATA(CRX0X1_MARK, PJ3MD_10),
PINMUX_DATA(IRQ1_PJ_MARK, PJ3MD_11),
PINMUX_DATA(PJ2_DATA, PJ2MD_000),
PINMUX_DATA(CTX1_MARK, PJ2MD_001),
PINMUX_DATA(CRX0CRX1_MARK, PJ2MD_010),
PINMUX_DATA(CS2_MARK, PJ2MD_011),
PINMUX_DATA(SCK0_MARK, PJ2MD_100),
PINMUX_DATA(LCD_M_DISP_MARK, PJ2MD_101),
PINMUX_DATA(PJ1_DATA, PJ1MD_000),
PINMUX_DATA(CRX0_MARK, PJ1MD_001),
PINMUX_DATA(IERXD_MARK, PJ1MD_010),
PINMUX_DATA(IRQ0_PJ_MARK, PJ1MD_011),
PINMUX_DATA(RXD0_MARK, PJ1MD_100),
PINMUX_DATA(PJ0_DATA, PJ0MD_000),
PINMUX_DATA(CTX0_MARK, PJ0MD_001),
PINMUX_DATA(IERXD_MARK, PJ0MD_010),
PINMUX_DATA(CS1_MARK, PJ0MD_011),
PINMUX_DATA(TXD0_MARK, PJ0MD_100),
PINMUX_DATA(A0_MARK, PJ0MD_101),
/* Port K */
PINMUX_DATA(PK11_DATA, PK11MD_00),
PINMUX_DATA(PWM2D_MARK, PK11MD_01),
PINMUX_DATA(SSITXD0_MARK, PK11MD_10),
PINMUX_DATA(PK10_DATA, PK10MD_00),
PINMUX_DATA(PWM2C_MARK, PK10MD_01),
PINMUX_DATA(SSIRXD0_MARK, PK10MD_10),
PINMUX_DATA(PK9_DATA, PK9MD_00),
PINMUX_DATA(PWM2B_MARK, PK9MD_01),
PINMUX_DATA(SSIWS0_MARK, PK9MD_10),
PINMUX_DATA(PK8_DATA, PK8MD_00),
PINMUX_DATA(PWM2A_MARK, PK8MD_01),
PINMUX_DATA(SSISCK0_MARK, PK8MD_10),
PINMUX_DATA(PK7_DATA, PK7MD_00),
PINMUX_DATA(PWM1H_MARK, PK7MD_01),
PINMUX_DATA(SD_CD_MARK, PK7MD_10),
PINMUX_DATA(PK6_DATA, PK6MD_00),
PINMUX_DATA(PWM1G_MARK, PK6MD_01),
PINMUX_DATA(SD_WP_MARK, PK6MD_10),
PINMUX_DATA(PK5_DATA, PK5MD_00),
PINMUX_DATA(PWM1F_MARK, PK5MD_01),
PINMUX_DATA(SD_D1_MARK, PK5MD_10),
PINMUX_DATA(PK4_DATA, PK4MD_00),
PINMUX_DATA(PWM1E_MARK, PK4MD_01),
PINMUX_DATA(SD_D0_MARK, PK4MD_10),
PINMUX_DATA(PK3_DATA, PK3MD_00),
PINMUX_DATA(PWM1D_MARK, PK3MD_01),
PINMUX_DATA(SD_CLK_MARK, PK3MD_10),
PINMUX_DATA(PK2_DATA, PK2MD_00),
PINMUX_DATA(PWM1C_MARK, PK2MD_01),
PINMUX_DATA(SD_CMD_MARK, PK2MD_10),
PINMUX_DATA(PK1_DATA, PK1MD_00),
PINMUX_DATA(PWM1B_MARK, PK1MD_01),
PINMUX_DATA(SD_D3_MARK, PK1MD_10),
PINMUX_DATA(PK0_DATA, PK0MD_00),
PINMUX_DATA(PWM1A_MARK, PK0MD_01),
PINMUX_DATA(SD_D2_MARK, PK0MD_10),
};
static struct pinmux_gpio pinmux_gpios[] = {
/* Port A */
PINMUX_GPIO(GPIO_PA3, PA3_DATA),
PINMUX_GPIO(GPIO_PA2, PA2_DATA),
PINMUX_GPIO(GPIO_PA1, PA1_DATA),
PINMUX_GPIO(GPIO_PA0, PA0_DATA),
/* Port B */
PINMUX_GPIO(GPIO_PB22, PB22_DATA),
PINMUX_GPIO(GPIO_PB21, PB21_DATA),
PINMUX_GPIO(GPIO_PB20, PB20_DATA),
PINMUX_GPIO(GPIO_PB19, PB19_DATA),
PINMUX_GPIO(GPIO_PB18, PB18_DATA),
PINMUX_GPIO(GPIO_PB17, PB17_DATA),
PINMUX_GPIO(GPIO_PB16, PB16_DATA),
PINMUX_GPIO(GPIO_PB15, PB15_DATA),
PINMUX_GPIO(GPIO_PB14, PB14_DATA),
PINMUX_GPIO(GPIO_PB13, PB13_DATA),
PINMUX_GPIO(GPIO_PB12, PB12_DATA),
PINMUX_GPIO(GPIO_PB11, PB11_DATA),
PINMUX_GPIO(GPIO_PB10, PB10_DATA),
PINMUX_GPIO(GPIO_PB9, PB9_DATA),
PINMUX_GPIO(GPIO_PB8, PB8_DATA),
PINMUX_GPIO(GPIO_PB7, PB7_DATA),
PINMUX_GPIO(GPIO_PB6, PB6_DATA),
PINMUX_GPIO(GPIO_PB5, PB5_DATA),
PINMUX_GPIO(GPIO_PB4, PB4_DATA),
PINMUX_GPIO(GPIO_PB3, PB3_DATA),
PINMUX_GPIO(GPIO_PB2, PB2_DATA),
PINMUX_GPIO(GPIO_PB1, PB1_DATA),
/* Port C */
PINMUX_GPIO(GPIO_PC10, PC10_DATA),
PINMUX_GPIO(GPIO_PC9, PC9_DATA),
PINMUX_GPIO(GPIO_PC8, PC8_DATA),
PINMUX_GPIO(GPIO_PC7, PC7_DATA),
PINMUX_GPIO(GPIO_PC6, PC6_DATA),
PINMUX_GPIO(GPIO_PC5, PC5_DATA),
PINMUX_GPIO(GPIO_PC4, PC4_DATA),
PINMUX_GPIO(GPIO_PC3, PC3_DATA),
PINMUX_GPIO(GPIO_PC2, PC2_DATA),
PINMUX_GPIO(GPIO_PC1, PC1_DATA),
PINMUX_GPIO(GPIO_PC0, PC0_DATA),
/* Port D */
PINMUX_GPIO(GPIO_PD15, PD15_DATA),
PINMUX_GPIO(GPIO_PD14, PD14_DATA),
PINMUX_GPIO(GPIO_PD13, PD13_DATA),
PINMUX_GPIO(GPIO_PD12, PD12_DATA),
PINMUX_GPIO(GPIO_PD11, PD11_DATA),
PINMUX_GPIO(GPIO_PD10, PD10_DATA),
PINMUX_GPIO(GPIO_PD9, PD9_DATA),
PINMUX_GPIO(GPIO_PD8, PD8_DATA),
PINMUX_GPIO(GPIO_PD7, PD7_DATA),
PINMUX_GPIO(GPIO_PD6, PD6_DATA),
PINMUX_GPIO(GPIO_PD5, PD5_DATA),
PINMUX_GPIO(GPIO_PD4, PD4_DATA),
PINMUX_GPIO(GPIO_PD3, PD3_DATA),
PINMUX_GPIO(GPIO_PD2, PD2_DATA),
PINMUX_GPIO(GPIO_PD1, PD1_DATA),
PINMUX_GPIO(GPIO_PD0, PD0_DATA),
/* Port E */
PINMUX_GPIO(GPIO_PE5, PE5_DATA),
PINMUX_GPIO(GPIO_PE4, PE4_DATA),
PINMUX_GPIO(GPIO_PE3, PE3_DATA),
PINMUX_GPIO(GPIO_PE2, PE2_DATA),
PINMUX_GPIO(GPIO_PE1, PE1_DATA),
PINMUX_GPIO(GPIO_PE0, PE0_DATA),
/* Port F */
PINMUX_GPIO(GPIO_PF12, PF12_DATA),
PINMUX_GPIO(GPIO_PF11, PF11_DATA),
PINMUX_GPIO(GPIO_PF10, PF10_DATA),
PINMUX_GPIO(GPIO_PF9, PF9_DATA),
PINMUX_GPIO(GPIO_PF8, PF8_DATA),
PINMUX_GPIO(GPIO_PF7, PF7_DATA),
PINMUX_GPIO(GPIO_PF6, PF6_DATA),
PINMUX_GPIO(GPIO_PF5, PF5_DATA),
PINMUX_GPIO(GPIO_PF4, PF4_DATA),
PINMUX_GPIO(GPIO_PF3, PF3_DATA),
PINMUX_GPIO(GPIO_PF2, PF2_DATA),
PINMUX_GPIO(GPIO_PF1, PF1_DATA),
PINMUX_GPIO(GPIO_PF0, PF0_DATA),
/* Port G */
PINMUX_GPIO(GPIO_PG24, PG24_DATA),
PINMUX_GPIO(GPIO_PG23, PG23_DATA),
PINMUX_GPIO(GPIO_PG22, PG22_DATA),
PINMUX_GPIO(GPIO_PG21, PG21_DATA),
PINMUX_GPIO(GPIO_PG20, PG20_DATA),
PINMUX_GPIO(GPIO_PG19, PG19_DATA),
PINMUX_GPIO(GPIO_PG18, PG18_DATA),
PINMUX_GPIO(GPIO_PG17, PG17_DATA),
PINMUX_GPIO(GPIO_PG16, PG16_DATA),
PINMUX_GPIO(GPIO_PG15, PG15_DATA),
PINMUX_GPIO(GPIO_PG14, PG14_DATA),
PINMUX_GPIO(GPIO_PG13, PG13_DATA),
PINMUX_GPIO(GPIO_PG12, PG12_DATA),
PINMUX_GPIO(GPIO_PG11, PG11_DATA),
PINMUX_GPIO(GPIO_PG10, PG10_DATA),
PINMUX_GPIO(GPIO_PG9, PG9_DATA),
PINMUX_GPIO(GPIO_PG8, PG8_DATA),
PINMUX_GPIO(GPIO_PG7, PG7_DATA),
PINMUX_GPIO(GPIO_PG6, PG6_DATA),
PINMUX_GPIO(GPIO_PG5, PG5_DATA),
PINMUX_GPIO(GPIO_PG4, PG4_DATA),
PINMUX_GPIO(GPIO_PG3, PG3_DATA),
PINMUX_GPIO(GPIO_PG2, PG2_DATA),
PINMUX_GPIO(GPIO_PG1, PG1_DATA),
PINMUX_GPIO(GPIO_PG0, PG0_DATA),
/* Port H - Port H does not have a Data Register */
/* Port I - not on device */
/* Port J */
PINMUX_GPIO(GPIO_PJ11, PJ11_DATA),
PINMUX_GPIO(GPIO_PJ10, PJ10_DATA),
PINMUX_GPIO(GPIO_PJ9, PJ9_DATA),
PINMUX_GPIO(GPIO_PJ8, PJ8_DATA),
PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
PINMUX_GPIO(GPIO_PJ0, PJ0_DATA),
/* Port K */
PINMUX_GPIO(GPIO_PK11, PK11_DATA),
PINMUX_GPIO(GPIO_PK10, PK10_DATA),
PINMUX_GPIO(GPIO_PK9, PK9_DATA),
PINMUX_GPIO(GPIO_PK8, PK8_DATA),
PINMUX_GPIO(GPIO_PK7, PK7_DATA),
PINMUX_GPIO(GPIO_PK6, PK6_DATA),
PINMUX_GPIO(GPIO_PK5, PK5_DATA),
PINMUX_GPIO(GPIO_PK4, PK4_DATA),
PINMUX_GPIO(GPIO_PK3, PK3_DATA),
PINMUX_GPIO(GPIO_PK2, PK2_DATA),
PINMUX_GPIO(GPIO_PK1, PK1_DATA),
PINMUX_GPIO(GPIO_PK0, PK0_DATA),
/* INTC */
PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK),
PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK),
PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK),
PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK),
PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK),
PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK),
PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK),
PINMUX_GPIO(GPIO_FN_IRQ7_PC, IRQ7_PC_MARK),
PINMUX_GPIO(GPIO_FN_IRQ6_PC, IRQ6_PC_MARK),
PINMUX_GPIO(GPIO_FN_IRQ5_PC, IRQ5_PC_MARK),
PINMUX_GPIO(GPIO_FN_IRQ4_PC, IRQ4_PC_MARK),
PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK),
PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK),
PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK),
PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK),
PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK),
PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK),
PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK),
PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK),
/* WDT */
PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
/* CAN */
PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK),
PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK),
PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK),
PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK),
PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0CRX1_MARK),
/* DMAC */
PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
/* ADC */
PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK),
/* BSCh */
PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
PINMUX_GPIO(GPIO_FN_A13, A13_MARK),
PINMUX_GPIO(GPIO_FN_A12, A12_MARK),
PINMUX_GPIO(GPIO_FN_A11, A11_MARK),
PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
PINMUX_GPIO(GPIO_FN_A6, A6_MARK),
PINMUX_GPIO(GPIO_FN_A5, A5_MARK),
PINMUX_GPIO(GPIO_FN_A4, A4_MARK),
PINMUX_GPIO(GPIO_FN_A3, A3_MARK),
PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK),
PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK),
PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK),
PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
PINMUX_GPIO(GPIO_FN_CS6CE1B, CS6CE1B_MARK),
PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK),
PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
PINMUX_GPIO(GPIO_FN_ICIOWRAH, ICIOWRAH_MARK),
PINMUX_GPIO(GPIO_FN_ICIORD, ICIORD_MARK),
PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK),
PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK),
PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK),
PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK),
PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK),
PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
/* TMU */
PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK),
PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK),
PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK),
PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK),
PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK),
PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK),
PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK),
PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK),
PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK),
PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK),
PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK),
PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK),
PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK),
PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK),
PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK),
PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK),
PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK),
PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK),
PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK),
PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK),
/* SCIF */
PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK),
PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK),
PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK),
PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK),
PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK),
PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK),
PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK),
PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK),
/* RSPI */
PINMUX_GPIO(GPIO_FN_RSPCK0, RSPCK0_MARK),
PINMUX_GPIO(GPIO_FN_MOSI0, MOSI0_MARK),
PINMUX_GPIO(GPIO_FN_MISO0_PF12, MISO0_PF12_MARK),
PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK),
PINMUX_GPIO(GPIO_FN_SSL00, SSL00_MARK),
PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK),
PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK),
PINMUX_GPIO(GPIO_FN_MISO1_PG19, MISO1_PG19_MARK),
PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK),
/* IIC3 */
PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
/* SSI */
PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK),
PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK),
PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK),
PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK),
PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK),
PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK),
PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK),
PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK),
PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK),
PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK),
PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK),
PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK),
PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK),
PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK),
/* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK),
PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK),
PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK),
PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK),
/* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK),
PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK),
/* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
/* VDC3 */
PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK),
PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK),
PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK),
PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK),
PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK),
PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK),
PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK),
PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
};
static struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) {
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PA3_IN, PA3_OUT,
PA2_IN, PA2_OUT,
PA1_IN, PA1_OUT,
PA0_IN, PA0_OUT }
},
{ PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4) {
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PB22MD_00, PB22MD_01, PB22MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PB21MD_0, PB21MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB20MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PBCR4", 0xfffe3826, 16, 4) {
0, PB19MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB18MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB17MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB16MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PBCR3", 0xfffe3828, 16, 4) {
0, PB15MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB14MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB13MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB12MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PBCR2", 0xfffe382a, 16, 4) {
0, PB11MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB10MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB9MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB8MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PBCR1", 0xfffe382c, 16, 4) {
0, PB7MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB6MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB5MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB4MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4) {
0, PB3MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB2MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PB1MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1) {
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0,
PB22_IN, PB22_OUT,
PB21_IN, PB21_OUT,
PB20_IN, PB20_OUT,
PB19_IN, PB19_OUT,
PB18_IN, PB18_OUT,
PB17_IN, PB17_OUT,
PB16_IN, PB16_OUT }
},
{ PINMUX_CFG_REG("PBIOR0", 0xfffe3832, 16, 1) {
PB15_IN, PB15_OUT,
PB14_IN, PB14_OUT,
PB13_IN, PB13_OUT,
PB12_IN, PB12_OUT,
PB11_IN, PB11_OUT,
PB10_IN, PB10_OUT,
PB9_IN, PB9_OUT,
PB8_IN, PB8_OUT,
PB7_IN, PB7_OUT,
PB6_IN, PB6_OUT,
PB5_IN, PB5_OUT,
PB4_IN, PB4_OUT,
PB3_IN, PB3_OUT,
PB2_IN, PB2_OUT,
PB1_IN, PB1_OUT,
0, 0 }
},
{ PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4) {
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PC10MD_0, PC10MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PC9MD_0, PC9MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PC8MD_00, PC8MD_01, PC8MD_10, PC8MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PCCR1", 0xfffe384c, 16, 4) {
PC7MD_00, PC7MD_01, PC7MD_10, PC7MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PC6MD_00, PC6MD_01, PC6MD_10, PC6MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PC5MD_00, PC5MD_01, PC5MD_10, PC5MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PC4MD_0, PC4MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PCCR0", 0xfffe384e, 16, 4) {
PC3MD_0, PC3MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PC2MD_0, PC2MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PC1MD_0, PC1MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PC0MD_0, PC0MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1) {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
PC10_IN, PC10_OUT,
PC9_IN, PC9_OUT,
PC8_IN, PC8_OUT,
PC7_IN, PC7_OUT,
PC6_IN, PC6_OUT,
PC5_IN, PC5_OUT,
PC4_IN, PC4_OUT,
PC3_IN, PC3_OUT,
PC2_IN, PC2_OUT,
PC1_IN, PC1_OUT,
PC0_IN, PC0_OUT
}
},
{ PINMUX_CFG_REG("PDCR3", 0xfffe3868, 16, 4) {
0, PD15MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PD14MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PD13MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PD12MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PDCR2", 0xfffe386a, 16, 4) {
0, PD11MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PD10MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PD9MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PD8MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PDCR1", 0xfffe386c, 16, 4) {
0, PD7MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PD6MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PD5MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PD4MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PDCR0", 0xfffe386e, 16, 4) {
0, PD3MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PD2MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PD1MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, PD0MD_01, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PDIOR0", 0xfffe3872, 16, 1) {
PD15_IN, PD15_OUT,
PD14_IN, PD14_OUT,
PD13_IN, PD13_OUT,
PD12_IN, PD12_OUT,
PD11_IN, PD11_OUT,
PD10_IN, PD10_OUT,
PD9_IN, PD9_OUT,
PD8_IN, PD8_OUT,
PD7_IN, PD7_OUT,
PD6_IN, PD6_OUT,
PD5_IN, PD5_OUT,
PD4_IN, PD4_OUT,
PD3_IN, PD3_OUT,
PD2_IN, PD2_OUT,
PD1_IN, PD1_OUT,
PD0_IN, PD0_OUT }
},
{ PINMUX_CFG_REG("PECR1", 0xfffe388c, 16, 4) {
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PE5MD_00, PE5MD_01, 0, PE5MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PE4MD_00, PE4MD_01, 0, PE4MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PECR0", 0xfffe388e, 16, 4) {
PE3MD_00, PE3MD_01, 0, PE3MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PE2MD_00, PE2MD_01, 0, PE2MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PE1MD_000, PE1MD_001, PE1MD_010, PE1MD_011,
PE1MD_100, PE1MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PEIOR0", 0xfffe3892, 16, 1) {
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0,
PE5_IN, PE5_OUT,
PE4_IN, PE4_OUT,
PE3_IN, PE3_OUT,
PE2_IN, PE2_OUT,
PE1_IN, PE1_OUT,
PE0_IN, PE0_OUT }
},
{ PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4) {
PF12MD_000, PF12MD_001, 0, PF12MD_011,
PF12MD_100, PF12MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PFCR2", 0xfffe38aa, 16, 4) {
PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011,
PF11MD_100, PF11MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PF10MD_000, PF10MD_001, PF10MD_010, PF10MD_011,
PF10MD_100, PF10MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PF9MD_000, PF9MD_001, PF9MD_010, PF9MD_011,
PF9MD_100, PF9MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PF8MD_00, PF8MD_01, PF8MD_10, PF8MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PFCR1", 0xfffe38ac, 16, 4) {
PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011,
PF7MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PF6MD_000, PF6MD_001, PF6MD_010, PF6MD_011,
PF6MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PF5MD_000, PF5MD_001, PF5MD_010, PF5MD_011,
PF5MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011,
PF4MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PFCR0", 0xfffe38ae, 16, 4) {
PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011,
PF3MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PF2MD_000, PF2MD_001, PF2MD_010, PF2MD_011,
PF2MD_100, PF2MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PF1MD_000, PF1MD_001, PF1MD_010, PF1MD_011,
PF1MD_100, PF1MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0
}
},
{ PINMUX_CFG_REG("PFIOR0", 0xfffe38b2, 16, 1) {
0, 0, 0, 0, 0, 0,
PF12_IN, PF12_OUT,
PF11_IN, PF11_OUT,
PF10_IN, PF10_OUT,
PF9_IN, PF9_OUT,
PF8_IN, PF8_OUT,
PF7_IN, PF7_OUT,
PF6_IN, PF6_OUT,
PF5_IN, PF5_OUT,
PF4_IN, PF4_OUT,
PF3_IN, PF3_OUT,
PF2_IN, PF2_OUT,
PF1_IN, PF1_OUT,
PF0_IN, PF0_OUT }
},
{ PINMUX_CFG_REG("PGCR7", 0xfffe38c0, 16, 4) {
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011,
PG0MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PGCR6", 0xfffe38c2, 16, 4) {
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PGCR5", 0xfffe38c4, 16, 4) {
PG23MD_00, PG23MD_01, PG23MD_10, PG23MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG22MD_00, PG22MD_01, PG22MD_10, PG22MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG21MD_00, PG21MD_01, PG21MD_10, PG21MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011,
PG20MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PGCR4", 0xfffe38c6, 16, 4) {
PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011,
PG19MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG18MD_000, PG18MD_001, PG18MD_010, PG18MD_011,
PG18MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG17MD_000, PG17MD_001, PG17MD_010, PG17MD_011,
PG17MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG16MD_000, PG16MD_001, PG16MD_010, PG16MD_011,
PG16MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PGCR3", 0xfffe38c8, 16, 4) {
PG15MD_000, PG15MD_001, PG15MD_010, PG15MD_011,
PG15MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG14MD_000, PG14MD_001, PG14MD_010, 0,
PG14MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG13MD_000, PG13MD_001, PG13MD_010, 0,
PG13MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG12MD_000, PG12MD_001, PG12MD_010, 0,
PG12MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PGCR2", 0xfffe38ca, 16, 4) {
PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011,
PG11MD_100, PG11MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG10MD_000, PG10MD_001, PG10MD_010, PG10MD_011,
PG10MD_100, PG10MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG9MD_000, PG9MD_001, PG9MD_010, PG9MD_011,
PG9MD_100, PG9MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011,
PG8MD_100, PG8MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PGCR1", 0xfffe38cc, 16, 4) {
PG7MD_00, PG7MD_01, PG7MD_10, PG7MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG6MD_00, PG6MD_01, PG6MD_10, PG6MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG5MD_00, PG5MD_01, PG5MD_10, PG5MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG4MD_00, PG4MD_01, PG4MD_10, PG4MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PGCR0", 0xfffe38ce, 16, 4) {
PG3MD_00, PG3MD_01, PG3MD_10, PG3MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG2MD_00, PG2MD_01, PG2MD_10, PG2MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PG1MD_00, PG1MD_01, PG1MD_10, PG1MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PGIOR1", 0xfffe38d0, 16, 1) {
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0,
PG24_IN, PG24_OUT,
PG23_IN, PG23_OUT,
PG22_IN, PG22_OUT,
PG21_IN, PG21_OUT,
PG20_IN, PG20_OUT,
PG19_IN, PG19_OUT,
PG18_IN, PG18_OUT,
PG17_IN, PG17_OUT,
PG16_IN, PG16_OUT }
},
{ PINMUX_CFG_REG("PGIOR0", 0xfffe38d2, 16, 1) {
PG15_IN, PG15_OUT,
PG14_IN, PG14_OUT,
PG13_IN, PG13_OUT,
PG12_IN, PG12_OUT,
PG11_IN, PG11_OUT,
PG10_IN, PG10_OUT,
PG9_IN, PG9_OUT,
PG8_IN, PG8_OUT,
PG7_IN, PG7_OUT,
PG6_IN, PG6_OUT,
PG5_IN, PG5_OUT,
PG4_IN, PG4_OUT,
PG3_IN, PG3_OUT,
PG2_IN, PG2_OUT,
PG1_IN, PG1_OUT,
PG0_IN, PG0_OUT
}
},
{ PINMUX_CFG_REG("PHCR1", 0xfffe38ec, 16, 4) {
PH7MD_0, PH7MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PH6MD_0, PH6MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PH5MD_0, PH5MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PH4MD_0, PH4MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PHCR0", 0xfffe38ee, 16, 4) {
PH3MD_0, PH3MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PH2MD_0, PH2MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PH1MD_0, PH1MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PH0MD_0, PH0MD_1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PJCR2", 0xfffe390a, 16, 4) {
PJ11MD_00, PJ11MD_01, PJ11MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PJ10MD_00, PJ10MD_01, PJ10MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PJ9MD_00, PJ9MD_01, PJ9MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PJ8MD_00, PJ8MD_01, PJ8MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PJCR1", 0xfffe390c, 16, 4) {
PJ7MD_00, PJ7MD_01, PJ7MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PJ6MD_00, PJ6MD_01, PJ6MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PJ5MD_00, PJ5MD_01, PJ5MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PJ4MD_00, PJ4MD_01, PJ4MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PJCR0", 0xfffe390e, 16, 4) {
PJ3MD_00, PJ3MD_01, PJ3MD_10, PJ3MD_11, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011,
PJ2MD_100, PJ2MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PJ1MD_000, PJ1MD_001, PJ1MD_010, PJ1MD_011,
PJ1MD_100, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011,
PJ0MD_100, PJ0MD_101, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, }
},
{ PINMUX_CFG_REG("PJIOR0", 0xfffe3912, 16, 1) {
0, 0, 0, 0, 0, 0, 0, 0,
PJ11_IN, PJ11_OUT,
PJ10_IN, PJ10_OUT,
PJ9_IN, PJ9_OUT,
PJ8_IN, PJ8_OUT,
PJ7_IN, PJ7_OUT,
PJ6_IN, PJ6_OUT,
PJ5_IN, PJ5_OUT,
PJ4_IN, PJ4_OUT,
PJ3_IN, PJ3_OUT,
PJ2_IN, PJ2_OUT,
PJ1_IN, PJ1_OUT,
PJ0_IN, PJ0_OUT }
},
{ PINMUX_CFG_REG("PKCR2", 0xfffe392a, 16, 4) {
PK11MD_00, PK11MD_01, PK11MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PK10MD_00, PK10MD_01, PK10MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PK9MD_00, PK9MD_01, PK9MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PK8MD_00, PK8MD_01, PK8MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PKCR1", 0xfffe392c, 16, 4) {
PK7MD_00, PK7MD_01, PK7MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PK6MD_00, PK6MD_01, PK6MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PK5MD_00, PK5MD_01, PK5MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PK4MD_00, PK4MD_01, PK4MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PKCR0", 0xfffe392e, 16, 4) {
PK3MD_00, PK3MD_01, PK3MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PK2MD_00, PK2MD_01, PK2MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PK1MD_00, PK1MD_01, PK1MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
PK0MD_00, PK0MD_01, PK0MD_10, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0 }
},
{ PINMUX_CFG_REG("PKIOR0", 0xfffe3932, 16, 1) {
0, 0, 0, 0, 0, 0, 0, 0,
PJ11_IN, PJ11_OUT,
PJ10_IN, PJ10_OUT,
PJ9_IN, PJ9_OUT,
PJ8_IN, PJ8_OUT,
PJ7_IN, PJ7_OUT,
PJ6_IN, PJ6_OUT,
PJ5_IN, PJ5_OUT,
PJ4_IN, PJ4_OUT,
PJ3_IN, PJ3_OUT,
PJ2_IN, PJ2_OUT,
PJ1_IN, PJ1_OUT,
PJ0_IN, PJ0_OUT }
},
{}
};
static struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR1", 0xfffe3814, 16) {
0, 0, 0, 0, 0, 0, 0, PA3_DATA,
0, 0, 0, 0, 0, 0, 0, PA2_DATA }
},
{ PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) {
0, 0, 0, 0, 0, 0, 0, PA1_DATA,
0, 0, 0, 0, 0, 0, 0, PA0_DATA }
},
{ PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16) {
0, 0, 0, 0, 0, 0, 0, 0,
0, PB22_DATA, PB21_DATA, PB20_DATA,
PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA }
},
{ PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16) {
PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA,
PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
PB3_DATA, PB2_DATA, PB1_DATA, 0 }
},
{ PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16) {
0, 0, 0, 0,
0, PC10_DATA, PC9_DATA, PC8_DATA,
PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
},
{ PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16) {
PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
},
{ PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16) {
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, PE5_DATA, PE4_DATA,
PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA }
},
{ PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16) {
0, 0, 0, PF12_DATA,
PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
},
{ PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16) {
0, 0, 0, 0, 0, 0, 0, PG24_DATA,
PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA,
PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA }
},
{ PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16) {
PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA,
PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA,
PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA }
},
{ PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16) {
0, 0, 0, PJ12_DATA,
PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA,
PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA }
},
{ PINMUX_DATA_REG("PKDR0", 0xfffe3936, 16) {
0, 0, 0, PK12_DATA,
PK11_DATA, PK10_DATA, PK9_DATA, PK8_DATA,
PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA }
},
{ }
};
static struct pinmux_info sh7264_pinmux_info = {
.name = "sh7264_pfc",
.reserved_id = PINMUX_RESERVED,
.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
.first_gpio = GPIO_PA3,
.last_gpio = GPIO_FN_LCD_M_DISP,
.gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
.gpio_data = pinmux_data,
.gpio_data_size = ARRAY_SIZE(pinmux_data),
};
static int __init plat_pinmux_setup(void)
{
return register_pinmux(&sh7264_pinmux_info);
}
arch_initcall(plat_pinmux_setup);
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