Commit 45c2da62 authored by Jim Lin's avatar Jim Lin Committed by Greg Kroah-Hartman

USB: EHCI: Tegra: Fix wrong register definition

Fix the issue that EHCI registers, hostpc[0] and usbmode_ex,
are not correctly accessed on Tegra3 platform.
Signed-off-by: default avatarJim Lin <jilin@nvidia.com>
Acked-by: default avatarAlan Stern <stern@rowland.harvard.edu>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 8d733e26
...@@ -171,18 +171,18 @@ struct ehci_regs { ...@@ -171,18 +171,18 @@ struct ehci_regs {
#define USBMODE_CM_HC (3<<0) /* host controller mode */ #define USBMODE_CM_HC (3<<0) /* host controller mode */
#define USBMODE_CM_IDLE (0<<0) /* idle state */ #define USBMODE_CM_IDLE (0<<0) /* idle state */
u32 reserved4[7]; u32 reserved4[6];
/* Moorestown has some non-standard registers, partially due to the fact that /* Moorestown has some non-standard registers, partially due to the fact that
* its EHCI controller has both TT and LPM support. HOSTPCx are extensions to * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to
* PORTSCx * PORTSCx
*/ */
/* HOSTPC: offset 0x84 */ /* HOSTPC: offset 0x84 */
u32 hostpc[0]; /* HOSTPC extension */ u32 hostpc[1]; /* HOSTPC extension */
#define HOSTPC_PHCD (1<<22) /* Phy clock disable */ #define HOSTPC_PHCD (1<<22) /* Phy clock disable */
#define HOSTPC_PSPD (3<<25) /* Port speed detection */ #define HOSTPC_PSPD (3<<25) /* Port speed detection */
u32 reserved5[17]; u32 reserved5[16];
/* USBMODE_EX: offset 0xc8 */ /* USBMODE_EX: offset 0xc8 */
u32 usbmode_ex; /* USB Device mode extension */ u32 usbmode_ex; /* USB Device mode extension */
......
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