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Commit 4652ae7a authored by Harry Wentland's avatar Harry Wentland Committed by Alex Deucher
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drm/amd/display: Rename DCN config to FP 

[Why & How]
The only reason we have the DCN config is for
floating point support. Rename it to make that
clear and (hopefully) avoid misuse of the config
in the future.
Reviewed-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c186c13e
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Showing with 32 additions and 32 deletions
drivers/gpu/drm/amd/display/Kconfig
View file @ 4652ae7a
...@@ -8,7 +8,7 @@ config DRM_AMD_DC ...@@ -8,7 +8,7 @@ config DRM_AMD_DC
depends on BROKEN || !CC_IS_CLANG || X86_64 || SPARC64 || ARM64 depends on BROKEN || !CC_IS_CLANG || X86_64 || SPARC64 || ARM64
select SND_HDA_COMPONENT if SND_HDA_CORE select SND_HDA_COMPONENT if SND_HDA_CORE
# !CC_IS_CLANG: https://github.com/ClangBuiltLinux/linux/issues/1752 # !CC_IS_CLANG: https://github.com/ClangBuiltLinux/linux/issues/1752
select DRM_AMD_DC_DCN if (X86 || PPC_LONG_DOUBLE_128 || (ARM64 && KERNEL_MODE_NEON && !CC_IS_CLANG)) select DRM_AMD_DC_FP if (X86 || PPC64 || (ARM64 && KERNEL_MODE_NEON && !CC_IS_CLANG))
help help
Choose this option if you want to use the new display engine Choose this option if you want to use the new display engine
support for AMDGPU. This adds required support for Vega and support for AMDGPU. This adds required support for Vega and
...@@ -20,10 +20,10 @@ config DRM_AMD_DC ...@@ -20,10 +20,10 @@ config DRM_AMD_DC
panic on most architectures. We'll revert this when the following bug report panic on most architectures. We'll revert this when the following bug report
has been resolved: https://github.com/llvm/llvm-project/issues/41896. has been resolved: https://github.com/llvm/llvm-project/issues/41896.
config DRM_AMD_DC_DCN config DRM_AMD_DC_FP
def_bool n def_bool n
help help
Raven, Navi, and newer family support for display engine Floating point support, required for DCN-based SoCs
config DRM_AMD_DC_SI config DRM_AMD_DC_SI
bool "AMD DC support for Southern Islands ASICs" bool "AMD DC support for Southern Islands ASICs"
...@@ -44,7 +44,7 @@ config DEBUG_KERNEL_DC ...@@ -44,7 +44,7 @@ config DEBUG_KERNEL_DC
config DRM_AMD_SECURE_DISPLAY config DRM_AMD_SECURE_DISPLAY
bool "Enable secure display support" bool "Enable secure display support"
depends on DEBUG_FS depends on DEBUG_FS
depends on DRM_AMD_DC_DCN depends on DRM_AMD_DC_FP
help help
Choose this option if you want to Choose this option if you want to
support secure display support secure display
......
drivers/gpu/drm/amd/display/amdgpu_dm/Makefile
View file @ 4652ae7a
...@@ -33,7 +33,7 @@ AMDGPUDM = \ ...@@ -33,7 +33,7 @@ AMDGPUDM = \
amdgpu_dm_mst_types.o \ amdgpu_dm_mst_types.o \
amdgpu_dm_color.o amdgpu_dm_color.o
ifdef CONFIG_DRM_AMD_DC_DCN ifdef CONFIG_DRM_AMD_DC_FP
AMDGPUDM += dc_fpu.o AMDGPUDM += dc_fpu.o
endif endif
......
drivers/gpu/drm/amd/display/dc/Makefile
View file @ 4652ae7a
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
DC_LIBS = basics bios dml clk_mgr dce gpio irq link virtual dsc DC_LIBS = basics bios dml clk_mgr dce gpio irq link virtual dsc
ifdef CONFIG_DRM_AMD_DC_DCN ifdef CONFIG_DRM_AMD_DC_FP
KCOV_INSTRUMENT := n KCOV_INSTRUMENT := n
......
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
View file @ 4652ae7a
...@@ -2064,7 +2064,7 @@ static enum bp_result bios_parser_get_encoder_cap_info( ...@@ -2064,7 +2064,7 @@ static enum bp_result bios_parser_get_encoder_cap_info(
if (!info) if (!info)
return BP_RESULT_BADINPUT; return BP_RESULT_BADINPUT;
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_FP)
/* encoder cap record not available in v1_5 */ /* encoder cap record not available in v1_5 */
if (bp->object_info_tbl.revision.minor == 5) if (bp->object_info_tbl.revision.minor == 5)
return BP_RESULT_NORECORD; return BP_RESULT_NORECORD;
......
drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
View file @ 4652ae7a
...@@ -74,7 +74,7 @@ CLK_MGR_DCE120 = dce120_clk_mgr.o ...@@ -74,7 +74,7 @@ CLK_MGR_DCE120 = dce120_clk_mgr.o
AMD_DAL_CLK_MGR_DCE120 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce120/,$(CLK_MGR_DCE120)) AMD_DAL_CLK_MGR_DCE120 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce120/,$(CLK_MGR_DCE120))
AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCE120) AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCE120)
ifdef CONFIG_DRM_AMD_DC_DCN ifdef CONFIG_DRM_AMD_DC_FP
############################################################################### ###############################################################################
# DCN10 # DCN10
############################################################################### ###############################################################################
......
drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
View file @ 4652ae7a
...@@ -221,7 +221,7 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p ...@@ -221,7 +221,7 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
dce120_clk_mgr_construct(ctx, clk_mgr); dce120_clk_mgr_construct(ctx, clk_mgr);
return &clk_mgr->base; return &clk_mgr->base;
} }
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_FP)
case FAMILY_RV: { case FAMILY_RV: {
struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
...@@ -351,7 +351,7 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p ...@@ -351,7 +351,7 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
} }
break; break;
#endif #endif /* CONFIG_DRM_AMD_DC_FP - Family RV */
default: default:
ASSERT(0); /* Unknown Asic */ ASSERT(0); /* Unknown Asic */
break; break;
...@@ -364,7 +364,7 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) ...@@ -364,7 +364,7 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
{ {
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
#ifdef CONFIG_DRM_AMD_DC_DCN #ifdef CONFIG_DRM_AMD_DC_FP
switch (clk_mgr_base->ctx->asic_id.chip_family) { switch (clk_mgr_base->ctx->asic_id.chip_family) {
case FAMILY_NV: case FAMILY_NV:
if (ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { if (ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {
...@@ -405,7 +405,7 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) ...@@ -405,7 +405,7 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
default: default:
break; break;
} }
#endif #endif /* CONFIG_DRM_AMD_DC_FP */
kfree(clk_mgr); kfree(clk_mgr);
} }
......
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
View file @ 4652ae7a
...@@ -706,7 +706,7 @@ void rn_clk_mgr_construct( ...@@ -706,7 +706,7 @@ void rn_clk_mgr_construct(
enum pp_smu_status status = 0; enum pp_smu_status status = 0;
int is_green_sardine = 0; int is_green_sardine = 0;
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_FP)
is_green_sardine = ASICREV_IS_GREEN_SARDINE(ctx->asic_id.hw_internal_rev); is_green_sardine = ASICREV_IS_GREEN_SARDINE(ctx->asic_id.hw_internal_rev);
#endif #endif
......
drivers/gpu/drm/amd/display/dc/core/dc.c
View file @ 4652ae7a
...@@ -994,7 +994,7 @@ static bool dc_construct(struct dc *dc, ...@@ -994,7 +994,7 @@ static bool dc_construct(struct dc *dc,
dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg);
if (!dc->clk_mgr) if (!dc->clk_mgr)
goto fail; goto fail;
#ifdef CONFIG_DRM_AMD_DC_DCN #ifdef CONFIG_DRM_AMD_DC_FP
dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present; dc->clk_mgr->force_smu_not_present = init_params->force_smu_not_present;
if (dc->res_pool->funcs->update_bw_bounding_box) { if (dc->res_pool->funcs->update_bw_bounding_box) {
......
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
View file @ 4652ae7a
...@@ -232,7 +232,7 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, ...@@ -232,7 +232,7 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc,
init_data->num_virtual_links, dc); init_data->num_virtual_links, dc);
break; break;
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_FP)
case DCN_VERSION_1_0: case DCN_VERSION_1_0:
case DCN_VERSION_1_01: case DCN_VERSION_1_01:
res_pool = dcn10_create_resource_pool(init_data, dc); res_pool = dcn10_create_resource_pool(init_data, dc);
...@@ -276,7 +276,7 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, ...@@ -276,7 +276,7 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc,
case DCN_VERSION_3_21: case DCN_VERSION_3_21:
res_pool = dcn321_create_resource_pool(init_data, dc); res_pool = dcn321_create_resource_pool(init_data, dc);
break; break;
#endif #endif /* CONFIG_DRM_AMD_DC_FP */
default: default:
break; break;
} }
...@@ -4027,14 +4027,14 @@ bool dc_resource_acquire_secondary_pipe_for_mpc_odm( ...@@ -4027,14 +4027,14 @@ bool dc_resource_acquire_secondary_pipe_for_mpc_odm(
else else
sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp; sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
if (sec_pipe->stream->timing.flags.DSC == 1) { if (sec_pipe->stream->timing.flags.DSC == 1) {
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_FP)
dcn20_acquire_dsc(dc, &state->res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); dcn20_acquire_dsc(dc, &state->res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
#endif #endif
ASSERT(sec_pipe->stream_res.dsc); ASSERT(sec_pipe->stream_res.dsc);
if (sec_pipe->stream_res.dsc == NULL) if (sec_pipe->stream_res.dsc == NULL)
return false; return false;
} }
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_FP)
dcn20_build_mapped_resource(dc, state, sec_pipe->stream); dcn20_build_mapped_resource(dc, state, sec_pipe->stream);
#endif #endif
} }
......
drivers/gpu/drm/amd/display/dc/dc.h
View file @ 4652ae7a
...@@ -2054,7 +2054,7 @@ struct dc_sink_dsc_caps { ...@@ -2054,7 +2054,7 @@ struct dc_sink_dsc_caps {
// 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
// 'false' if they are sink's DSC caps // 'false' if they are sink's DSC caps
bool is_virtual_dpcd_dsc; bool is_virtual_dpcd_dsc;
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_FP)
// 'true' if MST topology supports DSC passthrough for sink // 'true' if MST topology supports DSC passthrough for sink
// 'false' if MST topology does not support DSC passthrough // 'false' if MST topology does not support DSC passthrough
bool is_dsc_passthrough_supported; bool is_dsc_passthrough_supported;
......
drivers/gpu/drm/amd/display/dc/dc_hw_types.h
View file @ 4652ae7a
...@@ -829,7 +829,7 @@ struct dc_dsc_config { ...@@ -829,7 +829,7 @@ struct dc_dsc_config {
uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */ uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */
bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */ bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */
int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_FP)
bool is_frl; /* indicate if DSC is applied based on HDMI FRL sink's capability */ bool is_frl; /* indicate if DSC is applied based on HDMI FRL sink's capability */
#endif #endif
bool is_dp; /* indicate if DSC is applied based on DP's capability */ bool is_dp; /* indicate if DSC is applied based on DP's capability */
......
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
View file @ 4652ae7a
...@@ -97,7 +97,7 @@ static void enable_memory_low_power(struct dc *dc) ...@@ -97,7 +97,7 @@ static void enable_memory_low_power(struct dc *dc)
// Power down VPGs // Power down VPGs
for (i = 0; i < dc->res_pool->stream_enc_count; i++) for (i = 0; i < dc->res_pool->stream_enc_count; i++)
dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg); dc->res_pool->stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->stream_enc[i]->vpg);
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_FP)
for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++) for (i = 0; i < dc->res_pool->hpo_dp_stream_enc_count; i++)
dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg); dc->res_pool->hpo_dp_stream_enc[i]->vpg->funcs->vpg_powerdown(dc->res_pool->hpo_dp_stream_enc[i]->vpg);
#endif #endif
...@@ -291,7 +291,7 @@ void dcn31_init_hw(struct dc *dc) ...@@ -291,7 +291,7 @@ void dcn31_init_hw(struct dc *dc)
if (dc->res_pool->hubbub->funcs->force_pstate_change_control) if (dc->res_pool->hubbub->funcs->force_pstate_change_control)
dc->res_pool->hubbub->funcs->force_pstate_change_control( dc->res_pool->hubbub->funcs->force_pstate_change_control(
dc->res_pool->hubbub, false, false); dc->res_pool->hubbub, false, false);
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_FP)
if (dc->res_pool->hubbub->funcs->init_crb) if (dc->res_pool->hubbub->funcs->init_crb)
dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub); dc->res_pool->hubbub->funcs->init_crb(dc->res_pool->hubbub);
#endif #endif
......
drivers/gpu/drm/amd/display/dc/dml/Makefile
View file @ 4652ae7a
...@@ -128,7 +128,7 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/calcs/dcn_calc_math.o := $(dml_rcflags) ...@@ -128,7 +128,7 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/calcs/dcn_calc_math.o := $(dml_rcflags)
DML = calcs/dce_calcs.o calcs/custom_float.o calcs/bw_fixed.o DML = calcs/dce_calcs.o calcs/custom_float.o calcs/bw_fixed.o
ifdef CONFIG_DRM_AMD_DC_DCN ifdef CONFIG_DRM_AMD_DC_FP
DML += display_mode_lib.o display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o DML += display_mode_lib.o display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o
DML += dcn10/dcn10_fpu.o DML += dcn10/dcn10_fpu.o
DML += dcn20/dcn20_fpu.o DML += dcn20/dcn20_fpu.o
......
drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
View file @ 4652ae7a
...@@ -39,7 +39,7 @@ ...@@ -39,7 +39,7 @@
*/ */
void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps) void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps)
{ {
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_FP)
enum colour_mode mode; enum colour_mode mode;
enum bits_per_comp bpc; enum bits_per_comp bpc;
bool is_navite_422_or_420; bool is_navite_422_or_420;
......
drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
View file @ 4652ae7a
...@@ -202,7 +202,7 @@ struct dwbc_funcs { ...@@ -202,7 +202,7 @@ struct dwbc_funcs {
struct dwb_warmup_params *warmup_params); struct dwb_warmup_params *warmup_params);
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_FP)
void (*dwb_program_output_csc)( void (*dwb_program_output_csc)(
struct dwbc *dwbc, struct dwbc *dwbc,
......
drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
View file @ 4652ae7a
...@@ -146,7 +146,7 @@ struct hubp_funcs { ...@@ -146,7 +146,7 @@ struct hubp_funcs {
void (*set_blank)(struct hubp *hubp, bool blank); void (*set_blank)(struct hubp *hubp, bool blank);
void (*set_blank_regs)(struct hubp *hubp, bool blank); void (*set_blank_regs)(struct hubp *hubp, bool blank);
#ifdef CONFIG_DRM_AMD_DC_DCN #ifdef CONFIG_DRM_AMD_DC_FP
void (*phantom_hubp_post_enable)(struct hubp *hubp); void (*phantom_hubp_post_enable)(struct hubp *hubp);
#endif #endif
void (*set_hubp_blank_en)(struct hubp *hubp, bool blank); void (*set_hubp_blank_en)(struct hubp *hubp, bool blank);
......
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
View file @ 4652ae7a
...@@ -182,7 +182,7 @@ struct timing_generator_funcs { ...@@ -182,7 +182,7 @@ struct timing_generator_funcs {
bool (*enable_crtc)(struct timing_generator *tg); bool (*enable_crtc)(struct timing_generator *tg);
bool (*disable_crtc)(struct timing_generator *tg); bool (*disable_crtc)(struct timing_generator *tg);
#ifdef CONFIG_DRM_AMD_DC_DCN #ifdef CONFIG_DRM_AMD_DC_FP
void (*phantom_crtc_post_enable)(struct timing_generator *tg); void (*phantom_crtc_post_enable)(struct timing_generator *tg);
#endif #endif
void (*disable_phantom_crtc)(struct timing_generator *tg); void (*disable_phantom_crtc)(struct timing_generator *tg);
......
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h
View file @ 4652ae7a
...@@ -148,7 +148,7 @@ struct hwseq_private_funcs { ...@@ -148,7 +148,7 @@ struct hwseq_private_funcs {
void (*PLAT_58856_wa)(struct dc_state *context, void (*PLAT_58856_wa)(struct dc_state *context,
struct pipe_ctx *pipe_ctx); struct pipe_ctx *pipe_ctx);
void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable); void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);
#ifdef CONFIG_DRM_AMD_DC_DCN #ifdef CONFIG_DRM_AMD_DC_FP
void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context); void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context);
void (*subvp_update_force_pstate)(struct dc *dc, struct dc_state *context); void (*subvp_update_force_pstate)(struct dc *dc, struct dc_state *context);
void (*update_mall_sel)(struct dc *dc, struct dc_state *context); void (*update_mall_sel)(struct dc *dc, struct dc_state *context);
......
drivers/gpu/drm/amd/display/dc/inc/resource.h
View file @ 4652ae7a
...@@ -201,7 +201,7 @@ bool get_temp_dp_link_res(struct dc_link *link, ...@@ -201,7 +201,7 @@ bool get_temp_dp_link_res(struct dc_link *link,
struct link_resource *link_res, struct link_resource *link_res,
struct dc_link_settings *link_settings); struct dc_link_settings *link_settings);
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_FP)
struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt( struct hpo_dp_link_encoder *resource_get_hpo_dp_link_enc_for_det_lt(
const struct resource_context *res_ctx, const struct resource_context *res_ctx,
const struct resource_pool *pool, const struct resource_pool *pool,
......
drivers/gpu/drm/amd/display/dc/link/link_validation.c
View file @ 4652ae7a
...@@ -124,7 +124,7 @@ static bool dp_active_dongle_validate_timing( ...@@ -124,7 +124,7 @@ static bool dp_active_dongle_validate_timing(
if (dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps > 0) { // DP to HDMI FRL converter if (dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps > 0) { // DP to HDMI FRL converter
struct dc_crtc_timing outputTiming = *timing; struct dc_crtc_timing outputTiming = *timing;
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_FP)
if (timing->flags.DSC && !timing->dsc_cfg.is_frl) if (timing->flags.DSC && !timing->dsc_cfg.is_frl)
/* DP input has DSC, HDMI FRL output doesn't have DSC, remove DSC from output timing */ /* DP input has DSC, HDMI FRL output doesn't have DSC, remove DSC from output timing */
outputTiming.flags.DSC = 0; outputTiming.flags.DSC = 0;
......
drivers/gpu/drm/amd/display/dc/os_types.h
View file @ 4652ae7a
...@@ -53,11 +53,11 @@ ...@@ -53,11 +53,11 @@
#define dm_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__) #define dm_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__)
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_FP)
#include "amdgpu_dm/dc_fpu.h" #include "amdgpu_dm/dc_fpu.h"
#define DC_FP_START() dc_fpu_begin(__func__, __LINE__) #define DC_FP_START() dc_fpu_begin(__func__, __LINE__)
#define DC_FP_END() dc_fpu_end(__func__, __LINE__) #define DC_FP_END() dc_fpu_end(__func__, __LINE__)
#endif #endif /* CONFIG_DRM_AMD_DC_FP */
/* /*
* *
......
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