Commit 469030d4 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC platform updates from Olof Johansson:
 "Most of these are smaller fixes that have accrued, and some continued
  cleanup of OMAP platforms towards shared frameworks.

  One new SoC from Atmel/Microchip: sam9x60"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (35 commits)
  ARM: OMAP2+: Fix undefined reference to omap_secure_init
  ARM: s3c64xx: Drop unneeded select of TIMER_OF
  ARM: exynos: Drop unneeded select of MIGHT_HAVE_CACHE_L2X0
  ARM: s3c24xx: Switch to atomic pwm API in rx1950
  ARM: OMAP2+: sleep43xx: Call secure suspend/resume handlers
  ARM: OMAP2+: Use ARM SMC Calling Convention when OP-TEE is available
  ARM: OMAP2+: Introduce check for OP-TEE in omap_secure_init()
  ARM: OMAP2+: Add omap_secure_init callback hook for secure initialization
  ARM: at91: Documentation: add sam9x60 product and datasheet
  ARM: at91: pm: use of_device_id array to find the proper shdwc node
  ARM: at91: pm: use SAM9X60 PMC's compatible
  ARM: imx: only select ARM_ERRATA_814220 for ARMv7-A
  ARM: zynq: use physical cpuid in zynq_slcr_cpu_stop/start
  ARM: tegra: Use clk_m CPU on Tegra124 LP1 resume
  ARM: tegra: Modify reshift divider during LP1
  ARM: tegra: Enable PLLP bypass during Tegra124 LP1
  ARM: samsung: Rename Samsung and Exynos to lowercase
  ARM: exynos: Correct the help text for platform Kconfig option
  ARM: bcm: Select ARM_AMBA for ARCH_BRCMSTB
  ARM: brcmstb: Add debug UART entry for 7216
  ...
parents b85080c1 d8430df1
...@@ -92,6 +92,12 @@ the Microchip website: http://www.microchip.com. ...@@ -92,6 +92,12 @@ the Microchip website: http://www.microchip.com.
http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001517A.pdf http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001517A.pdf
- sam9x60
* Datasheet
http://ww1.microchip.com/downloads/en/DeviceDoc/SAM9X60-Data-Sheet-DS60001579A.pdf
* ARM Cortex-A5 based SoCs * ARM Cortex-A5 based SoCs
- sama5d3 family - sama5d3 family
......
...@@ -147,14 +147,14 @@ choice ...@@ -147,14 +147,14 @@ choice
0x80024000 | 0xf0024000 | UART9 0x80024000 | 0xf0024000 | UART9
config DEBUG_AT91_RM9200_DBGU config DEBUG_AT91_RM9200_DBGU
bool "Kernel low-level debugging on AT91RM9200, AT91SAM9 DBGU" bool "Kernel low-level debugging on AT91RM9200, AT91SAM9, SAM9X60 DBGU"
select DEBUG_AT91_UART select DEBUG_AT91_UART
depends on SOC_AT91RM9200 || SOC_AT91SAM9 depends on SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60
help help
Say Y here if you want kernel low-level debugging support Say Y here if you want kernel low-level debugging support
on the DBGU port of: on the DBGU port of:
at91rm9200, at91sam9260, at91sam9g20, at91sam9261, at91rm9200, at91sam9260, at91sam9g20, at91sam9261,
at91sam9g10, at91sam9n12, at91sam9rl64, at91sam9x5 at91sam9g10, at91sam9n12, at91sam9rl64, at91sam9x5, sam9x60
config DEBUG_AT91_SAM9263_DBGU config DEBUG_AT91_SAM9263_DBGU
bool "Kernel low-level debugging on AT91SAM{9263,9G45,A5D3} DBGU" bool "Kernel low-level debugging on AT91SAM{9263,9G45,A5D3} DBGU"
......
...@@ -31,6 +31,7 @@ ...@@ -31,6 +31,7 @@
#define UARTA_7268 UARTA_7255 #define UARTA_7268 UARTA_7255
#define UARTA_7271 UARTA_7268 #define UARTA_7271 UARTA_7268
#define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000) #define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000)
#define UARTA_7216 UARTA_7278
#define UARTA_7364 REG_PHYS_ADDR(0x40b000) #define UARTA_7364 REG_PHYS_ADDR(0x40b000)
#define UARTA_7366 UARTA_7364 #define UARTA_7366 UARTA_7364
#define UARTA_74371 REG_PHYS_ADDR(0x406b00) #define UARTA_74371 REG_PHYS_ADDR(0x406b00)
...@@ -82,17 +83,18 @@ ARM_BE8( rev \rv, \rv ) ...@@ -82,17 +83,18 @@ ARM_BE8( rev \rv, \rv )
/* Chip specific detection starts here */ /* Chip specific detection starts here */
20: checkuart(\rp, \rv, 0x33900000, 3390) 20: checkuart(\rp, \rv, 0x33900000, 3390)
21: checkuart(\rp, \rv, 0x72500000, 7250) 21: checkuart(\rp, \rv, 0x72160000, 7216)
22: checkuart(\rp, \rv, 0x72550000, 7255) 22: checkuart(\rp, \rv, 0x72500000, 7250)
23: checkuart(\rp, \rv, 0x72600000, 7260) 23: checkuart(\rp, \rv, 0x72550000, 7255)
24: checkuart(\rp, \rv, 0x72680000, 7268) 24: checkuart(\rp, \rv, 0x72600000, 7260)
25: checkuart(\rp, \rv, 0x72710000, 7271) 25: checkuart(\rp, \rv, 0x72680000, 7268)
26: checkuart(\rp, \rv, 0x72780000, 7278) 26: checkuart(\rp, \rv, 0x72710000, 7271)
27: checkuart(\rp, \rv, 0x73640000, 7364) 27: checkuart(\rp, \rv, 0x72780000, 7278)
28: checkuart(\rp, \rv, 0x73660000, 7366) 28: checkuart(\rp, \rv, 0x73640000, 7364)
29: checkuart(\rp, \rv, 0x07437100, 74371) 29: checkuart(\rp, \rv, 0x73660000, 7366)
30: checkuart(\rp, \rv, 0x74390000, 7439) 30: checkuart(\rp, \rv, 0x07437100, 74371)
31: checkuart(\rp, \rv, 0x74450000, 7445) 31: checkuart(\rp, \rv, 0x74390000, 7439)
32: checkuart(\rp, \rv, 0x74450000, 7445)
/* No valid UART found */ /* No valid UART found */
90: mov \rp, #0 90: mov \rp, #0
......
...@@ -105,11 +105,28 @@ config SOC_AT91SAM9 ...@@ -105,11 +105,28 @@ config SOC_AT91SAM9
AT91SAM9X35 AT91SAM9X35
AT91SAM9XE AT91SAM9XE
config SOC_SAM9X60
bool "SAM9X60"
depends on ARCH_MULTI_V5
select ATMEL_AIC5_IRQ
select ATMEL_PM if PM
select ATMEL_SDRAMC
select CPU_ARM926T
select HAVE_AT91_USB_CLK
select HAVE_AT91_GENERATED_CLK
select HAVE_AT91_SAM9X60_PLL
select MEMORY
select PINCTRL_AT91
select SOC_SAM_V4_V5
select SRAM if PM
help
Select this if you are using Microchip's SAM9X60 SoC
comment "Clocksource driver selection" comment "Clocksource driver selection"
config ATMEL_CLOCKSOURCE_PIT config ATMEL_CLOCKSOURCE_PIT
bool "Periodic Interval Timer (PIT) support" bool "Periodic Interval Timer (PIT) support"
depends on SOC_AT91SAM9 || SOC_SAMA5 depends on SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5
default SOC_AT91SAM9 || SOC_SAMA5 default SOC_AT91SAM9 || SOC_SAMA5
select ATMEL_PIT select ATMEL_PIT
help help
...@@ -119,7 +136,7 @@ config ATMEL_CLOCKSOURCE_PIT ...@@ -119,7 +136,7 @@ config ATMEL_CLOCKSOURCE_PIT
config ATMEL_CLOCKSOURCE_TCB config ATMEL_CLOCKSOURCE_TCB
bool "Timer Counter Blocks (TCB) support" bool "Timer Counter Blocks (TCB) support"
default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAMA5 default SOC_AT91RM9200 || SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5
select ATMEL_TCB_CLKSRC select ATMEL_TCB_CLKSRC
help help
Select this to get a high precision clocksource based on a Select this to get a high precision clocksource based on a
...@@ -154,6 +171,9 @@ config HAVE_AT91_AUDIO_PLL ...@@ -154,6 +171,9 @@ config HAVE_AT91_AUDIO_PLL
config HAVE_AT91_I2S_MUX_CLK config HAVE_AT91_I2S_MUX_CLK
bool bool
config HAVE_AT91_SAM9X60_PLL
bool
config SOC_SAM_V4_V5 config SOC_SAM_V4_V5
bool bool
......
...@@ -6,6 +6,7 @@ ...@@ -6,6 +6,7 @@
# CPU-specific support # CPU-specific support
obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o obj-$(CONFIG_SOC_AT91RM9200) += at91rm9200.o
obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o obj-$(CONFIG_SOC_AT91SAM9) += at91sam9.o
obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o
obj-$(CONFIG_SOC_SAMA5) += sama5.o obj-$(CONFIG_SOC_SAMA5) += sama5.o
obj-$(CONFIG_SOC_SAMV7) += samv7.o obj-$(CONFIG_SOC_SAMV7) += samv7.o
......
...@@ -31,21 +31,3 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM9") ...@@ -31,21 +31,3 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM9")
.init_machine = at91sam9_init, .init_machine = at91sam9_init,
.dt_compat = at91_dt_board_compat, .dt_compat = at91_dt_board_compat,
MACHINE_END MACHINE_END
static void __init sam9x60_init(void)
{
of_platform_default_populate(NULL, NULL, NULL);
sam9x60_pm_init();
}
static const char *const sam9x60_dt_board_compat[] __initconst = {
"microchip,sam9x60",
NULL
};
DT_MACHINE_START(sam9x60_dt, "Microchip SAM9X60")
/* Maintainer: Microchip */
.init_machine = sam9x60_init,
.dt_compat = sam9x60_dt_board_compat,
MACHINE_END
...@@ -691,6 +691,12 @@ static void __init at91_pm_use_default_mode(int pm_mode) ...@@ -691,6 +691,12 @@ static void __init at91_pm_use_default_mode(int pm_mode)
soc_pm.data.suspend_mode = AT91_PM_ULP0; soc_pm.data.suspend_mode = AT91_PM_ULP0;
} }
static const struct of_device_id atmel_shdwc_ids[] = {
{ .compatible = "atmel,sama5d2-shdwc" },
{ .compatible = "microchip,sam9x60-shdwc" },
{ /* sentinel. */ }
};
static void __init at91_pm_modes_init(void) static void __init at91_pm_modes_init(void)
{ {
struct device_node *np; struct device_node *np;
...@@ -700,7 +706,7 @@ static void __init at91_pm_modes_init(void) ...@@ -700,7 +706,7 @@ static void __init at91_pm_modes_init(void)
!at91_is_pm_mode_active(AT91_PM_ULP1)) !at91_is_pm_mode_active(AT91_PM_ULP1))
return; return;
np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-shdwc"); np = of_find_matching_node(NULL, atmel_shdwc_ids);
if (!np) { if (!np) {
pr_warn("%s: failed to find shdwc!\n", __func__); pr_warn("%s: failed to find shdwc!\n", __func__);
goto ulp1_default; goto ulp1_default;
...@@ -751,6 +757,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = { ...@@ -751,6 +757,7 @@ static const struct of_device_id atmel_pmc_ids[] __initconst = {
{ .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] }, { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
{ .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] }, { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
{ .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] }, { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
{ .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[1] },
{ /* sentinel */ }, { /* sentinel */ },
}; };
...@@ -805,7 +812,7 @@ void __init at91rm9200_pm_init(void) ...@@ -805,7 +812,7 @@ void __init at91rm9200_pm_init(void)
void __init sam9x60_pm_init(void) void __init sam9x60_pm_init(void)
{ {
if (!IS_ENABLED(CONFIG_SOC_AT91SAM9)) if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
return; return;
at91_pm_modes_init(); at91_pm_modes_init();
......
// SPDX-License-Identifier: GPL-2.0+
/*
* Setup code for SAM9X60.
*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
*
* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
*/
#include <linux/of.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include <asm/system_misc.h>
#include "generic.h"
static void __init sam9x60_init(void)
{
of_platform_default_populate(NULL, NULL, NULL);
sam9x60_pm_init();
}
static const char *const sam9x60_dt_board_compat[] __initconst = {
"microchip,sam9x60",
NULL
};
DT_MACHINE_START(sam9x60_dt, "Microchip SAM9X60")
/* Maintainer: Microchip */
.init_machine = sam9x60_init,
.dt_compat = sam9x60_dt_board_compat,
MACHINE_END
...@@ -211,6 +211,7 @@ config ARCH_BRCMSTB ...@@ -211,6 +211,7 @@ config ARCH_BRCMSTB
bool "Broadcom BCM7XXX based boards" bool "Broadcom BCM7XXX based boards"
depends on ARCH_MULTI_V7 depends on ARCH_MULTI_V7
select ARCH_HAS_RESET_CONTROLLER select ARCH_HAS_RESET_CONTROLLER
select ARM_AMBA
select ARM_GIC select ARM_GIC
select ARM_ERRATA_798181 if SMP select ARM_ERRATA_798181 if SMP
select HAVE_ARM_ARCH_TIMER select HAVE_ARM_ARCH_TIMER
......
...@@ -3,10 +3,10 @@ ...@@ -3,10 +3,10 @@
# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. # Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
# http://www.samsung.com/ # http://www.samsung.com/
# Configuration options for the EXYNOS # Configuration options for the Samsung Exynos
menuconfig ARCH_EXYNOS menuconfig ARCH_EXYNOS
bool "Samsung EXYNOS" bool "Samsung Exynos"
depends on ARCH_MULTI_V7 depends on ARCH_MULTI_V7
select ARCH_HAS_HOLES_MEMORYMODEL select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_SUPPORTS_BIG_ENDIAN select ARCH_SUPPORTS_BIG_ENDIAN
...@@ -42,7 +42,7 @@ menuconfig ARCH_EXYNOS ...@@ -42,7 +42,7 @@ menuconfig ARCH_EXYNOS
select POWER_RESET_SYSCON select POWER_RESET_SYSCON
select POWER_RESET_SYSCON_POWEROFF select POWER_RESET_SYSCON_POWEROFF
help help
Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5) Support for Samsung Exynos SoCs
if ARCH_EXYNOS if ARCH_EXYNOS
...@@ -52,63 +52,62 @@ config S5P_DEV_MFC ...@@ -52,63 +52,62 @@ config S5P_DEV_MFC
Compile in setup memory (init) code for MFC Compile in setup memory (init) code for MFC
config ARCH_EXYNOS3 config ARCH_EXYNOS3
bool "SAMSUNG EXYNOS3" bool "Samsung Exynos3"
default y default y
select ARM_CPU_SUSPEND if PM select ARM_CPU_SUSPEND if PM
help help
Samsung EXYNOS3 (Cortex-A7) SoC based systems Samsung Exynos3 (Cortex-A7) SoC based systems
config ARCH_EXYNOS4 config ARCH_EXYNOS4
bool "SAMSUNG EXYNOS4" bool "Samsung Exynos4"
default y default y
select ARM_CPU_SUSPEND if PM_SLEEP select ARM_CPU_SUSPEND if PM_SLEEP
select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210 select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210
select CPU_EXYNOS4210 select CPU_EXYNOS4210
select GIC_NON_BANKED select GIC_NON_BANKED
select MIGHT_HAVE_CACHE_L2X0
help help
Samsung EXYNOS4 (Cortex-A9) SoC based systems Samsung Exynos4 (Cortex-A9) SoC based systems
config ARCH_EXYNOS5 config ARCH_EXYNOS5
bool "SAMSUNG EXYNOS5" bool "Samsung Exynos5"
default y default y
help help
Samsung EXYNOS5 (Cortex-A15/A7) SoC based systems Samsung Exynos5 (Cortex-A15/A7) SoC based systems
comment "EXYNOS SoCs" comment "Exynos SoCs"
config SOC_EXYNOS3250 config SOC_EXYNOS3250
bool "SAMSUNG EXYNOS3250" bool "Samsung Exynos3250"
default y default y
depends on ARCH_EXYNOS3 depends on ARCH_EXYNOS3
config CPU_EXYNOS4210 config CPU_EXYNOS4210
bool "SAMSUNG EXYNOS4210" bool "Samsung Exynos4210"
default y default y
depends on ARCH_EXYNOS4 depends on ARCH_EXYNOS4
config SOC_EXYNOS4412 config SOC_EXYNOS4412
bool "SAMSUNG EXYNOS4412" bool "Samsung Exynos4412"
default y default y
depends on ARCH_EXYNOS4 depends on ARCH_EXYNOS4
config SOC_EXYNOS5250 config SOC_EXYNOS5250
bool "SAMSUNG EXYNOS5250" bool "Samsung Exynos5250"
default y default y
depends on ARCH_EXYNOS5 depends on ARCH_EXYNOS5
config SOC_EXYNOS5260 config SOC_EXYNOS5260
bool "SAMSUNG EXYNOS5260" bool "Samsung Exynos5260"
default y default y
depends on ARCH_EXYNOS5 depends on ARCH_EXYNOS5
config SOC_EXYNOS5410 config SOC_EXYNOS5410
bool "SAMSUNG EXYNOS5410" bool "Samsung Exynos5410"
default y default y
depends on ARCH_EXYNOS5 depends on ARCH_EXYNOS5
config SOC_EXYNOS5420 config SOC_EXYNOS5420
bool "SAMSUNG EXYNOS5420" bool "Samsung Exynos5420"
default y default y
depends on ARCH_EXYNOS5 depends on ARCH_EXYNOS5
select EXYNOS_MCPM if SMP select EXYNOS_MCPM if SMP
...@@ -116,7 +115,7 @@ config SOC_EXYNOS5420 ...@@ -116,7 +115,7 @@ config SOC_EXYNOS5420
select ARM_CPU_SUSPEND select ARM_CPU_SUSPEND
config SOC_EXYNOS5800 config SOC_EXYNOS5800
bool "SAMSUNG EXYNOS5800" bool "Samsung EXYNOS5800"
default y default y
depends on SOC_EXYNOS5420 depends on SOC_EXYNOS5420
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* Copyright (c) 2011 Samsung Electronics Co., Ltd. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com * http://www.samsung.com
* *
* Common Header for EXYNOS machines * Common Header for Exynos machines
*/ */
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
......
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
// //
// SAMSUNG EXYNOS Flattened Device Tree enabled machine // Samsung Exynos Flattened Device Tree enabled machine
// //
// Copyright (c) 2010-2014 Samsung Electronics Co., Ltd. // Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
// http://www.samsung.com // http://www.samsung.com
...@@ -192,7 +192,7 @@ static void __init exynos_dt_fixup(void) ...@@ -192,7 +192,7 @@ static void __init exynos_dt_fixup(void)
of_fdt_limit_memory(8); of_fdt_limit_memory(8);
} }
DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)") DT_MACHINE_START(EXYNOS_DT, "Samsung Exynos (Flattened Device Tree)")
.l2c_aux_val = 0x3c400001, .l2c_aux_val = 0x3c400001,
.l2c_aux_mask = 0xc20fffff, .l2c_aux_mask = 0xc20fffff,
.smp = smp_ops(exynos_smp_ops), .smp = smp_ops(exynos_smp_ops),
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/ * http://www.samsung.com/
* *
* EXYNOS - Memory map definitions * Exynos - Memory map definitions
*/ */
#ifndef __ASM_ARCH_MAP_H #ifndef __ASM_ARCH_MAP_H
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
// Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. // Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
// http://www.samsung.com // http://www.samsung.com
// //
// EXYNOS - Power Management support // Exynos - Power Management support
// //
// Based on arch/arm/mach-s3c2410/pm.c // Based on arch/arm/mach-s3c2410/pm.c
// Copyright (c) 2006 Simtec Electronics // Copyright (c) 2006 Simtec Electronics
......
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
/* /*
* Copyright (c) 2012 Samsung Electronics. * Copyright (c) 2012 Samsung Electronics.
* *
* EXYNOS - SMC Call * Exynos - SMC Call
*/ */
#ifndef __ASM_ARCH_EXYNOS_SMC_H #ifndef __ASM_ARCH_EXYNOS_SMC_H
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
// Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. // Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
// http://www.samsung.com // http://www.samsung.com
// //
// EXYNOS - Suspend support // Exynos - Suspend support
// //
// Based on arch/arm/mach-s3c2410/pm.c // Based on arch/arm/mach-s3c2410/pm.c
// Copyright (c) 2006 Simtec Electronics // Copyright (c) 2006 Simtec Electronics
......
...@@ -520,6 +520,7 @@ config SOC_IMX6UL ...@@ -520,6 +520,7 @@ config SOC_IMX6UL
bool "i.MX6 UltraLite support" bool "i.MX6 UltraLite support"
select PINCTRL_IMX6UL select PINCTRL_IMX6UL
select SOC_IMX6 select SOC_IMX6
select ARM_ERRATA_814220
help help
This enables support for Freescale i.MX6 UltraLite processor. This enables support for Freescale i.MX6 UltraLite processor.
...@@ -556,6 +557,7 @@ config SOC_IMX7D ...@@ -556,6 +557,7 @@ config SOC_IMX7D
select PINCTRL_IMX7D select PINCTRL_IMX7D
select SOC_IMX7D_CA7 if ARCH_MULTI_V7 select SOC_IMX7D_CA7 if ARCH_MULTI_V7
select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M select SOC_IMX7D_CM4 if ARM_SINGLE_ARMV7M
select ARM_ERRATA_814220 if ARCH_MULTI_V7
help help
This enables support for Freescale i.MX7 Dual processor. This enables support for Freescale i.MX7 Dual processor.
......
...@@ -15,6 +15,11 @@ ...@@ -15,6 +15,11 @@
#define OCOTP_UID_H 0x420 #define OCOTP_UID_H 0x420
#define OCOTP_UID_L 0x410 #define OCOTP_UID_L 0x410
#define OCOTP_ULP_UID_1 0x4b0
#define OCOTP_ULP_UID_2 0x4c0
#define OCOTP_ULP_UID_3 0x4d0
#define OCOTP_ULP_UID_4 0x4e0
unsigned int __mxc_cpu_type; unsigned int __mxc_cpu_type;
static unsigned int imx_soc_revision; static unsigned int imx_soc_revision;
...@@ -164,6 +169,7 @@ struct device * __init imx_soc_device_init(void) ...@@ -164,6 +169,7 @@ struct device * __init imx_soc_device_init(void)
soc_id = "i.MX7D"; soc_id = "i.MX7D";
break; break;
case MXC_CPU_IMX7ULP: case MXC_CPU_IMX7ULP:
ocotp_compat = "fsl,imx7ulp-ocotp";
soc_id = "i.MX7ULP"; soc_id = "i.MX7ULP";
break; break;
default: default:
...@@ -178,12 +184,26 @@ struct device * __init imx_soc_device_init(void) ...@@ -178,12 +184,26 @@ struct device * __init imx_soc_device_init(void)
} }
if (!IS_ERR_OR_NULL(ocotp)) { if (!IS_ERR_OR_NULL(ocotp)) {
if (__mxc_cpu_type == MXC_CPU_IMX7ULP) {
regmap_read(ocotp, OCOTP_ULP_UID_4, &val);
soc_uid = val & 0xffff;
regmap_read(ocotp, OCOTP_ULP_UID_3, &val);
soc_uid <<= 16;
soc_uid |= val & 0xffff;
regmap_read(ocotp, OCOTP_ULP_UID_2, &val);
soc_uid <<= 16;
soc_uid |= val & 0xffff;
regmap_read(ocotp, OCOTP_ULP_UID_1, &val);
soc_uid <<= 16;
soc_uid |= val & 0xffff;
} else {
regmap_read(ocotp, OCOTP_UID_H, &val); regmap_read(ocotp, OCOTP_UID_H, &val);
soc_uid = val; soc_uid = val;
regmap_read(ocotp, OCOTP_UID_L, &val); regmap_read(ocotp, OCOTP_UID_L, &val);
soc_uid <<= 32; soc_uid <<= 32;
soc_uid |= val; soc_uid |= val;
} }
}
soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d", soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d.%d",
(imx_soc_revision >> 4) & 0xf, (imx_soc_revision >> 4) & 0xf,
......
...@@ -16,10 +16,10 @@ hwmod-common = omap_hwmod.o omap_hwmod_reset.o \ ...@@ -16,10 +16,10 @@ hwmod-common = omap_hwmod.o omap_hwmod_reset.o \
clock-common = clock.o clock-common = clock.o
secure-common = omap-smc.o omap-secure.o secure-common = omap-smc.o omap-secure.o
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common) obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common) obj-$(CONFIG_SOC_AM33XX) += $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common)
......
...@@ -84,6 +84,15 @@ static struct clockdomain l3s_tsc_43xx_clkdm = { ...@@ -84,6 +84,15 @@ static struct clockdomain l3s_tsc_43xx_clkdm = {
.flags = CLKDM_CAN_SWSUP, .flags = CLKDM_CAN_SWSUP,
}; };
static struct clockdomain lcdc_43xx_clkdm = {
.name = "lcdc_clkdm",
.pwrdm = { .name = "per_pwrdm" },
.prcm_partition = AM43XX_CM_PARTITION,
.cm_inst = AM43XX_CM_PER_INST,
.clkdm_offs = AM43XX_CM_PER_LCDC_CDOFFS,
.flags = CLKDM_CAN_SWSUP,
};
static struct clockdomain dss_43xx_clkdm = { static struct clockdomain dss_43xx_clkdm = {
.name = "dss_clkdm", .name = "dss_clkdm",
.pwrdm = { .name = "per_pwrdm" }, .pwrdm = { .name = "per_pwrdm" },
...@@ -173,6 +182,7 @@ static struct clockdomain *clockdomains_am43xx[] __initdata = { ...@@ -173,6 +182,7 @@ static struct clockdomain *clockdomains_am43xx[] __initdata = {
&pruss_ocp_43xx_clkdm, &pruss_ocp_43xx_clkdm,
&ocpwp_l3_43xx_clkdm, &ocpwp_l3_43xx_clkdm,
&l3s_tsc_43xx_clkdm, &l3s_tsc_43xx_clkdm,
&lcdc_43xx_clkdm,
&dss_43xx_clkdm, &dss_43xx_clkdm,
&l3_aon_43xx_clkdm, &l3_aon_43xx_clkdm,
&emif_43xx_clkdm, &emif_43xx_clkdm,
......
...@@ -255,7 +255,7 @@ extern void gic_dist_disable(void); ...@@ -255,7 +255,7 @@ extern void gic_dist_disable(void);
extern void gic_dist_enable(void); extern void gic_dist_enable(void);
extern bool gic_dist_disabled(void); extern bool gic_dist_disabled(void);
extern void gic_timer_retrigger(void); extern void gic_timer_retrigger(void);
extern void omap_smc1(u32 fn, u32 arg); extern void _omap_smc1(u32 fn, u32 arg);
extern void omap4_sar_ram_init(void); extern void omap4_sar_ram_init(void);
extern void __iomem *omap4_get_sar_ram_base(void); extern void __iomem *omap4_get_sar_ram_base(void);
extern void omap4_mpuss_early_init(void); extern void omap4_mpuss_early_init(void);
......
...@@ -51,6 +51,7 @@ ...@@ -51,6 +51,7 @@
#include "prm33xx.h" #include "prm33xx.h"
#include "prm44xx.h" #include "prm44xx.h"
#include "opp2xxx.h" #include "opp2xxx.h"
#include "omap-secure.h"
/* /*
* omap_clk_soc_init: points to a function that does the SoC-specific * omap_clk_soc_init: points to a function that does the SoC-specific
...@@ -430,6 +431,7 @@ void __init omap2420_init_early(void) ...@@ -430,6 +431,7 @@ void __init omap2420_init_early(void)
omap_hwmod_init_postsetup(); omap_hwmod_init_postsetup();
omap_clk_soc_init = omap2420_dt_clk_init; omap_clk_soc_init = omap2420_dt_clk_init;
rate_table = omap2420_rate_table; rate_table = omap2420_rate_table;
omap_secure_init();
} }
void __init omap2420_init_late(void) void __init omap2420_init_late(void)
...@@ -454,6 +456,7 @@ void __init omap2430_init_early(void) ...@@ -454,6 +456,7 @@ void __init omap2430_init_early(void)
omap_hwmod_init_postsetup(); omap_hwmod_init_postsetup();
omap_clk_soc_init = omap2430_dt_clk_init; omap_clk_soc_init = omap2430_dt_clk_init;
rate_table = omap2430_rate_table; rate_table = omap2430_rate_table;
omap_secure_init();
} }
void __init omap2430_init_late(void) void __init omap2430_init_late(void)
...@@ -481,6 +484,7 @@ void __init omap3_init_early(void) ...@@ -481,6 +484,7 @@ void __init omap3_init_early(void)
omap3xxx_clockdomains_init(); omap3xxx_clockdomains_init();
omap3xxx_hwmod_init(); omap3xxx_hwmod_init();
omap_hwmod_init_postsetup(); omap_hwmod_init_postsetup();
omap_secure_init();
} }
void __init omap3430_init_early(void) void __init omap3430_init_early(void)
...@@ -533,6 +537,7 @@ void __init ti814x_init_early(void) ...@@ -533,6 +537,7 @@ void __init ti814x_init_early(void)
dm814x_hwmod_init(); dm814x_hwmod_init();
omap_hwmod_init_postsetup(); omap_hwmod_init_postsetup();
omap_clk_soc_init = dm814x_dt_clk_init; omap_clk_soc_init = dm814x_dt_clk_init;
omap_secure_init();
} }
void __init ti816x_init_early(void) void __init ti816x_init_early(void)
...@@ -549,6 +554,7 @@ void __init ti816x_init_early(void) ...@@ -549,6 +554,7 @@ void __init ti816x_init_early(void)
dm816x_hwmod_init(); dm816x_hwmod_init();
omap_hwmod_init_postsetup(); omap_hwmod_init_postsetup();
omap_clk_soc_init = dm816x_dt_clk_init; omap_clk_soc_init = dm816x_dt_clk_init;
omap_secure_init();
} }
#endif #endif
...@@ -566,6 +572,7 @@ void __init am33xx_init_early(void) ...@@ -566,6 +572,7 @@ void __init am33xx_init_early(void)
am33xx_hwmod_init(); am33xx_hwmod_init();
omap_hwmod_init_postsetup(); omap_hwmod_init_postsetup();
omap_clk_soc_init = am33xx_dt_clk_init; omap_clk_soc_init = am33xx_dt_clk_init;
omap_secure_init();
} }
void __init am33xx_init_late(void) void __init am33xx_init_late(void)
...@@ -589,6 +596,7 @@ void __init am43xx_init_early(void) ...@@ -589,6 +596,7 @@ void __init am43xx_init_early(void)
omap_hwmod_init_postsetup(); omap_hwmod_init_postsetup();
omap_l2_cache_init(); omap_l2_cache_init();
omap_clk_soc_init = am43xx_dt_clk_init; omap_clk_soc_init = am43xx_dt_clk_init;
omap_secure_init();
} }
void __init am43xx_init_late(void) void __init am43xx_init_late(void)
...@@ -617,6 +625,7 @@ void __init omap4430_init_early(void) ...@@ -617,6 +625,7 @@ void __init omap4430_init_early(void)
omap_hwmod_init_postsetup(); omap_hwmod_init_postsetup();
omap_l2_cache_init(); omap_l2_cache_init();
omap_clk_soc_init = omap4xxx_dt_clk_init; omap_clk_soc_init = omap4xxx_dt_clk_init;
omap_secure_init();
} }
void __init omap4430_init_late(void) void __init omap4430_init_late(void)
...@@ -643,6 +652,7 @@ void __init omap5_init_early(void) ...@@ -643,6 +652,7 @@ void __init omap5_init_early(void)
omap54xx_hwmod_init(); omap54xx_hwmod_init();
omap_hwmod_init_postsetup(); omap_hwmod_init_postsetup();
omap_clk_soc_init = omap5xxx_dt_clk_init; omap_clk_soc_init = omap5xxx_dt_clk_init;
omap_secure_init();
} }
void __init omap5_init_late(void) void __init omap5_init_late(void)
...@@ -666,6 +676,7 @@ void __init dra7xx_init_early(void) ...@@ -666,6 +676,7 @@ void __init dra7xx_init_early(void)
dra7xx_hwmod_init(); dra7xx_hwmod_init();
omap_hwmod_init_postsetup(); omap_hwmod_init_postsetup();
omap_clk_soc_init = dra7xx_dt_clk_init; omap_clk_soc_init = dra7xx_dt_clk_init;
omap_secure_init();
} }
void __init dra7xx_init_late(void) void __init dra7xx_init_late(void)
......
...@@ -8,36 +8,134 @@ ...@@ -8,36 +8,134 @@
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/err.h> #include <linux/err.h>
#include <linux/clk.h>
#include <linux/list.h>
#include "omap_hwmod.h" #include "clockdomain.h"
#include "omap_device.h"
#include "powerdomain.h" #include "powerdomain.h"
struct pwrdm_link {
struct device *dev;
struct powerdomain *pwrdm;
struct list_head node;
};
static DEFINE_SPINLOCK(iommu_lock);
static struct clockdomain *emu_clkdm;
static atomic_t emu_count;
static void omap_iommu_dra7_emu_swsup_config(struct platform_device *pdev,
bool enable)
{
struct device_node *np = pdev->dev.of_node;
unsigned long flags;
if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu"))
return;
if (!emu_clkdm) {
emu_clkdm = clkdm_lookup("emu_clkdm");
if (WARN_ON_ONCE(!emu_clkdm))
return;
}
spin_lock_irqsave(&iommu_lock, flags);
if (enable && (atomic_inc_return(&emu_count) == 1))
clkdm_deny_idle(emu_clkdm);
else if (!enable && (atomic_dec_return(&emu_count) == 0))
clkdm_allow_idle(emu_clkdm);
spin_unlock_irqrestore(&iommu_lock, flags);
}
static struct powerdomain *_get_pwrdm(struct device *dev)
{
struct clk *clk;
struct clk_hw_omap *hwclk;
struct clockdomain *clkdm;
struct powerdomain *pwrdm = NULL;
struct pwrdm_link *entry;
unsigned long flags;
static LIST_HEAD(cache);
spin_lock_irqsave(&iommu_lock, flags);
list_for_each_entry(entry, &cache, node) {
if (entry->dev == dev) {
pwrdm = entry->pwrdm;
break;
}
}
spin_unlock_irqrestore(&iommu_lock, flags);
if (pwrdm)
return pwrdm;
clk = of_clk_get(dev->of_node->parent, 0);
if (!clk) {
dev_err(dev, "no fck found\n");
return NULL;
}
hwclk = to_clk_hw_omap(__clk_get_hw(clk));
clk_put(clk);
if (!hwclk || !hwclk->clkdm_name) {
dev_err(dev, "no hwclk data\n");
return NULL;
}
clkdm = clkdm_lookup(hwclk->clkdm_name);
if (!clkdm) {
dev_err(dev, "clkdm not found: %s\n", hwclk->clkdm_name);
return NULL;
}
pwrdm = clkdm_get_pwrdm(clkdm);
if (!pwrdm) {
dev_err(dev, "pwrdm not found: %s\n", clkdm->name);
return NULL;
}
entry = kmalloc(sizeof(*entry), GFP_KERNEL);
if (entry) {
entry->dev = dev;
entry->pwrdm = pwrdm;
spin_lock_irqsave(&iommu_lock, flags);
list_add(&entry->node, &cache);
spin_unlock_irqrestore(&iommu_lock, flags);
}
return pwrdm;
}
int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request, int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request,
u8 *pwrst) u8 *pwrst)
{ {
struct powerdomain *pwrdm; struct powerdomain *pwrdm;
struct omap_device *od;
u8 next_pwrst; u8 next_pwrst;
int ret = 0;
od = to_omap_device(pdev); pwrdm = _get_pwrdm(&pdev->dev);
if (!od)
return -ENODEV;
if (od->hwmods_cnt != 1)
return -EINVAL;
pwrdm = omap_hwmod_get_pwrdm(od->hwmods[0]);
if (!pwrdm) if (!pwrdm)
return -EINVAL; return -ENODEV;
if (request) if (request) {
*pwrst = pwrdm_read_next_pwrst(pwrdm); *pwrst = pwrdm_read_next_pwrst(pwrdm);
omap_iommu_dra7_emu_swsup_config(pdev, true);
}
if (*pwrst > PWRDM_POWER_RET) if (*pwrst > PWRDM_POWER_RET)
return 0; goto out;
next_pwrst = request ? PWRDM_POWER_ON : *pwrst; next_pwrst = request ? PWRDM_POWER_ON : *pwrst;
return pwrdm_set_next_pwrst(pwrdm, next_pwrst); ret = pwrdm_set_next_pwrst(pwrdm, next_pwrst);
out:
if (!request)
omap_iommu_dra7_emu_swsup_config(pdev, false);
return ret;
} }
...@@ -8,18 +8,42 @@ ...@@ -8,18 +8,42 @@
* Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com> * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com>
*/ */
#include <linux/arm-smccc.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/memblock.h> #include <linux/memblock.h>
#include <linux/of.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <asm/memblock.h> #include <asm/memblock.h>
#include "common.h"
#include "omap-secure.h" #include "omap-secure.h"
static phys_addr_t omap_secure_memblock_base; static phys_addr_t omap_secure_memblock_base;
bool optee_available;
#define OMAP_SIP_SMC_STD_CALL_VAL(func_num) \
ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_32, \
ARM_SMCCC_OWNER_SIP, (func_num))
static void __init omap_optee_init_check(void)
{
struct device_node *np;
/*
* We only check that the OP-TEE node is present and available. The
* OP-TEE kernel driver is not needed for the type of interaction made
* with OP-TEE here so the driver's status is not checked.
*/
np = of_find_node_by_path("/firmware/optee");
if (np && of_device_is_available(np))
optee_available = true;
of_node_put(np);
}
/** /**
* omap_sec_dispatcher: Routine to dispatch low power secure * omap_sec_dispatcher: Routine to dispatch low power secure
* service routines * service routines
...@@ -53,6 +77,27 @@ u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2, ...@@ -53,6 +77,27 @@ u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
return ret; return ret;
} }
void omap_smccc_smc(u32 fn, u32 arg)
{
struct arm_smccc_res res;
arm_smccc_smc(OMAP_SIP_SMC_STD_CALL_VAL(fn), arg,
0, 0, 0, 0, 0, 0, &res);
WARN(res.a0, "Secure function call 0x%08x failed\n", fn);
}
void omap_smc1(u32 fn, u32 arg)
{
/*
* If this platform has OP-TEE installed we use ARM SMC calls
* otherwise fall back to the OMAP ROM style calls.
*/
if (optee_available)
omap_smccc_smc(fn, arg);
else
_omap_smc1(fn, arg);
}
/* Allocate the memory to save secure ram */ /* Allocate the memory to save secure ram */
int __init omap_secure_ram_reserve_memblock(void) int __init omap_secure_ram_reserve_memblock(void)
{ {
...@@ -163,3 +208,8 @@ u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag) ...@@ -163,3 +208,8 @@ u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag)
NO_FLAG, NO_FLAG,
3, ptr, count, flag, 0); 3, ptr, count, flag, 0);
} }
void __init omap_secure_init(void)
{
omap_optee_init_check();
}
...@@ -10,6 +10,8 @@ ...@@ -10,6 +10,8 @@
#ifndef OMAP_ARCH_OMAP_SECURE_H #ifndef OMAP_ARCH_OMAP_SECURE_H
#define OMAP_ARCH_OMAP_SECURE_H #define OMAP_ARCH_OMAP_SECURE_H
#include <linux/types.h>
/* Monitor error code */ /* Monitor error code */
#define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE #define API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR 0xFFFFFFFE
#define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF #define API_HAL_RET_VALUE_SERVICE_UNKNWON 0xFFFFFFFF
...@@ -51,6 +53,9 @@ ...@@ -51,6 +53,9 @@
#define OMAP4_PPA_L2_POR_INDEX 0x23 #define OMAP4_PPA_L2_POR_INDEX 0x23
#define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25 #define OMAP4_PPA_CPU_ACTRL_SMP_INDEX 0x25
#define AM43xx_PPA_SVC_PM_SUSPEND 0x71
#define AM43xx_PPA_SVC_PM_RESUME 0x72
/* Secure RX-51 PPA (Primary Protected Application) APIs */ /* Secure RX-51 PPA (Primary Protected Application) APIs */
#define RX51_PPA_HWRNG 29 #define RX51_PPA_HWRNG 29
#define RX51_PPA_L2_INVAL 40 #define RX51_PPA_L2_INVAL 40
...@@ -60,6 +65,8 @@ ...@@ -60,6 +65,8 @@
extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
u32 arg1, u32 arg2, u32 arg3, u32 arg4); u32 arg1, u32 arg2, u32 arg3, u32 arg4);
extern void omap_smccc_smc(u32 fn, u32 arg);
extern void omap_smc1(u32 fn, u32 arg);
extern u32 omap_smc2(u32 id, u32 falg, u32 pargs); extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs); extern u32 omap_smc3(u32 id, u32 process, u32 flag, u32 pargs);
extern phys_addr_t omap_secure_ram_mempool_base(void); extern phys_addr_t omap_secure_ram_mempool_base(void);
...@@ -72,6 +79,9 @@ extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs, ...@@ -72,6 +79,9 @@ extern u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits); extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag); extern u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag);
extern bool optee_available;
void omap_secure_init(void);
#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
void set_cntfreq(void); void set_cntfreq(void);
#else #else
......
...@@ -18,18 +18,18 @@ ...@@ -18,18 +18,18 @@
* the monitor API number. It uses few CPU registers * the monitor API number. It uses few CPU registers
* internally and hence they need be backed up including * internally and hence they need be backed up including
* link register "lr". * link register "lr".
* Function signature : void omap_smc1(u32 fn, u32 arg) * Function signature : void _omap_smc1(u32 fn, u32 arg)
*/ */
.arch armv7-a .arch armv7-a
.arch_extension sec .arch_extension sec
ENTRY(omap_smc1) ENTRY(_omap_smc1)
stmfd sp!, {r2-r12, lr} stmfd sp!, {r2-r12, lr}
mov r12, r0 mov r12, r0
mov r0, r1 mov r0, r1
dsb dsb
smc #0 smc #0
ldmfd sp!, {r2-r12, pc} ldmfd sp!, {r2-r12, pc}
ENDPROC(omap_smc1) ENDPROC(_omap_smc1)
/** /**
* u32 omap_smc2(u32 id, u32 falg, u32 pargs) * u32 omap_smc2(u32 id, u32 falg, u32 pargs)
......
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
#include <linux/platform_data/ti-sysc.h> #include <linux/platform_data/ti-sysc.h>
#include <linux/platform_data/wkup_m3.h> #include <linux/platform_data/wkup_m3.h>
#include <linux/platform_data/asoc-ti-mcbsp.h> #include <linux/platform_data/asoc-ti-mcbsp.h>
#include <linux/platform_data/ti-prm.h>
#include "clockdomain.h" #include "clockdomain.h"
#include "common.h" #include "common.h"
...@@ -42,6 +43,17 @@ struct pdata_init { ...@@ -42,6 +43,17 @@ struct pdata_init {
static struct of_dev_auxdata omap_auxdata_lookup[]; static struct of_dev_auxdata omap_auxdata_lookup[];
static struct twl4030_gpio_platform_data twl_gpio_auxdata; static struct twl4030_gpio_platform_data twl_gpio_auxdata;
#if IS_ENABLED(CONFIG_OMAP_IOMMU)
int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request,
u8 *pwrst);
#else
static inline int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev,
bool request, u8 *pwrst)
{
return 0;
}
#endif
#ifdef CONFIG_MACH_NOKIA_N8X0 #ifdef CONFIG_MACH_NOKIA_N8X0
static void __init omap2420_n8x0_legacy_init(void) static void __init omap2420_n8x0_legacy_init(void)
{ {
...@@ -260,16 +272,6 @@ static void __init omap3_pandora_legacy_init(void) ...@@ -260,16 +272,6 @@ static void __init omap3_pandora_legacy_init(void)
} }
#endif /* CONFIG_ARCH_OMAP3 */ #endif /* CONFIG_ARCH_OMAP3 */
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
static struct iommu_platform_data omap4_iommu_pdata = {
.reset_name = "mmu_cache",
.assert_reset = omap_device_assert_hardreset,
.deassert_reset = omap_device_deassert_hardreset,
.device_enable = omap_device_enable,
.device_idle = omap_device_idle,
};
#endif
#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
static struct wkup_m3_platform_data wkup_m3_data = { static struct wkup_m3_platform_data wkup_m3_data = {
.reset_name = "wkup_m3", .reset_name = "wkup_m3",
...@@ -285,6 +287,10 @@ static void __init omap5_uevm_legacy_init(void) ...@@ -285,6 +287,10 @@ static void __init omap5_uevm_legacy_init(void)
#endif #endif
#ifdef CONFIG_SOC_DRA7XX #ifdef CONFIG_SOC_DRA7XX
static struct iommu_platform_data dra7_ipu1_dsp_iommu_pdata = {
.set_pwrdm_constraint = omap_iommu_set_pwrdm_constraint,
};
static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc1; static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc1;
static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc2; static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc2;
static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc3; static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc3;
...@@ -412,6 +418,12 @@ void omap_pcs_legacy_init(int irq, void (*rearm)(void)) ...@@ -412,6 +418,12 @@ void omap_pcs_legacy_init(int irq, void (*rearm)(void))
pcs_pdata.rearm = rearm; pcs_pdata.rearm = rearm;
} }
static struct ti_prm_platform_data ti_prm_pdata = {
.clkdm_deny_idle = clkdm_deny_idle,
.clkdm_allow_idle = clkdm_allow_idle,
.clkdm_lookup = clkdm_lookup,
};
/* /*
* GPIOs for TWL are initialized by the I2C bus and need custom * GPIOs for TWL are initialized by the I2C bus and need custom
* handing until DSS has device tree bindings. * handing until DSS has device tree bindings.
...@@ -492,10 +504,6 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = { ...@@ -492,10 +504,6 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = {
&wkup_m3_data), &wkup_m3_data),
#endif #endif
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
OF_DEV_AUXDATA("ti,omap4-iommu", 0x4a066000, "4a066000.mmu",
&omap4_iommu_pdata),
OF_DEV_AUXDATA("ti,omap4-iommu", 0x55082000, "55082000.mmu",
&omap4_iommu_pdata),
OF_DEV_AUXDATA("ti,omap4-smartreflex-iva", 0x4a0db000, OF_DEV_AUXDATA("ti,omap4-smartreflex-iva", 0x4a0db000,
"4a0db000.smartreflex", &omap_sr_pdata[OMAP_SR_IVA]), "4a0db000.smartreflex", &omap_sr_pdata[OMAP_SR_IVA]),
OF_DEV_AUXDATA("ti,omap4-smartreflex-core", 0x4a0dd000, OF_DEV_AUXDATA("ti,omap4-smartreflex-core", 0x4a0dd000,
...@@ -510,10 +518,17 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = { ...@@ -510,10 +518,17 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = {
&dra7_hsmmc_data_mmc2), &dra7_hsmmc_data_mmc2),
OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480ad000, "480ad000.mmc", OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480ad000, "480ad000.mmc",
&dra7_hsmmc_data_mmc3), &dra7_hsmmc_data_mmc3),
OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x40d01000, "40d01000.mmu",
&dra7_ipu1_dsp_iommu_pdata),
OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x41501000, "41501000.mmu",
&dra7_ipu1_dsp_iommu_pdata),
OF_DEV_AUXDATA("ti,dra7-iommu", 0x58882000, "58882000.mmu",
&dra7_ipu1_dsp_iommu_pdata),
#endif #endif
/* Common auxdata */ /* Common auxdata */
OF_DEV_AUXDATA("ti,sysc", 0, NULL, &ti_sysc_pdata), OF_DEV_AUXDATA("ti,sysc", 0, NULL, &ti_sysc_pdata),
OF_DEV_AUXDATA("pinctrl-single", 0, NULL, &pcs_pdata), OF_DEV_AUXDATA("pinctrl-single", 0, NULL, &pcs_pdata),
OF_DEV_AUXDATA("ti,omap-prm-inst", 0, NULL, &ti_prm_pdata),
{ /* sentinel */ }, { /* sentinel */ },
}; };
......
...@@ -28,6 +28,7 @@ ...@@ -28,6 +28,7 @@
#include "prm33xx.h" #include "prm33xx.h"
#include "soc.h" #include "soc.h"
#include "sram.h" #include "sram.h"
#include "omap-secure.h"
static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm; static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm;
static struct clockdomain *gfx_l4ls_clkdm; static struct clockdomain *gfx_l4ls_clkdm;
...@@ -166,6 +167,16 @@ static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long), ...@@ -166,6 +167,16 @@ static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long),
{ {
int ret = 0; int ret = 0;
/* Suspend secure side on HS devices */
if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
if (optee_available)
omap_smccc_smc(AM43xx_PPA_SVC_PM_SUSPEND, 0);
else
omap_secure_dispatcher(AM43xx_PPA_SVC_PM_SUSPEND,
FLAG_START_CRITICAL,
0, 0, 0, 0, 0);
}
amx3_pre_suspend_common(); amx3_pre_suspend_common();
scu_power_mode(scu_base, SCU_PM_POWEROFF); scu_power_mode(scu_base, SCU_PM_POWEROFF);
ret = cpu_suspend(args, fn); ret = cpu_suspend(args, fn);
...@@ -174,6 +185,19 @@ static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long), ...@@ -174,6 +185,19 @@ static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long),
if (!am43xx_check_off_mode_enable()) if (!am43xx_check_off_mode_enable())
amx3_post_suspend_common(); amx3_post_suspend_common();
/*
* Resume secure side on HS devices.
*
* Note that even on systems with OP-TEE available this resume call is
* issued to the ROM. This is because upon waking from suspend the ROM
* is restored as the secure monitor. On systems with OP-TEE ROM will
* restore OP-TEE during this call.
*/
if (omap_type() != OMAP2_DEVICE_TYPE_GP)
omap_secure_dispatcher(AM43xx_PPA_SVC_PM_RESUME,
FLAG_START_CRITICAL,
0, 0, 0, 0, 0);
return ret; return ret;
} }
......
...@@ -68,6 +68,7 @@ ...@@ -68,6 +68,7 @@
#define AM43XX_CM_PER_ICSS_CDOFFS 0x0300 #define AM43XX_CM_PER_ICSS_CDOFFS 0x0300
#define AM43XX_CM_PER_L4LS_CDOFFS 0x0400 #define AM43XX_CM_PER_L4LS_CDOFFS 0x0400
#define AM43XX_CM_PER_EMIF_CDOFFS 0x0700 #define AM43XX_CM_PER_EMIF_CDOFFS 0x0700
#define AM43XX_CM_PER_LCDC_CDOFFS 0x0800
#define AM43XX_CM_PER_DSS_CDOFFS 0x0a00 #define AM43XX_CM_PER_DSS_CDOFFS 0x0a00
#define AM43XX_CM_PER_CPSW_CDOFFS 0x0b00 #define AM43XX_CM_PER_CPSW_CDOFFS 0x0b00
#define AM43XX_CM_PER_OCPWP_L3_CDOFFS 0x0c00 #define AM43XX_CM_PER_OCPWP_L3_CDOFFS 0x0c00
......
...@@ -19,12 +19,12 @@ config PLAT_S3C24XX ...@@ -19,12 +19,12 @@ config PLAT_S3C24XX
menu "SAMSUNG S3C24XX SoCs Support" menu "Samsung S3C24XX SoCs Support"
comment "S3C24XX SoCs" comment "S3C24XX SoCs"
config CPU_S3C2410 config CPU_S3C2410
bool "SAMSUNG S3C2410" bool "Samsung S3C2410"
default y default y
select CPU_ARM920T select CPU_ARM920T
select S3C2410_COMMON_CLK select S3C2410_COMMON_CLK
...@@ -35,7 +35,7 @@ config CPU_S3C2410 ...@@ -35,7 +35,7 @@ config CPU_S3C2410
of Samsung Mobile CPUs. of Samsung Mobile CPUs.
config CPU_S3C2412 config CPU_S3C2412
bool "SAMSUNG S3C2412" bool "Samsung S3C2412"
select CPU_ARM926T select CPU_ARM926T
select S3C2412_COMMON_CLK select S3C2412_COMMON_CLK
select S3C2412_PM if PM_SLEEP select S3C2412_PM if PM_SLEEP
...@@ -43,7 +43,7 @@ config CPU_S3C2412 ...@@ -43,7 +43,7 @@ config CPU_S3C2412
Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
config CPU_S3C2416 config CPU_S3C2416
bool "SAMSUNG S3C2416/S3C2450" bool "Samsung S3C2416/S3C2450"
select CPU_ARM926T select CPU_ARM926T
select S3C2416_PM if PM_SLEEP select S3C2416_PM if PM_SLEEP
select S3C2443_COMMON_CLK select S3C2443_COMMON_CLK
...@@ -51,7 +51,7 @@ config CPU_S3C2416 ...@@ -51,7 +51,7 @@ config CPU_S3C2416
Support for the S3C2416 SoC from the S3C24XX line Support for the S3C2416 SoC from the S3C24XX line
config CPU_S3C2440 config CPU_S3C2440
bool "SAMSUNG S3C2440" bool "Samsung S3C2440"
select CPU_ARM920T select CPU_ARM920T
select S3C2410_COMMON_CLK select S3C2410_COMMON_CLK
select S3C2410_PM if PM_SLEEP select S3C2410_PM if PM_SLEEP
...@@ -59,7 +59,7 @@ config CPU_S3C2440 ...@@ -59,7 +59,7 @@ config CPU_S3C2440
Support for S3C2440 Samsung Mobile CPU based systems. Support for S3C2440 Samsung Mobile CPU based systems.
config CPU_S3C2442 config CPU_S3C2442
bool "SAMSUNG S3C2442" bool "Samsung S3C2442"
select CPU_ARM920T select CPU_ARM920T
select S3C2410_COMMON_CLK select S3C2410_COMMON_CLK
select S3C2410_PM if PM_SLEEP select S3C2410_PM if PM_SLEEP
...@@ -71,7 +71,7 @@ config CPU_S3C244X ...@@ -71,7 +71,7 @@ config CPU_S3C244X
depends on CPU_S3C2440 || CPU_S3C2442 depends on CPU_S3C2440 || CPU_S3C2442
config CPU_S3C2443 config CPU_S3C2443
bool "SAMSUNG S3C2443" bool "Samsung S3C2443"
select CPU_ARM920T select CPU_ARM920T
select S3C2443_COMMON_CLK select S3C2443_COMMON_CLK
help help
...@@ -591,6 +591,6 @@ config PM_H1940 ...@@ -591,6 +591,6 @@ config PM_H1940
help help
Internal node for H1940 and related PM Internal node for H1940 and related PM
endmenu # SAMSUNG S3C24XX SoCs Support endmenu # Samsung S3C24XX SoCs Support
endif # ARCH_S3C24XX endif # ARCH_S3C24XX
...@@ -377,6 +377,7 @@ static struct pwm_lookup rx1950_pwm_lookup[] = { ...@@ -377,6 +377,7 @@ static struct pwm_lookup rx1950_pwm_lookup[] = {
}; };
static struct pwm_device *lcd_pwm; static struct pwm_device *lcd_pwm;
static struct pwm_state lcd_pwm_state;
static void rx1950_lcd_power(int enable) static void rx1950_lcd_power(int enable)
{ {
...@@ -429,15 +430,16 @@ static void rx1950_lcd_power(int enable) ...@@ -429,15 +430,16 @@ static void rx1950_lcd_power(int enable)
/* GPB1->OUTPUT, GPB1->0 */ /* GPB1->OUTPUT, GPB1->0 */
gpio_direction_output(S3C2410_GPB(1), 0); gpio_direction_output(S3C2410_GPB(1), 0);
pwm_config(lcd_pwm, 0, LCD_PWM_PERIOD);
pwm_disable(lcd_pwm); lcd_pwm_state.enabled = false;
pwm_apply_state(lcd_pwm, &lcd_pwm_state);
/* GPC0->0, GPC10->0 */ /* GPC0->0, GPC10->0 */
gpio_direction_output(S3C2410_GPC(0), 0); gpio_direction_output(S3C2410_GPC(0), 0);
gpio_direction_output(S3C2410_GPC(10), 0); gpio_direction_output(S3C2410_GPC(10), 0);
} else { } else {
pwm_config(lcd_pwm, LCD_PWM_DUTY, LCD_PWM_PERIOD); lcd_pwm_state.enabled = true;
pwm_enable(lcd_pwm); pwm_apply_state(lcd_pwm, &lcd_pwm_state);
gpio_direction_output(S3C2410_GPC(0), 1); gpio_direction_output(S3C2410_GPC(0), 1);
gpio_direction_output(S3C2410_GPC(5), 1); gpio_direction_output(S3C2410_GPC(5), 1);
...@@ -493,10 +495,13 @@ static int rx1950_backlight_init(struct device *dev) ...@@ -493,10 +495,13 @@ static int rx1950_backlight_init(struct device *dev)
} }
/* /*
* FIXME: pwm_apply_args() should be removed when switching to * This is only required to initialize .polarity; all other values are
* the atomic PWM API. * fixed in this driver.
*/ */
pwm_apply_args(lcd_pwm); pwm_init_state(lcd_pwm, &lcd_pwm_state);
lcd_pwm_state.period = LCD_PWM_PERIOD;
lcd_pwm_state.duty_cycle = LCD_PWM_DUTY;
rx1950_lcd_power(1); rx1950_lcd_power(1);
rx1950_bl_power(1); rx1950_bl_power(1);
......
...@@ -336,7 +336,6 @@ config MACH_WLF_CRAGG_6410 ...@@ -336,7 +336,6 @@ config MACH_WLF_CRAGG_6410
config MACH_S3C64XX_DT config MACH_S3C64XX_DT
bool "Samsung S3C6400/S3C6410 machine using Device Tree" bool "Samsung S3C6400/S3C6410 machine using Device Tree"
select TIMER_OF
select CPU_S3C6400 select CPU_S3C6400
select CPU_S3C6410 select CPU_S3C6410
select PINCTRL select PINCTRL
......
...@@ -59,6 +59,9 @@ ...@@ -59,6 +59,9 @@
#define CLK_RESET_PLLX_MISC3_IDDQ 3 #define CLK_RESET_PLLX_MISC3_IDDQ 3
#define CLK_RESET_PLLM_MISC_IDDQ 5 #define CLK_RESET_PLLM_MISC_IDDQ 5
#define CLK_RESET_PLLC_MISC_IDDQ 26 #define CLK_RESET_PLLC_MISC_IDDQ 26
#define CLK_RESET_PLLP_RESHIFT 0x528
#define CLK_RESET_PLLP_RESHIFT_DEFAULT 0x3b
#define CLK_RESET_PLLP_RESHIFT_ENABLE 0x3
#define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4 #define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4
...@@ -370,6 +373,18 @@ _pll_m_c_x_done: ...@@ -370,6 +373,18 @@ _pll_m_c_x_done:
pll_locked r1, r0, CLK_RESET_PLLC_BASE pll_locked r1, r0, CLK_RESET_PLLC_BASE
pll_locked r1, r0, CLK_RESET_PLLX_BASE pll_locked r1, r0, CLK_RESET_PLLX_BASE
tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
cmp r1, #TEGRA30
beq 1f
ldr r1, [r0, #CLK_RESET_PLLP_BASE]
bic r1, r1, #(1<<31) @ disable PllP bypass
str r1, [r0, #CLK_RESET_PLLP_BASE]
mov r1, #CLK_RESET_PLLP_RESHIFT_DEFAULT
str r1, [r0, #CLK_RESET_PLLP_RESHIFT]
1:
mov32 r7, TEGRA_TMRUS_BASE mov32 r7, TEGRA_TMRUS_BASE
ldr r1, [r7] ldr r1, [r7]
add r1, r1, #LOCK_DELAY add r1, r1, #LOCK_DELAY
...@@ -630,9 +645,16 @@ tegra30_switch_cpu_to_clk32k: ...@@ -630,9 +645,16 @@ tegra30_switch_cpu_to_clk32k:
str r0, [r4, #PMC_PLLP_WB0_OVERRIDE] str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
/* disable PLLP, PLLA, PLLC and PLLX */ /* disable PLLP, PLLA, PLLC and PLLX */
tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
cmp r1, #TEGRA30
ldr r0, [r5, #CLK_RESET_PLLP_BASE] ldr r0, [r5, #CLK_RESET_PLLP_BASE]
orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster
bic r0, r0, #(1 << 30) bic r0, r0, #(1 << 30)
str r0, [r5, #CLK_RESET_PLLP_BASE] str r0, [r5, #CLK_RESET_PLLP_BASE]
beq 1f
mov r0, #CLK_RESET_PLLP_RESHIFT_ENABLE
str r0, [r5, #CLK_RESET_PLLP_RESHIFT]
1:
ldr r0, [r5, #CLK_RESET_PLLA_BASE] ldr r0, [r5, #CLK_RESET_PLLA_BASE]
bic r0, r0, #(1 << 30) bic r0, r0, #(1 << 30)
str r0, [r5, #CLK_RESET_PLLA_BASE] str r0, [r5, #CLK_RESET_PLLA_BASE]
...@@ -648,8 +670,12 @@ tegra30_switch_cpu_to_clk32k: ...@@ -648,8 +670,12 @@ tegra30_switch_cpu_to_clk32k:
pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
_no_pll_in_iddq: _no_pll_in_iddq:
/* switch to CLKS */ /*
mov r0, #0 /* brust policy = 32KHz */ * Switch to clk_s (32KHz); bits 28:31=0
* Enable burst on CPU IRQ; bit 24=1
* Set IRQ burst clock source to clk_m; bits 10:8=0
*/
mov r0, #(1 << 24)
str r0, [r5, #CLK_RESET_SCLK_BURST] str r0, [r5, #CLK_RESET_SCLK_BURST]
ret lr ret lr
......
...@@ -15,6 +15,7 @@ ...@@ -15,6 +15,7 @@
#include <linux/init.h> #include <linux/init.h>
#include <linux/io.h> #include <linux/io.h>
#include <asm/cacheflush.h> #include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h> #include <asm/smp_scu.h>
#include <linux/irqchip/arm-gic.h> #include <linux/irqchip/arm-gic.h>
#include "common.h" #include "common.h"
...@@ -30,6 +31,7 @@ int zynq_cpun_start(u32 address, int cpu) ...@@ -30,6 +31,7 @@ int zynq_cpun_start(u32 address, int cpu)
{ {
u32 trampoline_code_size = &zynq_secondary_trampoline_end - u32 trampoline_code_size = &zynq_secondary_trampoline_end -
&zynq_secondary_trampoline; &zynq_secondary_trampoline;
u32 phy_cpuid = cpu_logical_map(cpu);
/* MS: Expectation that SLCR are directly map and accessible */ /* MS: Expectation that SLCR are directly map and accessible */
/* Not possible to jump to non aligned address */ /* Not possible to jump to non aligned address */
...@@ -39,7 +41,7 @@ int zynq_cpun_start(u32 address, int cpu) ...@@ -39,7 +41,7 @@ int zynq_cpun_start(u32 address, int cpu)
u32 trampoline_size = &zynq_secondary_trampoline_jump - u32 trampoline_size = &zynq_secondary_trampoline_jump -
&zynq_secondary_trampoline; &zynq_secondary_trampoline;
zynq_slcr_cpu_stop(cpu); zynq_slcr_cpu_stop(phy_cpuid);
if (address) { if (address) {
if (__pa(PAGE_OFFSET)) { if (__pa(PAGE_OFFSET)) {
zero = ioremap(0, trampoline_code_size); zero = ioremap(0, trampoline_code_size);
...@@ -68,7 +70,7 @@ int zynq_cpun_start(u32 address, int cpu) ...@@ -68,7 +70,7 @@ int zynq_cpun_start(u32 address, int cpu)
if (__pa(PAGE_OFFSET)) if (__pa(PAGE_OFFSET))
iounmap(zero); iounmap(zero);
} }
zynq_slcr_cpu_start(cpu); zynq_slcr_cpu_start(phy_cpuid);
return 0; return 0;
} }
......
...@@ -40,7 +40,7 @@ enum s3c_cpu_type { ...@@ -40,7 +40,7 @@ enum s3c_cpu_type {
TYPE_ADCV11, /* S3C2443 */ TYPE_ADCV11, /* S3C2443 */
TYPE_ADCV12, /* S3C2416, S3C2450 */ TYPE_ADCV12, /* S3C2416, S3C2450 */
TYPE_ADCV2, /* S3C64XX */ TYPE_ADCV2, /* S3C64XX */
TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */ TYPE_ADCV3, /* S5PV210, S5PC110, Exynos4210 */
}; };
struct s3c_adc_client { struct s3c_adc_client {
......
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
// Copyright (c) 2011 Samsung Electronics Co., Ltd. // Copyright (c) 2011 Samsung Electronics Co., Ltd.
// http://www.samsung.com // http://www.samsung.com
// //
// Base SAMSUNG platform device definitions // Base Samsung platform device definitions
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/types.h> #include <linux/types.h>
......
...@@ -8,7 +8,7 @@ ...@@ -8,7 +8,7 @@
// Ben Dooks <ben@simtec.co.uk> // Ben Dooks <ben@simtec.co.uk>
// http://armlinux.simtec.co.uk/ // http://armlinux.simtec.co.uk/
// //
// SAMSUNG - GPIOlib support // Samsung - GPIOlib support
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/irq.h> #include <linux/irq.h>
......
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
#ifndef __ASM_PLAT_SAMSUNG_TIME_H #ifndef __ASM_PLAT_SAMSUNG_TIME_H
#define __ASM_PLAT_SAMSUNG_TIME_H __FILE__ #define __ASM_PLAT_SAMSUNG_TIME_H __FILE__
/* SAMSUNG HR-Timer Clock mode */ /* Samsung HR-Timer Clock mode */
enum samsung_timer_mode { enum samsung_timer_mode {
SAMSUNG_PWM0, SAMSUNG_PWM0,
SAMSUNG_PWM1, SAMSUNG_PWM1,
......
...@@ -26,7 +26,7 @@ config POWER_RESET_AT91_POWEROFF ...@@ -26,7 +26,7 @@ config POWER_RESET_AT91_POWEROFF
config POWER_RESET_AT91_RESET config POWER_RESET_AT91_RESET
tristate "Atmel AT91 reset driver" tristate "Atmel AT91 reset driver"
depends on ARCH_AT91 depends on ARCH_AT91
default SOC_AT91SAM9 || SOC_SAMA5 default SOC_AT91SAM9 || SOC_SAM9X60 || SOC_SAMA5
help help
This driver supports restart for Atmel AT91SAM9 and SAMA5 This driver supports restart for Atmel AT91SAM9 and SAMA5
SoCs SoCs
...@@ -34,7 +34,7 @@ config POWER_RESET_AT91_RESET ...@@ -34,7 +34,7 @@ config POWER_RESET_AT91_RESET
config POWER_RESET_AT91_SAMA5D2_SHDWC config POWER_RESET_AT91_SAMA5D2_SHDWC
tristate "Atmel AT91 SAMA5D2-Compatible shutdown controller driver" tristate "Atmel AT91 SAMA5D2-Compatible shutdown controller driver"
depends on ARCH_AT91 depends on ARCH_AT91
default SOC_SAMA5 default SOC_SAM9X60 || SOC_SAMA5
help help
This driver supports the alternate shutdown controller for some Atmel This driver supports the alternate shutdown controller for some Atmel
SAMA5 SoCs. It is present for example on SAMA5D2 SoC. SAMA5 SoCs. It is present for example on SAMA5D2 SoC.
......
...@@ -66,8 +66,9 @@ static const struct at91_soc __initconst socs[] = { ...@@ -66,8 +66,9 @@ static const struct at91_soc __initconst socs[] = {
AT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, "at91sam9xe128", "at91sam9xe128"), AT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, "at91sam9xe128", "at91sam9xe128"),
AT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, "at91sam9xe256", "at91sam9xe256"), AT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, "at91sam9xe256", "at91sam9xe256"),
AT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, "at91sam9xe512", "at91sam9xe512"), AT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, "at91sam9xe512", "at91sam9xe512"),
AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, #endif
"sam9x60", "sam9x60"), #ifdef CONFIG_SOC_SAM9X60
AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, "sam9x60", "sam9x60"),
#endif #endif
#ifdef CONFIG_SOC_SAMA5 #ifdef CONFIG_SOC_SAMA5
AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH, AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH,
......
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