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Commit 49045b9c authored by David S. Miller's avatar David S. Miller
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Merge branch 'mediatek-next' 

Biao Huang says:

====================
MediaTek Ethernet Patches on MT8195

Changes in v13:
1. add reviewed-by in "net: dt-bindings: dwmac: add support for mt8195"
   as Rob's comments.
2. drop num_clks defined in mediatek_dwmac_plat_data struct in "stmmac:
   dwmac-mediatek: Reuse more common features" as Angelo's comments.

Changes in v12:
1. add a new patch "stmmac: dwmac-mediatek: re-arrange clock setting" to
   this series, to simplify clock handling in driver, which benefits to
   binding file mediatek-dwmac.yaml.
2. modify dt-binding description in patch "net: dt-bindings: dwmac: add
   support for mt8195" as Rob's comments in v10 series, put mac_cg to the
   end of clock list.
3. there are small changes in patch "stmmac: dwmac-mediatek: add support
   for mt8195", @AngeloGioacchino, please review it kindly.

Changes in v11:
1. add reivewed-by in "net: dt-bindings: dwmac: Convert mediatek-dwmac to
   DT schema" as Rob's comments.
2. fall back "net: dt-bindings: dwmac: add support for mt8195" to v8 version
   as mentioned in previous reply(https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20211216055328.15953-7-biao.huang@mediatek.com/):
   2.1 there is already a special clock named "rmii_internal", which need to
       be put to the end of the clock list(driver special handling),
       so we can't simply put new "mac_cg" for mt8195 to the end of the clock
       list.
   2.2 we prefer the if-then schema, which will make mt8195 clock list clearer
       with some duplicated information.
   2.3 we expect the future IC will follow mt2712 or mt8195, so we only need
       add new IC name to compatible list for future IC, and will not make the
       clock list binding files worse.

Changes in v10:
1. add detailed description in "arm64: dts: mt2712: update ethernet
   device node" to make the modifications clearer as Matthias's comments.
2. modify dt-binding description as Rob's comments, and "make dtbs_check" runs
   pass locally with "arm64: dts: mt2712: update ethernet device node"
   in this series.

Changes in v9:
1. remove oneOf for 1 entry as Rob's comments.
2. add new clocks to the end of existing clocks to simplify
   the binding as Rob's comments.

Changes in v8:
1. add acked-by in "stmmac: dwmac-mediatek: add platform level clocks
   management" patch

Changes in v7:
1. fix uninitialized warning as Jakub's comments.

Changes in v6:
1. update commit message as Jakub's comments.
2. split mt8195 eth dts patch("arm64: dts: mt8195: add ethernet device
   node") from this series, since mt8195 dtsi/dts basic patches is still
   under reviewing.
   https://patchwork.kernel.org/project/linux-mediatek/list/?series=579071
   we'll resend mt8195 eth dts patch once all the dependent patches are
   accepted.

Changes in v5:
1. remove useless inclusion in dwmac-mediatek.c as Angelo's comments.
2. add acked-by in "net-next: stmmac: dwmac-mediatek: add support for
   mt8195" patch

Changes in v4:
1. add changes in commit message in "net-next: dt-bindings: dwmac:
   Convert mediatek-dwmac to DT schema" patch.
2. remove ethernet-controller.yaml since snps,dwmac.yaml already include it.

Changes in v3:
1. Add prefix "net-next" to support new IC as Denis's suggestion.
2. Split dt-bindings to two patches, one for conversion, and the other for
   new IC.
3. add a new patch to update device node in mt2712-evb.dts to accommodate to
   changes in driver.
4. remove unnecessary wrapper as Angelo's suggestion.
5. Add acked-by in "net-next: stmmac: dwmac-mediatek: Reuse more common
   features" patch.

Changes in v2:
1. fix errors/warnings in mediatek-dwmac.yaml with upgraded dtschema tools

Changes in v1:
This series include 5 patches:
1. add platform level clocks management for dwmac-mediatek
2. resue more common features defined in stmmac_platform.c
3. add ethernet entry for mt8195
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 79b04108 ee410d51
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Documentation/devicetree/bindings/net/mediatek-dwmac.txt deleted 100644 → 0
View file @ 79b04108
MediaTek DWMAC glue layer controller
This file documents platform glue layer for stmmac.
Please see stmmac.txt for the other unchanged properties.
The device node has following properties.
Required properties:
- compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC
- reg: Address and length of the register set for the device
- interrupts: Should contain the MAC interrupts
- interrupt-names: Should contain a list of interrupt names corresponding to
the interrupts in the interrupts property, if available.
Should be "macirq" for the main MAC IRQ
- clocks: Must contain a phandle for each entry in clock-names.
- clock-names: The name of the clock listed in the clocks property. These are
"axi", "apb", "mac_main", "ptp_ref", "rmii_internal" for MT2712 SoC.
- mac-address: See ethernet.txt in the same directory
- phy-mode: See ethernet.txt in the same directory
- mediatek,pericfg: A phandle to the syscon node that control ethernet
interface and timing delay.
Optional properties:
- mediatek,tx-delay-ps: TX clock delay macro value. Default is 0.
It should be defined for RGMII/MII interface.
It should be defined for RMII interface when the reference clock is from MT2712 SoC.
- mediatek,rx-delay-ps: RX clock delay macro value. Default is 0.
It should be defined for RGMII/MII interface.
It should be defined for RMII interface.
Both delay properties need to be a multiple of 170 for RGMII interface,
or will round down. Range 0~31*170.
Both delay properties need to be a multiple of 550 for MII/RMII interface,
or will round down. Range 0~31*550.
- mediatek,rmii-rxc: boolean property, if present indicates that the RMII
reference clock, which is from external PHYs, is connected to RXC pin
on MT2712 SoC.
Otherwise, is connected to TXC pin.
- mediatek,rmii-clk-from-mac: boolean property, if present indicates that
MT2712 SoC provides the RMII reference clock, which outputs to TXC pin only.
- mediatek,txc-inverse: boolean property, if present indicates that
1. tx clock will be inversed in MII/RGMII case,
2. tx clock inside MAC will be inversed relative to reference clock
which is from external PHYs in RMII case, and it rarely happen.
3. the reference clock, which outputs to TXC pin will be inversed in RMII case
when the reference clock is from MT2712 SoC.
- mediatek,rxc-inverse: boolean property, if present indicates that
1. rx clock will be inversed in MII/RGMII case.
2. reference clock will be inversed when arrived at MAC in RMII case, when
the reference clock is from external PHYs.
3. the inside clock, which be sent to MAC, will be inversed in RMII case when
the reference clock is from MT2712 SoC.
- assigned-clocks: mac_main and ptp_ref clocks
- assigned-clock-parents: parent clocks of the assigned clocks
Example:
eth: ethernet@1101c000 {
compatible = "mediatek,mt2712-gmac";
reg = <0 0x1101c000 0 0x1300>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "macirq";
phy-mode ="rgmii-rxid";
mac-address = [00 55 7b b5 7d f7];
clock-names = "axi",
"apb",
"mac_main",
"ptp_ref",
"rmii_internal";
clocks = <&pericfg CLK_PERI_GMAC>,
<&pericfg CLK_PERI_GMAC_PCLK>,
<&topckgen CLK_TOP_ETHER_125M_SEL>,
<&topckgen CLK_TOP_ETHER_50M_SEL>,
<&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
<&topckgen CLK_TOP_ETHER_50M_SEL>,
<&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
<&topckgen CLK_TOP_APLL1_D3>,
<&topckgen CLK_TOP_ETHERPLL_50M>;
power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
mediatek,pericfg = <&pericfg>;
mediatek,tx-delay-ps = <1530>;
mediatek,rx-delay-ps = <1530>;
mediatek,rmii-rxc;
mediatek,txc-inverse;
mediatek,rxc-inverse;
snps,txpbl = <1>;
snps,rxpbl = <1>;
snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
};
Documentation/devicetree/bindings/net/mediatek-dwmac.yaml 0 → 100644
View file @ 49045b9c
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek DWMAC glue layer controller
maintainers:
- Biao Huang <biao.huang@mediatek.com>
description:
This file documents platform glue layer for stmmac.
# We need a select here so we don't match all nodes with 'snps,dwmac'
select:
properties:
compatible:
contains:
enum:
- mediatek,mt2712-gmac
- mediatek,mt8195-gmac
required:
- compatible
allOf:
- $ref: "snps,dwmac.yaml#"
properties:
compatible:
oneOf:
- items:
- enum:
- mediatek,mt2712-gmac
- const: snps,dwmac-4.20a
- items:
- enum:
- mediatek,mt8195-gmac
- const: snps,dwmac-5.10a
clocks:
minItems: 5
items:
- description: AXI clock
- description: APB clock
- description: MAC Main clock
- description: PTP clock
- description: RMII reference clock provided by MAC
- description: MAC clock gate
clock-names:
minItems: 5
items:
- const: axi
- const: apb
- const: mac_main
- const: ptp_ref
- const: rmii_internal
- const: mac_cg
mediatek,pericfg:
$ref: /schemas/types.yaml#/definitions/phandle
description:
The phandle to the syscon node that control ethernet
interface and timing delay.
mediatek,tx-delay-ps:
description:
The internal TX clock delay (provided by this driver) in nanoseconds.
For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
or will round down. Range 0~31*170.
For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
or will round down. Range 0~31*550.
For MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,
or will round down. Range 0~31*290.
mediatek,rx-delay-ps:
description:
The internal RX clock delay (provided by this driver) in nanoseconds.
For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
or will round down. Range 0~31*170.
For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
or will round down. Range 0~31*550.
For MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple
of 290, or will round down. Range 0~31*290.
mediatek,rmii-rxc:
type: boolean
description:
If present, indicates that the RMII reference clock, which is from external
PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin.
mediatek,rmii-clk-from-mac:
type: boolean
description:
If present, indicates that MAC provides the RMII reference clock, which
outputs to TXC pin only.
mediatek,txc-inverse:
type: boolean
description:
If present, indicates that
1. tx clock will be inversed in MII/RGMII case,
2. tx clock inside MAC will be inversed relative to reference clock
which is from external PHYs in RMII case, and it rarely happen.
3. the reference clock, which outputs to TXC pin will be inversed in RMII case
when the reference clock is from MAC.
mediatek,rxc-inverse:
type: boolean
description:
If present, indicates that
1. rx clock will be inversed in MII/RGMII case.
2. reference clock will be inversed when arrived at MAC in RMII case, when
the reference clock is from external PHYs.
3. the inside clock, which be sent to MAC, will be inversed in RMII case when
the reference clock is from MAC.
mediatek,mac-wol:
type: boolean
description:
If present, indicates that MAC supports WOL(Wake-On-LAN), and MAC WOL will be enabled.
Otherwise, PHY WOL is perferred.
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
- clock-names
- phy-mode
- mediatek,pericfg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/mt2712-clk.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt2712-power.h>
eth: ethernet@1101c000 {
compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
reg = <0x1101c000 0x1300>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "macirq";
phy-mode ="rgmii-rxid";
mac-address = [00 55 7b b5 7d f7];
clock-names = "axi",
"apb",
"mac_main",
"ptp_ref",
"rmii_internal";
clocks = <&pericfg CLK_PERI_GMAC>,
<&pericfg CLK_PERI_GMAC_PCLK>,
<&topckgen CLK_TOP_ETHER_125M_SEL>,
<&topckgen CLK_TOP_ETHER_50M_SEL>,
<&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
<&topckgen CLK_TOP_ETHER_50M_SEL>,
<&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
<&topckgen CLK_TOP_APLL1_D3>,
<&topckgen CLK_TOP_ETHERPLL_50M>;
power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
mediatek,pericfg = <&pericfg>;
mediatek,tx-delay-ps = <1530>;
snps,txpbl = <1>;
snps,rxpbl = <1>;
snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
snps,reset-delays-us = <0 10000 10000>;
};
arch/arm64/boot/dts/mediatek/mt2712-evb.dts
View file @ 49045b9c
......@@ -110,6 +110,7 @@ &eth {
phy-handle = <&ethernet_phy0>;
mediatek,tx-delay-ps = <1530>;
snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
snps,reset-delays-us = <0 10000 10000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&eth_default>;
pinctrl-1 = <&eth_sleep>;
......
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
View file @ 49045b9c
......@@ -726,7 +726,7 @@ queue2 {
};
eth: ethernet@1101c000 {
compatible = "mediatek,mt2712-gmac";
compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a";
reg = <0 0x1101c000 0 0x1300>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "macirq";
......@@ -734,15 +734,19 @@ eth: ethernet@1101c000 {
clock-names = "axi",
"apb",
"mac_main",
"ptp_ref";
"ptp_ref",
"rmii_internal";
clocks = <&pericfg CLK_PERI_GMAC>,
<&pericfg CLK_PERI_GMAC_PCLK>,
<&topckgen CLK_TOP_ETHER_125M_SEL>,
<&topckgen CLK_TOP_ETHER_50M_SEL>;
<&topckgen CLK_TOP_ETHER_50M_SEL>,
<&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
<&topckgen CLK_TOP_ETHER_50M_SEL>;
<&topckgen CLK_TOP_ETHER_50M_SEL>,
<&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
<&topckgen CLK_TOP_APLL1_D3>;
<&topckgen CLK_TOP_APLL1_D3>,
<&topckgen CLK_TOP_ETHERPLL_50M>;
power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
mediatek,pericfg = <&pericfg>;
snps,axi-config = <&stmmac_axi_setup>;
......
drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
View file @ 49045b9c
......@@ -9,7 +9,6 @@
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_net.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/stmmac.h>
......@@ -40,6 +39,33 @@
#define ETH_FINE_DLY_GTXC BIT(1)
#define ETH_FINE_DLY_RXC BIT(0)
/* Peri Configuration register for mt8195 */
#define MT8195_PERI_ETH_CTRL0 0xFD0
#define MT8195_RMII_CLK_SRC_INTERNAL BIT(28)
#define MT8195_RMII_CLK_SRC_RXC BIT(27)
#define MT8195_ETH_INTF_SEL GENMASK(26, 24)
#define MT8195_RGMII_TXC_PHASE_CTRL BIT(22)
#define MT8195_EXT_PHY_MODE BIT(21)
#define MT8195_DLY_GTXC_INV BIT(12)
#define MT8195_DLY_GTXC_ENABLE BIT(5)
#define MT8195_DLY_GTXC_STAGES GENMASK(4, 0)
#define MT8195_PERI_ETH_CTRL1 0xFD4
#define MT8195_DLY_RXC_INV BIT(25)
#define MT8195_DLY_RXC_ENABLE BIT(18)
#define MT8195_DLY_RXC_STAGES GENMASK(17, 13)
#define MT8195_DLY_TXC_INV BIT(12)
#define MT8195_DLY_TXC_ENABLE BIT(5)
#define MT8195_DLY_TXC_STAGES GENMASK(4, 0)
#define MT8195_PERI_ETH_CTRL2 0xFD8
#define MT8195_DLY_RMII_RXC_INV BIT(25)
#define MT8195_DLY_RMII_RXC_ENABLE BIT(18)
#define MT8195_DLY_RMII_RXC_STAGES GENMASK(17, 13)
#define MT8195_DLY_RMII_TXC_INV BIT(12)
#define MT8195_DLY_RMII_TXC_ENABLE BIT(5)
#define MT8195_DLY_RMII_TXC_STAGES GENMASK(4, 0)
struct mac_delay_struct {
u32 tx_delay;
u32 rx_delay;
......@@ -50,19 +76,21 @@ struct mac_delay_struct {
struct mediatek_dwmac_plat_data {
const struct mediatek_dwmac_variant *variant;
struct mac_delay_struct mac_delay;
struct clk *rmii_internal_clk;
struct clk_bulk_data *clks;
struct device_node *np;
struct regmap *peri_regmap;
struct device_node *np;
struct device *dev;
phy_interface_t phy_mode;
int num_clks_to_config;
bool rmii_clk_from_mac;
bool rmii_rxc;
bool mac_wol;
};
struct mediatek_dwmac_variant {
int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat);
int (*dwmac_set_delay)(struct mediatek_dwmac_plat_data *plat);
void (*dwmac_fix_mac_speed)(void *priv, unsigned int speed);
/* clock ids to be requested */
const char * const *clk_list;
......@@ -75,7 +103,11 @@ struct mediatek_dwmac_variant {
/* list of clocks required for mac */
static const char * const mt2712_dwmac_clk_l[] = {
"axi", "apb", "mac_main", "ptp_ref", "rmii_internal"
"axi", "apb", "mac_main", "ptp_ref"
};
static const char * const mt8195_dwmac_clk_l[] = {
"axi", "apb", "mac_cg", "mac_main", "ptp_ref"
};
static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat)
......@@ -84,23 +116,12 @@ static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat)
int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0;
u32 intf_val = 0;
/* The clock labeled as "rmii_internal" in mt2712_dwmac_clk_l is needed
* only in RMII(when MAC provides the reference clock), and useless for
* RGMII/MII/RMII(when PHY provides the reference clock).
* num_clks_to_config indicates the real number of clocks should be
* configured, equals to (plat->variant->num_clks - 1) in default for all the case,
* then +1 for rmii_clk_from_mac case.
*/
plat->num_clks_to_config = plat->variant->num_clks - 1;
/* select phy interface in top control domain */
switch (plat->phy_mode) {
case PHY_INTERFACE_MODE_MII:
intf_val |= PHY_INTF_MII;
break;
case PHY_INTERFACE_MODE_RMII:
if (plat->rmii_clk_from_mac)
plat->num_clks_to_config++;
intf_val |= (PHY_INTF_RMII | rmii_rxc | rmii_clk_from_mac);
break;
case PHY_INTERFACE_MODE_RGMII:
......@@ -268,6 +289,193 @@ static const struct mediatek_dwmac_variant mt2712_gmac_variant = {
.tx_delay_max = 17600,
};
static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat)
{
int rmii_clk_from_mac = plat->rmii_clk_from_mac ? MT8195_RMII_CLK_SRC_INTERNAL : 0;
int rmii_rxc = plat->rmii_rxc ? MT8195_RMII_CLK_SRC_RXC : 0;
u32 intf_val = 0;
/* select phy interface in top control domain */
switch (plat->phy_mode) {
case PHY_INTERFACE_MODE_MII:
intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_MII);
break;
case PHY_INTERFACE_MODE_RMII:
intf_val |= (rmii_rxc | rmii_clk_from_mac);
intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_RMII);
break;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
intf_val |= FIELD_PREP(MT8195_ETH_INTF_SEL, PHY_INTF_RGMII);
break;
default:
dev_err(plat->dev, "phy interface not supported\n");
return -EINVAL;
}
/* MT8195 only support external PHY */
intf_val |= MT8195_EXT_PHY_MODE;
regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL0, intf_val);
return 0;
}
static void mt8195_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)
{
struct mac_delay_struct *mac_delay = &plat->mac_delay;
/* 290ps per stage */
mac_delay->tx_delay /= 290;
mac_delay->rx_delay /= 290;
}
static void mt8195_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)
{
struct mac_delay_struct *mac_delay = &plat->mac_delay;
/* 290ps per stage */
mac_delay->tx_delay *= 290;
mac_delay->rx_delay *= 290;
}
static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat)
{
struct mac_delay_struct *mac_delay = &plat->mac_delay;
u32 gtxc_delay_val = 0, delay_val = 0, rmii_delay_val = 0;
mt8195_delay_ps2stage(plat);
switch (plat->phy_mode) {
case PHY_INTERFACE_MODE_MII:
delay_val |= FIELD_PREP(MT8195_DLY_TXC_ENABLE, !!mac_delay->tx_delay);
delay_val |= FIELD_PREP(MT8195_DLY_TXC_STAGES, mac_delay->tx_delay);
delay_val |= FIELD_PREP(MT8195_DLY_TXC_INV, mac_delay->tx_inv);
delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay->rx_delay);
delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv);
break;
case PHY_INTERFACE_MODE_RMII:
if (plat->rmii_clk_from_mac) {
/* case 1: mac provides the rmii reference clock,
* and the clock output to TXC pin.
* The egress timing can be adjusted by RMII_TXC delay macro circuit.
* The ingress timing can be adjusted by RMII_RXC delay macro circuit.
*/
rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_TXC_ENABLE,
!!mac_delay->tx_delay);
rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_TXC_STAGES,
mac_delay->tx_delay);
rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_TXC_INV,
mac_delay->tx_inv);
rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_RXC_ENABLE,
!!mac_delay->rx_delay);
rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_RXC_STAGES,
mac_delay->rx_delay);
rmii_delay_val |= FIELD_PREP(MT8195_DLY_RMII_RXC_INV,
mac_delay->rx_inv);
} else {
/* case 2: the rmii reference clock is from external phy,
* and the property "rmii_rxc" indicates which pin(TXC/RXC)
* the reference clk is connected to. The reference clock is a
* received signal, so rx_delay/rx_inv are used to indicate
* the reference clock timing adjustment
*/
if (plat->rmii_rxc) {
/* the rmii reference clock from outside is connected
* to RXC pin, the reference clock will be adjusted
* by RXC delay macro circuit.
*/
delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE,
!!mac_delay->rx_delay);
delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES,
mac_delay->rx_delay);
delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV,
mac_delay->rx_inv);
} else {
/* the rmii reference clock from outside is connected
* to TXC pin, the reference clock will be adjusted
* by TXC delay macro circuit.
*/
delay_val |= FIELD_PREP(MT8195_DLY_TXC_ENABLE,
!!mac_delay->rx_delay);
delay_val |= FIELD_PREP(MT8195_DLY_TXC_STAGES,
mac_delay->rx_delay);
delay_val |= FIELD_PREP(MT8195_DLY_TXC_INV,
mac_delay->rx_inv);
}
}
break;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_ID:
gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_ENABLE, !!mac_delay->tx_delay);
gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_STAGES, mac_delay->tx_delay);
gtxc_delay_val |= FIELD_PREP(MT8195_DLY_GTXC_INV, mac_delay->tx_inv);
delay_val |= FIELD_PREP(MT8195_DLY_RXC_ENABLE, !!mac_delay->rx_delay);
delay_val |= FIELD_PREP(MT8195_DLY_RXC_STAGES, mac_delay->rx_delay);
delay_val |= FIELD_PREP(MT8195_DLY_RXC_INV, mac_delay->rx_inv);
break;
default:
dev_err(plat->dev, "phy interface not supported\n");
return -EINVAL;
}
regmap_update_bits(plat->peri_regmap,
MT8195_PERI_ETH_CTRL0,
MT8195_RGMII_TXC_PHASE_CTRL |
MT8195_DLY_GTXC_INV |
MT8195_DLY_GTXC_ENABLE |
MT8195_DLY_GTXC_STAGES,
gtxc_delay_val);
regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL1, delay_val);
regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL2, rmii_delay_val);
mt8195_delay_stage2ps(plat);
return 0;
}
static void mt8195_fix_mac_speed(void *priv, unsigned int speed)
{
struct mediatek_dwmac_plat_data *priv_plat = priv;
if ((phy_interface_mode_is_rgmii(priv_plat->phy_mode))) {
/* prefer 2ns fixed delay which is controlled by TXC_PHASE_CTRL,
* when link speed is 1Gbps with RGMII interface,
* Fall back to delay macro circuit for 10/100Mbps link speed.
*/
if (speed == SPEED_1000)
regmap_update_bits(priv_plat->peri_regmap,
MT8195_PERI_ETH_CTRL0,
MT8195_RGMII_TXC_PHASE_CTRL |
MT8195_DLY_GTXC_ENABLE |
MT8195_DLY_GTXC_INV |
MT8195_DLY_GTXC_STAGES,
MT8195_RGMII_TXC_PHASE_CTRL);
else
mt8195_set_delay(priv_plat);
}
}
static const struct mediatek_dwmac_variant mt8195_gmac_variant = {
.dwmac_set_phy_interface = mt8195_set_interface,
.dwmac_set_delay = mt8195_set_delay,
.dwmac_fix_mac_speed = mt8195_fix_mac_speed,
.clk_list = mt8195_dwmac_clk_l,
.num_clks = ARRAY_SIZE(mt8195_dwmac_clk_l),
.dma_bit_mask = 35,
.rx_delay_max = 9280,
.tx_delay_max = 9280,
};
static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat)
{
struct mac_delay_struct *mac_delay = &plat->mac_delay;
......@@ -308,6 +516,7 @@ static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat)
mac_delay->rx_inv = of_property_read_bool(plat->np, "mediatek,rxc-inverse");
plat->rmii_rxc = of_property_read_bool(plat->np, "mediatek,rmii-rxc");
plat->rmii_clk_from_mac = of_property_read_bool(plat->np, "mediatek,rmii-clk-from-mac");
plat->mac_wol = of_property_read_bool(plat->np, "mediatek,mac-wol");
return 0;
}
......@@ -315,18 +524,34 @@ static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat)
static int mediatek_dwmac_clk_init(struct mediatek_dwmac_plat_data *plat)
{
const struct mediatek_dwmac_variant *variant = plat->variant;
int i, num = variant->num_clks;
int i, ret;
plat->clks = devm_kcalloc(plat->dev, num, sizeof(*plat->clks), GFP_KERNEL);
plat->clks = devm_kcalloc(plat->dev, variant->num_clks, sizeof(*plat->clks), GFP_KERNEL);
if (!plat->clks)
return -ENOMEM;
for (i = 0; i < num; i++)
for (i = 0; i < variant->num_clks; i++)
plat->clks[i].id = variant->clk_list[i];
plat->num_clks_to_config = variant->num_clks;
ret = devm_clk_bulk_get(plat->dev, variant->num_clks, plat->clks);
if (ret)
return ret;
/* The clock labeled as "rmii_internal" is needed only in RMII(when
* MAC provides the reference clock), and useless for RGMII/MII or
* RMII(when PHY provides the reference clock).
* So, "rmii_internal" clock is got and configured only when
* reference clock of RMII is from MAC.
*/
if (plat->rmii_clk_from_mac) {
plat->rmii_internal_clk = devm_clk_get(plat->dev, "rmii_internal");
if (IS_ERR(plat->rmii_internal_clk))
ret = PTR_ERR(plat->rmii_internal_clk);
} else {
plat->rmii_internal_clk = NULL;
}
return devm_clk_bulk_get(plat->dev, num, plat->clks);
return ret;
}
static int mediatek_dwmac_init(struct platform_device *pdev, void *priv)
......@@ -335,44 +560,117 @@ static int mediatek_dwmac_init(struct platform_device *pdev, void *priv)
const struct mediatek_dwmac_variant *variant = plat->variant;
int ret;
ret = dma_set_mask_and_coherent(plat->dev, DMA_BIT_MASK(variant->dma_bit_mask));
if (ret) {
dev_err(plat->dev, "No suitable DMA available, err = %d\n", ret);
return ret;
if (variant->dwmac_set_phy_interface) {
ret = variant->dwmac_set_phy_interface(plat);
if (ret) {
dev_err(plat->dev, "failed to set phy interface, err = %d\n", ret);
return ret;
}
}
ret = variant->dwmac_set_phy_interface(plat);
if (ret) {
dev_err(plat->dev, "failed to set phy interface, err = %d\n", ret);
return ret;
if (variant->dwmac_set_delay) {
ret = variant->dwmac_set_delay(plat);
if (ret) {
dev_err(plat->dev, "failed to set delay value, err = %d\n", ret);
return ret;
}
}
ret = variant->dwmac_set_delay(plat);
ret = clk_bulk_prepare_enable(variant->num_clks, plat->clks);
if (ret) {
dev_err(plat->dev, "failed to set delay value, err = %d\n", ret);
dev_err(plat->dev, "failed to enable clks, err = %d\n", ret);
return ret;
}
ret = clk_bulk_prepare_enable(plat->num_clks_to_config, plat->clks);
ret = clk_prepare_enable(plat->rmii_internal_clk);
if (ret) {
dev_err(plat->dev, "failed to enable clks, err = %d\n", ret);
return ret;
dev_err(plat->dev, "failed to enable rmii internal clk, err = %d\n", ret);
goto err_clk;
}
pm_runtime_enable(&pdev->dev);
pm_runtime_get_sync(&pdev->dev);
return 0;
err_clk:
clk_bulk_disable_unprepare(variant->num_clks, plat->clks);
return ret;
}
static void mediatek_dwmac_exit(struct platform_device *pdev, void *priv)
{
struct mediatek_dwmac_plat_data *plat = priv;
const struct mediatek_dwmac_variant *variant = plat->variant;
clk_bulk_disable_unprepare(plat->num_clks_to_config, plat->clks);
clk_disable_unprepare(plat->rmii_internal_clk);
clk_bulk_disable_unprepare(variant->num_clks, plat->clks);
}
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
static int mediatek_dwmac_clks_config(void *priv, bool enabled)
{
struct mediatek_dwmac_plat_data *plat = priv;
const struct mediatek_dwmac_variant *variant = plat->variant;
int ret = 0;
if (enabled) {
ret = clk_bulk_prepare_enable(variant->num_clks, plat->clks);
if (ret) {
dev_err(plat->dev, "failed to enable clks, err = %d\n", ret);
return ret;
}
ret = clk_prepare_enable(plat->rmii_internal_clk);
if (ret) {
dev_err(plat->dev, "failed to enable rmii internal clk, err = %d\n", ret);
return ret;
}
} else {
clk_disable_unprepare(plat->rmii_internal_clk);
clk_bulk_disable_unprepare(variant->num_clks, plat->clks);
}
return ret;
}
static int mediatek_dwmac_common_data(struct platform_device *pdev,
struct plat_stmmacenet_data *plat,
struct mediatek_dwmac_plat_data *priv_plat)
{
int i;
plat->interface = priv_plat->phy_mode;
plat->use_phy_wol = priv_plat->mac_wol ? 0 : 1;
plat->riwt_off = 1;
plat->maxmtu = ETH_DATA_LEN;
plat->addr64 = priv_plat->variant->dma_bit_mask;
plat->bsp_priv = priv_plat;
plat->init = mediatek_dwmac_init;
plat->exit = mediatek_dwmac_exit;
plat->clks_config = mediatek_dwmac_clks_config;
if (priv_plat->variant->dwmac_fix_mac_speed)
plat->fix_mac_speed = priv_plat->variant->dwmac_fix_mac_speed;
plat->safety_feat_cfg = devm_kzalloc(&pdev->dev,
sizeof(*plat->safety_feat_cfg),
GFP_KERNEL);
if (!plat->safety_feat_cfg)
return -ENOMEM;
plat->safety_feat_cfg->tsoee = 1;
plat->safety_feat_cfg->mrxpee = 0;
plat->safety_feat_cfg->mestee = 1;
plat->safety_feat_cfg->mrxee = 1;
plat->safety_feat_cfg->mtxee = 1;
plat->safety_feat_cfg->epsi = 0;
plat->safety_feat_cfg->edpp = 1;
plat->safety_feat_cfg->prtyen = 1;
plat->safety_feat_cfg->tmouten = 1;
for (i = 0; i < plat->tx_queues_to_use; i++) {
/* Default TX Q0 to use TSO and rest TXQ for TBS */
if (i > 0)
plat->tx_queues_cfg[i].tbs_en = 1;
}
return 0;
}
static int mediatek_dwmac_probe(struct platform_device *pdev)
......@@ -411,15 +709,7 @@ static int mediatek_dwmac_probe(struct platform_device *pdev)
if (IS_ERR(plat_dat))
return PTR_ERR(plat_dat);
plat_dat->interface = priv_plat->phy_mode;
plat_dat->has_gmac4 = 1;
plat_dat->has_gmac = 0;
plat_dat->pmt = 0;
plat_dat->riwt_off = 1;
plat_dat->maxmtu = ETH_DATA_LEN;
plat_dat->bsp_priv = priv_plat;
plat_dat->init = mediatek_dwmac_init;
plat_dat->exit = mediatek_dwmac_exit;
mediatek_dwmac_common_data(pdev, plat_dat, priv_plat);
mediatek_dwmac_init(pdev, priv_plat);
ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
......@@ -434,6 +724,8 @@ static int mediatek_dwmac_probe(struct platform_device *pdev)
static const struct of_device_id mediatek_dwmac_match[] = {
{ .compatible = "mediatek,mt2712-gmac",
.data = &mt2712_gmac_variant },
{ .compatible = "mediatek,mt8195-gmac",
.data = &mt8195_gmac_variant },
{ }
};
......
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