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Commit 498f2a4b authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'zynqmp-dt-for-v5.6' of https://github.com/Xilinx/linux-xlnx into arm/dt 

arm64: dts: zynqmp: DT changes for v5.6

- Switch from fixed to firmware based clock driver
- Wire power domain driver
- Wire all ina226 chips through IIO and IIO hwmon drivers
- Add missing dr_mode property to usb nodes
- Use gpio-line-names property instead of comments
- Use clock-output-names for si570 differentiation
- Minor DT fixes

* tag 'zynqmp-dt-for-v5.6' of https://github.com/Xilinx/linux-xlnx: (21 commits)
  arm64: zynqmp: Add label property to all ina226 on zcu106
  arm64: zynqmp: Enable iio-hwmon for ina226 on zcu106
  arm64: zynqmp: Add label property to all ina226 on zcu102
  arm64: zynqmp: Enable iio-hwmon for ina226 on zcu102
  arm64: zynqmp: Add label property to all ina226 on zcu111
  arm64: zynqmp: Enable iio-hwmon for ina226 on zcu111
  arm64: zynqmp: Enable iio-hwmon for ina226 on zcu100
  arm64: zynqmp: Setup default number of chipselects for zcu100
  arm64: zynqmp: Remove broken-cd from zcu100-revC
  arm64: zynqmp: Fix the si570 clock frequency on zcu111
  arm64: zynqmp: Setup clock-output-names for si570 chips
  arm64: zynqmp: Turn comment to gpio-line-names
  arm64: zynqmp: Fix address for tca6416_u97 chip on zcu104
  arm64: zynqmp: Remove addition number in node name
  arm64: zynqmp: Use ethernet-phy as node name for ethernet phys
  arm64: dts: xilinx: Add the power nodes for zynqmp
  arm64: dts: xilinx: Remove dtsi for fixed clock
  arm64: dts: xilinx: Add the clock nodes for zynqmp
  arm64: zynqmp: Add dr_mode property to usb node
  arm64: dts: zynqmp: Use decimal values for drm-clock properties
  ...

Link: https://lore.kernel.org/r/c70d2efa-9ee2-a764-5248-0e5bfbf29f8a@monstr.euSigned-off-by: default avatarOlof Johansson <olof@lixom.net>
parents c14e723e 5a25e646
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arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi 0 → 100644
View file @ 498f2a4b
// SPDX-License-Identifier: GPL-2.0+
/*
* Clock specification for Xilinx ZynqMP
*
* (C) Copyright 2017 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
/ {
pss_ref_clk: pss_ref_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33333333>;
};
video_clk: video_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
pss_alt_ref_clk: pss_alt_ref_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
gt_crx_ref_clk: gt_crx_ref_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <108000000>;
};
aux_ref_clk: aux_ref_clk {
u-boot,dm-pre-reloc;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
&can0 {
clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&can1 {
clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&cpu0 {
clocks = <&zynqmp_clk ACPU>;
};
&fpd_dma_chan1 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan2 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan3 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan4 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan5 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan6 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan7 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&fpd_dma_chan8 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan1 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan2 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan3 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan4 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan5 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan6 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan7 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&lpd_dma_chan8 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&gem0 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
<&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};
&gem1 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
<&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};
&gem2 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
<&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};
&gem3 {
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
<&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
<&zynqmp_clk GEM_TSU>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
};
&gpio {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&i2c0 {
clocks = <&zynqmp_clk I2C0_REF>;
};
&i2c1 {
clocks = <&zynqmp_clk I2C1_REF>;
};
&pcie {
clocks = <&zynqmp_clk PCIE_REF>;
};
&sata {
clocks = <&zynqmp_clk SATA_REF>;
};
&sdhci0 {
clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&sdhci1 {
clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&spi0 {
clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&spi1 {
clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&ttc0 {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&ttc1 {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&ttc2 {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&ttc3 {
clocks = <&zynqmp_clk LPD_LSBUS>;
};
&uart0 {
clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&uart1 {
clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
};
&usb0 {
clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
};
&usb1 {
clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
};
&watchdog0 {
clocks = <&zynqmp_clk WDT>;
};
arch/arm64/boot/dts/xilinx/zynqmp-clk.dtsi deleted 100644 → 0
View file @ c14e723e
// SPDX-License-Identifier: GPL-2.0+
/*
* Clock specification for Xilinx ZynqMP
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
/ {
clk100: clk100 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
clk125: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
clk200: clk200 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
clk250: clk250 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
};
clk300: clk300 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <300000000>;
};
clk600: clk600 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <600000000>;
};
dp_aclk: clock0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-accuracy = <100>;
};
dp_aud_clk: clock1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
clock-accuracy = <100>;
};
dpdma_clk: dpdma-clk {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <533000000>;
};
drm_clock: drm-clock {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <262750000>;
clock-accuracy = <0x64>;
};
};
&can0 {
clocks = <&clk100 &clk100>;
};
&can1 {
clocks = <&clk100 &clk100>;
};
&fpd_dma_chan1 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan2 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan3 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan4 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan5 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan6 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan7 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan8 {
clocks = <&clk600>, <&clk100>;
};
&lpd_dma_chan1 {
clocks = <&clk600>, <&clk100>;
};
&lpd_dma_chan2 {
clocks = <&clk600>, <&clk100>;
};
&lpd_dma_chan3 {
clocks = <&clk600>, <&clk100>;
};
&lpd_dma_chan4 {
clocks = <&clk600>, <&clk100>;
};
&lpd_dma_chan5 {
clocks = <&clk600>, <&clk100>;
};
&lpd_dma_chan6 {
clocks = <&clk600>, <&clk100>;
};
&lpd_dma_chan7 {
clocks = <&clk600>, <&clk100>;
};
&lpd_dma_chan8 {
clocks = <&clk600>, <&clk100>;
};
&gem0 {
clocks = <&clk125>, <&clk125>, <&clk125>;
};
&gem1 {
clocks = <&clk125>, <&clk125>, <&clk125>;
};
&gem2 {
clocks = <&clk125>, <&clk125>, <&clk125>;
};
&gem3 {
clocks = <&clk125>, <&clk125>, <&clk125>;
};
&gpio {
clocks = <&clk100>;
};
&i2c0 {
clocks = <&clk100>;
};
&i2c1 {
clocks = <&clk100>;
};
&sata {
clocks = <&clk250>;
};
&sdhci0 {
clocks = <&clk200 &clk200>;
};
&sdhci1 {
clocks = <&clk200 &clk200>;
};
&spi0 {
clocks = <&clk200 &clk200>;
};
&spi1 {
clocks = <&clk200 &clk200>;
};
&uart0 {
clocks = <&clk100 &clk100>;
};
&uart1 {
clocks = <&clk100 &clk100>;
};
&usb0 {
clocks = <&clk250>, <&clk250>;
};
&usb1 {
clocks = <&clk250>, <&clk250>;
};
&watchdog0 {
clocks = <&clk250>;
};
arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts
View file @ 498f2a4b
......@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZC1232
*
* (C) Copyright 2017 - 2018, Xilinx, Inc.
* (C) Copyright 2017 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
......@@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP ZC1232 RevA";
......
arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts
View file @ 498f2a4b
......@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZC1254
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
* (C) Copyright 2015 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
......@@ -11,7 +11,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP ZC1254 RevA";
......
arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dts
View file @ 498f2a4b
......@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZC1275
*
* (C) Copyright 2017 - 2018, Xilinx, Inc.
* (C) Copyright 2017 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
......@@ -11,7 +11,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP ZC1275 RevA";
......
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
View file @ 498f2a4b
......@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm015-dc1
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
* (C) Copyright 2015 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
......@@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
......@@ -73,7 +73,7 @@ &gem3 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@0 {
phy0: ethernet-phy@0 {
reg = <0>;
};
};
......@@ -128,4 +128,5 @@ &uart0 {
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
dr_mode = "host";
};
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
View file @ 498f2a4b
......@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
* (C) Copyright 2015 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
......@@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
......@@ -84,7 +84,7 @@ &gem2 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@5 {
phy0: ethernet-phy@5 {
reg = <5>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
......@@ -123,7 +123,7 @@ &spi0 {
status = "okay";
num-cs = <1>;
spi0_flash0: flash0@0 {
spi0_flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst,sst25wf080", "jedec,spi-nor";
......@@ -141,7 +141,7 @@ &spi1 {
status = "okay";
num-cs = <1>;
spi1_flash0: flash0@0 {
spi1_flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
......@@ -158,6 +158,7 @@ partition@0 {
/* ULPI SMSC USB3320 */
&usb1 {
status = "okay";
dr_mode = "host";
};
&uart0 {
......
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
View file @ 498f2a4b
......@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm017-dc3
*
* (C) Copyright 2016 - 2018, Xilinx, Inc.
* (C) Copyright 2016 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
......@@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP zc1751-xm017-dc3 RevA";
......@@ -73,7 +73,7 @@ &gem0 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@0 { /* VSC8211 */
phy0: ethernet-phy@0 { /* VSC8211 */
reg = <0>;
};
};
......
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
View file @ 498f2a4b
......@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm018-dc4
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
* (C) Copyright 2015 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
......@@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP zc1751-xm018-dc4";
......
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
View file @ 498f2a4b
......@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP zc1751-xm019-dc5
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
* (C) Copyright 2015 - 2019, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>
......@@ -11,7 +11,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
......@@ -74,7 +74,7 @@ &gem1 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@0 {
phy0: ethernet-phy@0 {
reg = <0>;
};
};
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
View file @ 498f2a4b
......@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU100 revC
*
* (C) Copyright 2016 - 2018, Xilinx, Inc.
* (C) Copyright 2016 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
* Nathalie Chan King Choy
......@@ -11,7 +11,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
......@@ -103,6 +103,11 @@ sdio_pwrseq: sdio-pwrseq {
reset-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; /* WIFI_EN */
post-power-on-delay-ms = <10>;
};
ina226 {
compatible = "iio-hwmon";
io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
};
};
&dcc {
......@@ -191,8 +196,9 @@ i2csw_5: i2c@5 {
#size-cells = <0>;
reg = <5>;
/* PS_PMBUS */
ina226@40 { /* u35 */
u35: ina226@40 { /* u35 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
reg = <0x40>;
shunt-resistor = <10000>;
/* MIO31 is alert which should be routed to PMUFW */
......@@ -226,7 +232,6 @@ &rtc {
&sdhci0 {
status = "okay";
no-1-8-v;
broken-cd; /* CD has to be enabled by default */
disable-wp;
};
......@@ -251,11 +256,13 @@ wlcore: wifi@2 {
&spi0 { /* Low Speed connector */
status = "okay";
label = "LS-SPI0";
num-cs = <1>;
};
&spi1 { /* High Speed connector */
status = "okay";
label = "HS-SPI1";
num-cs = <1>;
};
&uart0 {
......@@ -274,11 +281,13 @@ &uart1 {
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
dr_mode = "peripheral";
};
/* ULPI SMSC USB3320 */
&usb1 {
status = "okay";
dr_mode = "host";
};
&watchdog0 {
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
View file @ 498f2a4b
......@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU102 RevA
*
* (C) Copyright 2015 - 2018, Xilinx, Inc.
* (C) Copyright 2015 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
......@@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
......@@ -59,6 +59,79 @@ heartbeat-led {
linux,default-trigger = "heartbeat";
};
};
ina226-u76 {
compatible = "iio-hwmon";
io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
};
ina226-u77 {
compatible = "iio-hwmon";
io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
};
ina226-u78 {
compatible = "iio-hwmon";
io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
};
ina226-u87 {
compatible = "iio-hwmon";
io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
};
ina226-u85 {
compatible = "iio-hwmon";
io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
};
ina226-u86 {
compatible = "iio-hwmon";
io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
};
ina226-u93 {
compatible = "iio-hwmon";
io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
};
ina226-u88 {
compatible = "iio-hwmon";
io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
};
ina226-u15 {
compatible = "iio-hwmon";
io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
};
ina226-u92 {
compatible = "iio-hwmon";
io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
};
ina226-u79 {
compatible = "iio-hwmon";
io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
};
ina226-u81 {
compatible = "iio-hwmon";
io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
};
ina226-u80 {
compatible = "iio-hwmon";
io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
};
ina226-u84 {
compatible = "iio-hwmon";
io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
};
ina226-u16 {
compatible = "iio-hwmon";
io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
};
ina226-u65 {
compatible = "iio-hwmon";
io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
};
ina226-u74 {
compatible = "iio-hwmon";
io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
};
ina226-u75 {
compatible = "iio-hwmon";
io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
};
};
&can1 {
......@@ -105,7 +178,7 @@ &gem3 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@21 {
phy0: ethernet-phy@21 {
reg = <21>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
......@@ -125,21 +198,11 @@ &i2c0 {
tca6416_u97: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
gpio-controller; /* IRQ not connected */
#gpio-cells = <2>;
/*
* IRQ not connected
* Lines:
* 0 - PS_GTR_LAN_SEL0
* 1 - PS_GTR_LAN_SEL1
* 2 - PS_GTR_LAN_SEL2
* 3 - PS_GTR_LAN_SEL3
* 4 - PCI_CLK_DIR_SEL
* 5 - IIC_MUX_RESET_B
* 6 - GEM3_EXP_RESET_B
* 7, 10 - 17 - not connected
*/
gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
"PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
"", "", "", "", "", "", "", "", "";
gtr-sel0 {
gpio-hog;
gpios = <0 0>;
......@@ -169,27 +232,12 @@ gtr-sel3 {
tca6416_u61: gpio@21 {
compatible = "ti,tca6416";
reg = <0x21>;
gpio-controller;
gpio-controller; /* IRQ not connected */
#gpio-cells = <2>;
/*
* IRQ not connected
* Lines:
* 0 - VCCPSPLL_EN
* 1 - MGTRAVCC_EN
* 2 - MGTRAVTT_EN
* 3 - VCCPSDDRPLL_EN
* 4 - MIO26_PMU_INPUT_LS
* 5 - PL_PMBUS_ALERT
* 6 - PS_PMBUS_ALERT
* 7 - MAXIM_PMBUS_ALERT
* 10 - PL_DDR4_VTERM_EN
* 11 - PL_DDR4_VPP_2V5_EN
* 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
* 13 - PS_DIMM_SUSPEND_EN
* 14 - PS_DDR4_VTERM_EN
* 15 - PS_DDR4_VPP_2V5_EN
* 16 - 17 - not connected
*/
gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
"PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
"PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
"PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
};
i2c-mux@75 { /* u60 */
......@@ -202,53 +250,73 @@ i2c@0 {
#size-cells = <0>;
reg = <0>;
/* PS_PMBUS */
ina226@40 { /* u76 */
u76: ina226@40 { /* u76 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u76";
reg = <0x40>;
shunt-resistor = <5000>;
};
ina226@41 { /* u77 */
u77: ina226@41 { /* u77 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u77";
reg = <0x41>;
shunt-resistor = <5000>;
};
ina226@42 { /* u78 */
u78: ina226@42 { /* u78 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u78";
reg = <0x42>;
shunt-resistor = <5000>;
};
ina226@43 { /* u87 */
u87: ina226@43 { /* u87 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u87";
reg = <0x43>;
shunt-resistor = <5000>;
};
ina226@44 { /* u85 */
u85: ina226@44 { /* u85 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u85";
reg = <0x44>;
shunt-resistor = <5000>;
};
ina226@45 { /* u86 */
u86: ina226@45 { /* u86 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u86";
reg = <0x45>;
shunt-resistor = <5000>;
};
ina226@46 { /* u93 */
u93: ina226@46 { /* u93 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u93";
reg = <0x46>;
shunt-resistor = <5000>;
};
ina226@47 { /* u88 */
u88: ina226@47 { /* u88 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u88";
reg = <0x47>;
shunt-resistor = <5000>;
};
ina226@4a { /* u15 */
u15: ina226@4a { /* u15 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u15";
reg = <0x4a>;
shunt-resistor = <5000>;
};
ina226@4b { /* u92 */
u92: ina226@4b { /* u92 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u92";
reg = <0x4b>;
shunt-resistor = <5000>;
};
......@@ -258,43 +326,59 @@ i2c@1 {
#size-cells = <0>;
reg = <1>;
/* PL_PMBUS */
ina226@40 { /* u79 */
u79: ina226@40 { /* u79 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u79";
reg = <0x40>;
shunt-resistor = <2000>;
};
ina226@41 { /* u81 */
u81: ina226@41 { /* u81 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u81";
reg = <0x41>;
shunt-resistor = <5000>;
};
ina226@42 { /* u80 */
u80: ina226@42 { /* u80 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u80";
reg = <0x42>;
shunt-resistor = <5000>;
};
ina226@43 { /* u84 */
u84: ina226@43 { /* u84 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u84";
reg = <0x43>;
shunt-resistor = <5000>;
};
ina226@44 { /* u16 */
u16: ina226@44 { /* u16 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u16";
reg = <0x44>;
shunt-resistor = <5000>;
};
ina226@45 { /* u65 */
u65: ina226@45 { /* u65 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u65";
reg = <0x45>;
shunt-resistor = <5000>;
};
ina226@46 { /* u74 */
u74: ina226@46 { /* u74 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u74";
reg = <0x46>;
shunt-resistor = <5000>;
};
ina226@47 { /* u75 */
u75: ina226@47 { /* u75 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u75";
reg = <0x47>;
shunt-resistor = <5000>;
};
......@@ -414,6 +498,7 @@ si570_1: clock-generator@5d { /* USER SI570 - u42 */
temperature-stability = <50>;
factory-fout = <300000000>;
clock-frequency = <300000000>;
clock-output-names = "si570_user";
};
};
i2c@3 {
......@@ -427,6 +512,7 @@ si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
temperature-stability = <50>; /* copy from zc702 */
factory-fout = <156250000>;
clock-frequency = <148500000>;
clock-output-names = "si570_mgt";
};
};
i2c@4 {
......@@ -540,6 +626,7 @@ &uart1 {
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
dr_mode = "host";
};
&watchdog0 {
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts
View file @ 498f2a4b
......@@ -16,7 +16,7 @@ / {
&gem3 {
phy-handle = <&phyc>;
phyc: phy@c {
phyc: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
......@@ -24,7 +24,7 @@ phyc: phy@c {
ti,dp83867-rxctrl-strap-quirk;
};
/* Cleanup from RevA */
/delete-node/ phy@21;
/delete-node/ ethernet-phy@21;
};
/* Fix collision with u61 */
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
View file @ 498f2a4b
......@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU104
*
* (C) Copyright 2017 - 2018, Xilinx, Inc.
* (C) Copyright 2017 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
......@@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
......@@ -50,7 +50,7 @@ &gem3 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@c {
phy0: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
......@@ -118,9 +118,9 @@ i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
tca6416_u97: gpio@21 {
tca6416_u97: gpio@20 {
compatible = "ti,tca6416";
reg = <0x21>;
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
/*
......@@ -189,6 +189,7 @@ &uart1 {
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
dr_mode = "host";
};
&watchdog0 {
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
View file @ 498f2a4b
......@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU106
*
* (C) Copyright 2016, Xilinx, Inc.
* (C) Copyright 2016 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
......@@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
......@@ -59,6 +59,79 @@ heartbeat-led {
linux,default-trigger = "heartbeat";
};
};
ina226-u76 {
compatible = "iio-hwmon";
io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
};
ina226-u77 {
compatible = "iio-hwmon";
io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
};
ina226-u78 {
compatible = "iio-hwmon";
io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
};
ina226-u87 {
compatible = "iio-hwmon";
io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
};
ina226-u85 {
compatible = "iio-hwmon";
io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
};
ina226-u86 {
compatible = "iio-hwmon";
io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
};
ina226-u93 {
compatible = "iio-hwmon";
io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
};
ina226-u88 {
compatible = "iio-hwmon";
io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
};
ina226-u15 {
compatible = "iio-hwmon";
io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
};
ina226-u92 {
compatible = "iio-hwmon";
io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
};
ina226-u79 {
compatible = "iio-hwmon";
io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
};
ina226-u81 {
compatible = "iio-hwmon";
io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
};
ina226-u80 {
compatible = "iio-hwmon";
io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
};
ina226-u84 {
compatible = "iio-hwmon";
io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
};
ina226-u16 {
compatible = "iio-hwmon";
io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
};
ina226-u65 {
compatible = "iio-hwmon";
io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
};
ina226-u74 {
compatible = "iio-hwmon";
io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
};
ina226-u75 {
compatible = "iio-hwmon";
io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
};
};
&can1 {
......@@ -106,7 +179,7 @@ &gem3 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@c {
phy0: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
......@@ -177,53 +250,73 @@ i2c@0 {
#size-cells = <0>;
reg = <0>;
/* PS_PMBUS */
ina226@40 { /* u76 */
u76: ina226@40 { /* u76 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u76";
reg = <0x40>;
shunt-resistor = <5000>;
};
ina226@41 { /* u77 */
u77: ina226@41 { /* u77 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u77";
reg = <0x41>;
shunt-resistor = <5000>;
};
ina226@42 { /* u78 */
u78: ina226@42 { /* u78 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u78";
reg = <0x42>;
shunt-resistor = <5000>;
};
ina226@43 { /* u87 */
u87: ina226@43 { /* u87 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u87";
reg = <0x43>;
shunt-resistor = <5000>;
};
ina226@44 { /* u85 */
u85: ina226@44 { /* u85 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u85";
reg = <0x44>;
shunt-resistor = <5000>;
};
ina226@45 { /* u86 */
u86: ina226@45 { /* u86 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u86";
reg = <0x45>;
shunt-resistor = <5000>;
};
ina226@46 { /* u93 */
u93: ina226@46 { /* u93 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u93";
reg = <0x46>;
shunt-resistor = <5000>;
};
ina226@47 { /* u88 */
u88: ina226@47 { /* u88 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u88";
reg = <0x47>;
shunt-resistor = <5000>;
};
ina226@4a { /* u15 */
u15: ina226@4a { /* u15 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u15";
reg = <0x4a>;
shunt-resistor = <5000>;
};
ina226@4b { /* u92 */
u92: ina226@4b { /* u92 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u92";
reg = <0x4b>;
shunt-resistor = <5000>;
};
......@@ -233,43 +326,59 @@ i2c@1 {
#size-cells = <0>;
reg = <1>;
/* PL_PMBUS */
ina226@40 { /* u79 */
u79: ina226@40 { /* u79 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u79";
reg = <0x40>;
shunt-resistor = <2000>;
};
ina226@41 { /* u81 */
u81: ina226@41 { /* u81 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u81";
reg = <0x41>;
shunt-resistor = <5000>;
};
ina226@42 { /* u80 */
u80: ina226@42 { /* u80 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u80";
reg = <0x42>;
shunt-resistor = <5000>;
};
ina226@43 { /* u84 */
u84: ina226@43 { /* u84 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u84";
reg = <0x43>;
shunt-resistor = <5000>;
};
ina226@44 { /* u16 */
u16: ina226@44 { /* u16 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u16";
reg = <0x44>;
shunt-resistor = <5000>;
};
ina226@45 { /* u65 */
u65: ina226@45 { /* u65 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u65";
reg = <0x45>;
shunt-resistor = <5000>;
};
ina226@46 { /* u74 */
u74: ina226@46 { /* u74 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u74";
reg = <0x46>;
shunt-resistor = <5000>;
};
ina226@47 { /* u75 */
u75: ina226@47 { /* u75 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u75";
reg = <0x47>;
shunt-resistor = <5000>;
};
......@@ -388,6 +497,7 @@ si570_1: clock-generator@5d { /* USER SI570 - u42 */
temperature-stability = <50>;
factory-fout = <300000000>;
clock-frequency = <300000000>;
clock-output-names = "si570_user";
};
};
i2c@3 {
......@@ -401,6 +511,7 @@ si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
temperature-stability = <50>; /* copy from zc702 */
factory-fout = <156250000>;
clock-frequency = <148500000>;
clock-output-names = "si570_mgt";
};
};
i2c@4 {
......@@ -514,6 +625,7 @@ &uart1 {
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
dr_mode = "host";
};
&watchdog0 {
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
View file @ 498f2a4b
......@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP ZCU111
*
* (C) Copyright 2017 - 2018, Xilinx, Inc.
* (C) Copyright 2017 - 2019, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
......@@ -10,7 +10,7 @@
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
......@@ -59,6 +59,63 @@ heartbeat-led {
linux,default-trigger = "heartbeat";
};
};
ina226-u67 {
compatible = "iio-hwmon";
io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;
};
ina226-u59 {
compatible = "iio-hwmon";
io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;
};
ina226-u61 {
compatible = "iio-hwmon";
io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
};
ina226-u60 {
compatible = "iio-hwmon";
io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
};
ina226-u64 {
compatible = "iio-hwmon";
io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
};
ina226-u69 {
compatible = "iio-hwmon";
io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;
};
ina226-u66 {
compatible = "iio-hwmon";
io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;
};
ina226-u65 {
compatible = "iio-hwmon";
io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
};
ina226-u63 {
compatible = "iio-hwmon";
io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
};
ina226-u3 {
compatible = "iio-hwmon";
io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;
};
ina226-u71 {
compatible = "iio-hwmon";
io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;
};
ina226-u77 {
compatible = "iio-hwmon";
io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
};
ina226-u73 {
compatible = "iio-hwmon";
io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;
};
ina226-u79 {
compatible = "iio-hwmon";
io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
};
};
&dcc {
......@@ -101,7 +158,7 @@ &gem3 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: phy@c {
phy0: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
......@@ -152,73 +209,101 @@ i2c@0 {
reg = <0>;
/* PS_PMBUS */
/* PMBUS_ALERT done via pca9544 */
ina226@40 { /* u67 */
u67: ina226@40 { /* u67 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u67";
reg = <0x40>;
shunt-resistor = <2000>;
};
ina226@41 { /* u59 */
u59: ina226@41 { /* u59 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u59";
reg = <0x41>;
shunt-resistor = <5000>;
};
ina226@42 { /* u61 */
u61: ina226@42 { /* u61 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u61";
reg = <0x42>;
shunt-resistor = <5000>;
};
ina226@43 { /* u60 */
u60: ina226@43 { /* u60 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u60";
reg = <0x43>;
shunt-resistor = <5000>;
};
ina226@45 { /* u64 */
u64: ina226@45 { /* u64 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u64";
reg = <0x45>;
shunt-resistor = <5000>;
};
ina226@46 { /* u69 */
u69: ina226@46 { /* u69 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u69";
reg = <0x46>;
shunt-resistor = <2000>;
};
ina226@47 { /* u66 */
u66: ina226@47 { /* u66 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u66";
reg = <0x47>;
shunt-resistor = <5000>;
};
ina226@48 { /* u65 */
u65: ina226@48 { /* u65 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u65";
reg = <0x48>;
shunt-resistor = <5000>;
};
ina226@49 { /* u63 */
u63: ina226@49 { /* u63 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u63";
reg = <0x49>;
shunt-resistor = <5000>;
};
ina226@4a { /* u3 */
u3: ina226@4a { /* u3 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u3";
reg = <0x4a>;
shunt-resistor = <5000>;
};
ina226@4b { /* u71 */
u71: ina226@4b { /* u71 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u71";
reg = <0x4b>;
shunt-resistor = <5000>;
};
ina226@4c { /* u77 */
u77: ina226@4c { /* u77 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u77";
reg = <0x4c>;
shunt-resistor = <5000>;
};
ina226@4d { /* u73 */
u73: ina226@4d { /* u73 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u73";
reg = <0x4d>;
shunt-resistor = <5000>;
};
ina226@4e { /* u79 */
u79: ina226@4e { /* u79 */
compatible = "ti,ina226";
#io-channel-cells = <1>;
label = "ina226-u79";
reg = <0x4e>;
shunt-resistor = <5000>;
};
......@@ -304,6 +389,7 @@ si570_1: clock-generator@5d { /* USER SI570 - u47 */
temperature-stability = <50>;
factory-fout = <300000000>;
clock-frequency = <300000000>;
clock-output-names = "si570_user";
};
};
i2c@3 {
......@@ -316,7 +402,8 @@ si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
reg = <0x5d>;
temperature-stability = <50>;
factory-fout = <156250000>;
clock-frequency = <148500000>;
clock-frequency = <156250000>;
clock-output-names = "si570_mgt";
};
};
i2c@4 {
......@@ -440,4 +527,5 @@ &uart0 {
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
dr_mode = "host";
};
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
View file @ 498f2a4b
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