drm/amd/swsmu: update smu v14_0_0 header files and metrics table

Update driver if, pmfw and ppsmc header files.
Add new gpu_metrics_v3_0 for metrics table updated in driver if
and reserve legacy metrics table to maintain backward compatibility.
---
v1:
Update header files and add gpu_metrics_v3_0.
v2:
Update smu_types.h, smu headers and drop smu_cmn_get_smc_version in smu v14_0_0.
Signed-off-by: Li Ma <li.ma@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/include/kgd_pp_interface.h

@@ -1057,4 +1057,72 @@ struct gpu_metrics_v2_4 {
 	uint16_t			average_soc_current;
 	uint16_t			average_gfx_current;
 };
+
+struct gpu_metrics_v3_0 {
+	struct metrics_table_header	common_header;
+
+	/* Temperature */
+	/* gfx temperature on APUs */
+	uint16_t			temperature_gfx;
+	/* soc temperature on APUs */
+	uint16_t			temperature_soc;
+	/* CPU core temperature on APUs */
+	uint16_t			temperature_core[16];
+	/* skin temperature on APUs */
+	uint16_t			temperature_skin;
+
+	/* Utilization */
+	/* time filtered GFX busy % [0-100] */
+	uint16_t			average_gfx_activity;
+	/* time filtered VCN busy % [0-100] */
+	uint16_t			average_vcn_activity;
+	/* time filtered IPU per-column busy % [0-100] */
+	uint16_t			average_ipu_activity[8];
+	/* time filtered per-core C0 residency % [0-100]*/
+	uint16_t			average_core_c0_activity[16];
+	/* time filtered DRAM read bandwidth [GB/sec] */
+	uint16_t			average_dram_reads;
+	/* time filtered DRAM write bandwidth [GB/sec] */
+	uint16_t			average_dram_writes;
+
+	/* Driver attached timestamp (in ns) */
+	uint64_t			system_clock_counter;
+
+	/* Power/Energy */
+	/* average dGPU + APU power on A + A platform */
+	uint32_t			average_socket_power;
+	/* average IPU power [W] */
+	uint16_t			average_ipu_power;
+	/* average APU power [W] */
+	uint32_t			average_apu_power;
+	/* average dGPU power [W] */
+	uint32_t			average_dgpu_power;
+	/* sum of core power across all cores in the socket [W] */
+	uint32_t			average_core_power;
+	/* calculated core power [W] */
+	uint16_t			core_power[16];
+	/* maximum IRM defined STAPM power limit [W] */
+	uint16_t			stapm_power_limit;
+	/* time filtered STAPM power limit [W] */
+	uint16_t			current_stapm_power_limit;
+
+	/* Average clocks */
+	uint16_t			average_gfxclk_frequency;
+	uint16_t			average_socclk_frequency;
+	uint16_t			average_vpeclk_frequency;
+	uint16_t			average_ipuclk_frequency;
+	uint16_t			average_fclk_frequency;
+	uint16_t			average_vclk_frequency;
+
+	/* Current clocks */
+	/* target core frequency */
+	uint16_t			current_coreclk[16];
+	/* CCLK frequency limit enforced on classic cores [MHz] */
+	uint16_t			current_core_maxfreq;
+	/* GFXCLK frequency limit enforced on GFX [MHz] */
+	uint16_t			current_gfx_maxfreq;
+
+	/* Metrics table alpha filter time constant [us] */
+	uint32_t			time_filter_alphavalue;
+};
 #endif

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h

@@ -149,23 +149,37 @@ typedef struct {
   uint32_t MaxGfxClk;
 } DpmClocks_t;
 
-
-// Throttler Status Bitmask
-#define THROTTLER_STATUS_BIT_SPL              0
-#define THROTTLER_STATUS_BIT_FPPT             1
-#define THROTTLER_STATUS_BIT_SPPT             2
-#define THROTTLER_STATUS_BIT_SPPT_APU         3
-#define THROTTLER_STATUS_BIT_THM_CORE         4
-#define THROTTLER_STATUS_BIT_THM_GFX          5
-#define THROTTLER_STATUS_BIT_THM_SOC          6
-#define THROTTLER_STATUS_BIT_TDC_VDD          7
-#define THROTTLER_STATUS_BIT_TDC_VDDCCX       8
-#define THROTTLER_STATUS_BIT_TDC_SOC          9
-#define THROTTLER_STATUS_BIT_PROCHOT_CPU      10
-#define THROTTLER_STATUS_BIT_PROCHOT_GFX      11
-#define THROTTLER_STATUS_BIT_EDC_CPU_CLASSIC  12
-#define THROTTLER_STATUS_BIT_EDC_CPU_DENSE    13
-#define THROTTLER_STATUS_BIT_EDC_GFX          14
+typedef struct {
+  uint16_t CoreFrequency[16];           //Target core frequency [MHz]
+  uint16_t CorePower[16];               //CAC calculated core power [W] [Q8.8]
+  uint16_t CoreTemperature[16];         //TSEN measured core temperature [C] [Q8.8]
+  uint16_t GfxTemperature;              //TSEN measured GFX temperature [C] [Q8.8]
+  uint16_t SocTemperature;              //TSEN measured SOC temperature [C] [Q8.8]
+  uint16_t StapmOpnLimit;               //Maximum IRM defined STAPM power limit [W] [Q8.8]
+  uint16_t StapmCurrentLimit;           //Time filtered STAPM power limit [W] [Q8.8]
+  uint16_t InfrastructureCpuMaxFreq;    //CCLK frequency limit enforced on classic cores [MHz]
+  uint16_t InfrastructureGfxMaxFreq;    //GFXCLK frequency limit enforced on GFX [MHz]
+  uint16_t SkinTemp;                    //Maximum skin temperature reported by APU and HS2 chassis sensors [C] [Q8.8]
+  uint16_t AverageGfxclkFrequency;      //Time filtered target GFXCLK frequency [MHz]
+  uint16_t AverageFclkFrequency;        //Time filtered target FCLK frequency [MHz]
+  uint16_t AverageGfxActivity;          //Time filtered GFX busy % [0-100] [Q8.8]
+  uint16_t AverageSocclkFrequency;      //Time filtered target SOCCLK frequency [MHz]
+  uint16_t AverageVclkFrequency;        //Time filtered target VCLK frequency [MHz]
+  uint16_t AverageVcnActivity;          //Time filtered VCN busy % [0-100] [Q8.8]
+  uint16_t AverageVpeclkFrequency;      //Time filtered target VPECLK frequency [MHz]
+  uint16_t AverageIpuclkFrequency;      //Time filtered target IPUCLK frequency [MHz]
+  uint16_t AverageIpuBusy[8];           //Time filtered IPU per-column busy % [0-100] [Q8.8]
+  uint16_t AverageDRAMReads;            //Time filtered DRAM read bandwidth [GB/sec] [Q8.8]
+  uint16_t AverageDRAMWrites;           //Time filtered DRAM write bandwidth [GB/sec] [Q8.8]
+  uint16_t AverageCoreC0Residency[16];  //Time filtered per-core C0 residency % [0-100] [Q8.8]
+  uint16_t IpuPower;                    //Time filtered IPU power [W] [Q8.8]
+  uint32_t ApuPower;                    //Time filtered APU power [W] [Q24.8]
+  uint32_t dGpuPower;                   //Time filtered dGPU power [W] [Q24.8]
+  uint32_t AverageSocketPower;          //Time filtered power used for PPT/STAPM [APU+dGPU] [W] [Q24.8]
+  uint32_t AverageCorePower;            //Time filtered sum of core power across all cores in the socket [W] [Q24.8]
+  uint32_t FilterAlphaValue;            //Metrics table alpha filter time constant [us]
+  uint32_t MetricsCounter;              //Counter that is incremented on every metrics table update [PM_TIMER cycles]
+} SmuMetrics_t;
 
 typedef struct {
   uint16_t GfxclkFrequency;             //[MHz]
@@ -212,7 +226,6 @@ typedef struct {
   uint16_t CurTemp;                     //[centi-Celsius]
   uint16_t FilterAlphaValue;            //[m]
 
-  //PMFW-8735
   uint16_t AverageGfxclkFrequency;
   uint16_t AverageFclkFrequency;
   uint16_t AverageGfxActivity;
@@ -224,20 +237,9 @@ typedef struct {
   uint16_t AverageSocketPower;        //Filtered value of CurrentSocketPower
   uint16_t AverageCorePower[2];       //Filtered of [sum of CorePower[8] per ccx])
   uint16_t AverageCoreC0Residency[16]; //Filtered of [average C0 residency % per core]
-  uint16_t spare3;
+  uint16_t spare1;
   uint32_t MetricsCounter;            //Counts the # of metrics table parameter reads per update to the metrics table, i.e. if the metrics table update happens every 1 second, this value could be up to 1000 if the smu collected metrics data every cycle, or as low as 0 if the smu was asleep the whole time. Reset to 0 after writing.
-} SmuMetrics_t;
-
-typedef struct {
-  uint16_t StapmMaxPlatformLimit;            //[W]
-  uint16_t StapmMinPlatformLimit;            //[W]
-  uint16_t FastPptMaxPlatformLimit;          //[W]
-  uint16_t FastPptMinPlatformLimit;          //[W]
-  uint16_t SlowPptMaxPlatformLimit;          //[W]
-  uint16_t SlowPptMinPlatformLimit;          //[W]
-  uint16_t SlowPptApuMaxPlatformLimit;       //[W]
-  uint16_t SlowPptApuMinPlatformLimit;       //[W]
-} PmfInfo_t;
+} SmuMetrics_legacy_t;
 
 //ISP tile definitions
 typedef enum {
@@ -272,10 +274,9 @@ typedef enum {
 #define TABLE_CUSTOM_DPM            2 // Called by Driver
 #define TABLE_BIOS_GPIO_CONFIG      3 // Called by BIOS
 #define TABLE_DPMCLOCKS             4 // Called by Driver and VBIOS
-#define TABLE_MOMENTARY_PM          5 // Called by Tools
+#define TABLE_SPARE0                5 // Unused
 #define TABLE_MODERN_STDBY          6 // Called by Tools for Modern Standby Log
 #define TABLE_SMU_METRICS           7 // Called by Driver and SMF/PMF
-#define TABLE_INFRASTRUCTURE_LIMITS 8 // Called by SMF/PMF
-#define TABLE_COUNT                 9
+#define TABLE_COUNT                 8
 
 #endif

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_pmfw.h

@@ -58,22 +58,22 @@
 #define FEATURE_DS_LCLK_BIT                 23
 #define FEATURE_LOW_POWER_DCNCLKS_BIT       24  // for all DISP clks
 #define FEATURE_DS_SHUBCLK_BIT              25
-#define FEATURE_GFX_TEMP_VMIN_BIT           26
+#define FEATURE_SPARE0_BIT                  26  //SPARE
 #define FEATURE_ZSTATES_BIT                 27
 #define FEATURE_IOMMUL2_PG_BIT              28
 #define FEATURE_DS_FCLK_BIT                 29
 #define FEATURE_DS_SMNCLK_BIT               30
 #define FEATURE_DS_MP1CLK_BIT               31
-#define FEATURE_RESERVED3                   32
+#define FEATURE_WHISPER_MODE_BIT            32
 #define FEATURE_SMU_LOW_POWER_BIT           33
 #define FEATURE_SMART_L3_RINSER_BIT         34
-#define FEATURE_GFX_DEM_BIT                 35
+#define FEATURE_SPARE1_BIT                  35  //SPARE
 #define FEATURE_PSI_BIT                     36
 #define FEATURE_PROCHOT_BIT                 37
 #define FEATURE_CPUOFF_BIT                  38
 #define FEATURE_STAPM_BIT                   39
 #define FEATURE_S0I3_BIT                    40
-#define FEATURE_DF_LIGHT_CSTATE             41   // shift the order or DFCstate annd DF light Cstate
+#define FEATURE_DF_LIGHT_CSTATE             41
 #define FEATURE_PERF_LIMIT_BIT              42
 #define FEATURE_CORE_DLDO_BIT               43
 #define FEATURE_DVO_BIT                     44
@@ -81,7 +81,7 @@
 #define FEATURE_CPPC_BIT                    46
 #define FEATURE_CPPC_PREFERRED_CORES        47
 #define FEATURE_DF_CSTATES_BIT              48
-#define FEATURE_RESERVED4                   49
+#define FEATURE_SPARE2_BIT                  49  //SPARE
 #define FEATURE_ATHUB_PG_BIT                50
 #define FEATURE_VDDOFF_ECO_BIT              51
 #define FEATURE_ZSTATES_ECO_BIT             52
@@ -89,12 +89,12 @@
 #define FEATURE_DS_UMCCLK_BIT               54
 #define FEATURE_DS_ISPCLK_BIT               55
 #define FEATURE_DS_HSPCLK_BIT               56
-#define FEATURE_RESERVED5                   57
+#define FEATURE_P3T_BIT                     57
 #define FEATURE_DS_IPUCLK_BIT               58
 #define FEATURE_DS_VPECLK_BIT               59
 #define FEATURE_VPE_DPM_BIT                 60
-#define FEATURE_BABYPHASE_SVI3_BIT          61
-#define FEATURE_FP_DIDT_BIT                 62
+#define FEATURE_SPARE_61                    61
+#define FEATURE_FP_DIDT                     62
 #define NUM_FEATURES                        63
 
 // Firmware Header/Footer
@@ -123,12 +123,13 @@ typedef struct {
   uint32_t DpmHubTask           : 4;
   // MP1_EXT_SCRATCH1
   uint32_t CclkSyncStatus       : 8;
+  uint32_t Ccx0CpuOff           : 2;
+  uint32_t Ccx1CpuOff           : 2;
   uint32_t GfxOffStatus         : 2;
-  uint32_t CpuOff               : 2;
   uint32_t VddOff               : 1;
-  uint32_t spare0               : 3;
+  uint32_t InWhisperMode        : 1;
   uint32_t ZstateStatus         : 4;
-  uint32_t spare1               : 4;
+  uint32_t spare0               : 4;
   uint32_t DstateFun            : 4;
   uint32_t DstateDev            : 4;
   // MP1_EXT_SCRATCH2
@@ -140,10 +141,10 @@ typedef struct {
   uint32_t MsgPortBusy          :24;
   uint32_t RsmuPmiP1Pending     : 1;
   uint32_t DfCstateExitPending  : 1;
-  uint32_t Pc6EntryPending      : 1;
-  uint32_t Pc6ExitPending       : 1;
+  uint32_t Ccx0Pc6ExitPending   : 1;
+  uint32_t Ccx1Pc6ExitPending   : 1;
   uint32_t WarmResetPending     : 1;
-  uint32_t spare2               : 3;
+  uint32_t spare1               : 3;
   // MP1_EXT_SCRATCH5
   uint32_t IdleMask             :32;
   // MP1_EXT_SCRATCH6 = RTOS threads' status

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_0_ppsmc.h

@@ -75,8 +75,8 @@
 
 #define PPSMC_MSG_EnableGfxImu                  0x16 ///< Enable GFX IMU
 
-#define PPSMC_MSG_GetGfxclkFrequency            0x17 ///< Get GFX clock frequency
-#define PPSMC_MSG_GetFclkFrequency              0x18 ///< Get FCLK frequency
+#define PPSMC_MSG_spare_0x17                    0x17
+#define PPSMC_MSG_spare_0x18                    0x18
 #define PPSMC_MSG_AllowGfxOff                   0x19 ///< Inform PMFW of allowing GFXOFF entry
 #define PPSMC_MSG_DisallowGfxOff                0x1A ///< Inform PMFW of disallowing GFXOFF entry
 #define PPSMC_MSG_SetSoftMaxGfxClk              0x1B ///< Set soft max for GFX CLK
@@ -85,6 +85,7 @@
 #define PPSMC_MSG_SetSoftMaxSocclkByFreq        0x1D ///< Set soft max for SOC CLK
 #define PPSMC_MSG_SetSoftMaxFclkByFreq          0x1E ///< Set soft max for FCLK
 #define PPSMC_MSG_SetSoftMaxVcn                 0x1F ///< Set soft max for VCN clocks (VCLK and DCLK)
+#define PPSMC_MSG_spare_0x20                    0x20
 #define PPSMC_MSG_PowerDownJpeg                 0x21 ///< Power down Jpeg
 #define PPSMC_MSG_PowerUpJpeg                   0x22 ///< Power up Jpeg; VCN is power gated by default
 

drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h

@@ -422,7 +422,8 @@ enum smu_clk_type {
        __SMU_DUMMY_MAP(ATHUB_MMHUB_PG),			\
        __SMU_DUMMY_MAP(BACO_CG),			\
        __SMU_DUMMY_MAP(SOC_CG),    \
-       __SMU_DUMMY_MAP(LOW_POWER_DCNCLKS),
+       __SMU_DUMMY_MAP(LOW_POWER_DCNCLKS),       \
+       __SMU_DUMMY_MAP(WHISPER_MODE),
 
 #undef __SMU_DUMMY_MAP
 #define __SMU_DUMMY_MAP(feature)	SMU_FEATURE_##feature##_BIT