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Commit 4c33e517 authored by Vijendar Mukunda's avatar Vijendar Mukunda Committed by Alex Deucher
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drm/amdgpu: create I2S platform devices for Jadeite platform 

Jadeite platform uses I2S MICSP instance.
Create platform devices for DMA controller and I2S controller for
Jadeite platform.
Signed-off-by: default avatarVijendar Mukunda <Vijendar.Mukunda@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 49062ee3
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Showing with 184 additions and 109 deletions
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
View file @ 4c33e517
...@@ -262,125 +262,200 @@ static int acp_hw_init(void *handle) ...@@ -262,125 +262,200 @@ static int acp_hw_init(void *handle)
adev->acp.acp_genpd->adev = adev; adev->acp.acp_genpd->adev = adev;
pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false); pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false);
dmi_check_system(acp_quirk_table);
switch (acp_machine_id) {
case ST_JADEITE:
{
adev->acp.acp_cell = kcalloc(2, sizeof(struct mfd_cell),
GFP_KERNEL);
if (!adev->acp.acp_cell) {
r = -ENOMEM;
goto failure;
}
adev->acp.acp_cell = kcalloc(ACP_DEVS, sizeof(struct mfd_cell), GFP_KERNEL); adev->acp.acp_res = kcalloc(3, sizeof(struct resource), GFP_KERNEL);
if (!adev->acp.acp_res) {
if (!adev->acp.acp_cell) { r = -ENOMEM;
r = -ENOMEM; goto failure;
goto failure; }
}
adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL);
if (!adev->acp.acp_res) {
r = -ENOMEM;
goto failure;
}
i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL); i2s_pdata = kcalloc(1, sizeof(struct i2s_platform_data), GFP_KERNEL);
if (!i2s_pdata) { if (!i2s_pdata) {
r = -ENOMEM; r = -ENOMEM;
goto failure; goto failure;
} }
switch (adev->asic_type) {
case CHIP_STONEY:
i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
i2s_pdata[0].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;
i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
adev->acp.acp_res[0].name = "acp2x_dma";
adev->acp.acp_res[0].flags = IORESOURCE_MEM;
adev->acp.acp_res[0].start = acp_base;
adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END;
adev->acp.acp_res[1].name = "acp2x_dw_i2s_play_cap";
adev->acp.acp_res[1].flags = IORESOURCE_MEM;
adev->acp.acp_res[1].start = acp_base + ACP_I2S_CAP_REGS_START;
adev->acp.acp_res[1].end = acp_base + ACP_I2S_CAP_REGS_END;
adev->acp.acp_res[2].name = "acp2x_dma_irq";
adev->acp.acp_res[2].flags = IORESOURCE_IRQ;
adev->acp.acp_res[2].start = amdgpu_irq_create_mapping(adev, 162);
adev->acp.acp_res[2].end = adev->acp.acp_res[2].start;
adev->acp.acp_cell[0].name = "acp_audio_dma";
adev->acp.acp_cell[0].num_resources = 3;
adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
adev->acp.acp_cell[0].platform_data = &adev->asic_type;
adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);
adev->acp.acp_cell[1].name = "designware-i2s";
adev->acp.acp_cell[1].num_resources = 1;
adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1];
adev->acp.acp_cell[1].platform_data = &i2s_pdata[0];
adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data);
r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell, 2);
if (r)
goto failure;
r = device_for_each_child(adev->acp.parent, &adev->acp.acp_genpd->gpd,
acp_genpd_add_device);
if (r)
goto failure;
break; break;
default:
i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
} }
i2s_pdata[0].cap = DWC_I2S_PLAY;
i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;
i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;
switch (adev->asic_type) {
case CHIP_STONEY:
i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
DW_I2S_QUIRK_COMP_PARAM1 |
DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
break;
default: default:
i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | adev->acp.acp_cell = kcalloc(ACP_DEVS, sizeof(struct mfd_cell),
DW_I2S_QUIRK_COMP_PARAM1; GFP_KERNEL);
}
i2s_pdata[1].cap = DWC_I2S_RECORD; if (!adev->acp.acp_cell) {
i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000; r = -ENOMEM;
i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET; goto failure;
i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET; }
i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL);
switch (adev->asic_type) { if (!adev->acp.acp_res) {
case CHIP_STONEY: r = -ENOMEM;
i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; goto failure;
break; }
default:
break; i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL);
} if (!i2s_pdata) {
r = -ENOMEM;
goto failure;
}
switch (adev->asic_type) {
case CHIP_STONEY:
i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
break;
default:
i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
}
i2s_pdata[0].cap = DWC_I2S_PLAY;
i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;
i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;
switch (adev->asic_type) {
case CHIP_STONEY:
i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
DW_I2S_QUIRK_COMP_PARAM1 |
DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
break;
default:
i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
DW_I2S_QUIRK_COMP_PARAM1;
}
i2s_pdata[1].cap = DWC_I2S_RECORD;
i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000;
i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD; i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000; switch (adev->asic_type) {
i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET; case CHIP_STONEY:
i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET; i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
break;
adev->acp.acp_res[0].name = "acp2x_dma"; default:
adev->acp.acp_res[0].flags = IORESOURCE_MEM; break;
adev->acp.acp_res[0].start = acp_base; }
adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END;
i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;
adev->acp.acp_res[1].name = "acp2x_dw_i2s_play"; i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000;
adev->acp.acp_res[1].flags = IORESOURCE_MEM; i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;
adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START; i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;
adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END;
i2s_pdata[3].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap"; switch (adev->asic_type) {
adev->acp.acp_res[2].flags = IORESOURCE_MEM; case CHIP_STONEY:
adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START; i2s_pdata[3].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END; break;
default:
adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap"; break;
adev->acp.acp_res[3].flags = IORESOURCE_MEM; }
adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START; adev->acp.acp_res[0].name = "acp2x_dma";
adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END; adev->acp.acp_res[0].flags = IORESOURCE_MEM;
adev->acp.acp_res[0].start = acp_base;
adev->acp.acp_res[4].name = "acp2x_dma_irq"; adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END;
adev->acp.acp_res[4].flags = IORESOURCE_IRQ;
adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162); adev->acp.acp_res[1].name = "acp2x_dw_i2s_play";
adev->acp.acp_res[4].end = adev->acp.acp_res[4].start; adev->acp.acp_res[1].flags = IORESOURCE_MEM;
adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START;
adev->acp.acp_cell[0].name = "acp_audio_dma"; adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END;
adev->acp.acp_cell[0].num_resources = 5;
adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0]; adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap";
adev->acp.acp_cell[0].platform_data = &adev->asic_type; adev->acp.acp_res[2].flags = IORESOURCE_MEM;
adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type); adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START;
adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END;
adev->acp.acp_cell[1].name = "designware-i2s";
adev->acp.acp_cell[1].num_resources = 1; adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap";
adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1]; adev->acp.acp_res[3].flags = IORESOURCE_MEM;
adev->acp.acp_cell[1].platform_data = &i2s_pdata[0]; adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START;
adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data); adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END;
adev->acp.acp_cell[2].name = "designware-i2s"; adev->acp.acp_res[4].name = "acp2x_dma_irq";
adev->acp.acp_cell[2].num_resources = 1; adev->acp.acp_res[4].flags = IORESOURCE_IRQ;
adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2]; adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162);
adev->acp.acp_cell[2].platform_data = &i2s_pdata[1]; adev->acp.acp_res[4].end = adev->acp.acp_res[4].start;
adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data);
adev->acp.acp_cell[0].name = "acp_audio_dma";
adev->acp.acp_cell[3].name = "designware-i2s"; adev->acp.acp_cell[0].num_resources = 5;
adev->acp.acp_cell[3].num_resources = 1; adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3]; adev->acp.acp_cell[0].platform_data = &adev->asic_type;
adev->acp.acp_cell[3].platform_data = &i2s_pdata[2]; adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);
adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data);
adev->acp.acp_cell[1].name = "designware-i2s";
r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell, ACP_DEVS); adev->acp.acp_cell[1].num_resources = 1;
if (r) adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1];
goto failure; adev->acp.acp_cell[1].platform_data = &i2s_pdata[0];
adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data);
r = device_for_each_child(adev->acp.parent, &adev->acp.acp_genpd->gpd,
acp_genpd_add_device); adev->acp.acp_cell[2].name = "designware-i2s";
if (r) adev->acp.acp_cell[2].num_resources = 1;
goto failure; adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2];
adev->acp.acp_cell[2].platform_data = &i2s_pdata[1];
adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data);
adev->acp.acp_cell[3].name = "designware-i2s";
adev->acp.acp_cell[3].num_resources = 1;
adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3];
adev->acp.acp_cell[3].platform_data = &i2s_pdata[2];
adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data);
r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell, ACP_DEVS);
if (r)
goto failure;
r = device_for_each_child(adev->acp.parent, &adev->acp.acp_genpd->gpd,
acp_genpd_add_device);
if (r)
goto failure;
}
/* Assert Soft reset of ACP */ /* Assert Soft reset of ACP */
val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
......
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