Skip to content

L
linux
Commit 4dbacf2c authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files
Options

Merge tag 'imx-dt-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt 

Pull "i.MX device tree changes for 4.9" from Shawn Guo:

 - Add SoC support for i.MX7 Solo which is a reduced version of i.MX7
   Dual.
 - New board support: Gateworks Ventana i.MX6Q/DL GW553x, Inverse Path
   i.MX53 USB armory, i.MX6Q/DL TS-4900 from Technologic Systems,
   i.MX6UL GEA M6UL modules from Engicam, i.MX7 Solo Warp7 board.
 - Add DMA and IPU CSI devices for i.MX53 SoC support.
 - Refine i.MX7 Dual SoC DTS as a preparation of i.MX7 Solo support.
 - Use of_graph dt nodes to describe the panel for vf610-colibri and
   ls1021a-twr boards.
 - Add gpio-ranges property to i.MX6 GPIO controllers, which will be
   useful when GPIO driver is changed to request pad configuration as
   GPIO function.
 - Random device additions or small changes for various board support.

* tag 'imx-dt-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (41 commits)
  ARM: dts: add gpio-ranges property to iMX GPIO controllers
  ARM: dts: imx35: add iim module to imx35.dtsi
  ARM: dts: vf610-colibri: use of_graph dt nodes to describe the panel
  ARM: dts: ls1021a: Add of_graph dt nodes to describe the panel
  ARM: dts: imx53: add support for USB armory board
  devicetree: Add vendor prefix for Inverse Path
  ARM: dts: imx7s-warp: Add Bluetooth support
  ARM: dts: imx7s-warp: Add User Button support
  ARM: dts: imx7s-warp: Enable I2C2 device support
  ARM: dts: imx6ul-geam: Add Engicam IMX6UL GEA M6UL initial support
  ARM: dts: imx6ul iomuxc syscon is compatible to imx6q
  ARM: dts: imx7-colibri: add Audio support
  ARM: dts: imx7-colibri: add basic supply regulators
  ARM: dts: imx7-colibri: move SD-card to module level
  ARM: dts: imx6sx: Add GPU bindings
  ARM: dts: imx7s-warp: Let the codec control MCLK pinctrl
  ARM: dts: imx6ul-pico-hobbit: Use WDOG_B pin reset
  ARM: dts: imx6q-bx50v3: configure unused pca953x pins
  ARM: dts: imx6sx: document SION necessity of ENET1_REF_CLK1
  ARM: dts: imx7s-warp: Use WDOG_B pin reset
  ...
parents 971b4c6e bb728d66
Show whitespace changes
Inline Side-by-side
Showing with 3365 additions and 506 deletions
Documentation/devicetree/bindings/arm/technologic.txt
View file @ 4dbacf2c
...@@ -4,3 +4,9 @@ Technologic Systems Platforms Device Tree Bindings ...@@ -4,3 +4,9 @@ Technologic Systems Platforms Device Tree Bindings
TS-4800 board TS-4800 board
Required root node properties: Required root node properties:
- compatible = "technologic,imx51-ts4800", "fsl,imx51"; - compatible = "technologic,imx51-ts4800", "fsl,imx51";
TS-4900 is a System-on-Module based on the Freescale i.MX6 System-on-Chip.
It can be mounted on a carrier board providing additional peripheral connectors.
Required root node properties:
- compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl"
- compatible = "technologic,imx6q-ts4900", "fsl,imx6q"
Documentation/devicetree/bindings/vendor-prefixes.txt
View file @ 4dbacf2c
...@@ -136,6 +136,7 @@ innolux Innolux Corporation ...@@ -136,6 +136,7 @@ innolux Innolux Corporation
intel Intel Corporation intel Intel Corporation
intercontrol Inter Control Group intercontrol Inter Control Group
invensense InvenSense Inc. invensense InvenSense Inc.
inversepath Inverse Path
isee ISEE 2007 S.L. isee ISEE 2007 S.L.
isil Intersil isil Intersil
issi Integrated Silicon Solutions Inc. issi Integrated Silicon Solutions Inc.
......
arch/arm/boot/dts/Makefile
View file @ 4dbacf2c
...@@ -315,6 +315,7 @@ dtb-$(CONFIG_SOC_IMX53) += \ ...@@ -315,6 +315,7 @@ dtb-$(CONFIG_SOC_IMX53) += \
imx53-smd.dtb \ imx53-smd.dtb \
imx53-tx53-x03x.dtb \ imx53-tx53-x03x.dtb \
imx53-tx53-x13x.dtb \ imx53-tx53-x13x.dtb \
imx53-usbarmory.dtb \
imx53-voipac-bsb.dtb imx53-voipac-bsb.dtb
dtb-$(CONFIG_SOC_IMX6Q) += \ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-apf6dev.dtb \ imx6dl-apf6dev.dtb \
...@@ -330,6 +331,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ ...@@ -330,6 +331,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-gw54xx.dtb \ imx6dl-gw54xx.dtb \
imx6dl-gw551x.dtb \ imx6dl-gw551x.dtb \
imx6dl-gw552x.dtb \ imx6dl-gw552x.dtb \
imx6dl-gw553x.dtb \
imx6dl-hummingboard.dtb \ imx6dl-hummingboard.dtb \
imx6dl-nit6xlite.dtb \ imx6dl-nit6xlite.dtb \
imx6dl-nitrogen6x.dtb \ imx6dl-nitrogen6x.dtb \
...@@ -339,6 +341,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ ...@@ -339,6 +341,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-sabreauto.dtb \ imx6dl-sabreauto.dtb \
imx6dl-sabrelite.dtb \ imx6dl-sabrelite.dtb \
imx6dl-sabresd.dtb \ imx6dl-sabresd.dtb \
imx6dl-ts4900.dtb \
imx6dl-tx6dl-comtft.dtb \ imx6dl-tx6dl-comtft.dtb \
imx6dl-tx6s-8034.dtb \ imx6dl-tx6s-8034.dtb \
imx6dl-tx6s-8035.dtb \ imx6dl-tx6s-8035.dtb \
...@@ -368,6 +371,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ ...@@ -368,6 +371,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-gw54xx.dtb \ imx6q-gw54xx.dtb \
imx6q-gw551x.dtb \ imx6q-gw551x.dtb \
imx6q-gw552x.dtb \ imx6q-gw552x.dtb \
imx6q-gw553x.dtb \
imx6q-h100.dtb \ imx6q-h100.dtb \
imx6q-hummingboard.dtb \ imx6q-hummingboard.dtb \
imx6q-icore-rqs.dtb \ imx6q-icore-rqs.dtb \
...@@ -382,6 +386,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ ...@@ -382,6 +386,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-sabresd.dtb \ imx6q-sabresd.dtb \
imx6q-sbc6x.dtb \ imx6q-sbc6x.dtb \
imx6q-tbs2910.dtb \ imx6q-tbs2910.dtb \
imx6q-ts4900.dtb \
imx6q-tx6q-1010.dtb \ imx6q-tx6q-1010.dtb \
imx6q-tx6q-1010-comtft.dtb \ imx6q-tx6q-1010-comtft.dtb \
imx6q-tx6q-1020.dtb \ imx6q-tx6q-1020.dtb \
...@@ -407,6 +412,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \ ...@@ -407,6 +412,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
imx6sx-sdb.dtb imx6sx-sdb.dtb
dtb-$(CONFIG_SOC_IMX6UL) += \ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-14x14-evk.dtb \ imx6ul-14x14-evk.dtb \
imx6ul-geam-kit.dtb \
imx6ul-pico-hobbit.dtb \ imx6ul-pico-hobbit.dtb \
imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-0011.dtb \
...@@ -417,7 +423,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ ...@@ -417,7 +423,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-nitrogen7.dtb \ imx7d-nitrogen7.dtb \
imx7d-sbc-imx7.dtb \ imx7d-sbc-imx7.dtb \
imx7d-sdb.dtb \ imx7d-sdb.dtb \
imx7s-colibri-eval-v3.dtb imx7s-colibri-eval-v3.dtb \
imx7s-warp.dtb
dtb-$(CONFIG_SOC_LS1021A) += \ dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-qds.dtb \ ls1021a-qds.dtb \
ls1021a-twr.dtb ls1021a-twr.dtb
......
arch/arm/boot/dts/imx35.dtsi
View file @ 4dbacf2c
...@@ -309,6 +309,13 @@ can2: can@53fe8000 { ...@@ -309,6 +309,13 @@ can2: can@53fe8000 {
status = "disabled"; status = "disabled";
}; };
iim@53ff0000 {
compatible = "fsl,imx35-iim";
reg = <0x53ff0000 0x4000>;
interrupts = <19>;
clocks = <&clks 80>;
};
usbotg: usb@53ff4000 { usbotg: usb@53ff4000 {
compatible = "fsl,imx35-usb", "fsl,imx27-usb"; compatible = "fsl,imx35-usb", "fsl,imx27-usb";
reg = <0x53ff4000 0x0200>; reg = <0x53ff4000 0x0200>;
......
arch/arm/boot/dts/imx50.dtsi
View file @ 4dbacf2c
...@@ -227,6 +227,7 @@ gpio1: gpio@53f84000 { ...@@ -227,6 +227,7 @@ gpio1: gpio@53f84000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 151 28>;
}; };
gpio2: gpio@53f88000 { gpio2: gpio@53f88000 {
...@@ -237,6 +238,10 @@ gpio2: gpio@53f88000 { ...@@ -237,6 +238,10 @@ gpio2: gpio@53f88000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 75 8>, <&iomuxc 8 100 8>,
<&iomuxc 16 83 1>, <&iomuxc 17 85 1>,
<&iomuxc 18 87 1>, <&iomuxc 19 84 1>,
<&iomuxc 20 88 1>, <&iomuxc 21 86 1>;
}; };
gpio3: gpio@53f8c000 { gpio3: gpio@53f8c000 {
...@@ -247,6 +252,7 @@ gpio3: gpio@53f8c000 { ...@@ -247,6 +252,7 @@ gpio3: gpio@53f8c000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 108 32>;
}; };
gpio4: gpio@53f90000 { gpio4: gpio@53f90000 {
...@@ -257,6 +263,8 @@ gpio4: gpio@53f90000 { ...@@ -257,6 +263,8 @@ gpio4: gpio@53f90000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 8 8>, <&iomuxc 8 45 12>,
<&iomuxc 20 140 11>;
}; };
wdog1: wdog@53f98000 { wdog1: wdog@53f98000 {
...@@ -346,6 +354,7 @@ gpio5: gpio@53fdc000 { ...@@ -346,6 +354,7 @@ gpio5: gpio@53fdc000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>;
}; };
gpio6: gpio@53fe0000 { gpio6: gpio@53fe0000 {
...@@ -356,6 +365,7 @@ gpio6: gpio@53fe0000 { ...@@ -356,6 +365,7 @@ gpio6: gpio@53fe0000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>;
}; };
i2c3: i2c@53fec000 { i2c3: i2c@53fec000 {
......
arch/arm/boot/dts/imx53-usbarmory.dts 0 → 100644
View file @ 4dbacf2c
/*
* USB armory MkI device tree file
* https://inversepath.com/usbarmory
*
* Copyright (C) 2015, Inverse Path
* Andrej Rosano <andrej@inversepath.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx53.dtsi"
/ {
model = "Inverse Path USB armory";
compatible = "inversepath,imx53-usbarmory", "fsl,imx53";
};
/ {
chosen {
stdout-path = &uart1;
};
memory {
reg = <0x70000000 0x20000000>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
user {
label = "LED";
gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
};
};
/*
* Not every i.MX53 P/N supports clock > 800MHz.
* As USB armory does not mount a specific P/N set a safe clock upper limit.
*/
&cpu0 {
operating-points = <
/* kHz */
166666 850000
400000 900000
800000 1050000
>;
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
status = "okay";
};
&iomuxc {
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
>;
};
pinctrl_i2c1_pmic: i2c1grp {
fsl,pins = <
MX53_PAD_EIM_D21__I2C1_SCL 0x80
MX53_PAD_EIM_D28__I2C1_SDA 0x80
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
MX53_PAD_DISP0_DAT6__GPIO4_27 0x1e4
>;
};
/*
* UART mode pin header configration
* 3 - GPIO5[26], pull-down 100K
* 4 - GPIO5[27], pull-down 100K
* 5 - TX, pull-up 100K
* 6 - RX, pull-up 100K
* 7 - GPIO5[30], pull-down 100K
*/
pinctrl_uart1: uart1grp {
fsl,pins = <
MX53_PAD_CSI0_DAT8__GPIO5_26 0xc0
MX53_PAD_CSI0_DAT9__GPIO5_27 0xc0
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
MX53_PAD_CSI0_DAT12__GPIO5_30 0xc0
>;
};
};
&i2c1 {
pinctrl-0 = <&pinctrl_i2c1_pmic>;
status = "okay";
ltc3589: pmic@34 {
compatible = "lltc,ltc3589-2";
reg = <0x34>;
regulators {
sw1_reg: sw1 {
regulator-min-microvolt = <591930>;
regulator-max-microvolt = <1224671>;
lltc,fb-voltage-divider = <100000 158000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
sw2_reg: sw2 {
regulator-min-microvolt = <704123>;
regulator-max-microvolt = <1456803>;
lltc,fb-voltage-divider = <180000 191000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
sw3_reg: sw3 {
regulator-min-microvolt = <1341250>;
regulator-max-microvolt = <2775000>;
lltc,fb-voltage-divider = <270000 100000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
bb_out_reg: bb-out {
regulator-min-microvolt = <3387341>;
regulator-max-microvolt = <3387341>;
lltc,fb-voltage-divider = <511000 158000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: ldo1 {
regulator-min-microvolt = <1306329>;
regulator-max-microvolt = <1306329>;
lltc,fb-voltage-divider = <100000 158000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: ldo2 {
regulator-min-microvolt = <704123>;
regulator-max-microvolt = <1456806>;
lltc,fb-voltage-divider = <180000 191000>;
regulator-ramp-delay = <7000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: ldo3 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-boot-on;
};
ldo4_reg: ldo4 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3200000>;
};
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usbotg {
dr_mode = "peripheral";
status = "okay";
};
arch/arm/boot/dts/imx53.dtsi
View file @ 4dbacf2c
...@@ -136,6 +136,14 @@ ipu: ipu@18000000 { ...@@ -136,6 +136,14 @@ ipu: ipu@18000000 {
clock-names = "bus", "di0", "di1"; clock-names = "bus", "di0", "di1";
resets = <&src 2>; resets = <&src 2>;
ipu_csi0: port@0 {
reg = <0>;
};
ipu_csi1: port@1 {
reg = <1>;
};
ipu_di0: port@2 { ipu_di0: port@2 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -217,6 +225,8 @@ uart3: serial@5000c000 { ...@@ -217,6 +225,8 @@ uart3: serial@5000c000 {
clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
<&clks IMX5_CLK_UART3_PER_GATE>; <&clks IMX5_CLK_UART3_PER_GATE>;
clock-names = "ipg", "per"; clock-names = "ipg", "per";
dmas = <&sdma 42 4 0>, <&sdma 43 4 0>;
dma-names = "rx", "tx";
status = "disabled"; status = "disabled";
}; };
...@@ -498,6 +508,8 @@ uart1: serial@53fbc000 { ...@@ -498,6 +508,8 @@ uart1: serial@53fbc000 {
clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
<&clks IMX5_CLK_UART1_PER_GATE>; <&clks IMX5_CLK_UART1_PER_GATE>;
clock-names = "ipg", "per"; clock-names = "ipg", "per";
dmas = <&sdma 18 4 0>, <&sdma 19 4 0>;
dma-names = "rx", "tx";
status = "disabled"; status = "disabled";
}; };
...@@ -508,6 +520,8 @@ uart2: serial@53fc0000 { ...@@ -508,6 +520,8 @@ uart2: serial@53fc0000 {
clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
<&clks IMX5_CLK_UART2_PER_GATE>; <&clks IMX5_CLK_UART2_PER_GATE>;
clock-names = "ipg", "per"; clock-names = "ipg", "per";
dmas = <&sdma 12 4 0>, <&sdma 13 4 0>;
dma-names = "rx", "tx";
status = "disabled"; status = "disabled";
}; };
...@@ -591,6 +605,8 @@ uart4: serial@53ff0000 { ...@@ -591,6 +605,8 @@ uart4: serial@53ff0000 {
clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
<&clks IMX5_CLK_UART4_PER_GATE>; <&clks IMX5_CLK_UART4_PER_GATE>;
clock-names = "ipg", "per"; clock-names = "ipg", "per";
dmas = <&sdma 2 4 0>, <&sdma 3 4 0>;
dma-names = "rx", "tx";
status = "disabled"; status = "disabled";
}; };
}; };
...@@ -621,6 +637,8 @@ uart5: serial@63f90000 { ...@@ -621,6 +637,8 @@ uart5: serial@63f90000 {
clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
<&clks IMX5_CLK_UART5_PER_GATE>; <&clks IMX5_CLK_UART5_PER_GATE>;
clock-names = "ipg", "per"; clock-names = "ipg", "per";
dmas = <&sdma 16 4 0>, <&sdma 17 4 0>;
dma-names = "rx", "tx";
status = "disabled"; status = "disabled";
}; };
......
arch/arm/boot/dts/imx6dl-gw553x.dts 0 → 100644
View file @ 4dbacf2c
/*
* Copyright 2016 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-gw553x.dtsi"
/ {
model = "Gateworks Ventana i.MX6 DualLite/Solo GW553X";
compatible = "gw,imx6dl-gw553x", "gw,ventana", "fsl,imx6dl";
};
arch/arm/boot/dts/imx6dl-riotboard.dts
View file @ 4dbacf2c
...@@ -376,18 +376,18 @@ pinctrl_enet: enetgrp { ...@@ -376,18 +376,18 @@ pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 /* AR8035 pin strapping: IO voltage: pull up */ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 /* AR8035 pin strapping: IO voltage: pull up */
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 /* AR8035 pin strapping: PHYADDR#0: pull down */ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 /* AR8035 pin strapping: PHYADDR#0: pull down */
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 /* AR8035 pin strapping: PHYADDR#1: pull down */ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 /* AR8035 pin strapping: PHYADDR#1: pull down */
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 /* AR8035 pin strapping: MODE#1: pull up */ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#1: pull up */
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 /* AR8035 pin strapping: MODE#3: pull up */ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */
......
arch/arm/boot/dts/imx6dl-ts4900.dts 0 → 100644
View file @ 4dbacf2c
/*
* Copyright 2015 Technologic Systems
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6dl.dtsi"
#include "imx6qdl-ts4900.dtsi"
/ {
model = "Technologic Systems i.MX6 Solo/DualLite TS-4900 (Default Device Tree)";
compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl";
};
arch/arm/boot/dts/imx6dl.dtsi
View file @ 4dbacf2c
...@@ -111,6 +111,59 @@ gpu-subsystem { ...@@ -111,6 +111,59 @@ gpu-subsystem {
}; };
}; };
&gpio1 {
gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>,
<&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
<&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
<&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
<&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
<&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
<&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
};
&gpio2 {
gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>,
<&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>,
<&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>,
<&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
<&iomuxc 28 113 4>;
};
&gpio3 {
gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
<&iomuxc 16 81 16>;
};
&gpio4 {
gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>,
<&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>,
<&iomuxc 11 151 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
<&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>,
<&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>;
};
&gpio5 {
gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>,
<&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
<&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
<&iomuxc 22 29 6>, <&iomuxc 28 19 4>;
};
&gpio6 {
gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>,
<&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>,
<&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
<&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
<&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
<&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>;
};
&gpio7 {
gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>,
<&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>,
<&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
};
&gpt { &gpt {
compatible = "fsl,imx6dl-gpt"; compatible = "fsl,imx6dl-gpt";
}; };
......
arch/arm/boot/dts/imx6q-arm2.dts
View file @ 4dbacf2c
...@@ -79,19 +79,19 @@ pinctrl_enet: enetgrp { ...@@ -79,19 +79,19 @@ pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>; >;
}; };
......
arch/arm/boot/dts/imx6q-b450v3.dts
View file @ 4dbacf2c
...@@ -89,3 +89,19 @@ lvds0_out: endpoint { ...@@ -89,3 +89,19 @@ lvds0_out: endpoint {
}; };
}; };
}; };
&pca9539 {
P04 {
gpio-hog;
gpios = <4 0>;
output-low;
line-name = "PCA9539-P04";
};
P05 {
gpio-hog;
gpios = <5 0>;
output-low;
line-name = "PCA9539-P05";
};
};
arch/arm/boot/dts/imx6q-b650v3.dts
View file @ 4dbacf2c
...@@ -89,3 +89,12 @@ lvds0_out: endpoint { ...@@ -89,3 +89,12 @@ lvds0_out: endpoint {
}; };
}; };
}; };
&pca9539 {
P05 {
gpio-hog;
gpios = <5 0>;
output-low;
line-name = "PCA9539-P05";
};
};
arch/arm/boot/dts/imx6q-ba16.dtsi
View file @ 4dbacf2c
...@@ -448,19 +448,19 @@ pinctrl_enet: enetgrp { ...@@ -448,19 +448,19 @@ pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
/* FEC Reset */ /* FEC Reset */
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
/* AR8033 Interrupt */ /* AR8033 Interrupt */
......
arch/arm/boot/dts/imx6q-bx50v3.dtsi
View file @ 4dbacf2c
...@@ -183,6 +183,76 @@ pca9539: pca9539@74 { ...@@ -183,6 +183,76 @@ pca9539: pca9539@74 {
interrupt-controller; interrupt-controller;
interrupt-parent = <&gpio2>; interrupt-parent = <&gpio2>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
P06 {
gpio-hog;
gpios = <6 0>;
output-low;
line-name = "PCA9539-P06";
};
P07 {
gpio-hog;
gpios = <7 0>;
output-low;
line-name = "PCA9539-P07";
};
P10 {
gpio-hog;
gpios = <8 0>;
output-low;
line-name = "PCA9539-P10";
};
P11 {
gpio-hog;
gpios = <9 0>;
output-low;
line-name = "PCA9539-P11";
};
P12 {
gpio-hog;
gpios = <10 0>;
output-low;
line-name = "PCA9539-P12";
};
P13 {
gpio-hog;
gpios = <11 0>;
output-low;
line-name = "PCA9539-P13";
};
P14 {
gpio-hog;
gpios = <12 0>;
output-low;
line-name = "PCA9539-P14";
};
P15 {
gpio-hog;
gpios = <13 0>;
output-low;
line-name = "PCA9539-P15";
};
P16 {
gpio-hog;
gpios = <14 0>;
output-low;
line-name = "PCA9539-P16";
};
P17 {
gpio-hog;
gpios = <15 0>;
output-low;
line-name = "PCA9539-P17";
};
}; };
}; };
......
arch/arm/boot/dts/imx6q-cm-fx6.dts
View file @ 4dbacf2c
...@@ -168,18 +168,18 @@ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 ...@@ -168,18 +168,18 @@ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1
pinctrl_enet: enetgrp { pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
......
arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
View file @ 4dbacf2c
...@@ -324,18 +324,18 @@ MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x80000000 ...@@ -324,18 +324,18 @@ MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x80000000
pinctrl_enet: enetgrp { pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
......
arch/arm/boot/dts/imx6q-evi.dts
View file @ 4dbacf2c
...@@ -139,6 +139,9 @@ &fec { ...@@ -139,6 +139,9 @@ &fec {
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii"; phy-mode = "rgmii";
phy-reset-gpios = <&gpio1 25 0>; phy-reset-gpios = <&gpio1 25 0>;
interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
<&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
fsl,err006687-workaround-present;
status = "okay"; status = "okay";
}; };
...@@ -303,21 +306,22 @@ pinctrl_enet: enetgrp { ...@@ -303,21 +306,22 @@ pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x4001b0a8 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x4001b0a8
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>; >;
}; };
......
arch/arm/boot/dts/imx6q-gw5400-a.dts
View file @ 4dbacf2c
...@@ -421,18 +421,18 @@ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */ ...@@ -421,18 +421,18 @@ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */
pinctrl_enet: enetgrp { pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
......
arch/arm/boot/dts/imx6q-gw553x.dts 0 → 100644
View file @ 4dbacf2c
/*
* Copyright 2016 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-gw553x.dtsi"
/ {
model = "Gateworks Ventana i.MX6 Dual/Quad GW553X";
compatible = "gw,imx6q-gw553x", "gw,ventana", "fsl,imx6q";
};
arch/arm/boot/dts/imx6q-marsboard.dts
View file @ 4dbacf2c
...@@ -252,26 +252,26 @@ pinctrl_enet: enetgrp { ...@@ -252,26 +252,26 @@ pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1
/* AR8035 pin strapping: IO voltage: pull up */ /* AR8035 pin strapping: IO voltage: pull up */
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
/* AR8035 pin strapping: PHYADDR#0: pull down */ /* AR8035 pin strapping: PHYADDR#0: pull down */
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030
/* AR8035 pin strapping: PHYADDR#1: pull down */ /* AR8035 pin strapping: PHYADDR#1: pull down */
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030
/* AR8035 pin strapping: MODE#1: pull up */ /* AR8035 pin strapping: MODE#1: pull up */
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
/* AR8035 pin strapping: MODE#3: pull up */ /* AR8035 pin strapping: MODE#3: pull up */
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
/* AR8035 pin strapping: MODE#0: pull down */ /* AR8035 pin strapping: MODE#0: pull down */
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030
/* GPIO16 -> AR8035 25MHz */ /* GPIO16 -> AR8035 25MHz */
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
/* RGMII_nRST */ /* RGMII_nRST */
......
arch/arm/boot/dts/imx6q-novena.dts
View file @ 4dbacf2c
...@@ -549,12 +549,12 @@ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b028 ...@@ -549,12 +549,12 @@ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b028
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b028 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b028
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b028 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b028
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
/* Ethernet reset */ /* Ethernet reset */
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b1 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b1
......
arch/arm/boot/dts/imx6q-sbc6x.dts
View file @ 4dbacf2c
...@@ -31,19 +31,19 @@ pinctrl_enet: enetgrp { ...@@ -31,19 +31,19 @@ pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>; >;
}; };
......
arch/arm/boot/dts/imx6q-tbs2910.dts
View file @ 4dbacf2c
...@@ -284,19 +284,19 @@ pinctrl_enet: enetgrp { ...@@ -284,19 +284,19 @@ pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059
>; >;
......
arch/arm/boot/dts/imx6q-ts4900.dts 0 → 100644
View file @ 4dbacf2c
/*
* Copyright 2015 Technologic Systems
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "imx6q.dtsi"
#include "imx6qdl-ts4900.dtsi"
/ {
model = "Technologic Systems i.MX6 Quad TS-4900 (Default Device Tree)";
compatible = "technologic,imx6q-ts4900", "fsl,imx6q";
};
&sata {
status = "okay";
};
arch/arm/boot/dts/imx6q.dtsi
View file @ 4dbacf2c
...@@ -209,6 +209,43 @@ gpu-subsystem { ...@@ -209,6 +209,43 @@ gpu-subsystem {
}; };
}; };
&gpio1 {
gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
<&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>,
<&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>,
<&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>,
<&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
<&iomuxc 22 116 10>;
};
&gpio2 {
gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
<&iomuxc 31 44 1>;
};
&gpio3 {
gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
};
&gpio4 {
gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
};
&gpio5 {
gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
<&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
};
&gpio6 {
gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
<&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>,
<&iomuxc 31 86 1>;
};
&gpio7 {
gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
};
&hdmi { &hdmi {
compatible = "fsl,imx6q-hdmi"; compatible = "fsl,imx6q-hdmi";
......
arch/arm/boot/dts/imx6qdl-apalis.dtsi
View file @ 4dbacf2c
...@@ -586,19 +586,19 @@ pinctrl_enet: enetgrp { ...@@ -586,19 +586,19 @@ pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
/* Ethernet PHY reset */ /* Ethernet PHY reset */
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
/* Ethernet PHY interrupt */ /* Ethernet PHY interrupt */
......
arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
View file @ 4dbacf2c
...@@ -67,18 +67,18 @@ MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000030b0 /* Backlight enable */ ...@@ -67,18 +67,18 @@ MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000030b0 /* Backlight enable */
pinctrl_enet: enetgrp { pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
......
arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
View file @ 4dbacf2c
...@@ -228,22 +228,28 @@ &usbh1 { ...@@ -228,22 +228,28 @@ &usbh1 {
status = "okay"; status = "okay";
}; };
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc { &iomuxc {
imx6qdl-gw51xx { imx6qdl-gw51xx {
pinctrl_enet: enetgrp { pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
...@@ -364,5 +370,11 @@ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 ...@@ -364,5 +370,11 @@ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
>; >;
}; };
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
>;
};
}; };
}; };
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
View file @ 4dbacf2c
...@@ -315,6 +315,8 @@ &ssi1 { ...@@ -315,6 +315,8 @@ &ssi1 {
&uart1 { &uart1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>; pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
status = "okay"; status = "okay";
}; };
...@@ -353,6 +355,12 @@ &usdhc3 { ...@@ -353,6 +355,12 @@ &usdhc3 {
status = "okay"; status = "okay";
}; };
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc { &iomuxc {
imx6qdl-gw52xx { imx6qdl-gw52xx {
pinctrl_audmux: audmuxgrp { pinctrl_audmux: audmuxgrp {
...@@ -376,18 +384,18 @@ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 ...@@ -376,18 +384,18 @@ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
pinctrl_enet: enetgrp { pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
...@@ -487,6 +495,7 @@ pinctrl_uart1: uart1grp { ...@@ -487,6 +495,7 @@ pinctrl_uart1: uart1grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
>; >;
}; };
...@@ -549,5 +558,11 @@ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ ...@@ -549,5 +558,11 @@ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
>; >;
}; };
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
>;
};
}; };
}; };
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
View file @ 4dbacf2c
...@@ -312,6 +312,8 @@ &ssi1 { ...@@ -312,6 +312,8 @@ &ssi1 {
&uart1 { &uart1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>; pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
status = "okay"; status = "okay";
}; };
...@@ -351,6 +353,12 @@ &usdhc3 { ...@@ -351,6 +353,12 @@ &usdhc3 {
status = "okay"; status = "okay";
}; };
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc { &iomuxc {
imx6qdl-gw53xx { imx6qdl-gw53xx {
pinctrl_audmux: audmuxgrp { pinctrl_audmux: audmuxgrp {
...@@ -365,18 +373,18 @@ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ ...@@ -365,18 +373,18 @@ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
pinctrl_enet: enetgrp { pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
...@@ -476,6 +484,7 @@ pinctrl_uart1: uart1grp { ...@@ -476,6 +484,7 @@ pinctrl_uart1: uart1grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
>; >;
}; };
...@@ -539,5 +548,11 @@ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ ...@@ -539,5 +548,11 @@ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
>; >;
}; };
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
>;
};
}; };
}; };
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
View file @ 4dbacf2c
...@@ -414,6 +414,8 @@ &ssi2 { ...@@ -414,6 +414,8 @@ &ssi2 {
&uart1 { &uart1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>; pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
status = "okay"; status = "okay";
}; };
...@@ -453,6 +455,17 @@ &usdhc3 { ...@@ -453,6 +455,17 @@ &usdhc3 {
status = "okay"; status = "okay";
}; };
&wdog1 {
status = "disabled";
};
&wdog2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc { &iomuxc {
imx6qdl-gw54xx { imx6qdl-gw54xx {
pinctrl_audmux: audmuxgrp { pinctrl_audmux: audmuxgrp {
...@@ -467,18 +480,18 @@ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ ...@@ -467,18 +480,18 @@ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
pinctrl_enet: enetgrp { pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
...@@ -592,6 +605,7 @@ pinctrl_uart1: uart1grp { ...@@ -592,6 +605,7 @@ pinctrl_uart1: uart1grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
>; >;
}; };
...@@ -654,5 +668,11 @@ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ ...@@ -654,5 +668,11 @@ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
>; >;
}; };
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
>;
};
}; };
}; };
arch/arm/boot/dts/imx6qdl-gw551x.dtsi
View file @ 4dbacf2c
...@@ -239,6 +239,12 @@ &usbh1 { ...@@ -239,6 +239,12 @@ &usbh1 {
status = "okay"; status = "okay";
}; };
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc { &iomuxc {
imx6qdl-gw51xx { imx6qdl-gw51xx {
pinctrl_flexcan1: flexcan1grp { pinctrl_flexcan1: flexcan1grp {
...@@ -333,5 +339,11 @@ pinctrl_usbotg: usbotggrp { ...@@ -333,5 +339,11 @@ pinctrl_usbotg: usbotggrp {
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
>; >;
}; };
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
>;
};
}; };
}; };
arch/arm/boot/dts/imx6qdl-gw552x.dtsi
View file @ 4dbacf2c
...@@ -197,6 +197,12 @@ &usbh1 { ...@@ -197,6 +197,12 @@ &usbh1 {
status = "okay"; status = "okay";
}; };
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc { &iomuxc {
imx6qdl-gw552x { imx6qdl-gw552x {
pinctrl_gpio_leds: gpioledsgrp { pinctrl_gpio_leds: gpioledsgrp {
...@@ -286,5 +292,11 @@ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 ...@@ -286,5 +292,11 @@ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>; >;
}; };
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
>;
};
}; };
}; };
arch/arm/boot/dts/imx6qdl-gw553x.dtsi 0 → 100644
View file @ 4dbacf2c
/*
* Copyright 2016 Gateworks Corporation
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
/ {
/* these are used by bootloader for disabling nodes */
aliases {
led0 = &led0;
led1 = &led1;
nand = &gpmi;
usb0 = &usbh1;
usb1 = &usbotg;
};
chosen {
stdout-path = &uart2;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led0: user1 {
label = "user1";
gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
default-state = "on";
linux,default-trigger = "heartbeat";
};
led1: user2 {
label = "user2";
gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
default-state = "off";
};
};
memory {
reg = <0x10000000 0x20000000>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
status = "okay";
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P0V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_5p0v: regulator-5p0v {
compatible = "regulator-fixed";
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&hdmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gpio: pca9555@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
};
eeprom1: eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom2: eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom3: eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom4: eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
rtc: ds1672@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
status = "disabled";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
status = "disabled";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
status = "disabled";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbh1 {
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc {
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
>;
};
pinctrl_hdmi: hdmigrp {
fsl,pins = <
MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
>;
};
};
arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
View file @ 4dbacf2c
...@@ -254,19 +254,19 @@ pinctrl_enet: enetgrp { ...@@ -254,19 +254,19 @@ pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
>; >;
}; };
......
arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
View file @ 4dbacf2c
...@@ -361,12 +361,12 @@ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 ...@@ -361,12 +361,12 @@ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
/* Phy reset */ /* Phy reset */
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
......
arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
View file @ 4dbacf2c
...@@ -484,19 +484,19 @@ pinctrl_enet: enetgrp { ...@@ -484,19 +484,19 @@ pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
/* Phy reset */ /* Phy reset */
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
......
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
View file @ 4dbacf2c
...@@ -394,19 +394,19 @@ pinctrl_enet: enetgrp { ...@@ -394,19 +394,19 @@ pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
/* Phy reset */ /* Phy reset */
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
......
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
View file @ 4dbacf2c
...@@ -231,19 +231,19 @@ pinctrl_enet: enetgrp { ...@@ -231,19 +231,19 @@ pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
>; >;
}; };
...@@ -379,6 +379,18 @@ &pcie { ...@@ -379,6 +379,18 @@ &pcie {
status = "disabled"; status = "disabled";
}; };
&reg_arm {
vin-supply = <&vddcore_reg>;
};
&reg_pu {
vin-supply = <&vddsoc_reg>;
};
&reg_soc {
vin-supply = <&vddsoc_reg>;
};
&uart3 { &uart3 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>; pinctrl-0 = <&pinctrl_uart3>;
......
arch/arm/boot/dts/imx6qdl-rex.dtsi
View file @ 4dbacf2c
...@@ -196,19 +196,19 @@ pinctrl_enet: enetgrp { ...@@ -196,19 +196,19 @@ pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
/* Phy reset */ /* Phy reset */
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
......
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
View file @ 4dbacf2c
...@@ -345,19 +345,19 @@ pinctrl_enet: enetgrp { ...@@ -345,19 +345,19 @@ pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>; >;
}; };
......
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
View file @ 4dbacf2c
...@@ -359,19 +359,19 @@ pinctrl_enet: enetgrp { ...@@ -359,19 +359,19 @@ pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
/* Phy reset */ /* Phy reset */
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
......
arch/arm/boot/dts/imx6qdl-sabresd.dtsi
View file @ 4dbacf2c
...@@ -380,19 +380,19 @@ pinctrl_enet: enetgrp { ...@@ -380,19 +380,19 @@ pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
>; >;
}; };
......
arch/arm/boot/dts/imx6qdl-ts4900.dtsi 0 → 100644
View file @ 4dbacf2c
/*
* Copyright 2015 Technologic Systems
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
aliases {
ethernet0 = &fec;
};
leds {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds1>;
compatible = "gpio-leds";
green-led {
label = "green-led";
gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
default-state = "on";
};
red-led {
label = "red-led";
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3p3v";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
n25q064: flash@0 {
compatible = "micron,n25q064", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
};
};
&ecspi2 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
status = "okay";
isl12022: rtc@6f {
compatible = "isil,isl12022";
reg = <0x6f>;
};
gpio8: gpio@28 {
compatible = "technologic,ts4900-gpio";
reg = <0x28>;
#gpio-cells = <2>;
gpio-controller;
ngpio = <32>;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard flash CS1# */
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1
MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1
MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1
MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 /* Offboard CS0# */
MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x100b1 /* FPGA CS1# */
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 /* FPGA_RESET# */
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* FPGA_DONE */
MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */
MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 /* FPGA_IRQ */
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001b0a8
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b1 /* ETH_PHY_RESET */
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1
MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b1 /* OFF_BD_RESET# */
MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 /* EN_USB_5V# */
MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b1 /* EN_LCD_3.3V */
MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */
MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 /* DIO_1 */
MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b1 /* DIO_2 */
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b1 /* DIO_3 */
MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b1 /* DIO_4 */
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 /* DIO_5 */
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b1 /* DIO_7 */
MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b1 /* DIO_8 */
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b1 /* DIO_9 */
MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* DIO_0 */
MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b1 /* DIO_6 */
MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b1 /* CPU_DIO_A */
MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b1 /* DIO_2 */
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b1 /* CPU_DIO_B */
MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1 /* BUS_ALE# */
MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1 /* DIO_15 */
MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1 /* BUS_DIR */
MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 /* BUS_CS# */
MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* DIO_14 */
MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b1 /* DIO_16 */
MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b0b1 /* DIO_12 */
MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1 /* DIO_18 */
MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b1 /* DIO_19 */
MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1 /* DIO_20 */
MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b1 /* BUS_BHE# */
MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1 /* DIO_13 */
MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1 /* EIM_WAIT# */
MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b1 /* DIO_10 */
MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1 /* MUX_AD_00 */
MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1 /* MUX_AD_01 */
MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 /* MUX_AD_02 */
MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1 /* MUX_AD_03 */
MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 /* MUX_AD_04 */
MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 /* MUX_AD_05 */
MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1 /* MUX_AD_06 */
MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 /* MUX_AD_07 */
MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1 /* MUX_AD_08 */
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1 /* MUX_AD_09 */
MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1 /* MUX_AD_10 */
MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1 /* MUX_AD_11 */
MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1 /* MUX_AD_12 */
MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1 /* MUX_AD_13 */
MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1 /* MUX_AD_14 */
MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1 /* MUX_AD_15 */
MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1 /* LCD_CLK */
MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b1 /* DE */
MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b1 /* Hsync */
MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b1 /* Vsync */
MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b1
MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x1b0b1
MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x1b0b1
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b1
MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1
MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b1
MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b1
MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b1
MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x1b0b1
MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b1
MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b1
MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b0b1
MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b1
MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1
MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1
MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1
MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1
MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b1
MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1
MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b1
MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1
MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b1
MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
>;
};
pinctrl_leds1: leds1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 /* RED_LED# */
MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 /* GREEN_LED# */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1
MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1
MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x17059 /* WIFI IRQ */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b1 /* EN_SD_POWER# */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
};
&pcie {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
uart-has-rtscts;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay";
};
&usbh1 {
status = "okay";
};
&usbotg {
vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
status = "okay";
};
/* SD */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
vmmc-supply = <&reg_3p3v>;
bus-width = <4>;
fsl,wp-controller;
status = "okay";
};
/* eMMC */
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3>;
vmmc-supply = <&reg_3p3v>;
bus-width = <4>;
non-removable;
status = "okay";
};
arch/arm/boot/dts/imx6qdl-udoo.dtsi
View file @ 4dbacf2c
...@@ -132,18 +132,18 @@ &iomuxc { ...@@ -132,18 +132,18 @@ &iomuxc {
imx6q-udoo { imx6q-udoo {
pinctrl_enet: enetgrp { pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
......
arch/arm/boot/dts/imx6qdl-wandboard.dtsi
View file @ 4dbacf2c
...@@ -109,19 +109,19 @@ pinctrl_enet: enetgrp { ...@@ -109,19 +109,19 @@ pinctrl_enet: enetgrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>; >;
......
arch/arm/boot/dts/imx6sl.dtsi
View file @ 4dbacf2c
...@@ -375,6 +375,12 @@ gpio1: gpio@0209c000 { ...@@ -375,6 +375,12 @@ gpio1: gpio@0209c000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>,
<&iomuxc 3 23 1>, <&iomuxc 4 25 1>,
<&iomuxc 5 24 1>, <&iomuxc 6 19 1>,
<&iomuxc 7 36 2>, <&iomuxc 9 44 8>,
<&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
<&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
}; };
gpio2: gpio@020a0000 { gpio2: gpio@020a0000 {
...@@ -386,6 +392,13 @@ gpio2: gpio@020a0000 { ...@@ -386,6 +392,13 @@ gpio2: gpio@020a0000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>,
<&iomuxc 5 34 2>, <&iomuxc 7 57 4>,
<&iomuxc 11 56 1>, <&iomuxc 12 61 3>,
<&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
<&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
<&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
<&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
}; };
gpio3: gpio@020a4000 { gpio3: gpio@020a4000 {
...@@ -397,6 +410,14 @@ gpio3: gpio@020a4000 { ...@@ -397,6 +410,14 @@ gpio3: gpio@020a4000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>,
<&iomuxc 12 97 4>, <&iomuxc 16 166 3>,
<&iomuxc 19 85 2>, <&iomuxc 21 137 2>,
<&iomuxc 23 136 1>, <&iomuxc 24 91 1>,
<&iomuxc 25 99 1>, <&iomuxc 26 92 1>,
<&iomuxc 27 100 1>, <&iomuxc 28 93 1>,
<&iomuxc 29 101 1>, <&iomuxc 30 94 1>,
<&iomuxc 31 102 1>;
}; };
gpio4: gpio@020a8000 { gpio4: gpio@020a8000 {
...@@ -408,6 +429,21 @@ gpio4: gpio@020a8000 { ...@@ -408,6 +429,21 @@ gpio4: gpio@020a8000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>,
<&iomuxc 2 96 1>, <&iomuxc 3 104 1>,
<&iomuxc 4 97 1>, <&iomuxc 5 105 1>,
<&iomuxc 6 98 1>, <&iomuxc 7 106 1>,
<&iomuxc 8 28 1>, <&iomuxc 9 27 1>,
<&iomuxc 10 26 1>, <&iomuxc 11 29 1>,
<&iomuxc 12 32 1>, <&iomuxc 13 31 1>,
<&iomuxc 14 30 1>, <&iomuxc 15 33 1>,
<&iomuxc 16 84 1>, <&iomuxc 17 79 2>,
<&iomuxc 19 78 1>, <&iomuxc 20 76 1>,
<&iomuxc 21 81 2>, <&iomuxc 23 75 1>,
<&iomuxc 24 83 1>, <&iomuxc 25 74 1>,
<&iomuxc 26 77 1>, <&iomuxc 27 159 1>,
<&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
<&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
}; };
gpio5: gpio@020ac000 { gpio5: gpio@020ac000 {
...@@ -419,6 +455,17 @@ gpio5: gpio@020ac000 { ...@@ -419,6 +455,17 @@ gpio5: gpio@020ac000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>,
<&iomuxc 2 155 1>, <&iomuxc 3 153 1>,
<&iomuxc 4 150 1>, <&iomuxc 5 149 1>,
<&iomuxc 6 144 1>, <&iomuxc 7 147 1>,
<&iomuxc 8 142 1>, <&iomuxc 9 146 1>,
<&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
<&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
<&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
<&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
<&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
<&iomuxc 21 161 1>;
}; };
kpp: kpp@020b8000 { kpp: kpp@020b8000 {
......
arch/arm/boot/dts/imx6sx-pinfunc.h
View file @ 4dbacf2c
...@@ -308,6 +308,20 @@ ...@@ -308,6 +308,20 @@
#define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0 #define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0
#define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0 #define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0
#define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0 #define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0
/*
* SION bit is necessary for ENET1_REF_CLK1 (ENET2_REF_CLK2 untested) if it is
* used as clock output of IMX6SX_CLK_ENET_REF (ENET1_TX_CLK) to e.g. supply a
* PHY in RMII mode. This configuration is valid if:
* - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK is set
* - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK unset
* It seems to be a silicon bug that in this configuration ENET1_TX reference
* clock isn't provided automatically. According to i.MX6SX reference manual
* (IOMUXC_GPR_GPR1 field descriptions: ENET1_CLK_SEL, Rev. 0 from 2/2015) it
* should be the case.
* So this might have unwanted side effects for other hardware units that are
* also connected to that pin and using respective function as input (e.g.
* UART1's DTR handling on MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B).
*/
#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1 #define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1
#define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1 #define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1
#define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0 #define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0
......
arch/arm/boot/dts/imx6sx.dtsi
View file @ 4dbacf2c
...@@ -159,6 +159,16 @@ L2: l2-cache@00a02000 { ...@@ -159,6 +159,16 @@ L2: l2-cache@00a02000 {
arm,data-latency = <4 2 3>; arm,data-latency = <4 2 3>;
}; };
gpu: gpu@01800000 {
compatible = "vivante,gc";
reg = <0x01800000 0x4000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SX_CLK_GPU>,
<&clks IMX6SX_CLK_GPU>,
<&clks IMX6SX_CLK_GPU>;
clock-names = "bus", "core", "shader";
};
dma_apbh: dma-apbh@01804000 { dma_apbh: dma-apbh@01804000 {
compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
reg = <0x01804000 0x2000>; reg = <0x01804000 0x2000>;
...@@ -438,6 +448,7 @@ gpio1: gpio@0209c000 { ...@@ -438,6 +448,7 @@ gpio1: gpio@0209c000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 5 26>;
}; };
gpio2: gpio@020a0000 { gpio2: gpio@020a0000 {
...@@ -449,6 +460,7 @@ gpio2: gpio@020a0000 { ...@@ -449,6 +460,7 @@ gpio2: gpio@020a0000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 31 20>;
}; };
gpio3: gpio@020a4000 { gpio3: gpio@020a4000 {
...@@ -460,6 +472,7 @@ gpio3: gpio@020a4000 { ...@@ -460,6 +472,7 @@ gpio3: gpio@020a4000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 51 29>;
}; };
gpio4: gpio@020a8000 { gpio4: gpio@020a8000 {
...@@ -471,6 +484,7 @@ gpio4: gpio@020a8000 { ...@@ -471,6 +484,7 @@ gpio4: gpio@020a8000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 80 32>;
}; };
gpio5: gpio@020ac000 { gpio5: gpio@020ac000 {
...@@ -482,6 +496,7 @@ gpio5: gpio@020ac000 { ...@@ -482,6 +496,7 @@ gpio5: gpio@020ac000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 112 24>;
}; };
gpio6: gpio@020b0000 { gpio6: gpio@020b0000 {
...@@ -493,6 +508,7 @@ gpio6: gpio@020b0000 { ...@@ -493,6 +508,7 @@ gpio6: gpio@020b0000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>;
}; };
gpio7: gpio@020b4000 { gpio7: gpio@020b4000 {
...@@ -504,6 +520,7 @@ gpio7: gpio@020b4000 { ...@@ -504,6 +520,7 @@ gpio7: gpio@020b4000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>;
}; };
kpp: kpp@020b8000 { kpp: kpp@020b8000 {
...@@ -1273,4 +1290,9 @@ pcie: pcie@0x08000000 { ...@@ -1273,4 +1290,9 @@ pcie: pcie@0x08000000 {
status = "disabled"; status = "disabled";
}; };
}; };
gpu-subsystem {
compatible = "fsl,imx-gpu-subsystem";
cores = <&gpu>;
};
}; };
arch/arm/boot/dts/imx6ul-geam-kit.dts 0 → 100644
View file @ 4dbacf2c
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6ul-geam.dtsi"
/ {
model = "Engicam GEAM6UL";
compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
};
&can1 {
status = "okay";
};
&can2 {
status = "okay";
};
&lcdif {
display = <&display0>;
status = "okay";
display0: display {
bits-per-pixel = <16>;
bus-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <28000000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <30>;
hback-porch = <30>;
hsync-len = <64>;
vback-porch = <5>;
vfront-porch = <5>;
vsync-len = <20>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
status = "okay";
};
&tsc {
measure-delay-time = <0x1ffff>;
pre-charge-time = <0x1fff>;
status = "okay";
};
arch/arm/boot/dts/imx6ul-geam.dtsi 0 → 100644
View file @ 4dbacf2c
/*
* Copyright (C) 2016 Amarula Solutions B.V.
* Copyright (C) 2016 Engicam S.r.l.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6ul.dtsi"
/ {
memory {
reg = <0x80000000 0x08000000>;
};
chosen {
stdout-path = &uart1;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_3p3v>;
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_3p3v>;
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 {
clock_frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
display = <&display0>;
};
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbotg1 {
dr_mode = "peripheral";
status = "okay";
};
&usbotg2 {
dr_mode = "host";
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <4>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
no-1-8-v;
status = "okay";
};
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* ENET_nRST */
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x4001b031
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
>;
};
pinctrl_gpmi_nand: gpmi-nand {
fsl,pins = <
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
>;
};
pinctrl_lcdif_ctrl: lcdifctrlgrp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
>;
};
pinctrl_lcdif_dat: lcdifdatgrp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
>;
};
pinctrl_tsc: tscgrp {
fsl,pin = <
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17070
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x10070
MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17070
MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17070
MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17070
MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17070
>;
};
};
arch/arm/boot/dts/imx6ul-pico-hobbit.dts
View file @ 4dbacf2c
...@@ -100,6 +100,18 @@ reg_usb_otg_vbus: regulator-usb-otg-vbus { ...@@ -100,6 +100,18 @@ reg_usb_otg_vbus: regulator-usb-otg-vbus {
gpio = <&gpio1 6 0>; gpio = <&gpio1 6 0>;
}; };
reg_brcm: regulator-brcm {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_brcm_reg>;
regulator-name = "brcm_reg";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <200000>;
};
sound { sound {
compatible = "fsl,imx-audio-sgtl5000"; compatible = "fsl,imx-audio-sgtl5000";
model = "imx6ul-sgtl5000"; model = "imx6ul-sgtl5000";
...@@ -325,12 +337,27 @@ &usdhc2 { /* Wifi SDIO */ ...@@ -325,12 +337,27 @@ &usdhc2 { /* Wifi SDIO */
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>; pinctrl-0 = <&pinctrl_usdhc2>;
no-1-8-v; no-1-8-v;
non-removable;
keep-power-in-suspend; keep-power-in-suspend;
wakeup-source; wakeup-source;
vmmc-supply = <&reg_brcm>;
status = "okay"; status = "okay";
}; };
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
};
&iomuxc { &iomuxc {
pinctrl_brcm_reg: brcmreggrp {
fsl,pins = <
MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */
MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */
>;
};
pinctrl_enet2: enet2grp { pinctrl_enet2: enet2grp {
fsl,pins = < fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0 MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0
...@@ -513,4 +540,10 @@ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 ...@@ -513,4 +540,10 @@ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
>; >;
}; };
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
>;
};
}; };
arch/arm/boot/dts/imx6ul.dtsi
View file @ 4dbacf2c
...@@ -411,6 +411,8 @@ gpio1: gpio@0209c000 { ...@@ -411,6 +411,8 @@ gpio1: gpio@0209c000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
<&iomuxc 16 33 16>;
}; };
gpio2: gpio@020a0000 { gpio2: gpio@020a0000 {
...@@ -422,6 +424,7 @@ gpio2: gpio@020a0000 { ...@@ -422,6 +424,7 @@ gpio2: gpio@020a0000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
}; };
gpio3: gpio@020a4000 { gpio3: gpio@020a4000 {
...@@ -433,6 +436,7 @@ gpio3: gpio@020a4000 { ...@@ -433,6 +436,7 @@ gpio3: gpio@020a4000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 65 29>;
}; };
gpio4: gpio@020a8000 { gpio4: gpio@020a8000 {
...@@ -444,6 +448,7 @@ gpio4: gpio@020a8000 { ...@@ -444,6 +448,7 @@ gpio4: gpio@020a8000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
}; };
gpio5: gpio@020ac000 { gpio5: gpio@020ac000 {
...@@ -455,6 +460,7 @@ gpio5: gpio@020ac000 { ...@@ -455,6 +460,7 @@ gpio5: gpio@020ac000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
}; };
fec2: ethernet@020b4000 { fec2: ethernet@020b4000 {
...@@ -644,7 +650,8 @@ iomuxc: iomuxc@020e0000 { ...@@ -644,7 +650,8 @@ iomuxc: iomuxc@020e0000 {
}; };
gpr: iomuxc-gpr@020e4000 { gpr: iomuxc-gpr@020e4000 {
compatible = "fsl,imx6ul-iomuxc-gpr", "syscon"; compatible = "fsl,imx6ul-iomuxc-gpr",
"fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x020e4000 0x4000>; reg = <0x020e4000 0x4000>;
}; };
......
arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
View file @ 4dbacf2c
...@@ -138,10 +138,6 @@ &usbotg1 { ...@@ -138,10 +138,6 @@ &usbotg1 {
}; };
&usdhc1 { &usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
no-1-8-v;
cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
keep-power-in-suspend; keep-power-in-suspend;
wakeup-source; wakeup-source;
status = "okay"; status = "okay";
......
arch/arm/boot/dts/imx7-colibri.dtsi
View file @ 4dbacf2c
...@@ -46,12 +46,18 @@ bl: backlight { ...@@ -46,12 +46,18 @@ bl: backlight {
pwms = <&pwm1 0 5000000>; pwms = <&pwm1 0 5000000>;
}; };
reg_3p3v: regulator-3p3v { reg_module_3v3: regulator-module-3v3 {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
regulator-name = "3P3V"; regulator-name = "+V3.3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_module_3v3_avdd: regulator-module-3v3-avdd {
compatible = "regulator-fixed";
regulator-name = "+V3.3_AVDD_AUDIO";
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-always-on;
}; };
reg_vref_1v8: regulator-vref-1v8 { reg_vref_1v8: regulator-vref-1v8 {
...@@ -60,6 +66,22 @@ reg_vref_1v8: regulator-vref-1v8 { ...@@ -60,6 +66,22 @@ reg_vref_1v8: regulator-vref-1v8 {
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
}; };
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "imx7-sgtl5000";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,cpu {
sound-dai = <&sai1>;
};
dailink_master: simple-audio-card,codec {
sound-dai = <&codec>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
};
};
}; };
&adc1 { &adc1 {
...@@ -97,6 +119,18 @@ &i2c1 { ...@@ -97,6 +119,18 @@ &i2c1 {
pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>; pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
status = "okay"; status = "okay";
codec: sgtl5000@0a {
compatible = "fsl,sgtl5000";
#sound-dai-cells = <0>;
reg = <0x0a>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1_mclk>;
VDDA-supply = <&reg_module_3v3_avdd>;
VDDIO-supply = <&reg_module_3v3>;
VDDD-supply = <&reg_DCDC3>;
};
ad7879@2c { ad7879@2c {
compatible = "adi,ad7879-1"; compatible = "adi,ad7879-1";
reg = <0x2c>; reg = <0x2c>;
...@@ -217,6 +251,12 @@ &reg_1p0d { ...@@ -217,6 +251,12 @@ &reg_1p0d {
vin-supply = <&reg_DCDC3>; vin-supply = <&reg_DCDC3>;
}; };
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
status = "okay";
};
&snvs_pwrkey { &snvs_pwrkey {
status = "disabled"; status = "disabled";
}; };
...@@ -251,6 +291,14 @@ &usbotg1 { ...@@ -251,6 +291,14 @@ &usbotg1 {
dr_mode = "host"; dr_mode = "host";
}; };
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
no-1-8-v;
cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
disable-wp;
};
&iomuxc { &iomuxc {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>; pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>;
...@@ -528,13 +576,18 @@ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 ...@@ -528,13 +576,18 @@ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
pinctrl_sai1: sai1-grp { pinctrl_sai1: sai1-grp {
fsl,pins = < fsl,pins = <
MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
>; >;
}; };
pinctrl_sai1_mclk: sai1grp_mclk {
fsl,pins = <
MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
>;
};
}; };
&iomuxc_lpsr { &iomuxc_lpsr {
......
arch/arm/boot/dts/imx7d.dtsi
View file @ 4dbacf2c
...@@ -45,13 +45,24 @@ ...@@ -45,13 +45,24 @@
/ { / {
cpus { cpus {
cpu0: cpu@0 {
operating-points = <
/* KHz uV */
996000 1075000
792000 975000
>;
clock-frequency = <996000000>;
};
cpu1: cpu@1 { cpu1: cpu@1 {
compatible = "arm,cortex-a7"; compatible = "arm,cortex-a7";
device_type = "cpu"; device_type = "cpu";
reg = <1>; reg = <1>;
clock-frequency = <996000000>;
}; };
}; };
soc {
etm@3007d000 { etm@3007d000 {
compatible = "arm,coresight-etm3x", "arm,primecell"; compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x3007d000 0x1000>; reg = <0x3007d000 0x1000>;
...@@ -72,6 +83,7 @@ etm1_out_port: endpoint { ...@@ -72,6 +83,7 @@ etm1_out_port: endpoint {
}; };
}; };
}; };
};
}; };
&aips3 { &aips3 {
......
arch/arm/boot/dts/imx7s-warp.dts 0 → 100644
View file @ 4dbacf2c
/*
* Copyright (C) 2016 NXP Semiconductors.
* Author: Fabio Estevam <fabio.estevam@nxp.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "imx7s.dtsi"
/ {
model = "Warp i.MX7 Board";
compatible = "warp,imx7s-warp", "fsl,imx7s";
memory {
reg = <0x80000000 0x20000000>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&pinctrl_gpio>;
autorepeat;
back {
label = "Back";
gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_BACK>;
wakeup-source;
};
};
reg_brcm: regulator-brcm {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_brcm_reg>;
regulator-name = "brcm_reg";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
startup-delay-us = <200000>;
};
reg_bt: regulator-bt {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bt_reg>;
enable-active-high;
gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
regulator-name = "bt_reg";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "imx7-sgtl5000";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,cpu {
sound-dai = <&sai1>;
};
dailink_master: simple-audio-card,codec {
sound-dai = <&codec>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
};
};
};
&clks {
assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
assigned-clock-rates = <884736000>;
};
&cpu0 {
arm-supply = <&sw1a_reg>;
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pfuze3000@08 {
compatible = "fsl,pfuze3000";
reg = <0x08>;
regulators {
sw1a_reg: sw1a {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1475000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
/* use sw1c_reg to align with pfuze100/pfuze200 */
sw1c_reg: sw1b {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1475000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1650000>;
regulator-boot-on;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen2_reg: vldo2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vccsd {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: v33 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vldo3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vldo4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
codec: sgtl5000@0a {
#sound-dai-cells = <0>;
reg = <0x0a>;
compatible = "fsl,sgtl5000";
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1_mclk>;
VDDA-supply = <&vgen4_reg>;
VDDIO-supply = <&vgen4_reg>;
VDDD-supply = <&vgen2_reg>;
};
mpl3115@60 {
compatible = "fsl,mpl3115";
reg = <0x60>;
};
};
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
<&clks IMX7D_SAI1_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
assigned-clock-rates = <0>, <36864000>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
dr_mode = "peripheral";
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <4>;
keep-power-in-suspend;
no-1-8-v;
non-removable;
vmmc-supply = <&reg_brcm>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
assigned-clock-rates = <400000000>;
bus-width = <8>;
fsl,tuning-step = <2>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_brcm_reg: brcmreggrp {
fsl,pins = <
MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */
>;
};
pinctrl_bt_reg: btreggrp {
fsl,pins = <
MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */
>;
};
pinctrl_gpio: gpiogrp {
fsl,pins = <
MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f
MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f
MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30
>;
};
pinctrl_sai1_mclk: sai1mclkgrp {
fsl,pins = <
MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79
MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79
MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79
MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
MX7D_PAD_SD3_CLK__SD3_CLK 0x19
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74
>;
};
};
arch/arm/boot/dts/imx7s.dtsi
View file @ 4dbacf2c
...@@ -85,26 +85,12 @@ cpu0: cpu@0 { ...@@ -85,26 +85,12 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a7"; compatible = "arm,cortex-a7";
device_type = "cpu"; device_type = "cpu";
reg = <0>; reg = <0>;
operating-points = < clock-frequency = <792000000>;
/* KHz uV */
996000 1075000
792000 975000
>;
clock-latency = <61036>; /* two CLK32 periods */ clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX7D_CLK_ARM>; clocks = <&clks IMX7D_CLK_ARM>;
}; };
}; };
intc: interrupt-controller@31001000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x31001000 0x1000>,
<0x31002000 0x1000>,
<0x31004000 0x2000>,
<0x31006000 0x2000>;
};
ckil: clock-cki { ckil: clock-cki {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>; #clock-cells = <0>;
...@@ -119,77 +105,92 @@ osc: clock-osc { ...@@ -119,77 +105,92 @@ osc: clock-osc {
clock-output-names = "osc"; clock-output-names = "osc";
}; };
timer { soc {
compatible = "arm,armv7-timer"; #address-cells = <1>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, #size-cells = <1>;
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, compatible = "simple-bus";
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
}; ranges;
etr@30086000 { funnel@30041000 {
compatible = "arm,coresight-tmc", "arm,primecell"; compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0x30086000 0x1000>; reg = <0x30041000 0x1000>;
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
port { ca_funnel_ports: ports {
etr_in_port: endpoint { #address-cells = <1>;
#size-cells = <0>;
/* funnel input ports */
port@0 {
reg = <0>;
ca_funnel_in_port0: endpoint {
slave-mode; slave-mode;
remote-endpoint = <&replicator_out_port1>; remote-endpoint = <&etm0_out_port>;
}; };
}; };
/* funnel output port */
port@2 {
reg = <0>;
ca_funnel_out_port0: endpoint {
remote-endpoint = <&hugo_funnel_in_port0>;
};
}; };
tpiu@30087000 { /* the other input ports are not connect to anything */
compatible = "arm,coresight-tpiu", "arm,primecell"; };
reg = <0x30087000 0x1000>; };
etm@3007c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x3007c000 0x1000>;
cpu = <&cpu0>;
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
port { port {
tpiu_in_port: endpoint { etm0_out_port: endpoint {
slave-mode; remote-endpoint = <&ca_funnel_in_port0>;
remote-endpoint = <&replicator_out_port1>;
}; };
}; };
}; };
replicator { funnel@30083000 {
/* compatible = "arm,coresight-funnel", "arm,primecell";
* non-configurable replicators don't show up on the reg = <0x30083000 0x1000>;
* AMBA bus. As such no need to add "arm,primecell" clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
*/ clock-names = "apb_pclk";
compatible = "arm,coresight-replicator";
ports { ports {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
/* replicator output ports */ /* funnel input ports */
port@0 { port@0 {
reg = <0>; reg = <0>;
replicator_out_port0: endpoint { hugo_funnel_in_port0: endpoint {
remote-endpoint = <&tpiu_in_port>; slave-mode;
remote-endpoint = <&ca_funnel_out_port0>;
}; };
}; };
port@1 { port@1 {
reg = <1>; reg = <1>;
replicator_out_port1: endpoint { hugo_funnel_in_port1: endpoint {
remote-endpoint = <&etr_in_port>; slave-mode; /* M4 input */
}; };
}; };
/* replicator input port */
port@2 { port@2 {
reg = <0>; reg = <0>;
replicator_in_port0: endpoint { hugo_funnel_out_port0: endpoint {
slave-mode; remote-endpoint = <&etf_in_port>;
remote-endpoint = <&etf_out_port>;
}; };
}; };
/* the other input ports are not connect to anything */
}; };
}; };
...@@ -220,94 +221,89 @@ etf_out_port: endpoint { ...@@ -220,94 +221,89 @@ etf_out_port: endpoint {
}; };
}; };
funnel@30083000 { etr@30086000 {
compatible = "arm,coresight-funnel", "arm,primecell"; compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x30083000 0x1000>; reg = <0x30086000 0x1000>;
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
ports { port {
#address-cells = <1>; etr_in_port: endpoint {
#size-cells = <0>;
/* funnel input ports */
port@0 {
reg = <0>;
hugo_funnel_in_port0: endpoint {
slave-mode; slave-mode;
remote-endpoint = <&ca_funnel_out_port0>; remote-endpoint = <&replicator_out_port1>;
};
}; };
port@1 {
reg = <1>;
hugo_funnel_in_port1: endpoint {
slave-mode; /* M4 input */
}; };
}; };
port@2 { tpiu@30087000 {
reg = <0>; compatible = "arm,coresight-tpiu", "arm,primecell";
hugo_funnel_out_port0: endpoint { reg = <0x30087000 0x1000>;
remote-endpoint = <&etf_in_port>; clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
}; clock-names = "apb_pclk";
};
/* the other input ports are not connect to anything */ port {
tpiu_in_port: endpoint {
slave-mode;
remote-endpoint = <&replicator_out_port1>;
};
}; };
}; };
funnel@30041000 { replicator {
compatible = "arm,coresight-funnel", "arm,primecell"; /*
reg = <0x30041000 0x1000>; * non-configurable replicators don't show up on the
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; * AMBA bus. As such no need to add "arm,primecell"
clock-names = "apb_pclk"; */
compatible = "arm,coresight-replicator";
ca_funnel_ports: ports { ports {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
/* funnel input ports */ /* replicator output ports */
port@0 { port@0 {
reg = <0>; reg = <0>;
ca_funnel_in_port0: endpoint { replicator_out_port0: endpoint {
slave-mode; remote-endpoint = <&tpiu_in_port>;
remote-endpoint = <&etm0_out_port>;
}; };
}; };
/* funnel output port */ port@1 {
port@2 { reg = <1>;
reg = <0>; replicator_out_port1: endpoint {
ca_funnel_out_port0: endpoint { remote-endpoint = <&etr_in_port>;
remote-endpoint = <&hugo_funnel_in_port0>;
}; };
}; };
/* the other input ports are not connect to anything */ /* replicator input port */
port@2 {
reg = <0>;
replicator_in_port0: endpoint {
slave-mode;
remote-endpoint = <&etf_out_port>;
}; };
}; };
etm@3007c000 {
compatible = "arm,coresight-etm3x", "arm,primecell";
reg = <0x3007c000 0x1000>;
cpu = <&cpu0>;
clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
clock-names = "apb_pclk";
port {
etm0_out_port: endpoint {
remote-endpoint = <&ca_funnel_in_port0>;
}; };
}; };
intc: interrupt-controller@31001000 {
compatible = "arm,cortex-a7-gic";
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x31001000 0x1000>,
<0x31002000 0x2000>,
<0x31004000 0x2000>,
<0x31006000 0x2000>;
}; };
soc { timer {
#address-cells = <1>; compatible = "arm,armv7-timer";
#size-cells = <1>; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
compatible = "simple-bus"; <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
interrupt-parent = <&intc>; <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
ranges; <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
aips1: aips-bus@30000000 { aips1: aips-bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus"; compatible = "fsl,aips-bus", "simple-bus";
...@@ -325,6 +321,7 @@ gpio1: gpio@30200000 { ...@@ -325,6 +321,7 @@ gpio1: gpio@30200000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
}; };
gpio2: gpio@30210000 { gpio2: gpio@30210000 {
...@@ -336,6 +333,7 @@ gpio2: gpio@30210000 { ...@@ -336,6 +333,7 @@ gpio2: gpio@30210000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 13 32>;
}; };
gpio3: gpio@30220000 { gpio3: gpio@30220000 {
...@@ -347,6 +345,7 @@ gpio3: gpio@30220000 { ...@@ -347,6 +345,7 @@ gpio3: gpio@30220000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 45 29>;
}; };
gpio4: gpio@30230000 { gpio4: gpio@30230000 {
...@@ -358,6 +357,7 @@ gpio4: gpio@30230000 { ...@@ -358,6 +357,7 @@ gpio4: gpio@30230000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 74 24>;
}; };
gpio5: gpio@30240000 { gpio5: gpio@30240000 {
...@@ -369,6 +369,7 @@ gpio5: gpio@30240000 { ...@@ -369,6 +369,7 @@ gpio5: gpio@30240000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 98 18>;
}; };
gpio6: gpio@30250000 { gpio6: gpio@30250000 {
...@@ -380,6 +381,7 @@ gpio6: gpio@30250000 { ...@@ -380,6 +381,7 @@ gpio6: gpio@30250000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 116 23>;
}; };
gpio7: gpio@30260000 { gpio7: gpio@30260000 {
...@@ -391,6 +393,7 @@ gpio7: gpio@30260000 { ...@@ -391,6 +393,7 @@ gpio7: gpio@30260000 {
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 139 16>;
}; };
wdog1: wdog@30280000 { wdog1: wdog@30280000 {
...@@ -723,6 +726,51 @@ uart3: serial@30880000 { ...@@ -723,6 +726,51 @@ uart3: serial@30880000 {
status = "disabled"; status = "disabled";
}; };
sai1: sai@308a0000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
reg = <0x308a0000 0x10000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_SAI1_IPG_CLK>,
<&clks IMX7D_SAI1_ROOT_CLK>,
<&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_CLK_DUMMY>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "rx", "tx";
dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
status = "disabled";
};
sai2: sai@308b0000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
reg = <0x308b0000 0x10000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_SAI2_IPG_CLK>,
<&clks IMX7D_SAI2_ROOT_CLK>,
<&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_CLK_DUMMY>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "rx", "tx";
dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
status = "disabled";
};
sai3: sai@308c0000 {
#sound-dai-cells = <0>;
compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
reg = <0x308c0000 0x10000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_SAI3_IPG_CLK>,
<&clks IMX7D_SAI3_ROOT_CLK>,
<&clks IMX7D_CLK_DUMMY>,
<&clks IMX7D_CLK_DUMMY>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";
dma-names = "rx", "tx";
dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
status = "disabled";
};
flexcan1: can@30a00000 { flexcan1: can@30a00000 {
compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
reg = <0x30a00000 0x10000>; reg = <0x30a00000 0x10000>;
...@@ -911,6 +959,17 @@ usdhc3: usdhc@30b60000 { ...@@ -911,6 +959,17 @@ usdhc3: usdhc@30b60000 {
status = "disabled"; status = "disabled";
}; };
sdma: sdma@30bd0000 {
compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
reg = <0x30bd0000 0x10000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_SDMA_CORE_CLK>,
<&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
fec1: ethernet@30be0000 { fec1: ethernet@30be0000 {
compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
reg = <0x30be0000 0x10000>; reg = <0x30be0000 0x10000>;
......
arch/arm/boot/dts/ls1021a-twr.dts
View file @ 4dbacf2c
...@@ -108,12 +108,23 @@ simple-audio-card,codec { ...@@ -108,12 +108,23 @@ simple-audio-card,codec {
panel: panel { panel: panel {
compatible = "nec,nl4827hc19-05b"; compatible = "nec,nl4827hc19-05b";
port {
panel_in: endpoint {
remote-endpoint = <&dcu_out>;
};
};
}; };
}; };
&dcu { &dcu {
fsl,panel = <&panel>;
status = "okay"; status = "okay";
port {
dcu_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
}; };
&dspi1 { &dspi1 {
......
arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
View file @ 4dbacf2c
...@@ -53,6 +53,12 @@ clk16m: clk16m { ...@@ -53,6 +53,12 @@ clk16m: clk16m {
panel: panel { panel: panel {
compatible = "edt,et057090dhu"; compatible = "edt,et057090dhu";
backlight = <&bl>; backlight = <&bl>;
port {
panel_in: endpoint {
remote-endpoint = <&dcu_out>;
};
};
}; };
reg_3v3: regulator-3v3 { reg_3v3: regulator-3v3 {
...@@ -91,8 +97,13 @@ &bl { ...@@ -91,8 +97,13 @@ &bl {
&dcu0 { &dcu0 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dcu0_1>; pinctrl-0 = <&pinctrl_dcu0_1>;
fsl,panel = <&panel>;
status = "okay"; status = "okay";
port {
dcu_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
}; };
&dspi1 { &dspi1 {
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7