Commit 4f6da36f authored by Magnus Damm's avatar Magnus Damm Committed by Simon Horman

ARM: shmobile: Remove old SCU boot code

Remove shmobile_secondary_vector_scu now when all SCU enabled
SMP platforms instead make use of shmobile_boot_scu. This
removes two inline virtual to physical address conversions.
Signed-off-by: default avatarMagnus Damm <damm@opensource.se>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent a188bfca
......@@ -25,32 +25,12 @@
__CPUINIT
/*
* Reset vector for secondary CPUs.
* Boot code for secondary CPUs.
*
* First we turn on L1 cache coherency for our CPU. Then we jump to
* shmobile_invalidate_start that invalidates the cache and hands over control
* to the common ARM startup code.
* This function will be mapped to address 0 by the SBAR register.
* A normal branch is out of range here so we need a long jump. We jump to
* the physical address as the MMU is still turned off.
*/
.align 12
ENTRY(shmobile_secondary_vector_scu)
mrc p15, 0, r0, c0, c0, 5 @ read MIPDR
and r0, r0, #3 @ mask out cpu ID
lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits
ldr r1, 2f
ldr r1, [r1] @ SCU base address
ldr r2, [r1, #8] @ SCU Power Status Register
mov r3, #3
bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode)
str r2, [r1, #8] @ write back
ldr pc, 1f
1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
2: .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET
ENDPROC(shmobile_secondary_vector_scu)
ENTRY(shmobile_boot_scu)
@ r0 = SCU base address
mrc p15, 0, r1, c0, c0, 5 @ read MIPDR
......
......@@ -10,7 +10,6 @@ extern void shmobile_setup_console(void);
extern void shmobile_boot_vector(void);
extern unsigned long shmobile_boot_fn;
extern unsigned long shmobile_boot_arg;
extern void shmobile_secondary_vector_scu(void);
extern void shmobile_boot_scu(void);
struct clk;
extern int shmobile_clk_init(void);
......
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