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Commit 50aaccb1 authored by Anton Blanchard's avatar Anton Blanchard
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ppc64: store trap into exception frame, make DSISR 32bit and create 

CCR field - from Dave Engebretsen
parent 7e43513d
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Showing with 94 additions and 89 deletions
arch/ppc64/kernel/head.S
View file @ 50aaccb1
......@@ -163,14 +163,18 @@ _GLOBAL(__secondary_hold)
#define EX_R23 40
#define EX_DAR 48
#define EX_DSISR 56
#define EX_CCR 60
#define EX_TRAP 60
#define EXCEPTION_PROLOG_PSERIES(label) \
#define EXCEPTION_PROLOG_PSERIES(n,label) \
mtspr SPRG2,r20; /* use SPRG2 as scratch reg */ \
mtspr SPRG1,r21; /* save r21 */ \
mfspr r20,SPRG3; /* get paca virt addr */ \
ld r21,PACAEXCSP(r20); /* get exception stack ptr */ \
addi r21,r21,EXC_FRAME_SIZE; /* make exception frame */ \
std r22,EX_R22(r21); /* Save r22 in exc. frame */ \
li r22,n; /* Save the ex # in exc. frame*/ \
stw r22,EX_TRAP(r21); /* */ \
std r23,EX_R23(r21); /* Save r23 in exc. frame */ \
mfspr r22,SRR0; /* EA of interrupted instr */ \
std r22,EX_SRR0(r21); /* Save SRR0 in exc. frame */ \
......@@ -192,18 +196,20 @@ _GLOBAL(__secondary_hold)
* This is the start of the interrupt handlers for i_series
* This code runs with relocation on.
*/
#define EXCEPTION_PROLOG_ISERIES \
mtspr SPRG2,r20; /* use SPRG2 as scratch reg */\
mtspr SPRG1,r21; /* save r21 */\
mfspr r20,SPRG3; /* get paca */\
ld r21,PACAEXCSP(r20); /* get exception stack ptr */\
addi r21,r21,EXC_FRAME_SIZE; /* make exception frame */\
std r22,EX_R22(r21); /* save r22 on exception frame */\
std r23,EX_R23(r21); /* Save r23 in exc. frame */\
ld r22,LPPACA+LPPACASRR0(r20); /* Get SRR0 from ItLpPaca */\
std r22,EX_SRR0(r21); /* save SRR0 in exc. frame */\
ld r23,LPPACA+LPPACASRR1(r20); /* Get SRR1 from ItLpPaca */\
std r23,EX_SRR1(r21); /* save SRR1 in exc. frame */\
#define EXCEPTION_PROLOG_ISERIES(n) \
mtspr SPRG2,r20; /* use SPRG2 as scratch reg */ \
mtspr SPRG1,r21; /* save r21 */ \
mfspr r20,SPRG3; /* get paca */ \
ld r21,PACAEXCSP(r20); /* get exception stack ptr */ \
addi r21,r21,EXC_FRAME_SIZE; /* make exception frame */ \
std r22,EX_R22(r21); /* save r22 on exception frame */ \
li r22,n; /* Save the ex # in exc. frame */ \
stw r22,EX_TRAP(r21); /* */ \
std r23,EX_R23(r21); /* Save r23 in exc. frame */ \
ld r22,LPPACA+LPPACASRR0(r20); /* Get SRR0 from ItLpPaca */ \
std r22,EX_SRR0(r21); /* save SRR0 in exc. frame */ \
ld r23,LPPACA+LPPACASRR1(r20); /* Get SRR1 from ItLpPaca */ \
std r23,EX_SRR1(r21); /* save SRR1 in exc. frame */ \
mfcr r23; /* save CR in r23 */
/*
......@@ -225,7 +231,7 @@ _GLOBAL(__secondary_hold)
std r21,PACAEXCSP(r20); /* update exception stack ptr */ \
/* iff no protection flt */ \
mfspr r22,DSISR; /* Save DSISR in exc. frame */ \
std r22,EX_DSISR(r21); \
stw r22,EX_DSISR(r21); \
ld r22,EX_SRR1(r21); /* Get SRR1 from exc. frame */ \
andi. r22,r22,MSR_PR; /* Set CR for later branch */ \
mr r22,r1; /* Save r1 */ \
......@@ -251,7 +257,7 @@ _GLOBAL(__secondary_hold)
std r22,_XER(r1); \
ld r23,EX_DAR(r21); /* move DAR to stackframe */ \
std r23,_DAR(r1); \
ld r22,EX_DSISR(r21); /* move DSISR to stackframe */ \
lwz r22,EX_DSISR(r21); /* move DSISR to stackframe */ \
std r22,_DSISR(r1); \
lbz r22,PACAPROCENABLED(r20); \
std r22,SOFTE(r1); \
......@@ -277,18 +283,18 @@ _GLOBAL(__secondary_hold)
. = n; \
.globl label##_Pseries; \
label##_Pseries: \
EXCEPTION_PROLOG_PSERIES( label##_common )
EXCEPTION_PROLOG_PSERIES( n, label##_common )
#define STD_EXCEPTION_ISERIES( label ) \
#define STD_EXCEPTION_ISERIES( n, label ) \
.globl label##_Iseries; \
label##_Iseries: \
EXCEPTION_PROLOG_ISERIES; \
EXCEPTION_PROLOG_ISERIES( n ); \
b label##_common
#define MASKABLE_EXCEPTION_ISERIES( label ) \
#define MASKABLE_EXCEPTION_ISERIES( n, label ) \
.globl label##_Iseries; \
label##_Iseries: \
EXCEPTION_PROLOG_ISERIES; \
EXCEPTION_PROLOG_ISERIES( n ); \
lbz r22,PACAPROFENABLED(r20); \
cmpi 0,r22,0; \
bne- label##_Iseries_profile; \
......@@ -364,7 +370,6 @@ __start_naca:
* For LPAR, the hypervisor must fill in at least one entry
* before we get control (with relocate on)
*/
. = 0x5000
.globl __end_naca
.globl __start_stab
......@@ -403,22 +408,22 @@ __end_stab:
/*** ISeries-LPAR interrupt handlers ***/
STD_EXCEPTION_ISERIES( MachineCheck )
STD_EXCEPTION_ISERIES( DataAccess )
STD_EXCEPTION_ISERIES( DataAccessSLB )
STD_EXCEPTION_ISERIES( InstructionAccess )
STD_EXCEPTION_ISERIES( InstructionAccessSLB )
MASKABLE_EXCEPTION_ISERIES( HardwareInterrupt )
STD_EXCEPTION_ISERIES( Alignment )
STD_EXCEPTION_ISERIES( ProgramCheck )
STD_EXCEPTION_ISERIES( FPUnavailable )
MASKABLE_EXCEPTION_ISERIES( Decrementer )
STD_EXCEPTION_ISERIES( Trap_0a )
STD_EXCEPTION_ISERIES( Trap_0b )
STD_EXCEPTION_ISERIES( SystemCall )
STD_EXCEPTION_ISERIES( SingleStep )
STD_EXCEPTION_ISERIES( Trap_0e )
STD_EXCEPTION_ISERIES( PerformanceMonitor )
STD_EXCEPTION_ISERIES( 0x200, MachineCheck )
STD_EXCEPTION_ISERIES( 0x300, DataAccess )
STD_EXCEPTION_ISERIES( 0x380, DataAccessSLB )
STD_EXCEPTION_ISERIES( 0x400, InstructionAccess )
STD_EXCEPTION_ISERIES( 0x480, InstructionAccessSLB )
MASKABLE_EXCEPTION_ISERIES( 0x500, HardwareInterrupt )
STD_EXCEPTION_ISERIES( 0x600, Alignment )
STD_EXCEPTION_ISERIES( 0x700, ProgramCheck )
STD_EXCEPTION_ISERIES( 0x800, FPUnavailable )
MASKABLE_EXCEPTION_ISERIES( 0x900, Decrementer )
STD_EXCEPTION_ISERIES( 0xa00, Trap_0a )
STD_EXCEPTION_ISERIES( 0xb00, Trap_0b )
STD_EXCEPTION_ISERIES( 0xc00, SystemCall )
STD_EXCEPTION_ISERIES( 0xd00, SingleStep )
STD_EXCEPTION_ISERIES( 0xe00, Trap_0e )
STD_EXCEPTION_ISERIES( 0xf00, PerformanceMonitor )
.globl SystemReset_Iseries
SystemReset_Iseries:
......@@ -503,10 +508,10 @@ fwnmi_data_area:
. = 0x8000
.globl SystemReset_FWNMI
SystemReset_FWNMI:
//EXCEPTION_PROLOG_PSERIES(0x100, SystemReset_common)
EXCEPTION_PROLOG_PSERIES(0x100, SystemReset_common)
.globl MachineCheck_FWNMI
MachineCheck_FWNMI:
//EXCEPTION_PROLOG_PSERIES(0x200, MachineCheck_common)
EXCEPTION_PROLOG_PSERIES(0x200, MachineCheck_common)
/*** Common interrupt handlers ***/
......@@ -839,7 +844,7 @@ _GLOBAL(do_hash_page_DSI)
* We assume we aren't going to take any exceptions during this procedure.
*/
_GLOBAL(do_stab_bolted)
std r23,EX_DAR(r21) /* save CR in exc. frame */
stw r23,EX_CCR(r21) /* save CR in exc. frame */
mfspr r22,DSISR
andis. r22,r22,0x0020
......@@ -945,7 +950,7 @@ _GLOBAL(do_stab_bolted)
mfsprg r20,3 /* Load the PACA pointer */
ld r21,PACAEXCSP(r20) /* Get the exception frame pointer */
addi r21,r21,EXC_FRAME_SIZE
ld r23,EX_DAR(r21) /* get saved CR */
lwz r23,EX_CCR(r21) /* get saved CR */
/* note that this is almost identical to maskable_exception_exit */
mtcr r23 /* restore CR */
ld r22,EX_SRR0(r21) /* Get SRR0 from exc. frame */
......@@ -966,7 +971,7 @@ _TRACEBACK(do_stab_bolted)
* We assume we aren't going to take any exceptions during this procedure.
*/
_GLOBAL(do_slb_bolted)
std r23,48(r21) /* save CR in exc. frame */
stw r23,EX_CCR(r21) /* save CR in exc. frame */
/* (((ea >> 28) & 0x1fff) << 15) | (ea >> 60) */
mfspr r21,DAR
......@@ -1033,7 +1038,7 @@ SLB_NUM_ENTRIES = 64
mfsprg r20,3 /* Load the PACA pointer */
ld r21,PACAEXCSP(r20) /* Get the exception frame pointer */
addi r21,r21,EXC_FRAME_SIZE
ld r23,EX_DAR(r21) /* get saved CR */
lwz r23,EX_CCR(r21) /* get saved CR */
/* note that this is almost identical to maskable_exception_exit */
mtcr r23 /* restore CR */
ld r22,EX_SRR0(r21) /* Get SRR0 from exc. frame */
......
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