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Commit 53729698 authored by Paul Mundt's avatar Paul Mundt Committed by Linus Torvalds
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[PATCH] sh: sh-sci updates 

sh-sci updates all around the board.  Support for the newly added subtypes,
some compilation cleanups, etc.
Signed-off-by: default avatarPaul Mundt <paul.mundt@nokia.com>
Signed-off-by: default avatarAndrew Morton <akpm@osdl.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 6c1f40ef
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Showing with 127 additions and 19 deletions
drivers/serial/sh-sci.c
View file @ 53729698
......@@ -3,7 +3,7 @@
*
* SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
*
* Copyright (C) 2002, 2003 Paul Mundt
* Copyright (C) 2002, 2003, 2004 Paul Mundt
*
* based off of the old drivers/char/sh-sci.c by:
*
......@@ -18,7 +18,8 @@
* for more details.
*/
#define DEBUG
#undef DEBUG
#include <linux/config.h>
#include <linux/module.h>
#include <linux/errno.h>
......@@ -332,7 +333,7 @@ static void sci_init_pins_sci(struct uart_port *port, unsigned int cflag)
#if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
#if defined(CONFIG_CPU_SH3)
/* For SH7707, SH7709, SH7709A, SH7729, SH7300*/
/* For SH7705, SH7707, SH7709, SH7709A, SH7729, SH7300*/
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
{
unsigned int fcr_val = 0;
......@@ -798,7 +799,7 @@ static int sci_notifier(struct notifier_block *self, unsigned long phase, void *
if ((phase == CPUFREQ_POSTCHANGE) ||
(phase == CPUFREQ_RESUMECHANGE)){
for (i = 0; i < SCI_NPORTS; i++) {
struct uart_port *port = &sci_ports[i];
struct uart_port *port = &sci_ports[i].port;
/*
* Update the uartclk per-port if frequency has
......@@ -1139,6 +1140,35 @@ static struct sci_port sci_ports[SCI_NPORTS] = {
.irqs = SCI_IRQS,
.init_pins = sci_init_pins_sci,
},
#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
{
.port = {
.membase = (void *)SCIF0,
.mapbase = SCIF0,
.iotype = SERIAL_IO_MEM,
.irq = 55,
.ops = &sci_uart_ops,
.flags = ASYNC_BOOT_AUTOCONF,
.line = 0,
},
.type = PORT_SCIF,
.irqs = SH3_IRDA_IRQS,
.init_pins = sci_init_pins_scif,
},
{
.port = {
.membase = (void *)SCIF2,
.mapbase = SCIF2,
.iotype = SERIAL_IO_MEM,
.irq = 59,
.ops = &sci_uart_ops,
.flags = ASYNC_BOOT_AUTOCONF,
.line = 1,
},
.type = PORT_SCIF,
.irqs = SH3_SCIF_IRQS,
.init_pins = sci_init_pins_scif,
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
{
.port = {
......@@ -1197,6 +1227,21 @@ static struct sci_port sci_ports[SCI_NPORTS] = {
.irqs = SH7300_SCIF0_IRQS,
.init_pins = sci_init_pins_scif,
},
#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
{
.port = {
.membase = (void *)0xffe00000,
.mapbase = 0xffe00000,
.iotype = SERIAL_IO_MEM,
.irq = 25,
.ops = &sci_uart_ops,
.flags = ASYNC_BOOT_AUTOCONF,
.line = 0,
},
.type = PORT_SCIF,
.irqs = SH73180_SCIF_IRQS,
.init_pins = sci_init_pins_scif,
},
#elif defined(CONFIG_SH_RTS7751R2D)
{
.port = {
......@@ -1284,6 +1329,21 @@ static struct sci_port sci_ports[SCI_NPORTS] = {
.irqs = SH7760_SCIF2_IRQS,
.init_pins = sci_init_pins_scif,
},
#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
{
.port = {
.membase = (void *)0xffe80000,
.mapbase = 0xffe80000,
.iotype = SERIAL_IO_MEM,
.irq = 43,
.ops = &sci_uart_ops,
.flags = ASYNC_BOOT_AUTOCONF,
.line = 0,
},
.type = PORT_SCIF,
.irqs = SH4_SCIF_IRQS,
.init_pins = sci_init_pins_scif,
},
#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
{
.port = {
......
drivers/serial/sh-sci.h
View file @ 53729698
......@@ -38,6 +38,7 @@
#define SH7760_SCIF1_IRQS { 72, 73, 75, 74 }
#define SH7760_SCIF2_IRQS { 76, 77, 79, 78 }
#define SH7300_SCIF0_IRQS {80, 80, 80, 80 }
#define SH73180_SCIF_IRQS {80, 81, 83, 82 }
#define H8300H_SCI_IRQS0 {52, 53, 54, 0 }
#define H8300H_SCI_IRQS1 {56, 57, 58, 0 }
#define H8300H_SCI_IRQS2 {60, 61, 62, 0 }
......@@ -57,6 +58,21 @@
# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
# define SCI_AND_SCIF
#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
# define SCIF0 0xA4400000
# define SCIF2 0xA4410000
# define SCSMR_Ir 0xA44A0000
# define IRDA_SCIF SCIF0
# define SCI_NPORTS 2
# define SCPCR 0xA4000116
# define SCPDR 0xA4000136
/* Set the clock source,
* SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
* SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
*/
# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
# define SCIF_ONLY
#elif defined(CONFIG_SH_RTS7751R2D)
# define SCI_NPORTS 1
# define SCSPTR1 0xffe0001c /* 8 bit SCI */
......@@ -87,6 +103,19 @@
# define SCPDR 0xA4050136 /* 16 bit SCIF */
# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
# define SCIF_ONLY
#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
# define SCI_NPORTS 1
# define SCPDR 0xA4050138 /* 16 bit SCIF */
# define SCSPTR2 SCPDR
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */
# define SCIF_ONLY
#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
# define SCI_NPORTS 1
# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* overrun error bit */
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
# define SCIF_ONLY
#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
# define SCI_NPORTS 2
# define SCSPTR1 0xffe00020 /* 16 bit SCIF */
......@@ -152,16 +181,16 @@
#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
/* SCxSR SCIF */
#define SCIF_ER 0x0080 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_TEND 0x0040 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_TDFE 0x0020 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_BRK 0x0010 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_FER 0x0008 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_PER 0x0004 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_RDF 0x0002 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_DR 0x0001 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
#define SCIF_ORER 0x0200
#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
#define SCIF_RFDC_MASK 0x007f
......@@ -190,7 +219,7 @@
# define SCxSR_ERRORS(port) SCIF_ERRORS
# define SCxSR_RDxF(port) SCIF_RDF
# define SCxSR_TDxE(port) SCIF_TDFE
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
# define SCxSR_ORER(port) SCIF_ORER
#else
# define SCxSR_ORER(port) 0x0000
......@@ -198,12 +227,13 @@
# define SCxSR_FER(port) SCIF_FER
# define SCxSR_PER(port) SCIF_PER
# define SCxSR_BRK(port) SCIF_BRK
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
# define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
#else
/* SH7705 can also use this, clearing is same between 7705 and 7709 and 7300 */
# define SCxSR_RDxF_CLEAR(port) 0x00fc
# define SCxSR_ERROR_CLEAR(port) 0x0073
# define SCxSR_TDxE_CLEAR(port) 0x00df
......@@ -307,7 +337,7 @@ struct sci_port {
}
#ifdef CONFIG_CPU_SH3
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
#define SCIF_FNS(name, scif_offset, scif_size) \
CPU_SCIF_FNS(name, scif_offset, scif_size)
#else
......@@ -333,7 +363,7 @@ struct sci_port {
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
SCIF_FNS(SCSMR, 0x00, 16)
SCIF_FNS(SCBRR, 0x04, 8)
SCIF_FNS(SCSCR, 0x08, 16)
......@@ -422,7 +452,18 @@ static inline int sci_rxd_in(struct uart_port *port)
return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == SCIF0)
return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
if (port->mapbase == SCIF2)
return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
defined(CONFIG_CPU_SUBTYPE_SH7751) || \
defined(CONFIG_CPU_SUBTYPE_SH4_202)
static inline int sci_rxd_in(struct uart_port *port)
{
#ifndef SCIF_ONLY
......@@ -452,6 +493,11 @@ static inline int sci_rxd_in(struct uart_port *port)
return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
return 1;
}
#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
static inline int sci_rxd_in(struct uart_port *port)
{
return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
}
#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
static inline int sci_rxd_in(struct uart_port *port)
{
......@@ -510,6 +556,8 @@ static inline int sci_rxd_in(struct uart_port *port)
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
#define SCBRR_VALUE(bps) ((PCLK+16*bps)/(16*bps)-1)
#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
#define SCBRR_VALUE(bps) (((PCLK*2)+16*bps)/(32*bps)-1)
#elif !defined(__H8300H__) && !defined(__H8300S__)
#define SCBRR_VALUE(bps) ((PCLK+16*bps)/(32*bps)-1)
#else
......
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