Merge bk://dsaxena.bkbits.net/linux-2.6-for-rmk

into flint.arm.linux.org.uk:/usr/src/bk/linux-2.6-rmk

arch/arm/mach-ixp4xx/common.c

+/*
+ * arch/arm/mach-ixp4xx/common.c
+ *
+ * Generic code shared across all IXP4XX platforms
+ *
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2002 (c) Intel Corporation
+ * Copyright 2003-2004 (c) MontaVista, Software, Inc. 
+ * 
+ * This file is licensed under  the terms of the GNU General Public 
+ * License version 2. This program is licensed "as is" without any 
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/sched.h>
+#include <linux/tty.h>
+#include <linux/serial_core.h>
+#include <linux/bootmem.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <linux/time.h>
+#include <linux/timex.h>
+
+#include <asm/hardware.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/irq.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+
+/*************************************************************************
+ * GPIO acces functions
+ *************************************************************************/
+
+/*
+ * Configure GPIO line for input, interrupt, or output operation
+ *
+ * TODO: Enable/disable the irq_desc based on interrupt or output mode.
+ * TODO: Should these be named ixp4xx_gpio_?
+ */
+void gpio_line_config(u8 line, u32 style)
+{
+	u32 enable;
+	volatile u32 *int_reg;
+	u32 int_style;
+
+	enable = *IXP4XX_GPIO_GPOER;
+
+	if (style & IXP4XX_GPIO_OUT) {
+		enable &= ~((1) << line);
+	} else if (style & IXP4XX_GPIO_IN) {
+		enable |= ((1) << line);
+
+		switch (style & IXP4XX_GPIO_INTSTYLE_MASK)
+		{
+		case (IXP4XX_GPIO_ACTIVE_HIGH):
+			int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
+			break;
+		case (IXP4XX_GPIO_ACTIVE_LOW):
+			int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
+			break;
+		case (IXP4XX_GPIO_RISING_EDGE):
+			int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
+			break;
+		case (IXP4XX_GPIO_FALLING_EDGE):
+			int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
+			break;
+		case (IXP4XX_GPIO_TRANSITIONAL):
+			int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
+			break;
+		default:
+			int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
+			break;
+		}
+
+		if (line >= 8) {	/* pins 8-15 */ 
+			line -= 8;
+			int_reg = IXP4XX_GPIO_GPIT2R;
+		}
+		else {			/* pins 0-7 */
+			int_reg = IXP4XX_GPIO_GPIT1R;
+		}
+
+		/* Clear the style for the appropriate pin */
+		*int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR << 
+		    		(line * IXP4XX_GPIO_STYLE_SIZE));
+
+		/* Set the new style */
+		*int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
+	}
+
+	*IXP4XX_GPIO_GPOER = enable;
+}
+
+EXPORT_SYMBOL(gpio_line_config);
+
+/*************************************************************************
+ * IXP4xx chipset I/O mapping
+ *************************************************************************/
+static struct map_desc ixp4xx_io_desc[] __initdata = {
+	{	/* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
+		.virtual	= IXP4XX_PERIPHERAL_BASE_VIRT,
+		.physical	= IXP4XX_PERIPHERAL_BASE_PHYS,
+		.length		= IXP4XX_PERIPHERAL_REGION_SIZE,
+		.type		= MT_DEVICE
+	}, {	/* Expansion Bus Config Registers */
+		.virtual	= IXP4XX_EXP_CFG_BASE_VIRT,
+		.physical	= IXP4XX_EXP_CFG_BASE_PHYS,
+		.length		= IXP4XX_EXP_CFG_REGION_SIZE,
+		.type		= MT_DEVICE
+	}, {	/* PCI Registers */
+		.virtual	= IXP4XX_PCI_CFG_BASE_VIRT,
+		.physical	= IXP4XX_PCI_CFG_BASE_PHYS,
+		.length		= IXP4XX_PCI_CFG_REGION_SIZE,
+		.type		= MT_DEVICE
+	}
+};
+
+void __init ixp4xx_map_io(void)
+{
+  	iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
+}
+
+
+/*************************************************************************
+ * IXP4xx chipset IRQ handling
+ *
+ * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
+ *       (be it PCI or something else) configures that GPIO line
+ *       as an IRQ. Also, we should use a different chip structure for 
+ *       level-based GPIO vs edge-based GPIO. Currently nobody needs this as 
+ *       all HW that's publically available uses level IRQs, so we'll
+ *       worry about it if/when we have HW to test.
+ **************************************************************************/
+static void ixp4xx_irq_mask(unsigned int irq)
+{
+	*IXP4XX_ICMR &= ~(1 << irq);
+}
+
+static void ixp4xx_irq_mask_ack(unsigned int irq)
+{
+	ixp4xx_irq_mask(irq);
+}
+
+static void ixp4xx_irq_unmask(unsigned int irq)
+{
+	static int irq2gpio[NR_IRQS] = {
+		-1, -1, -1, -1, -1, -1,  0,  1,
+		-1, -1, -1, -1, -1, -1, -1, -1,
+		-1, -1, -1,  2,  3,  4,  5,  6,
+		 7,  8,  9, 10, 11, 12, -1, -1,
+	};
+	int line = irq2gpio[irq];
+
+	/*
+	 * This only works for LEVEL gpio IRQs as per the IXP4xx developer's
+	 * manual. If edge-triggered, need to move it to the mask_ack.
+	 * Nobody seems to be using the edge-triggered mode on the GPIOs. 
+	 */
+	if (line > 0)
+		gpio_line_isr_clear(line);
+
+	*IXP4XX_ICMR |= (1 << irq);
+}
+
+static struct irqchip ixp4xx_irq_chip = {
+	.ack	= ixp4xx_irq_mask_ack,
+	.mask	= ixp4xx_irq_mask,
+	.unmask	= ixp4xx_irq_unmask,
+};
+
+void __init ixp4xx_init_irq(void)
+{
+	int i = 0;
+
+	/* Route all sources to IRQ instead of FIQ */
+	*IXP4XX_ICLR = 0x0;
+
+	/* Disable all interrupt */
+	*IXP4XX_ICMR = 0x0; 
+
+	for(i = 0; i < NR_IRQS; i++)
+	{
+		set_irq_chip(i, &ixp4xx_irq_chip);
+		set_irq_handler(i, do_level_IRQ);
+		set_irq_flags(i, IRQF_VALID);
+	}
+}
+
+
+/*************************************************************************
+ * IXP4xx timer tick
+ * We use OS timer1 on the CPU for the timer tick and the timestamp 
+ * counter as a source of real clock ticks to account for missed jiffies.
+ *************************************************************************/
+
+static unsigned volatile last_jiffy_time;
+
+#define CLOCK_TICKS_PER_USEC	(CLOCK_TICK_RATE / USEC_PER_SEC)
+
+/* IRQs are disabled before entering here from do_gettimeofday() */
+static unsigned long ixp4xx_gettimeoffset(void)
+{
+	u32 elapsed;
+
+	elapsed = *IXP4XX_OSTS - last_jiffy_time;
+
+	return elapsed / CLOCK_TICKS_PER_USEC;
+}
+
+static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	/* Clear Pending Interrupt by writing '1' to it */
+	*IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
+
+	/*
+	 * Catch up with the real idea of time
+	 */
+	do {	
+		do_timer(regs);
+		last_jiffy_time += LATCH;
+	} while((*IXP4XX_OSTS - last_jiffy_time) > LATCH);
+
+	return IRQ_HANDLED;
+}
+
+extern unsigned long (*gettimeoffset)(void);
+
+static struct irqaction timer_irq = {
+	.name	= "IXP4xx Timer Tick",
+	.flags	= SA_INTERRUPT
+};
+
+void __init time_init(void)
+{
+	gettimeoffset = ixp4xx_gettimeoffset;
+	timer_irq.handler = ixp4xx_timer_interrupt;
+
+	/* Clear Pending Interrupt by writing '1' to it */
+	*IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
+
+	/* Setup the Timer counter value */
+	*IXP4XX_OSRT1 = (LATCH & ~IXP4XX_OST_RELOAD_MASK) | IXP4XX_OST_ENABLE;
+
+	/* Reset time-stamp counter */
+	*IXP4XX_OSTS = 0;
+	last_jiffy_time = 0;
+
+	/* Connect the interrupt handler and enable the interrupt */
+	setup_irq(IRQ_IXP4XX_TIMER1, &timer_irq);
+}
+
+

arch/arm/mach-ixp4xx/coyote-setup.c

@@ -73,18 +73,11 @@ static struct platform_device coyote_flash_device = {
 	.resource	= &coyote_flash_resource,
 };
 
-static int __init coyote_init(void)
+static void __init coyote_init(void)
 {
-	if (!machine_is_adi_coyote())
-		return -ENODEV;
-
 	platform_add_device(&coyote_flash_device);
-
-	return 0;
 }
 
-arch_initcall(coyote_init);
-
 MACHINE_START(ADI_COYOTE, "ADI Engineering IXP4XX Coyote Development Platform")
         MAINTAINER("MontaVista Software, Inc.")
         BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS,
@@ -92,6 +85,6 @@ MACHINE_START(ADI_COYOTE, "ADI Engineering IXP4XX Coyote Development Platform")
         MAPIO(coyote_map_io)
         INITIRQ(ixp4xx_init_irq)
         BOOT_PARAMS(0x0100)
+	INIT_MACHINE(coyote_init)
 MACHINE_END
 
-

arch/arm/mach-ixp4xx/ixdp425-setup.c

@@ -101,21 +101,12 @@ static struct platform_device ixdp425_i2c_controller = {
 	.num_resources	= 0
 };
 
-static int __init ixdp425_init(void)
+static void __init ixdp425_init(void)
 {
-	if (!machine_is_ixdp425() 
-		&& !machine_is_ixcdp1100()
-		&& !machine_is_avila())
-		return -ENODEV;
-
 	platform_add_device(&ixdp425_flash_device);
 	platform_add_device(&ixdp425_i2c_controller);
-
-	return 0;
 }
 
-arch_initcall(ixdp425_init);
-
 MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
 	MAINTAINER("MontaVista Software, Inc.")
 	BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS,
@@ -123,6 +114,7 @@ MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
 	MAPIO(ixdp425_map_io)
 	INITIRQ(ixp4xx_init_irq)
 	BOOT_PARAMS(0x0100)
+	INIT_MACHINE(ixdp425_init)
 MACHINE_END
 
 MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
@@ -132,6 +124,7 @@ MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
 	MAPIO(ixdp425_map_io)
 	INITIRQ(ixp4xx_init_irq)
 	BOOT_PARAMS(0x0100)
+	INIT_MACHINE(ixdp425_init)
 MACHINE_END
 
 /*
@@ -148,6 +141,7 @@ MACHINE_START(AVILA, "Gateworks Avila Network Platform")
 	MAPIO(ixdp425_map_io)
 	INITIRQ(ixp4xx_init_irq)
 	BOOT_PARAMS(0x0100)
+	INIT_MACHINE(ixdp425_init)
 MACHINE_END
 #endif
 

arch/arm/mach-ixp4xx/prpmc1100-setup.c

@@ -73,18 +73,11 @@ static struct platform_device prpmc1100_flash_device = {
 	.resource	= &prpmc1100_flash_resource,
 };
 
-static int __init prpmc1100_init(void)
+static void __init prpmc1100_init(void)
 {
-	if (!machine_is_prpmc1100())
-		return -ENODEV;
-
 	platform_add_device(&prpmc1100_flash_device);
-
-	return 0;
 }
 
-arch_initcall(prpmc1100_init);
-
 MACHINE_START(PRPMC1100, "Motorola PrPMC1100")
         MAINTAINER("MontaVista Software, Inc.")
         BOOT_MEM(PHYS_OFFSET, IXP4XX_PERIPHERAL_BASE_PHYS,
@@ -92,5 +85,6 @@ MACHINE_START(PRPMC1100, "Motorola PrPMC1100")
         MAPIO(prpmc1100_map_io)
         INITIRQ(ixp4xx_init_irq)
         BOOT_PARAMS(0x0100)
+	INIT_MACHINE(prpmc1100_init)
 MACHINE_END