Commit 5640e06e authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher

drm/amdgpu: Move jpeg ras block init to ras sw_init

Initialize jpeg ras block only when jpeg ip block
supports ras features. Driver queries ras capabilities
after early_init, ras block init needs to be moved to
sw_int.
Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarStanley Yang <Stanley.Yang@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c69d5139
...@@ -236,19 +236,28 @@ int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev, ...@@ -236,19 +236,28 @@ int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev,
return 0; return 0;
} }
void jpeg_set_ras_funcs(struct amdgpu_device *adev) int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev)
{ {
int err;
struct amdgpu_jpeg_ras *ras;
if (!adev->jpeg.ras) if (!adev->jpeg.ras)
return; return 0;
amdgpu_ras_register_ras_block(adev, &adev->jpeg.ras->ras_block); ras = adev->jpeg.ras;
err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
if (err) {
dev_err(adev->dev, "Failed to register jpeg ras block!\n");
return err;
}
strcpy(adev->jpeg.ras->ras_block.ras_comm.name, "jpeg"); strcpy(ras->ras_block.ras_comm.name, "jpeg");
adev->jpeg.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG; ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG;
adev->jpeg.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON;
adev->jpeg.ras_if = &adev->jpeg.ras->ras_block.ras_comm; adev->jpeg.ras_if = &ras->ras_block.ras_comm;
/* If don't define special ras_late_init function, use default ras_late_init */ if (!ras->ras_block.ras_late_init)
if (!adev->jpeg.ras->ras_block.ras_late_init) ras->ras_block.ras_late_init = amdgpu_ras_block_late_init;
adev->jpeg.ras->ras_block.ras_late_init = amdgpu_ras_block_late_init;
return 0;
} }
...@@ -72,6 +72,6 @@ int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout); ...@@ -72,6 +72,6 @@ int amdgpu_jpeg_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout);
int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev, int amdgpu_jpeg_process_poison_irq(struct amdgpu_device *adev,
struct amdgpu_irq_src *source, struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry); struct amdgpu_iv_entry *entry);
void jpeg_set_ras_funcs(struct amdgpu_device *adev); int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev);
#endif /*__AMDGPU_JPEG_H__*/ #endif /*__AMDGPU_JPEG_H__*/
...@@ -138,6 +138,10 @@ static int jpeg_v2_5_sw_init(void *handle) ...@@ -138,6 +138,10 @@ static int jpeg_v2_5_sw_init(void *handle)
adev->jpeg.inst[i].external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_PITCH); adev->jpeg.inst[i].external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_PITCH);
} }
r = amdgpu_jpeg_ras_sw_init(adev);
if (r)
return r;
return 0; return 0;
} }
...@@ -806,6 +810,4 @@ static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev) ...@@ -806,6 +810,4 @@ static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev)
default: default:
break; break;
} }
jpeg_set_ras_funcs(adev);
} }
...@@ -113,6 +113,10 @@ static int jpeg_v4_0_sw_init(void *handle) ...@@ -113,6 +113,10 @@ static int jpeg_v4_0_sw_init(void *handle)
adev->jpeg.internal.jpeg_pitch = regUVD_JPEG_PITCH_INTERNAL_OFFSET; adev->jpeg.internal.jpeg_pitch = regUVD_JPEG_PITCH_INTERNAL_OFFSET;
adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH); adev->jpeg.inst->external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH);
r = amdgpu_jpeg_ras_sw_init(adev);
if (r)
return r;
return 0; return 0;
} }
...@@ -685,6 +689,4 @@ static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev) ...@@ -685,6 +689,4 @@ static void jpeg_v4_0_set_ras_funcs(struct amdgpu_device *adev)
default: default:
break; break;
} }
jpeg_set_ras_funcs(adev);
} }
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