Commit 5807bb4d authored by fred gao's avatar fred gao Committed by Zhenyu Wang

drm/i915/gvt: Refine port select logic for CFL platform

Refine the code since the port select definition for CFL is different
than SKL/BXT.

v2:
- replace PCH_CNP with IS_COFFEELAKE. (zhenyu)

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Reviewed-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: default avatarfred gao <fred.gao@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 360f864e
...@@ -77,6 +77,22 @@ static unsigned char edid_get_byte(struct intel_vgpu *vgpu) ...@@ -77,6 +77,22 @@ static unsigned char edid_get_byte(struct intel_vgpu *vgpu)
return chr; return chr;
} }
static inline int cnp_get_port_from_gmbus0(u32 gmbus0)
{
int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
int port = -EINVAL;
if (port_select == GMBUS_PIN_1_BXT)
port = PORT_B;
else if (port_select == GMBUS_PIN_2_BXT)
port = PORT_C;
else if (port_select == GMBUS_PIN_3_BXT)
port = PORT_D;
else if (port_select == GMBUS_PIN_4_CNP)
port = PORT_E;
return port;
}
static inline int bxt_get_port_from_gmbus0(u32 gmbus0) static inline int bxt_get_port_from_gmbus0(u32 gmbus0)
{ {
int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK; int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
...@@ -133,6 +149,8 @@ static int gmbus0_mmio_write(struct intel_vgpu *vgpu, ...@@ -133,6 +149,8 @@ static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
if (IS_BROXTON(dev_priv)) if (IS_BROXTON(dev_priv))
port = bxt_get_port_from_gmbus0(pin_select); port = bxt_get_port_from_gmbus0(pin_select);
else if (IS_COFFEELAKE(dev_priv))
port = cnp_get_port_from_gmbus0(pin_select);
else else
port = get_port_from_gmbus0(pin_select); port = get_port_from_gmbus0(pin_select);
if (WARN_ON(port < 0)) if (WARN_ON(port < 0))
......
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