Commit 5ae42de5 authored by YueHaibing's avatar YueHaibing Committed by David S. Miller

liquidio: remove redundant function cn23xx_dump_vf_iq_regs

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Signed-off-by: default avatarYueHaibing <yuehaibing@huawei.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d339377c
...@@ -682,33 +682,3 @@ int cn23xx_setup_octeon_vf_device(struct octeon_device *oct) ...@@ -682,33 +682,3 @@ int cn23xx_setup_octeon_vf_device(struct octeon_device *oct)
return 0; return 0;
} }
void cn23xx_dump_vf_iq_regs(struct octeon_device *oct)
{
u32 regval, q_no;
dev_dbg(&oct->pci_dev->dev, "SLI_IQ_DOORBELL_0 [0x%x]: 0x%016llx\n",
CN23XX_VF_SLI_IQ_DOORBELL(0),
CVM_CAST64(octeon_read_csr64(
oct, CN23XX_VF_SLI_IQ_DOORBELL(0))));
dev_dbg(&oct->pci_dev->dev, "SLI_IQ_BASEADDR_0 [0x%x]: 0x%016llx\n",
CN23XX_VF_SLI_IQ_BASE_ADDR64(0),
CVM_CAST64(octeon_read_csr64(
oct, CN23XX_VF_SLI_IQ_BASE_ADDR64(0))));
dev_dbg(&oct->pci_dev->dev, "SLI_IQ_FIFO_RSIZE_0 [0x%x]: 0x%016llx\n",
CN23XX_VF_SLI_IQ_SIZE(0),
CVM_CAST64(octeon_read_csr64(oct, CN23XX_VF_SLI_IQ_SIZE(0))));
for (q_no = 0; q_no < oct->sriov_info.rings_per_vf; q_no++) {
dev_dbg(&oct->pci_dev->dev, "SLI_PKT[%d]_INPUT_CTL [0x%x]: 0x%016llx\n",
q_no, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no),
CVM_CAST64(octeon_read_csr64(
oct, CN23XX_VF_SLI_IQ_PKT_CONTROL64(q_no))));
}
pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, &regval);
dev_dbg(&oct->pci_dev->dev, "Config DevCtl [0x%x]: 0x%08x\n",
CN23XX_CONFIG_PCIE_DEVCTL, regval);
}
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