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Commit 5ccf1978 authored by Tony Lindgren's avatar Tony Lindgren
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Merge branch 'for-next' into omap-for-linus

parents 24ed45aa 435bb827
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Showing with 8195 additions and 1517 deletions
Documentation/kernel-parameters.txt
View file @ 5ccf1978
......@@ -1787,6 +1787,11 @@ and is between 256 and 4096 characters. It is defined in the file
waiting for the ACK, so if this is set too high
interrupts *may* be lost!
omap_mux= [OMAP] Override bootloader pin multiplexing.
Format: <mux_mode0.mode_name=value>...
For example, to override I2C bus2:
omap_mux=i2c2_scl.i2c2_scl=0x100,i2c2_sda.i2c2_sda=0x100
opl3= [HW,OSS]
Format: <io>
......
arch/arm/configs/htcherald_defconfig
View file @ 5ccf1978
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.32-rc6
# Sat Nov 14 10:56:01 2009
# Linux kernel version: 2.6.32-rc8
# Sat Dec 5 12:16:24 2009
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
......@@ -198,7 +198,9 @@ CONFIG_ARCH_OMAP1=y
# OMAP Feature Selections
#
# CONFIG_OMAP_RESET_CLOCKS is not set
# CONFIG_OMAP_MUX is not set
CONFIG_OMAP_MUX=y
# CONFIG_OMAP_MUX_DEBUG is not set
CONFIG_OMAP_MUX_WARNINGS=y
CONFIG_OMAP_MCBSP=y
# CONFIG_OMAP_MBOX_FWK is not set
CONFIG_OMAP_MPU_TIMER=y
......@@ -207,6 +209,7 @@ CONFIG_OMAP_LL_DEBUG_UART1=y
# CONFIG_OMAP_LL_DEBUG_UART2 is not set
# CONFIG_OMAP_LL_DEBUG_UART3 is not set
# CONFIG_OMAP_LL_DEBUG_NONE is not set
CONFIG_OMAP_SERIAL_WAKE=y
# CONFIG_OMAP_PM_NONE is not set
CONFIG_OMAP_PM_NOOP=y
......
arch/arm/configs/omap3_touchbook_defconfig 0 → 100644
View file @ 5ccf1978
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.32-rc8
# Fri Dec 4 16:02:17 2009
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_ARCH_HAS_CPUFREQ=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_OPROFILE_ARMV7=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_CONSTRUCTORS=y
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_LOCK_KERNEL=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
CONFIG_BSD_PROCESS_ACCT=y
# CONFIG_BSD_PROCESS_ACCT_V3 is not set
CONFIG_TASKSTATS=y
CONFIG_TASK_DELAY_ACCT=y
CONFIG_TASK_XACCT=y
CONFIG_TASK_IO_ACCOUNTING=y
# CONFIG_AUDIT is not set
#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
# CONFIG_TREE_PREEMPT_RCU is not set
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_FANOUT=32
# CONFIG_RCU_FANOUT_EXACT is not set
# CONFIG_TREE_RCU_TRACE is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=15
CONFIG_GROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
# CONFIG_RT_GROUP_SCHED is not set
CONFIG_USER_SCHED=y
# CONFIG_CGROUP_SCHED is not set
# CONFIG_CGROUPS is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
CONFIG_BLK_DEV_INITRD=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_RD_GZIP=y
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_LZMA is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
# CONFIG_ELF_CORE is not set
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
#
# Kernel Performance Events And Counters
#
CONFIG_VM_EVENT_COUNTERS=y
# CONFIG_COMPAT_BRK is not set
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
CONFIG_PROFILING=y
CONFIG_TRACEPOINTS=y
CONFIG_OPROFILE=y
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_CLK=y
#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_SLOW_WORK=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_BLOCK=y
CONFIG_LBDAF=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
# CONFIG_DEFAULT_AS is not set
# CONFIG_DEFAULT_DEADLINE is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
CONFIG_FREEZER=y
#
# System Type
#
CONFIG_MMU=y
# CONFIG_ARCH_AAEC2000 is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_GEMINI is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_STMP3XXX is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_NOMADIK is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_KIRKWOOD is not set
# CONFIG_ARCH_LOKI is not set
# CONFIG_ARCH_MV78XX0 is not set
# CONFIG_ARCH_ORION5X is not set
# CONFIG_ARCH_MMP is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_W90X900 is not set
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_MSM is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_S3C64XX is not set
# CONFIG_ARCH_S5PC1XX is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_U300 is not set
# CONFIG_ARCH_DAVINCI is not set
CONFIG_ARCH_OMAP=y
# CONFIG_ARCH_BCMRING is not set
#
# TI OMAP Implementations
#
CONFIG_ARCH_OMAP_OTG=y
# CONFIG_ARCH_OMAP1 is not set
# CONFIG_ARCH_OMAP2 is not set
CONFIG_ARCH_OMAP3=y
# CONFIG_ARCH_OMAP4 is not set
#
# OMAP Feature Selections
#
# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
CONFIG_OMAP_RESET_CLOCKS=y
# CONFIG_OMAP_MUX is not set
CONFIG_OMAP_MCBSP=y
# CONFIG_OMAP_MBOX_FWK is not set
# CONFIG_OMAP_MPU_TIMER is not set
CONFIG_OMAP_32K_TIMER=y
CONFIG_OMAP_32K_TIMER_HZ=128
CONFIG_OMAP_DM_TIMER=y
# CONFIG_OMAP_LL_DEBUG_UART1 is not set
# CONFIG_OMAP_LL_DEBUG_UART2 is not set
CONFIG_OMAP_LL_DEBUG_UART3=y
# CONFIG_OMAP_LL_DEBUG_NONE is not set
# CONFIG_OMAP_PM_NONE is not set
CONFIG_OMAP_PM_NOOP=y
CONFIG_ARCH_OMAP34XX=y
CONFIG_ARCH_OMAP3430=y
#
# OMAP Board Type
#
# CONFIG_MACH_OMAP3_BEAGLE is not set
# CONFIG_MACH_OMAP_LDP is not set
# CONFIG_MACH_OVERO is not set
# CONFIG_MACH_OMAP3EVM is not set
# CONFIG_MACH_OMAP3517EVM is not set
# CONFIG_MACH_OMAP3_PANDORA is not set
CONFIG_MACH_OMAP3_TOUCHBOOK=y
# CONFIG_MACH_OMAP_3430SDP is not set
# CONFIG_MACH_NOKIA_RX51 is not set
# CONFIG_MACH_OMAP_ZOOM2 is not set
# CONFIG_MACH_OMAP_ZOOM3 is not set
# CONFIG_MACH_CM_T35 is not set
# CONFIG_MACH_IGEP0020 is not set
# CONFIG_MACH_OMAP_3630SDP is not set
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_V7=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
#
# Processor Features
#
CONFIG_ARM_THUMB=y
CONFIG_ARM_THUMBEE=y
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
CONFIG_HAS_TLS_REG=y
CONFIG_ARM_L1_CACHE_SHIFT=6
# CONFIG_ARM_ERRATA_430973 is not set
# CONFIG_ARM_ERRATA_458693 is not set
# CONFIG_ARM_ERRATA_460075 is not set
CONFIG_COMMON_CLKDEV=y
#
# Bus support
#
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set
#
# Kernel Features
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_VMSPLIT_3G=y
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xC0000000
# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_HZ=128
# CONFIG_THUMB2_KERNEL is not set
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
# CONFIG_HIGHMEM is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_VIRT_TO_BUS=y
CONFIG_HAVE_MLOCK=y
CONFIG_HAVE_MLOCKED_PAGE_BIT=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_LEDS=y
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_UACCESS_WITH_MEMCPY is not set
#
# Boot options
#
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE=" debug "
# CONFIG_XIP_KERNEL is not set
CONFIG_KEXEC=y
CONFIG_ATAGS_PROC=y
#
# CPU Power Management
#
# CONFIG_CPU_FREQ is not set
# CONFIG_CPU_IDLE is not set
#
# Floating point emulation
#
#
# At least one emulation must be selected
#
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_NEON=y
#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
CONFIG_HAVE_AOUT=y
CONFIG_BINFMT_AOUT=m
CONFIG_BINFMT_MISC=y
#
# Power management options
#
CONFIG_PM=y
CONFIG_PM_DEBUG=y
# CONFIG_PM_VERBOSE is not set
CONFIG_CAN_PM_TRACE=y
CONFIG_PM_SLEEP=y
CONFIG_SUSPEND=y
# CONFIG_PM_TEST_SUSPEND is not set
CONFIG_SUSPEND_FREEZER=y
# CONFIG_APM_EMULATION is not set
# CONFIG_PM_RUNTIME is not set
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
CONFIG_PACKET_MMAP=y
CONFIG_UNIX=y
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_XFRM_STATISTICS is not set
CONFIG_XFRM_IPCOMP=m
CONFIG_NET_KEY=y
# CONFIG_NET_KEY_MIGRATE is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPIP=m
CONFIG_NET_IPGRE=m
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
CONFIG_INET_AH=m
CONFIG_INET_ESP=m
CONFIG_INET_IPCOMP=m
CONFIG_INET_XFRM_TUNNEL=m
CONFIG_INET_TUNNEL=m
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
CONFIG_INET_LRO=y
CONFIG_INET_DIAG=m
CONFIG_INET_TCP_DIAG=m
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_TCP_CONG_BIC=m
CONFIG_TCP_CONG_CUBIC=y
CONFIG_TCP_CONG_WESTWOOD=m
CONFIG_TCP_CONG_HTCP=m
CONFIG_TCP_CONG_HSTCP=m
CONFIG_TCP_CONG_HYBLA=m
CONFIG_TCP_CONG_VEGAS=m
CONFIG_TCP_CONG_SCALABLE=m
CONFIG_TCP_CONG_LP=m
CONFIG_TCP_CONG_VENO=m
CONFIG_TCP_CONG_YEAH=m
CONFIG_TCP_CONG_ILLINOIS=m
# CONFIG_DEFAULT_BIC is not set
CONFIG_DEFAULT_CUBIC=y
# CONFIG_DEFAULT_HTCP is not set
# CONFIG_DEFAULT_VEGAS is not set
# CONFIG_DEFAULT_WESTWOOD is not set
# CONFIG_DEFAULT_RENO is not set
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
CONFIG_IPV6=m
# CONFIG_IPV6_PRIVACY is not set
# CONFIG_IPV6_ROUTER_PREF is not set
# CONFIG_IPV6_OPTIMISTIC_DAD is not set
CONFIG_INET6_AH=m
CONFIG_INET6_ESP=m
CONFIG_INET6_IPCOMP=m
CONFIG_IPV6_MIP6=m
CONFIG_INET6_XFRM_TUNNEL=m
CONFIG_INET6_TUNNEL=m
CONFIG_INET6_XFRM_MODE_TRANSPORT=m
CONFIG_INET6_XFRM_MODE_TUNNEL=m
CONFIG_INET6_XFRM_MODE_BEET=m
CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
CONFIG_IPV6_SIT=m
CONFIG_IPV6_NDISC_NODETYPE=y
CONFIG_IPV6_TUNNEL=m
CONFIG_IPV6_MULTIPLE_TABLES=y
CONFIG_IPV6_SUBTREES=y
CONFIG_IPV6_MROUTE=y
# CONFIG_IPV6_PIMSM_V2 is not set
# CONFIG_NETWORK_SECMARK is not set
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_DEBUG is not set
CONFIG_NETFILTER_ADVANCED=y
CONFIG_BRIDGE_NETFILTER=y
#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_NETLINK=m
CONFIG_NETFILTER_NETLINK_QUEUE=m
CONFIG_NETFILTER_NETLINK_LOG=m
CONFIG_NF_CONNTRACK=m
CONFIG_NF_CT_ACCT=y
CONFIG_NF_CONNTRACK_MARK=y
CONFIG_NF_CONNTRACK_EVENTS=y
CONFIG_NF_CT_PROTO_DCCP=m
CONFIG_NF_CT_PROTO_GRE=m
CONFIG_NF_CT_PROTO_SCTP=m
CONFIG_NF_CT_PROTO_UDPLITE=m
CONFIG_NF_CONNTRACK_AMANDA=m
CONFIG_NF_CONNTRACK_FTP=m
CONFIG_NF_CONNTRACK_H323=m
CONFIG_NF_CONNTRACK_IRC=m
CONFIG_NF_CONNTRACK_NETBIOS_NS=m
CONFIG_NF_CONNTRACK_PPTP=m
CONFIG_NF_CONNTRACK_SANE=m
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=m
CONFIG_NF_CT_NETLINK=m
# CONFIG_NETFILTER_TPROXY is not set
CONFIG_NETFILTER_XTABLES=m
CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
CONFIG_NETFILTER_XT_TARGET_HL=m
# CONFIG_NETFILTER_XT_TARGET_LED is not set
CONFIG_NETFILTER_XT_TARGET_MARK=m
CONFIG_NETFILTER_XT_TARGET_NFLOG=m
CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
CONFIG_NETFILTER_XT_TARGET_RATEEST=m
# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
CONFIG_NETFILTER_XT_MATCH_COMMENT=m
CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_DCCP=m
CONFIG_NETFILTER_XT_MATCH_DSCP=m
CONFIG_NETFILTER_XT_MATCH_ESP=m
CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
CONFIG_NETFILTER_XT_MATCH_HELPER=m
CONFIG_NETFILTER_XT_MATCH_HL=m
CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
CONFIG_NETFILTER_XT_MATCH_LENGTH=m
CONFIG_NETFILTER_XT_MATCH_LIMIT=m
CONFIG_NETFILTER_XT_MATCH_MAC=m
CONFIG_NETFILTER_XT_MATCH_MARK=m
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
CONFIG_NETFILTER_XT_MATCH_OWNER=m
CONFIG_NETFILTER_XT_MATCH_POLICY=m
# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
CONFIG_NETFILTER_XT_MATCH_QUOTA=m
CONFIG_NETFILTER_XT_MATCH_RATEEST=m
CONFIG_NETFILTER_XT_MATCH_REALM=m
CONFIG_NETFILTER_XT_MATCH_RECENT=m
# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set
CONFIG_NETFILTER_XT_MATCH_SCTP=m
CONFIG_NETFILTER_XT_MATCH_STATE=m
CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
CONFIG_NETFILTER_XT_MATCH_STRING=m
CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
CONFIG_NETFILTER_XT_MATCH_TIME=m
CONFIG_NETFILTER_XT_MATCH_U32=m
# CONFIG_NETFILTER_XT_MATCH_OSF is not set
CONFIG_IP_VS=m
CONFIG_IP_VS_IPV6=y
CONFIG_IP_VS_DEBUG=y
CONFIG_IP_VS_TAB_BITS=12
#
# IPVS transport protocol load balancing support
#
CONFIG_IP_VS_PROTO_TCP=y
CONFIG_IP_VS_PROTO_UDP=y
CONFIG_IP_VS_PROTO_AH_ESP=y
CONFIG_IP_VS_PROTO_ESP=y
CONFIG_IP_VS_PROTO_AH=y
#
# IPVS scheduler
#
CONFIG_IP_VS_RR=m
CONFIG_IP_VS_WRR=m
CONFIG_IP_VS_LC=m
CONFIG_IP_VS_WLC=m
CONFIG_IP_VS_LBLC=m
CONFIG_IP_VS_LBLCR=m
CONFIG_IP_VS_DH=m
CONFIG_IP_VS_SH=m
CONFIG_IP_VS_SED=m
CONFIG_IP_VS_NQ=m
#
# IPVS application helper
#
CONFIG_IP_VS_FTP=m
#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=m
CONFIG_NF_CONNTRACK_IPV4=m
CONFIG_NF_CONNTRACK_PROC_COMPAT=y
CONFIG_IP_NF_QUEUE=m
CONFIG_IP_NF_IPTABLES=m
CONFIG_IP_NF_MATCH_ADDRTYPE=m
CONFIG_IP_NF_MATCH_AH=m
CONFIG_IP_NF_MATCH_ECN=m
CONFIG_IP_NF_MATCH_TTL=m
CONFIG_IP_NF_FILTER=m
CONFIG_IP_NF_TARGET_REJECT=m
CONFIG_IP_NF_TARGET_LOG=m
CONFIG_IP_NF_TARGET_ULOG=m
CONFIG_NF_NAT=m
CONFIG_NF_NAT_NEEDED=y
CONFIG_IP_NF_TARGET_MASQUERADE=m
CONFIG_IP_NF_TARGET_NETMAP=m
CONFIG_IP_NF_TARGET_REDIRECT=m
CONFIG_NF_NAT_SNMP_BASIC=m
CONFIG_NF_NAT_PROTO_DCCP=m
CONFIG_NF_NAT_PROTO_GRE=m
CONFIG_NF_NAT_PROTO_UDPLITE=m
CONFIG_NF_NAT_PROTO_SCTP=m
CONFIG_NF_NAT_FTP=m
CONFIG_NF_NAT_IRC=m
CONFIG_NF_NAT_TFTP=m
CONFIG_NF_NAT_AMANDA=m
CONFIG_NF_NAT_PPTP=m
CONFIG_NF_NAT_H323=m
CONFIG_NF_NAT_SIP=m
CONFIG_IP_NF_MANGLE=m
CONFIG_IP_NF_TARGET_CLUSTERIP=m
CONFIG_IP_NF_TARGET_ECN=m
CONFIG_IP_NF_TARGET_TTL=m
CONFIG_IP_NF_RAW=m
CONFIG_IP_NF_ARPTABLES=m
CONFIG_IP_NF_ARPFILTER=m
CONFIG_IP_NF_ARP_MANGLE=m
#
# IPv6: Netfilter Configuration
#
CONFIG_NF_CONNTRACK_IPV6=m
CONFIG_IP6_NF_QUEUE=m
CONFIG_IP6_NF_IPTABLES=m
CONFIG_IP6_NF_MATCH_AH=m
CONFIG_IP6_NF_MATCH_EUI64=m
CONFIG_IP6_NF_MATCH_FRAG=m
CONFIG_IP6_NF_MATCH_OPTS=m
CONFIG_IP6_NF_MATCH_HL=m
CONFIG_IP6_NF_MATCH_IPV6HEADER=m
CONFIG_IP6_NF_MATCH_MH=m
CONFIG_IP6_NF_MATCH_RT=m
CONFIG_IP6_NF_TARGET_HL=m
CONFIG_IP6_NF_TARGET_LOG=m
CONFIG_IP6_NF_FILTER=m
CONFIG_IP6_NF_TARGET_REJECT=m
CONFIG_IP6_NF_MANGLE=m
CONFIG_IP6_NF_RAW=m
# CONFIG_BRIDGE_NF_EBTABLES is not set
CONFIG_IP_DCCP=m
CONFIG_INET_DCCP_DIAG=m
#
# DCCP CCIDs Configuration (EXPERIMENTAL)
#
# CONFIG_IP_DCCP_CCID2_DEBUG is not set
CONFIG_IP_DCCP_CCID3=y
# CONFIG_IP_DCCP_CCID3_DEBUG is not set
CONFIG_IP_DCCP_CCID3_RTO=100
CONFIG_IP_DCCP_TFRC_LIB=y
#
# DCCP Kernel Hacking
#
# CONFIG_IP_DCCP_DEBUG is not set
CONFIG_IP_SCTP=m
# CONFIG_SCTP_DBG_MSG is not set
# CONFIG_SCTP_DBG_OBJCNT is not set
# CONFIG_SCTP_HMAC_NONE is not set
# CONFIG_SCTP_HMAC_SHA1 is not set
CONFIG_SCTP_HMAC_MD5=y
# CONFIG_RDS is not set
CONFIG_TIPC=m
# CONFIG_TIPC_ADVANCED is not set
# CONFIG_TIPC_DEBUG is not set
CONFIG_ATM=m
CONFIG_ATM_CLIP=m
# CONFIG_ATM_CLIP_NO_ICMP is not set
CONFIG_ATM_LANE=m
CONFIG_ATM_MPOA=m
CONFIG_ATM_BR2684=m
# CONFIG_ATM_BR2684_IPFILTER is not set
CONFIG_STP=m
CONFIG_GARP=m
CONFIG_BRIDGE=m
# CONFIG_NET_DSA is not set
CONFIG_VLAN_8021Q=m
CONFIG_VLAN_8021Q_GVRP=y
# CONFIG_DECNET is not set
CONFIG_LLC=m
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
CONFIG_WAN_ROUTER=m
# CONFIG_PHONET is not set
# CONFIG_IEEE802154 is not set
CONFIG_NET_SCHED=y
#
# Queueing/Scheduling
#
CONFIG_NET_SCH_CBQ=m
CONFIG_NET_SCH_HTB=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_ATM=m
CONFIG_NET_SCH_PRIO=m
CONFIG_NET_SCH_MULTIQ=m
CONFIG_NET_SCH_RED=m
CONFIG_NET_SCH_SFQ=m
CONFIG_NET_SCH_TEQL=m
CONFIG_NET_SCH_TBF=m
CONFIG_NET_SCH_GRED=m
CONFIG_NET_SCH_DSMARK=m
CONFIG_NET_SCH_NETEM=m
CONFIG_NET_SCH_DRR=m
#
# Classification
#
CONFIG_NET_CLS=y
CONFIG_NET_CLS_BASIC=m
CONFIG_NET_CLS_TCINDEX=m
CONFIG_NET_CLS_ROUTE4=m
CONFIG_NET_CLS_ROUTE=y
CONFIG_NET_CLS_FW=m
CONFIG_NET_CLS_U32=m
CONFIG_CLS_U32_PERF=y
CONFIG_CLS_U32_MARK=y
CONFIG_NET_CLS_RSVP=m
CONFIG_NET_CLS_RSVP6=m
CONFIG_NET_CLS_FLOW=m
# CONFIG_NET_EMATCH is not set
# CONFIG_NET_CLS_ACT is not set
CONFIG_NET_CLS_IND=y
CONFIG_NET_SCH_FIFO=y
# CONFIG_DCB is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_NET_DROP_MONITOR is not set
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
CONFIG_BT=y
CONFIG_BT_L2CAP=y
CONFIG_BT_SCO=y
CONFIG_BT_RFCOMM=y
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=y
CONFIG_BT_BNEP_MC_FILTER=y
CONFIG_BT_BNEP_PROTO_FILTER=y
CONFIG_BT_HIDP=y
#
# Bluetooth device drivers
#
CONFIG_BT_HCIBTUSB=y
CONFIG_BT_HCIBTSDIO=y
CONFIG_BT_HCIUART=y
CONFIG_BT_HCIUART_H4=y
CONFIG_BT_HCIUART_BCSP=y
CONFIG_BT_HCIUART_LL=y
CONFIG_BT_HCIBCM203X=y
CONFIG_BT_HCIBPA10X=y
CONFIG_BT_HCIBFUSB=y
# CONFIG_BT_HCIVHCI is not set
# CONFIG_BT_MRVL is not set
CONFIG_AF_RXRPC=m
# CONFIG_AF_RXRPC_DEBUG is not set
# CONFIG_RXKAD is not set
CONFIG_FIB_RULES=y
CONFIG_WIRELESS=y
CONFIG_CFG80211=m
# CONFIG_NL80211_TESTMODE is not set
# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
# CONFIG_CFG80211_REG_DEBUG is not set
CONFIG_CFG80211_DEFAULT_PS=y
CONFIG_CFG80211_DEFAULT_PS_VALUE=1
# CONFIG_CFG80211_DEBUGFS is not set
# CONFIG_WIRELESS_OLD_REGULATORY is not set
CONFIG_WIRELESS_EXT=y
CONFIG_WIRELESS_EXT_SYSFS=y
CONFIG_LIB80211=y
# CONFIG_LIB80211_DEBUG is not set
CONFIG_MAC80211=m
CONFIG_MAC80211_RC_PID=y
# CONFIG_MAC80211_RC_MINSTREL is not set
CONFIG_MAC80211_RC_DEFAULT_PID=y
# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
CONFIG_MAC80211_RC_DEFAULT="pid"
# CONFIG_MAC80211_MESH is not set
# CONFIG_MAC80211_LEDS is not set
# CONFIG_MAC80211_DEBUGFS is not set
# CONFIG_MAC80211_DEBUG_MENU is not set
CONFIG_WIMAX=m
CONFIG_WIMAX_DEBUG_LEVEL=8
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_DEVTMPFS is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_DEBUG_DRIVER is not set
# CONFIG_DEBUG_DEVRES is not set
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_TESTS is not set
CONFIG_MTD_CONCAT=y
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
# CONFIG_MTD_AFS_PARTS is not set
# CONFIG_MTD_AR7_PARTS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_M25P80 is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
CONFIG_MTD_NAND=y
# CONFIG_MTD_NAND_VERIFY_WRITE is not set
# CONFIG_MTD_NAND_ECC_SMC is not set
# CONFIG_MTD_NAND_MUSEUM_IDS is not set
# CONFIG_MTD_NAND_GPIO is not set
CONFIG_MTD_NAND_OMAP2=y
CONFIG_MTD_NAND_OMAP_PREFETCH=y
# CONFIG_MTD_NAND_OMAP_PREFETCH_DMA is not set
CONFIG_MTD_NAND_IDS=y
# CONFIG_MTD_NAND_DISKONCHIP is not set
# CONFIG_MTD_NAND_NANDSIM is not set
CONFIG_MTD_NAND_PLATFORM=y
# CONFIG_MTD_ALAUDA is not set
# CONFIG_MTD_ONENAND is not set
#
# LPDDR flash memory drivers
#
# CONFIG_MTD_LPDDR is not set
#
# UBI - Unsorted block images
#
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_RESERVE=1
# CONFIG_MTD_UBI_GLUEBI is not set
#
# UBI debugging options
#
# CONFIG_MTD_UBI_DEBUG is not set
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_CRYPTOLOOP=m
# CONFIG_BLK_DEV_NBD is not set
# CONFIG_BLK_DEV_UB is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=16384
# CONFIG_BLK_DEV_XIP is not set
CONFIG_CDROM_PKTCDVD=m
CONFIG_CDROM_PKTCDVD_BUFFERS=8
# CONFIG_CDROM_PKTCDVD_WCACHE is not set
# CONFIG_ATA_OVER_ETH is not set
# CONFIG_MG_DISK is not set
CONFIG_MISC_DEVICES=y
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_ISL29003 is not set
# CONFIG_C2PORT is not set
#
# EEPROM support
#
# CONFIG_EEPROM_AT24 is not set
# CONFIG_EEPROM_AT25 is not set
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
CONFIG_EEPROM_93CX6=y
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
#
# SCSI device support
#
CONFIG_RAID_ATTRS=m
CONFIG_SCSI=y
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
CONFIG_SCSI_PROC_FS=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
CONFIG_BLK_DEV_SR=y
CONFIG_BLK_DEV_SR_VENDOR=y
CONFIG_CHR_DEV_SG=y
CONFIG_CHR_DEV_SCH=m
CONFIG_SCSI_MULTI_LUN=y
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
CONFIG_SCSI_WAIT_SCAN=m
#
# SCSI Transports
#
# CONFIG_SCSI_SPI_ATTRS is not set
# CONFIG_SCSI_FC_ATTRS is not set
CONFIG_SCSI_ISCSI_ATTRS=m
# CONFIG_SCSI_SAS_LIBSAS is not set
# CONFIG_SCSI_SRP_ATTRS is not set
CONFIG_SCSI_LOWLEVEL=y
CONFIG_ISCSI_TCP=m
# CONFIG_LIBFC is not set
# CONFIG_LIBFCOE is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_DH is not set
# CONFIG_SCSI_OSD_INITIATOR is not set
# CONFIG_ATA is not set
CONFIG_MD=y
CONFIG_BLK_DEV_MD=m
CONFIG_MD_LINEAR=m
CONFIG_MD_RAID0=m
CONFIG_MD_RAID1=m
CONFIG_MD_RAID10=m
CONFIG_MD_RAID456=m
CONFIG_MD_RAID6_PQ=m
# CONFIG_ASYNC_RAID6_TEST is not set
CONFIG_MD_MULTIPATH=m
CONFIG_MD_FAULTY=m
CONFIG_BLK_DEV_DM=m
# CONFIG_DM_DEBUG is not set
CONFIG_DM_CRYPT=m
CONFIG_DM_SNAPSHOT=m
CONFIG_DM_MIRROR=m
# CONFIG_DM_LOG_USERSPACE is not set
CONFIG_DM_ZERO=m
CONFIG_DM_MULTIPATH=m
# CONFIG_DM_MULTIPATH_QL is not set
# CONFIG_DM_MULTIPATH_ST is not set
CONFIG_DM_DELAY=m
# CONFIG_DM_UEVENT is not set
CONFIG_NETDEVICES=y
CONFIG_DUMMY=m
CONFIG_BONDING=m
CONFIG_MACVLAN=m
CONFIG_EQUALIZER=m
CONFIG_TUN=m
CONFIG_VETH=m
# CONFIG_NET_ETHERNET is not set
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
CONFIG_WLAN=y
# CONFIG_WLAN_PRE80211 is not set
CONFIG_WLAN_80211=y
# CONFIG_LIBERTAS is not set
# CONFIG_LIBERTAS_THINFIRM is not set
# CONFIG_AT76C50X_USB is not set
# CONFIG_USB_ZD1201 is not set
# CONFIG_USB_NET_RNDIS_WLAN is not set
# CONFIG_RTL8187 is not set
# CONFIG_MAC80211_HWSIM is not set
# CONFIG_P54_COMMON is not set
# CONFIG_ATH_COMMON is not set
# CONFIG_HOSTAP is not set
# CONFIG_B43 is not set
# CONFIG_B43LEGACY is not set
# CONFIG_ZD1211RW is not set
# CONFIG_RT2X00 is not set
# CONFIG_WL12XX is not set
# CONFIG_IWM is not set
#
# WiMAX Wireless Broadband devices
#
# CONFIG_WIMAX_I2400M_USB is not set
# CONFIG_WIMAX_I2400M_SDIO is not set
#
# USB Network Adapters
#
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET is not set
# CONFIG_WAN is not set
# CONFIG_ATM_DRIVERS is not set
CONFIG_PPP=m
CONFIG_PPP_MULTILINK=y
CONFIG_PPP_FILTER=y
CONFIG_PPP_ASYNC=m
CONFIG_PPP_SYNC_TTY=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_MPPE=m
CONFIG_PPPOE=m
# CONFIG_PPPOATM is not set
CONFIG_PPPOL2TP=m
# CONFIG_SLIP is not set
CONFIG_SLHC=m
CONFIG_NETCONSOLE=m
CONFIG_NETCONSOLE_DYNAMIC=y
CONFIG_NETPOLL=y
CONFIG_NETPOLL_TRAP=y
CONFIG_NET_POLL_CONTROLLER=y
# CONFIG_ISDN is not set
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
CONFIG_INPUT_FF_MEMLESS=y
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_QT2160 is not set
# CONFIG_KEYBOARD_LKKBD is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_LM8323 is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_TWL4030 is not set
# CONFIG_KEYBOARD_XTKBD is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
# CONFIG_MOUSE_PS2_SENTELIC is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_APPLETOUCH is not set
# CONFIG_MOUSE_BCM5974 is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_MOUSE_GPIO is not set
# CONFIG_MOUSE_SYNAPTICS_I2C is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y
# CONFIG_TOUCHSCREEN_AD7877 is not set
# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
# CONFIG_TOUCHSCREEN_MCS5000 is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_INEXIO is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TSC2007 is not set
# CONFIG_TOUCHSCREEN_W90X900 is not set
CONFIG_INPUT_MISC=y
# CONFIG_INPUT_ATI_REMOTE is not set
# CONFIG_INPUT_ATI_REMOTE2 is not set
# CONFIG_INPUT_KEYSPAN_REMOTE is not set
# CONFIG_INPUT_POWERMATE is not set
# CONFIG_INPUT_YEALINK is not set
# CONFIG_INPUT_CM109 is not set
CONFIG_INPUT_TWL4030_PWRBUTTON=y
CONFIG_INPUT_UINPUT=y
# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=y
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_DEVKMEM=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=32
CONFIG_SERIAL_8250_RUNTIME_UARTS=4
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_MANY_PORTS=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_DETECT_IRQ=y
CONFIG_SERIAL_8250_RSA=y
#
# Non-8250 serial port support
#
# CONFIG_SERIAL_MAX3100 is not set
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
# CONFIG_LEGACY_PTYS is not set
# CONFIG_IPMI_HANDLER is not set
CONFIG_HW_RANDOM=y
# CONFIG_HW_RANDOM_TIMERIOMEM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_COMPAT=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_HELPER_AUTO=y
#
# I2C Hardware Bus support
#
#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_DESIGNWARE is not set
# CONFIG_I2C_GPIO is not set
# CONFIG_I2C_OCORES is not set
CONFIG_I2C_OMAP=y
# CONFIG_I2C_SIMTEC is not set
#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set
#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_STUB is not set
#
# Miscellaneous I2C Chip support
#
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_I2C_DEBUG_CHIP is not set
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
#
# SPI Master Controller Drivers
#
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_GPIO is not set
CONFIG_SPI_OMAP24XX=y
#
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=y
# CONFIG_SPI_TLE62X0 is not set
#
# PPS support
#
# CONFIG_PPS is not set
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
CONFIG_GPIO_SYSFS=y
#
# Memory mapped GPIO expanders:
#
#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCA953X is not set
# CONFIG_GPIO_PCF857X is not set
CONFIG_GPIO_TWL4030=y
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MCP23S08 is not set
# CONFIG_GPIO_MC33880 is not set
#
# AC97 GPIO expanders:
#
# CONFIG_W1 is not set
CONFIG_POWER_SUPPLY=y
# CONFIG_POWER_SUPPLY_DEBUG is not set
# CONFIG_PDA_POWER is not set
# CONFIG_BATTERY_DS2760 is not set
# CONFIG_BATTERY_DS2782 is not set
CONFIG_BATTERY_BQ27x00=y
# CONFIG_BATTERY_MAX17040 is not set
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
# CONFIG_HWMON_DEBUG_CHIP is not set
#
# Native drivers
#
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
# CONFIG_SENSORS_ADCXX is not set
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7473 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM70 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LTC4215 is not set
# CONFIG_SENSORS_LTC4245 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_MAX1111 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX6650 is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_SENSORS_LIS3_SPI is not set
CONFIG_THERMAL=y
CONFIG_THERMAL_HWMON=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
CONFIG_OMAP_WATCHDOG=y
# CONFIG_TWL4030_WATCHDOG is not set
#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
#
# Sonics Silicon Backplane
#
# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_ASIC3 is not set
# CONFIG_HTC_EGPIO is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_TPS65010 is not set
CONFIG_TWL4030_CORE=y
# CONFIG_TWL4030_POWER is not set
# CONFIG_TWL4030_CODEC is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_MC13783 is not set
# CONFIG_AB3100_CORE is not set
# CONFIG_EZX_PCAP is not set
CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_BQ24022 is not set
# CONFIG_REGULATOR_MAX1586 is not set
CONFIG_REGULATOR_TWL4030=y
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
# CONFIG_MEDIA_SUPPORT is not set
#
# Graphics support
#
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
CONFIG_FB=y
# CONFIG_FIRMWARE_EDID is not set
# CONFIG_FB_DDC is not set
# CONFIG_FB_BOOT_VESA_SUPPORT is not set
# CONFIG_FB_CFB_FILLRECT is not set
# CONFIG_FB_CFB_COPYAREA is not set
# CONFIG_FB_CFB_IMAGEBLIT is not set
# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
# CONFIG_FB_SYS_FILLRECT is not set
# CONFIG_FB_SYS_COPYAREA is not set
# CONFIG_FB_SYS_IMAGEBLIT is not set
# CONFIG_FB_FOREIGN_ENDIAN is not set
# CONFIG_FB_SYS_FOPS is not set
# CONFIG_FB_SVGALIB is not set
# CONFIG_FB_MACMODES is not set
# CONFIG_FB_BACKLIGHT is not set
# CONFIG_FB_MODE_HELPERS is not set
# CONFIG_FB_TILEBLITTING is not set
#
# Frame buffer hardware drivers
#
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MB862XX is not set
# CONFIG_FB_BROADSHEET is not set
# CONFIG_FB_OMAP is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_BACKLIGHT_GENERIC=y
#
# Display device support
#
CONFIG_DISPLAY_SUPPORT=y
#
# Display hardware drivers
#
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
# CONFIG_FONTS is not set
CONFIG_FONT_8x8=y
CONFIG_FONT_8x16=y
CONFIG_LOGO=y
CONFIG_LOGO_LINUX_MONO=y
CONFIG_LOGO_LINUX_VGA16=y
CONFIG_LOGO_LINUX_CLUT224=y
CONFIG_SOUND=y
CONFIG_SOUND_OSS_CORE=y
CONFIG_SOUND_OSS_CORE_PRECLAIM=y
CONFIG_SND=y
CONFIG_SND_TIMER=y
CONFIG_SND_PCM=y
CONFIG_SND_HWDEP=y
CONFIG_SND_RAWMIDI=y
CONFIG_SND_JACK=y
CONFIG_SND_SEQUENCER=m
# CONFIG_SND_SEQ_DUMMY is not set
CONFIG_SND_OSSEMUL=y
CONFIG_SND_MIXER_OSS=y
CONFIG_SND_PCM_OSS=y
CONFIG_SND_PCM_OSS_PLUGINS=y
CONFIG_SND_SEQUENCER_OSS=y
CONFIG_SND_HRTIMER=m
CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
# CONFIG_SND_DYNAMIC_MINORS is not set
CONFIG_SND_SUPPORT_OLD_API=y
CONFIG_SND_VERBOSE_PROCFS=y
# CONFIG_SND_VERBOSE_PRINTK is not set
# CONFIG_SND_DEBUG is not set
CONFIG_SND_RAWMIDI_SEQ=m
# CONFIG_SND_OPL3_LIB_SEQ is not set
# CONFIG_SND_OPL4_LIB_SEQ is not set
# CONFIG_SND_SBAWE_SEQ is not set
# CONFIG_SND_EMU10K1_SEQ is not set
CONFIG_SND_DRIVERS=y
# CONFIG_SND_DUMMY is not set
# CONFIG_SND_VIRMIDI is not set
# CONFIG_SND_MTPAV is not set
# CONFIG_SND_SERIAL_U16550 is not set
# CONFIG_SND_MPU401 is not set
# CONFIG_SND_ARM is not set
CONFIG_SND_SPI=y
CONFIG_SND_USB=y
CONFIG_SND_USB_AUDIO=y
CONFIG_SND_USB_CAIAQ=m
CONFIG_SND_USB_CAIAQ_INPUT=y
CONFIG_SND_SOC=y
CONFIG_SND_OMAP_SOC=y
CONFIG_SND_SOC_I2C_AND_SPI=y
# CONFIG_SND_SOC_ALL_CODECS is not set
# CONFIG_SOUND_PRIME is not set
CONFIG_HID_SUPPORT=y
CONFIG_HID=y
# CONFIG_HIDRAW is not set
#
# USB Input Devices
#
CONFIG_USB_HID=y
# CONFIG_HID_PID is not set
# CONFIG_USB_HIDDEV is not set
#
# Special HID drivers
#
# CONFIG_HID_A4TECH is not set
# CONFIG_HID_APPLE is not set
# CONFIG_HID_BELKIN is not set
# CONFIG_HID_CHERRY is not set
# CONFIG_HID_CHICONY is not set
# CONFIG_HID_CYPRESS is not set
# CONFIG_HID_DRAGONRISE is not set
# CONFIG_HID_EZKEY is not set
# CONFIG_HID_KYE is not set
# CONFIG_HID_GYRATION is not set
# CONFIG_HID_TWINHAN is not set
# CONFIG_HID_KENSINGTON is not set
# CONFIG_HID_LOGITECH is not set
# CONFIG_HID_MICROSOFT is not set
# CONFIG_HID_MONTEREY is not set
# CONFIG_HID_NTRIG is not set
# CONFIG_HID_PANTHERLORD is not set
# CONFIG_HID_PETALYNX is not set
# CONFIG_HID_SAMSUNG is not set
# CONFIG_HID_SONY is not set
# CONFIG_HID_SUNPLUS is not set
# CONFIG_HID_GREENASIA is not set
# CONFIG_HID_SMARTJOYPLUS is not set
# CONFIG_HID_TOPSEED is not set
# CONFIG_HID_THRUSTMASTER is not set
# CONFIG_HID_WACOM is not set
# CONFIG_HID_ZEROPLUS is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB_ARCH_HAS_OHCI=y
# CONFIG_USB_ARCH_HAS_EHCI is not set
CONFIG_USB=y
# CONFIG_USB_DEBUG is not set
# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
#
# Miscellaneous USB options
#
CONFIG_USB_DEVICEFS=y
CONFIG_USB_DEVICE_CLASS=y
# CONFIG_USB_DYNAMIC_MINORS is not set
CONFIG_USB_SUSPEND=y
CONFIG_USB_OTG=y
# CONFIG_USB_OTG_WHITELIST is not set
# CONFIG_USB_OTG_BLACKLIST_HUB is not set
CONFIG_USB_MON=y
# CONFIG_USB_WUSB is not set
# CONFIG_USB_WUSB_CBAF is not set
#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
CONFIG_USB_OXU210HP_HCD=y
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_ISP1760_HCD is not set
# CONFIG_USB_ISP1362_HCD is not set
# CONFIG_USB_OHCI_HCD is not set
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_HWA_HCD is not set
CONFIG_USB_MUSB_HDRC=y
CONFIG_USB_MUSB_SOC=y
#
# OMAP 343x high speed USB support
#
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_PERIPHERAL is not set
CONFIG_USB_MUSB_OTG=y
CONFIG_USB_GADGET_MUSB_HDRC=y
CONFIG_USB_MUSB_HDRC_HCD=y
# CONFIG_MUSB_PIO_ONLY is not set
CONFIG_USB_INVENTRA_DMA=y
# CONFIG_USB_TI_CPPI_DMA is not set
# CONFIG_USB_MUSB_DEBUG is not set
#
# USB Device Class drivers
#
CONFIG_USB_ACM=m
CONFIG_USB_PRINTER=m
CONFIG_USB_WDM=m
CONFIG_USB_TMC=m
#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#
#
# also be needed; see USB_STORAGE Help for more info
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_ISD200 is not set
# CONFIG_USB_STORAGE_USBAT is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_STORAGE_SDDR55 is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_ALAUDA is not set
# CONFIG_USB_STORAGE_ONETOUCH is not set
# CONFIG_USB_STORAGE_KARMA is not set
# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
# CONFIG_USB_LIBUSUAL is not set
#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_MICROTEK is not set
#
# USB port drivers
#
CONFIG_USB_SERIAL=m
CONFIG_USB_EZUSB=y
CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_AIRCABLE=m
CONFIG_USB_SERIAL_ARK3116=m
CONFIG_USB_SERIAL_BELKIN=m
CONFIG_USB_SERIAL_CH341=m
CONFIG_USB_SERIAL_WHITEHEAT=m
CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
# CONFIG_USB_SERIAL_CP210X is not set
CONFIG_USB_SERIAL_CYPRESS_M8=m
CONFIG_USB_SERIAL_EMPEG=m
CONFIG_USB_SERIAL_FTDI_SIO=m
CONFIG_USB_SERIAL_FUNSOFT=m
CONFIG_USB_SERIAL_VISOR=m
CONFIG_USB_SERIAL_IPAQ=m
CONFIG_USB_SERIAL_IR=m
CONFIG_USB_SERIAL_EDGEPORT=m
CONFIG_USB_SERIAL_EDGEPORT_TI=m
CONFIG_USB_SERIAL_GARMIN=m
CONFIG_USB_SERIAL_IPW=m
CONFIG_USB_SERIAL_IUU=m
CONFIG_USB_SERIAL_KEYSPAN_PDA=m
CONFIG_USB_SERIAL_KEYSPAN=m
CONFIG_USB_SERIAL_KEYSPAN_MPR=y
CONFIG_USB_SERIAL_KEYSPAN_USA28=y
CONFIG_USB_SERIAL_KEYSPAN_USA28X=y
CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y
CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y
CONFIG_USB_SERIAL_KEYSPAN_USA19=y
CONFIG_USB_SERIAL_KEYSPAN_USA18X=y
CONFIG_USB_SERIAL_KEYSPAN_USA19W=y
CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y
CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y
CONFIG_USB_SERIAL_KEYSPAN_USA49W=y
CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y
CONFIG_USB_SERIAL_KLSI=m
CONFIG_USB_SERIAL_KOBIL_SCT=m
CONFIG_USB_SERIAL_MCT_U232=m
CONFIG_USB_SERIAL_MOS7720=m
CONFIG_USB_SERIAL_MOS7840=m
CONFIG_USB_SERIAL_MOTOROLA=m
CONFIG_USB_SERIAL_NAVMAN=m
CONFIG_USB_SERIAL_PL2303=m
CONFIG_USB_SERIAL_OTI6858=m
# CONFIG_USB_SERIAL_QUALCOMM is not set
CONFIG_USB_SERIAL_SPCP8X5=m
CONFIG_USB_SERIAL_HP4X=m
CONFIG_USB_SERIAL_SAFE=m
# CONFIG_USB_SERIAL_SAFE_PADDED is not set
CONFIG_USB_SERIAL_SIEMENS_MPI=m
CONFIG_USB_SERIAL_SIERRAWIRELESS=m
# CONFIG_USB_SERIAL_SYMBOL is not set
CONFIG_USB_SERIAL_TI=m
CONFIG_USB_SERIAL_CYBERJACK=m
CONFIG_USB_SERIAL_XIRCOM=m
CONFIG_USB_SERIAL_OPTION=m
CONFIG_USB_SERIAL_OMNINET=m
CONFIG_USB_SERIAL_OPTICON=m
CONFIG_USB_SERIAL_DEBUG=m
#
# USB Miscellaneous drivers
#
CONFIG_USB_EMI62=m
CONFIG_USB_EMI26=m
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_SEVSEG is not set
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_BERRY_CHARGE is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
CONFIG_USB_SISUSBVGA=m
CONFIG_USB_SISUSBVGA_CON=y
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
CONFIG_USB_TEST=m
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_VST is not set
# CONFIG_USB_ATM is not set
CONFIG_USB_GADGET=m
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
CONFIG_USB_GADGET_DEBUG_FS=y
CONFIG_USB_GADGET_VBUS_DRAW=2
CONFIG_USB_GADGET_SELECTED=y
# CONFIG_USB_GADGET_AT91 is not set
# CONFIG_USB_GADGET_ATMEL_USBA is not set
# CONFIG_USB_GADGET_FSL_USB2 is not set
# CONFIG_USB_GADGET_LH7A40X is not set
# CONFIG_USB_GADGET_OMAP is not set
# CONFIG_USB_GADGET_PXA25X is not set
# CONFIG_USB_GADGET_R8A66597 is not set
# CONFIG_USB_GADGET_PXA27X is not set
# CONFIG_USB_GADGET_S3C_HSOTG is not set
# CONFIG_USB_GADGET_IMX is not set
# CONFIG_USB_GADGET_S3C2410 is not set
# CONFIG_USB_GADGET_M66592 is not set
# CONFIG_USB_GADGET_AMD5536UDC is not set
# CONFIG_USB_GADGET_FSL_QE is not set
# CONFIG_USB_GADGET_CI13XXX is not set
# CONFIG_USB_GADGET_NET2280 is not set
# CONFIG_USB_GADGET_GOKU is not set
# CONFIG_USB_GADGET_LANGWELL is not set
# CONFIG_USB_GADGET_DUMMY_HCD is not set
CONFIG_USB_GADGET_DUALSPEED=y
CONFIG_USB_ZERO=m
CONFIG_USB_ZERO_HNPTEST=y
# CONFIG_USB_AUDIO is not set
CONFIG_USB_ETH=m
CONFIG_USB_ETH_RNDIS=y
# CONFIG_USB_ETH_EEM is not set
CONFIG_USB_GADGETFS=m
CONFIG_USB_FILE_STORAGE=m
# CONFIG_USB_FILE_STORAGE_TEST is not set
CONFIG_USB_G_SERIAL=m
CONFIG_USB_MIDI_GADGET=m
CONFIG_USB_G_PRINTER=m
CONFIG_USB_CDC_COMPOSITE=m
#
# OTG and related infrastructure
#
CONFIG_USB_OTG_UTILS=y
CONFIG_USB_GPIO_VBUS=y
# CONFIG_ISP1301_OMAP is not set
CONFIG_TWL4030_USB=y
# CONFIG_NOP_USB_XCEIV is not set
CONFIG_MMC=y
# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_UNSAFE_RESUME=y
#
# MMC/SD/SDIO Card Drivers
#
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_BOUNCE=y
CONFIG_SDIO_UART=y
# CONFIG_MMC_TEST is not set
#
# MMC/SD/SDIO Host Controller Drivers
#
# CONFIG_MMC_SDHCI is not set
# CONFIG_MMC_OMAP is not set
CONFIG_MMC_OMAP_HS=y
# CONFIG_MMC_AT91 is not set
# CONFIG_MMC_ATMELMCI is not set
CONFIG_MMC_SPI=m
# CONFIG_MEMSTICK is not set
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
#
# LED drivers
#
# CONFIG_LEDS_PCA9532 is not set
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_GPIO_PLATFORM=y
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_PCA955X is not set
# CONFIG_LEDS_DAC124S085 is not set
# CONFIG_LEDS_BD2802 is not set
#
# LED Triggers
#
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=m
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=m
# CONFIG_LEDS_TRIGGER_GPIO is not set
CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
#
# iptables trigger is under Netfilter config (LED target)
#
# CONFIG_ACCESSIBILITY is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set
#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set
#
# I2C RTC drivers
#
# CONFIG_RTC_DRV_DS1307 is not set
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
CONFIG_RTC_DRV_TWL4030=y
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8581 is not set
# CONFIG_RTC_DRV_RX8025 is not set
#
# SPI RTC drivers
#
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_DS3234 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_CMOS is not set
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_V3020 is not set
#
# on-CPU RTC drivers
#
# CONFIG_DMADEVICES is not set
# CONFIG_AUXDISPLAY is not set
CONFIG_UIO=m
CONFIG_UIO_PDRV=m
CONFIG_UIO_PDRV_GENIRQ=m
# CONFIG_UIO_SMX is not set
# CONFIG_UIO_SERCOS3 is not set
#
# TI VLYNQ
#
CONFIG_STAGING=y
# CONFIG_STAGING_EXCLUDE_BUILD is not set
# CONFIG_USB_IP_COMMON is not set
# CONFIG_W35UND is not set
# CONFIG_PRISM2_USB is not set
# CONFIG_ECHO is not set
# CONFIG_OTUS is not set
# CONFIG_COMEDI is not set
# CONFIG_ASUS_OLED is not set
# CONFIG_INPUT_MIMIO is not set
# CONFIG_TRANZPORT is not set
#
# Android
#
#
# Qualcomm MSM Camera And Video
#
#
# Camera Sensor Selection
#
# CONFIG_INPUT_GPIO is not set
# CONFIG_DST is not set
# CONFIG_POHMELFS is not set
# CONFIG_PLAN9AUTH is not set
# CONFIG_LINE6_USB is not set
# CONFIG_USB_SERIAL_QUATECH2 is not set
# CONFIG_USB_SERIAL_QUATECH_USB2 is not set
# CONFIG_VT6656 is not set
# CONFIG_FB_UDL is not set
#
# RAR Register Driver
#
# CONFIG_RAR_REGISTER is not set
# CONFIG_IIO is not set
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT2_FS_XIP is not set
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
# CONFIG_EXT3_FS_XATTR is not set
CONFIG_EXT4_FS=m
CONFIG_EXT4_FS_XATTR=y
# CONFIG_EXT4_FS_POSIX_ACL is not set
# CONFIG_EXT4_FS_SECURITY is not set
# CONFIG_EXT4_DEBUG is not set
CONFIG_JBD=y
# CONFIG_JBD_DEBUG is not set
CONFIG_JBD2=m
# CONFIG_JBD2_DEBUG is not set
CONFIG_FS_MBCACHE=m
CONFIG_REISERFS_FS=m
# CONFIG_REISERFS_CHECK is not set
CONFIG_REISERFS_PROC_INFO=y
CONFIG_REISERFS_FS_XATTR=y
# CONFIG_REISERFS_FS_POSIX_ACL is not set
# CONFIG_REISERFS_FS_SECURITY is not set
CONFIG_JFS_FS=m
# CONFIG_JFS_POSIX_ACL is not set
# CONFIG_JFS_SECURITY is not set
# CONFIG_JFS_DEBUG is not set
# CONFIG_JFS_STATISTICS is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_XFS_FS=m
# CONFIG_XFS_QUOTA is not set
# CONFIG_XFS_POSIX_ACL is not set
# CONFIG_XFS_RT is not set
# CONFIG_XFS_DEBUG is not set
# CONFIG_GFS2_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
CONFIG_FILE_LOCKING=y
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_QUOTA=y
# CONFIG_QUOTA_NETLINK_INTERFACE is not set
CONFIG_PRINT_QUOTA_WARNING=y
CONFIG_QUOTA_TREE=y
# CONFIG_QFMT_V1 is not set
CONFIG_QFMT_V2=y
CONFIG_QUOTACTL=y
# CONFIG_AUTOFS_FS is not set
CONFIG_AUTOFS4_FS=m
CONFIG_FUSE_FS=y
# CONFIG_CUSE is not set
#
# Caches
#
# CONFIG_FSCACHE is not set
#
# CD-ROM/DVD Filesystems
#
CONFIG_ISO9660_FS=m
CONFIG_JOLIET=y
CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
CONFIG_UDF_NLS=y
#
# DOS/FAT/NT Filesystems
#
CONFIG_FAT_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
CONFIG_NTFS_FS=m
# CONFIG_NTFS_DEBUG is not set
CONFIG_NTFS_RW=y
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_CONFIGFS_FS=m
CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_ECRYPT_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
CONFIG_JFFS2_SUMMARY=y
CONFIG_JFFS2_FS_XATTR=y
CONFIG_JFFS2_FS_POSIX_ACL=y
CONFIG_JFFS2_FS_SECURITY=y
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_LZO=y
CONFIG_JFFS2_RTIME=y
CONFIG_JFFS2_RUBIN=y
# CONFIG_JFFS2_CMODE_NONE is not set
# CONFIG_JFFS2_CMODE_PRIORITY is not set
# CONFIG_JFFS2_CMODE_SIZE is not set
CONFIG_JFFS2_CMODE_FAVOURLZO=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_XATTR=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
# CONFIG_UBIFS_FS_DEBUG is not set
# CONFIG_CRAMFS is not set
CONFIG_SQUASHFS=y
# CONFIG_SQUASHFS_EMBEDDED is not set
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V3_ACL is not set
CONFIG_NFS_V4=y
# CONFIG_NFS_V4_1 is not set
CONFIG_ROOT_NFS=y
CONFIG_NFSD=m
CONFIG_NFSD_V2_ACL=y
CONFIG_NFSD_V3=y
CONFIG_NFSD_V3_ACL=y
CONFIG_NFSD_V4=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_EXPORTFS=m
CONFIG_NFS_ACL_SUPPORT=m
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=y
CONFIG_RPCSEC_GSS_KRB5=y
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
CONFIG_CIFS=m
CONFIG_CIFS_STATS=y
CONFIG_CIFS_STATS2=y
# CONFIG_CIFS_WEAK_PW_HASH is not set
# CONFIG_CIFS_UPCALL is not set
# CONFIG_CIFS_XATTR is not set
# CONFIG_CIFS_DEBUG2 is not set
# CONFIG_CIFS_DFS_UPCALL is not set
CONFIG_CIFS_EXPERIMENTAL=y
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
CONFIG_PARTITION_ADVANCED=y
# CONFIG_ACORN_PARTITION is not set
# CONFIG_OSF_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_ATARI_PARTITION is not set
# CONFIG_MAC_PARTITION is not set
CONFIG_MSDOS_PARTITION=y
CONFIG_BSD_DISKLABEL=y
CONFIG_MINIX_SUBPARTITION=y
CONFIG_SOLARIS_X86_PARTITION=y
CONFIG_UNIXWARE_DISKLABEL=y
# CONFIG_LDM_PARTITION is not set
# CONFIG_SGI_PARTITION is not set
# CONFIG_ULTRIX_PARTITION is not set
# CONFIG_SUN_PARTITION is not set
# CONFIG_KARMA_PARTITION is not set
CONFIG_EFI_PARTITION=y
# CONFIG_SYSV68_PARTITION is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_737=m
CONFIG_NLS_CODEPAGE_775=m
CONFIG_NLS_CODEPAGE_850=m
CONFIG_NLS_CODEPAGE_852=m
CONFIG_NLS_CODEPAGE_855=m
CONFIG_NLS_CODEPAGE_857=m
CONFIG_NLS_CODEPAGE_860=m
CONFIG_NLS_CODEPAGE_861=m
CONFIG_NLS_CODEPAGE_862=m
CONFIG_NLS_CODEPAGE_863=m
CONFIG_NLS_CODEPAGE_864=m
CONFIG_NLS_CODEPAGE_865=m
CONFIG_NLS_CODEPAGE_866=m
CONFIG_NLS_CODEPAGE_869=m
CONFIG_NLS_CODEPAGE_936=m
CONFIG_NLS_CODEPAGE_950=m
CONFIG_NLS_CODEPAGE_932=m
CONFIG_NLS_CODEPAGE_949=m
CONFIG_NLS_CODEPAGE_874=m
CONFIG_NLS_ISO8859_8=m
CONFIG_NLS_CODEPAGE_1250=m
CONFIG_NLS_CODEPAGE_1251=m
CONFIG_NLS_ASCII=m
CONFIG_NLS_ISO8859_1=m
CONFIG_NLS_ISO8859_2=m
CONFIG_NLS_ISO8859_3=m
CONFIG_NLS_ISO8859_4=m
CONFIG_NLS_ISO8859_5=m
CONFIG_NLS_ISO8859_6=m
CONFIG_NLS_ISO8859_7=m
CONFIG_NLS_ISO8859_9=m
CONFIG_NLS_ISO8859_13=m
CONFIG_NLS_ISO8859_14=m
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_KOI8_R=m
CONFIG_NLS_KOI8_U=m
CONFIG_NLS_UTF8=y
# CONFIG_DLM is not set
#
# Kernel hacking
#
CONFIG_PRINTK_TIME=y
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=1024
CONFIG_MAGIC_SYSRQ=y
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_UNUSED_SYMBOLS is not set
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
CONFIG_SCHED_DEBUG=y
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_DEBUG_SLAB is not set
# CONFIG_DEBUG_KMEMLEAK is not set
CONFIG_DEBUG_PREEMPT=y
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
CONFIG_DEBUG_MUTEXES=y
# CONFIG_DEBUG_LOCK_ALLOC is not set
# CONFIG_PROVE_LOCKING is not set
# CONFIG_LOCK_STAT is not set
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
CONFIG_STACKTRACE=y
# CONFIG_DEBUG_KOBJECT is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_DEBUG_INFO is not set
# CONFIG_DEBUG_VM is not set
# CONFIG_DEBUG_WRITECOUNT is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_DEBUG_CREDENTIALS is not set
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_LATENCYTOP is not set
# CONFIG_PAGE_POISONING is not set
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_RING_BUFFER=y
CONFIG_EVENT_TRACING=y
CONFIG_CONTEXT_SWITCH_TRACER=y
CONFIG_RING_BUFFER_ALLOW_SWAP=y
CONFIG_TRACING=y
CONFIG_TRACING_SUPPORT=y
CONFIG_FTRACE=y
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_PREEMPT_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_ENABLE_DEFAULT_TRACERS is not set
# CONFIG_BOOT_TRACER is not set
CONFIG_BRANCH_PROFILE_NONE=y
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_KMEMTRACE is not set
# CONFIG_WORKQUEUE_TRACER is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_RING_BUFFER_BENCHMARK is not set
# CONFIG_DYNAMIC_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
CONFIG_ARM_UNWIND=y
# CONFIG_DEBUG_USER is not set
# CONFIG_DEBUG_ERRORS is not set
# CONFIG_DEBUG_STACK_USAGE is not set
# CONFIG_DEBUG_LL is not set
#
# Security options
#
CONFIG_KEYS=y
# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
CONFIG_XOR_BLOCKS=m
CONFIG_ASYNC_CORE=m
CONFIG_ASYNC_MEMCPY=m
CONFIG_ASYNC_XOR=m
CONFIG_ASYNC_PQ=m
CONFIG_ASYNC_RAID6_RECOV=m
CONFIG_CRYPTO=y
#
# Crypto core or helper
#
CONFIG_CRYPTO_FIPS=y
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=m
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=m
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_PCOMP=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_GF128MUL=m
CONFIG_CRYPTO_NULL=m
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_CRYPTO_CRYPTD=m
CONFIG_CRYPTO_AUTHENC=m
CONFIG_CRYPTO_TEST=m
#
# Authenticated Encryption with Associated Data
#
CONFIG_CRYPTO_CCM=m
CONFIG_CRYPTO_GCM=m
CONFIG_CRYPTO_SEQIV=m
#
# Block modes
#
CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_CTR=m
CONFIG_CRYPTO_CTS=m
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_LRW=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_XTS=m
#
# Hash modes
#
CONFIG_CRYPTO_HMAC=m
CONFIG_CRYPTO_XCBC=m
# CONFIG_CRYPTO_VMAC is not set
#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
CONFIG_CRYPTO_GHASH=m
CONFIG_CRYPTO_MD4=m
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_MICHAEL_MIC=y
CONFIG_CRYPTO_RMD128=m
CONFIG_CRYPTO_RMD160=m
CONFIG_CRYPTO_RMD256=m
CONFIG_CRYPTO_RMD320=m
CONFIG_CRYPTO_SHA1=m
CONFIG_CRYPTO_SHA256=m
CONFIG_CRYPTO_SHA512=m
CONFIG_CRYPTO_TGR192=m
CONFIG_CRYPTO_WP512=m
#
# Ciphers
#
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_ANUBIS=m
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_BLOWFISH=m
CONFIG_CRYPTO_CAMELLIA=m
CONFIG_CRYPTO_CAST5=m
CONFIG_CRYPTO_CAST6=m
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_FCRYPT=m
CONFIG_CRYPTO_KHAZAD=m
CONFIG_CRYPTO_SALSA20=m
CONFIG_CRYPTO_SEED=m
CONFIG_CRYPTO_SERPENT=m
CONFIG_CRYPTO_TEA=m
CONFIG_CRYPTO_TWOFISH=m
CONFIG_CRYPTO_TWOFISH_COMMON=m
#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
# CONFIG_CRYPTO_ZLIB is not set
CONFIG_CRYPTO_LZO=y
#
# Random Number Generation
#
CONFIG_CRYPTO_ANSI_CPRNG=m
CONFIG_CRYPTO_HW=y
CONFIG_BINARY_PRINTF=y
#
# Library routines
#
CONFIG_BITREVERSE=y
CONFIG_GENERIC_FIND_LAST_BIT=y
CONFIG_CRC_CCITT=y
CONFIG_CRC16=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC32=y
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_DECOMPRESS_GZIP=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=m
CONFIG_TEXTSEARCH_BM=m
CONFIG_TEXTSEARCH_FSM=m
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
CONFIG_NLATTR=y
arch/arm/configs/omap_4430sdp_defconfig
View file @ 5ccf1978
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.30-rc7
# Tue Jun 9 12:36:23 2009
# Linux kernel version: 2.6.32
# Sun Dec 6 23:37:45 2009
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_MMU=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_LOCKBREAK=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_ARCH_HAS_CPUFREQ=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_CONSTRUCTORS=y
#
# General setup
......@@ -39,11 +42,12 @@ CONFIG_BSD_PROCESS_ACCT=y
#
# RCU Subsystem
#
CONFIG_CLASSIC_RCU=y
# CONFIG_TREE_RCU is not set
# CONFIG_PREEMPT_RCU is not set
CONFIG_TREE_RCU=y
# CONFIG_TREE_PREEMPT_RCU is not set
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_FANOUT=32
# CONFIG_RCU_FANOUT_EXACT is not set
# CONFIG_TREE_RCU_TRACE is not set
# CONFIG_PREEMPT_RCU_TRACE is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_GROUP_SCHED=y
......@@ -52,8 +56,7 @@ CONFIG_FAIR_GROUP_SCHED=y
CONFIG_USER_SCHED=y
# CONFIG_CGROUP_SCHED is not set
# CONFIG_CGROUPS is not set
# CONFIG_SYSFS_DEPRECATED=y is not set
# CONFIG_SYSFS_DEPRECATED_V2=y is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
CONFIG_BLK_DEV_INITRD=y
......@@ -70,7 +73,6 @@ CONFIG_UID16=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_ALL is not set
# CONFIG_KALLSYMS_EXTRA_PASS is not set
# CONFIG_STRIP_ASM_SYMS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
......@@ -83,6 +85,10 @@ CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
#
# Kernel Performance Events And Counters
#
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_DEBUG=y
CONFIG_COMPAT_BRK=y
......@@ -90,13 +96,16 @@ CONFIG_COMPAT_BRK=y
CONFIG_SLUB=y
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_USE_GENERIC_SMP_HELPERS=y
CONFIG_HAVE_CLK=y
#
# GCOV-based kernel profiling
#
# CONFIG_SLOW_WORK is not set
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
......@@ -110,7 +119,7 @@ CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_STOP_MACHINE=y
CONFIG_BLOCK=y
# CONFIG_LBD is not set
CONFIG_LBDAF=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
......@@ -131,6 +140,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
#
# System Type
#
CONFIG_MMU=y
# CONFIG_ARCH_AAEC2000 is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
......@@ -142,8 +152,10 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_MXC is not set
# CONFIG_ARCH_STMP3XXX is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_NOMADIK is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
......@@ -166,10 +178,13 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_S3C64XX is not set
# CONFIG_ARCH_S5PC1XX is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_U300 is not set
# CONFIG_ARCH_DAVINCI is not set
CONFIG_ARCH_OMAP=y
# CONFIG_ARCH_BCMRING is not set
#
# TI OMAP Implementations
......@@ -190,9 +205,12 @@ CONFIG_ARCH_OMAP4=y
CONFIG_OMAP_32K_TIMER=y
CONFIG_OMAP_32K_TIMER_HZ=128
CONFIG_OMAP_DM_TIMER=y
CONFIG_OMAP_LL_DEBUG_UART1=y
# CONFIG_OMAP_LL_DEBUG_UART1 is not set
# CONFIG_OMAP_LL_DEBUG_UART2 is not set
# CONFIG_OMAP_LL_DEBUG_UART3 is not set
CONFIG_OMAP_LL_DEBUG_UART3=y
# CONFIG_OMAP_LL_DEBUG_NONE is not set
# CONFIG_OMAP_PM_NONE is not set
CONFIG_OMAP_PM_NOOP=y
#
# OMAP Board Type
......@@ -207,7 +225,7 @@ CONFIG_CPU_32v6K=y
CONFIG_CPU_V7=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_PABRT_IFAR=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
......@@ -222,9 +240,10 @@ CONFIG_CPU_CP15_MMU=y
# CONFIG_ARM_THUMB is not set
# CONFIG_ARM_THUMBEE is not set
# CONFIG_CPU_ICACHE_DISABLE is not set
CONFIG_CPU_DCACHE_DISABLE=y
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
CONFIG_HAS_TLS_REG=y
CONFIG_ARM_L1_CACHE_SHIFT=5
# CONFIG_ARM_ERRATA_430973 is not set
# CONFIG_ARM_ERRATA_458693 is not set
# CONFIG_ARM_ERRATA_460075 is not set
......@@ -245,18 +264,20 @@ CONFIG_ARM_GIC=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_SMP=y
CONFIG_HAVE_ARM_SCU=y
CONFIG_HAVE_ARM_TWD=y
CONFIG_VMSPLIT_3G=y
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_NR_CPUS=2
# CONFIG_HOTPLUG_CPU is not set
CONFIG_LOCAL_TIMERS=y
# CONFIG_PREEMPT is not set
# CONFIG_LOCAL_TIMERS is not set
# CONFIG_PREEMPT_NONE is not set
# CONFIG_PREEMPT_VOLUNTARY is not set
CONFIG_PREEMPT=y
CONFIG_HZ=128
# CONFIG_THUMB2_KERNEL is not set
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_OABI_COMPAT=y
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
# CONFIG_HIGHMEM is not set
......@@ -271,10 +292,13 @@ CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_VIRT_TO_BUS=y
# CONFIG_UNEVICTABLE_LRU is not set
CONFIG_HAVE_MLOCK=y
CONFIG_HAVE_MLOCKED_PAGE_BIT=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
# CONFIG_LEDS is not set
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_UACCESS_WITH_MEMCPY is not set
#
# Boot options
......@@ -298,9 +322,11 @@ CONFIG_CMDLINE="root=/dev/ram0 rw mem=128M console=ttyS0,115200n8 initrd=0x81600
#
# At least one emulation must be selected
#
# CONFIG_FPE_NWFPE is not set
# CONFIG_FPE_FASTFPE is not set
CONFIG_VFP=y
CONFIG_VFPv3=y
# CONFIG_NEON is not set
CONFIG_NEON=y
#
# Userspace binary formats
......@@ -325,6 +351,7 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_DEVTMPFS is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
......@@ -342,6 +369,7 @@ CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=16384
# CONFIG_BLK_DEV_XIP is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_MG_DISK is not set
# CONFIG_MISC_DEVICES is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
......@@ -355,6 +383,7 @@ CONFIG_HAVE_IDE=y
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
# CONFIG_PHONE is not set
#
# Input device support
......@@ -427,6 +456,11 @@ CONFIG_HW_RANDOM=y
# CONFIG_TCG_TPM is not set
# CONFIG_I2C is not set
# CONFIG_SPI is not set
#
# PPS support
#
# CONFIG_PPS is not set
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
# CONFIG_DEBUG_GPIO is not set
......@@ -447,11 +481,14 @@ CONFIG_GPIOLIB=y
#
# SPI GPIO expanders:
#
#
# AC97 GPIO expanders:
#
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
# CONFIG_THERMAL is not set
# CONFIG_THERMAL_HWMON is not set
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y
......@@ -472,21 +509,8 @@ CONFIG_SSB_POSSIBLE=y
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
#
# Multimedia devices
#
#
# Multimedia core support
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_VIDEO_MEDIA is not set
#
# Multimedia drivers
#
CONFIG_DAB=y
# CONFIG_REGULATOR is not set
# CONFIG_MEDIA_SUPPORT is not set
#
# Graphics support
......@@ -511,14 +535,17 @@ CONFIG_DUMMY_CONSOLE=y
# CONFIG_USB_SUPPORT is not set
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_ACCESSIBILITY is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
# CONFIG_DMADEVICES is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_REGULATOR is not set
# CONFIG_UIO is not set
#
# TI VLYNQ
#
# CONFIG_STAGING is not set
#
......@@ -535,9 +562,12 @@ CONFIG_JBD=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
CONFIG_FILE_LOCKING=y
# CONFIG_XFS_FS is not set
# CONFIG_GFS2_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
CONFIG_FILE_LOCKING=y
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
......@@ -601,7 +631,6 @@ CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
# CONFIG_NILFS2_FS is not set
#
# Partition Types
......@@ -673,23 +702,24 @@ CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_FRAME_WARN=1024
CONFIG_MAGIC_SYSRQ=y
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
CONFIG_DEBUG_KERNEL=y
# CONFIG_DEBUG_SHIRQ is not set
CONFIG_DETECT_SOFTLOCKUP=y
# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
# CONFIG_DETECT_SOFTLOCKUP is not set
CONFIG_DETECT_HUNG_TASK=y
# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
CONFIG_SCHED_DEBUG=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_SCHEDSTATS is not set
# CONFIG_TIMER_STATS is not set
# CONFIG_DEBUG_OBJECTS is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SLUB_STATS is not set
# CONFIG_DEBUG_KMEMLEAK is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_DEBUG_RT_MUTEXES is not set
# CONFIG_RT_MUTEX_TESTER is not set
# CONFIG_DEBUG_SPINLOCK is not set
......@@ -708,31 +738,22 @@ CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_LIST is not set
# CONFIG_DEBUG_SG is not set
# CONFIG_DEBUG_NOTIFIERS is not set
# CONFIG_DEBUG_CREDENTIALS is not set
CONFIG_FRAME_POINTER=y
# CONFIG_BOOT_PRINTK_DELAY is not set
# CONFIG_RCU_TORTURE_TEST is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
# CONFIG_FAULT_INJECTION is not set
# CONFIG_PAGE_POISONING is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_TRACING_SUPPORT=y
#
# Tracers
#
# CONFIG_FUNCTION_TRACER is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_CONTEXT_SWITCH_TRACER is not set
# CONFIG_EVENT_TRACER is not set
# CONFIG_BOOT_TRACER is not set
# CONFIG_TRACE_BRANCH_PROFILING is not set
# CONFIG_STACK_TRACER is not set
# CONFIG_KMEMTRACE is not set
# CONFIG_WORKQUEUE_TRACER is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_FTRACE is not set
# CONFIG_BRANCH_PROFILE_NONE is not set
# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
# CONFIG_PROFILE_ALL_BRANCHES is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_KGDB is not set
......@@ -754,7 +775,6 @@ CONFIG_CRYPTO=y
#
# Crypto core or helper
#
# CONFIG_CRYPTO_FIPS is not set
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD2=y
......@@ -796,11 +816,13 @@ CONFIG_CRYPTO_PCBC=m
#
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_VMAC is not set
#
# Digest
#
CONFIG_CRYPTO_CRC32C=y
# CONFIG_CRYPTO_GHASH is not set
# CONFIG_CRYPTO_MD4 is not set
CONFIG_CRYPTO_MD5=y
# CONFIG_CRYPTO_MICHAEL_MIC is not set
......
arch/arm/configs/omap_zoom2_defconfig
View file @ 5ccf1978
......@@ -610,7 +610,8 @@ CONFIG_INPUT_EVDEV=y
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_TWL4030=y
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
......
arch/arm/configs/omap_zoom3_defconfig
View file @ 5ccf1978
......@@ -629,7 +629,8 @@ CONFIG_INPUT_EVDEV=y
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_TWL4030=y
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
......
arch/arm/mach-omap1/Makefile
View file @ 5ccf1978
......@@ -18,6 +18,9 @@ obj-$(CONFIG_PM) += pm.o sleep.o
obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox_mach.o
mailbox_mach-objs := mailbox.o
i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
obj-y += $(i2c-omap-m) $(i2c-omap-y)
led-y := leds.o
# Specific board support
......@@ -49,3 +52,7 @@ led-$(CONFIG_MACH_OMAP_INNOVATOR) += leds-innovator.o
led-$(CONFIG_MACH_OMAP_PERSEUS2) += leds-h2p2-debug.o
led-$(CONFIG_MACH_OMAP_OSK) += leds-osk.o
obj-$(CONFIG_LEDS) += $(led-y)
ifneq ($(CONFIG_FB_OMAP),)
obj-y += lcd_dma.o
endif
arch/arm/mach-omap1/board-fsample.c
View file @ 5ccf1978
......@@ -19,6 +19,7 @@
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <linux/smc91x.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
......@@ -30,7 +31,6 @@
#include <mach/gpio.h>
#include <plat/mux.h>
#include <plat/fpga.h>
#include <plat/nand.h>
#include <plat/keypad.h>
#include <plat/common.h>
#include <plat/board.h>
......@@ -100,6 +100,12 @@ static int fsample_keymap[] = {
0
};
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource smc91x_resources[] = {
[0] = {
.start = H2P2_DBG_FPGA_ETHR_START, /* Physical */
......@@ -167,8 +173,40 @@ static struct platform_device nor_device = {
.resource = &nor_resource,
};
static struct omap_nand_platform_data nand_data = {
.options = NAND_SAMSUNG_LP_OPTIONS,
static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
unsigned long mask;
if (cmd == NAND_CMD_NONE)
return;
mask = (ctrl & NAND_CLE) ? 0x02 : 0;
if (ctrl & NAND_ALE)
mask |= 0x04;
writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
}
#define FSAMPLE_NAND_RB_GPIO_PIN 62
static int nand_dev_ready(struct mtd_info *mtd)
{
return gpio_get_value(FSAMPLE_NAND_RB_GPIO_PIN);
}
static const char *part_probes[] = { "cmdlinepart", NULL };
static struct platform_nand_data nand_data = {
.chip = {
.nr_chips = 1,
.chip_offset = 0,
.options = NAND_SAMSUNG_LP_OPTIONS,
.part_probe_types = part_probes,
},
.ctrl = {
.cmd_ctrl = nand_cmd_ctl,
.dev_ready = nand_dev_ready,
},
};
static struct resource nand_resource = {
......@@ -178,7 +216,7 @@ static struct resource nand_resource = {
};
static struct platform_device nand_device = {
.name = "omapnand",
.name = "gen_nand",
.id = 0,
.dev = {
.platform_data = &nand_data,
......@@ -190,6 +228,9 @@ static struct platform_device nand_device = {
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.dev = {
.platform_data = &smc91x_info,
},
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
......@@ -233,13 +274,6 @@ static struct platform_device *devices[] __initdata = {
&lcd_device,
};
#define P2_NAND_RB_GPIO_PIN 62
static int nand_dev_ready(struct omap_nand_platform_data *data)
{
return gpio_get_value(P2_NAND_RB_GPIO_PIN);
}
static struct omap_lcd_config fsample_lcd_config __initdata = {
.ctrl_name = "internal",
};
......@@ -250,9 +284,9 @@ static struct omap_board_config_kernel fsample_config[] = {
static void __init omap_fsample_init(void)
{
if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0)
BUG();
nand_data.dev_ready = nand_dev_ready;
gpio_direction_input(FSAMPLE_NAND_RB_GPIO_PIN);
omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
......
arch/arm/mach-omap1/board-h2.c
View file @ 5ccf1978
......@@ -28,6 +28,7 @@
#include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <linux/i2c/tps65010.h>
#include <linux/smc91x.h>
#include <mach/hardware.h>
#include <asm/gpio.h>
......@@ -40,7 +41,6 @@
#include <plat/mux.h>
#include <plat/dma.h>
#include <plat/tc.h>
#include <plat/nand.h>
#include <plat/irda.h>
#include <plat/usb.h>
#include <plat/keypad.h>
......@@ -179,11 +179,43 @@ static struct mtd_partition h2_nand_partitions[] = {
},
};
/* dip switches control NAND chip access: 8 bit, 16 bit, or neither */
static struct omap_nand_platform_data h2_nand_data = {
.options = NAND_SAMSUNG_LP_OPTIONS,
.parts = h2_nand_partitions,
.nr_parts = ARRAY_SIZE(h2_nand_partitions),
static void h2_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
unsigned long mask;
if (cmd == NAND_CMD_NONE)
return;
mask = (ctrl & NAND_CLE) ? 0x02 : 0;
if (ctrl & NAND_ALE)
mask |= 0x04;
writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
}
#define H2_NAND_RB_GPIO_PIN 62
static int h2_nand_dev_ready(struct mtd_info *mtd)
{
return gpio_get_value(H2_NAND_RB_GPIO_PIN);
}
static const char *h2_part_probes[] = { "cmdlinepart", NULL };
struct platform_nand_data h2_nand_platdata = {
.chip = {
.nr_chips = 1,
.chip_offset = 0,
.nr_partitions = ARRAY_SIZE(h2_nand_partitions),
.partitions = h2_nand_partitions,
.options = NAND_SAMSUNG_LP_OPTIONS,
.part_probe_types = h2_part_probes,
},
.ctrl = {
.cmd_ctrl = h2_nand_cmd_ctl,
.dev_ready = h2_nand_dev_ready,
},
};
static struct resource h2_nand_resource = {
......@@ -191,15 +223,21 @@ static struct resource h2_nand_resource = {
};
static struct platform_device h2_nand_device = {
.name = "omapnand",
.name = "gen_nand",
.id = 0,
.dev = {
.platform_data = &h2_nand_data,
.platform_data = &h2_nand_platdata,
},
.num_resources = 1,
.resource = &h2_nand_resource,
};
static struct smc91x_platdata h2_smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource h2_smc91x_resources[] = {
[0] = {
.start = OMAP1610_ETHR_START, /* Physical */
......@@ -216,6 +254,9 @@ static struct resource h2_smc91x_resources[] = {
static struct platform_device h2_smc91x_device = {
.name = "smc91x",
.id = 0,
.dev = {
.platform_data = &h2_smc91x_info,
},
.num_resources = ARRAY_SIZE(h2_smc91x_resources),
.resource = h2_smc91x_resources,
};
......@@ -368,8 +409,6 @@ static struct omap_board_config_kernel h2_config[] __initdata = {
{ OMAP_TAG_LCD, &h2_lcd_config },
};
#define H2_NAND_RB_GPIO_PIN 62
static void __init h2_init(void)
{
/* Here we assume the NOR boot config: NOR on CS3 (possibly swapped
......
arch/arm/mach-omap1/board-h3.c
View file @ 5ccf1978
......@@ -28,6 +28,7 @@
#include <linux/input.h>
#include <linux/spi/spi.h>
#include <linux/i2c/tps65010.h>
#include <linux/smc91x.h>
#include <asm/setup.h>
#include <asm/page.h>
......@@ -42,7 +43,6 @@
#include <mach/irqs.h>
#include <plat/mux.h>
#include <plat/tc.h>
#include <plat/nand.h>
#include <plat/usb.h>
#include <plat/keypad.h>
#include <plat/dma.h>
......@@ -181,11 +181,43 @@ static struct mtd_partition nand_partitions[] = {
},
};
/* dip switches control NAND chip access: 8 bit, 16 bit, or neither */
static struct omap_nand_platform_data nand_data = {
.options = NAND_SAMSUNG_LP_OPTIONS,
.parts = nand_partitions,
.nr_parts = ARRAY_SIZE(nand_partitions),
static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
unsigned long mask;
if (cmd == NAND_CMD_NONE)
return;
mask = (ctrl & NAND_CLE) ? 0x02 : 0;
if (ctrl & NAND_ALE)
mask |= 0x04;
writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
}
#define H3_NAND_RB_GPIO_PIN 10
static int nand_dev_ready(struct mtd_info *mtd)
{
return gpio_get_value(H3_NAND_RB_GPIO_PIN);
}
static const char *part_probes[] = { "cmdlinepart", NULL };
struct platform_nand_data nand_platdata = {
.chip = {
.nr_chips = 1,
.chip_offset = 0,
.nr_partitions = ARRAY_SIZE(nand_partitions),
.partitions = nand_partitions,
.options = NAND_SAMSUNG_LP_OPTIONS,
.part_probe_types = part_probes,
},
.ctrl = {
.cmd_ctrl = nand_cmd_ctl,
.dev_ready = nand_dev_ready,
},
};
static struct resource nand_resource = {
......@@ -193,15 +225,21 @@ static struct resource nand_resource = {
};
static struct platform_device nand_device = {
.name = "omapnand",
.name = "gen_nand",
.id = 0,
.dev = {
.platform_data = &nand_data,
.platform_data = &nand_platdata,
},
.num_resources = 1,
.resource = &nand_resource,
};
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource smc91x_resources[] = {
[0] = {
.start = OMAP1710_ETHR_START, /* Physical */
......@@ -218,6 +256,9 @@ static struct resource smc91x_resources[] = {
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.dev = {
.platform_data = &smc91x_info,
},
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
......@@ -332,13 +373,6 @@ static struct i2c_board_info __initdata h3_i2c_board_info[] = {
},
};
#define H3_NAND_RB_GPIO_PIN 10
static int nand_dev_ready(struct omap_nand_platform_data *data)
{
return gpio_get_value(H3_NAND_RB_GPIO_PIN);
}
static void __init h3_init(void)
{
/* Here we assume the NOR boot config: NOR on CS3 (possibly swapped
......@@ -356,7 +390,7 @@ static void __init h3_init(void)
nand_resource.end += SZ_4K - 1;
if (gpio_request(H3_NAND_RB_GPIO_PIN, "NAND ready") < 0)
BUG();
nand_data.dev_ready = nand_dev_ready;
gpio_direction_input(H3_NAND_RB_GPIO_PIN);
/* GPIO10 Func_MUX_CTRL reg bit 29:27, Configure V2 to mode1 as GPIO */
/* GPIO10 pullup/down register, Enable pullup on GPIO10 */
......
arch/arm/mach-omap1/board-htcherald.c
View file @ 5ccf1978
......@@ -39,6 +39,7 @@
#include <plat/common.h>
#include <plat/board.h>
#include <plat/keypad.h>
#include <plat/usb.h>
#include <mach/irqs.h>
......@@ -140,6 +141,15 @@ static struct platform_device kp_device = {
.resource = kp_resources,
};
/* USB Device */
static struct omap_usb_config htcherald_usb_config __initdata = {
.otg = 0,
.register_host = 0,
.register_dev = 1,
.hmc_mode = 4,
.pins[0] = 2,
};
/* LCD Device resources */
static struct platform_device lcd_device = {
.name = "lcd_htcherald",
......@@ -214,6 +224,57 @@ static void __init htcherald_disable_watchdog(void)
}
}
#define HTCHERALD_GPIO_USB_EN1 33
#define HTCHERALD_GPIO_USB_EN2 73
#define HTCHERALD_GPIO_USB_DM 35
#define HTCHERALD_GPIO_USB_DP 36
static void __init htcherald_usb_enable(void)
{
unsigned int tries = 20;
unsigned int value = 0;
/* Request the GPIOs we need to control here */
if (gpio_request(HTCHERALD_GPIO_USB_EN1, "herald_usb") < 0)
goto err1;
if (gpio_request(HTCHERALD_GPIO_USB_EN2, "herald_usb") < 0)
goto err2;
if (gpio_request(HTCHERALD_GPIO_USB_DM, "herald_usb") < 0)
goto err3;
if (gpio_request(HTCHERALD_GPIO_USB_DP, "herald_usb") < 0)
goto err4;
/* force USB_EN GPIO to 0 */
do {
/* output low */
gpio_direction_output(HTCHERALD_GPIO_USB_EN1, 0);
} while ((value = gpio_get_value(HTCHERALD_GPIO_USB_EN1)) == 1 &&
--tries);
if (value == 1)
printk(KERN_WARNING "Unable to reset USB, trying to continue\n");
gpio_direction_output(HTCHERALD_GPIO_USB_EN2, 0); /* output low */
gpio_direction_input(HTCHERALD_GPIO_USB_DM); /* input */
gpio_direction_input(HTCHERALD_GPIO_USB_DP); /* input */
goto done;
err4:
gpio_free(HTCHERALD_GPIO_USB_DM);
err3:
gpio_free(HTCHERALD_GPIO_USB_EN2);
err2:
gpio_free(HTCHERALD_GPIO_USB_EN1);
err1:
printk(KERN_ERR "Unabled to request GPIO for USB\n");
done:
printk(KERN_INFO "USB setup complete.\n");
}
static void __init htcherald_init(void)
{
printk(KERN_INFO "HTC Herald init.\n");
......@@ -225,6 +286,9 @@ static void __init htcherald_init(void)
platform_add_devices(devices, ARRAY_SIZE(devices));
htcherald_disable_watchdog();
htcherald_usb_enable();
omap_usb_init(&htcherald_usb_config);
}
static void __init htcherald_init_irq(void)
......
arch/arm/mach-omap1/board-innovator.c
View file @ 5ccf1978
......@@ -23,6 +23,7 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <linux/smc91x.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
......@@ -142,6 +143,11 @@ static struct platform_device innovator_kp_device = {
.resource = innovator_kp_resources,
};
static struct smc91x_platdata innovator_smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
#ifdef CONFIG_ARCH_OMAP15XX
......@@ -175,6 +181,9 @@ static struct resource innovator1510_smc91x_resources[] = {
static struct platform_device innovator1510_smc91x_device = {
.name = "smc91x",
.id = 0,
.dev = {
.platform_data = &innovator_smc91x_info,
},
.num_resources = ARRAY_SIZE(innovator1510_smc91x_resources),
.resource = innovator1510_smc91x_resources,
};
......@@ -241,6 +250,9 @@ static struct resource innovator1610_smc91x_resources[] = {
static struct platform_device innovator1610_smc91x_device = {
.name = "smc91x",
.id = 0,
.dev = {
.platform_data = &innovator_smc91x_info,
},
.num_resources = ARRAY_SIZE(innovator1610_smc91x_resources),
.resource = innovator1610_smc91x_resources,
};
......
arch/arm/mach-omap1/board-osk.c
View file @ 5ccf1978
......@@ -33,6 +33,7 @@
#include <linux/irq.h>
#include <linux/i2c.h>
#include <linux/leds.h>
#include <linux/smc91x.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
......@@ -115,6 +116,12 @@ static struct platform_device osk5912_flash_device = {
.resource = &osk_flash_resource,
};
static struct smc91x_platdata osk5912_smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource osk5912_smc91x_resources[] = {
[0] = {
.start = OMAP_OSK_ETHR_START, /* Physical */
......@@ -131,6 +138,9 @@ static struct resource osk5912_smc91x_resources[] = {
static struct platform_device osk5912_smc91x_device = {
.name = "smc91x",
.id = -1,
.dev = {
.platform_data = &osk5912_smc91x_info,
},
.num_resources = ARRAY_SIZE(osk5912_smc91x_resources),
.resource = osk5912_smc91x_resources,
};
......
arch/arm/mach-omap1/board-perseus2.c
View file @ 5ccf1978
......@@ -19,6 +19,7 @@
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/input.h>
#include <linux/smc91x.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
......@@ -30,7 +31,6 @@
#include <mach/gpio.h>
#include <plat/mux.h>
#include <plat/fpga.h>
#include <plat/nand.h>
#include <plat/keypad.h>
#include <plat/common.h>
#include <plat/board.h>
......@@ -67,6 +67,12 @@ static int p2_keymap[] = {
0
};
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource smc91x_resources[] = {
[0] = {
.start = H2P2_DBG_FPGA_ETHR_START, /* Physical */
......@@ -134,8 +140,40 @@ static struct platform_device nor_device = {
.resource = &nor_resource,
};
static struct omap_nand_platform_data nand_data = {
.options = NAND_SAMSUNG_LP_OPTIONS,
static void nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *this = mtd->priv;
unsigned long mask;
if (cmd == NAND_CMD_NONE)
return;
mask = (ctrl & NAND_CLE) ? 0x02 : 0;
if (ctrl & NAND_ALE)
mask |= 0x04;
writeb(cmd, (unsigned long)this->IO_ADDR_W | mask);
}
#define P2_NAND_RB_GPIO_PIN 62
static int nand_dev_ready(struct mtd_info *mtd)
{
return gpio_get_value(P2_NAND_RB_GPIO_PIN);
}
static const char *part_probes[] = { "cmdlinepart", NULL };
static struct platform_nand_data nand_data = {
.chip = {
.nr_chips = 1,
.chip_offset = 0,
.options = NAND_SAMSUNG_LP_OPTIONS,
.part_probe_types = part_probes,
},
.ctrl = {
.cmd_ctrl = nand_cmd_ctl,
.dev_ready = nand_dev_ready,
},
};
static struct resource nand_resource = {
......@@ -145,7 +183,7 @@ static struct resource nand_resource = {
};
static struct platform_device nand_device = {
.name = "omapnand",
.name = "gen_nand",
.id = 0,
.dev = {
.platform_data = &nand_data,
......@@ -157,6 +195,9 @@ static struct platform_device nand_device = {
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.dev = {
.platform_data = &smc91x_info,
},
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
......@@ -201,13 +242,6 @@ static struct platform_device *devices[] __initdata = {
&lcd_device,
};
#define P2_NAND_RB_GPIO_PIN 62
static int nand_dev_ready(struct omap_nand_platform_data *data)
{
return gpio_get_value(P2_NAND_RB_GPIO_PIN);
}
static struct omap_lcd_config perseus2_lcd_config __initdata = {
.ctrl_name = "internal",
};
......@@ -220,7 +254,7 @@ static void __init omap_perseus2_init(void)
{
if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
BUG();
nand_data.dev_ready = nand_dev_ready;
gpio_direction_input(P2_NAND_RB_GPIO_PIN);
omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
......
arch/arm/mach-omap1/board-voiceblue.c
View file @ 5ccf1978
......@@ -22,6 +22,7 @@
#include <linux/reboot.h>
#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/smc91x.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
......@@ -106,6 +107,12 @@ static struct platform_device voiceblue_flash_device = {
.resource = &voiceblue_flash_resource,
};
static struct smc91x_platdata voiceblue_smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource voiceblue_smc91x_resources[] = {
[0] = {
.start = OMAP_CS2_PHYS + 0x300,
......@@ -122,6 +129,9 @@ static struct resource voiceblue_smc91x_resources[] = {
static struct platform_device voiceblue_smc91x_device = {
.name = "smc91x",
.id = 0,
.dev = {
.platform_data = &voiceblue_smc91x_info,
},
.num_resources = ARRAY_SIZE(voiceblue_smc91x_resources),
.resource = voiceblue_smc91x_resources,
};
......
arch/arm/mach-omap1/clock_data.c
View file @ 5ccf1978
......@@ -655,9 +655,9 @@ static struct omap_clk omap_clks[] = {
CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
/* Virtual clocks */
CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310),
CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX),
CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX),
CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310),
CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX),
CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX),
CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310),
......
arch/arm/mach-omap1/i2c.c 0 → 100644
View file @ 5ccf1978
/*
* Helper module for board specific I2C bus registration
*
* Copyright (C) 2009 Nokia Corporation.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#include <plat/i2c.h>
#include <plat/mux.h>
#include <plat/cpu.h>
int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len)
{
if (cpu_is_omap7xx()) {
omap_cfg_reg(I2C_7XX_SDA);
omap_cfg_reg(I2C_7XX_SCL);
} else {
omap_cfg_reg(I2C_SDA);
omap_cfg_reg(I2C_SCL);
}
return omap_plat_register_i2c_bus(bus_id, clkrate, info, len);
}
arch/arm/mach-omap1/include/mach/lcd_dma.h 0 → 100644
View file @ 5ccf1978
/*
* arch/arm/mach-omap1/include/mach/lcd_dma.h
*
* Extracted from arch/arm/plat-omap/include/plat/dma.h
* Copyright (C) 2003 Nokia Corporation
* Author: Juha Yrjölä <juha.yrjola@nokia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __MACH_OMAP1_LCD_DMA_H__
#define __MACH_OMAP1_LCD_DMA_H__
/* Hardware registers for LCD DMA */
#define OMAP1510_DMA_LCD_BASE (0xfffedb00)
#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
#define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04)
#define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06)
#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
#define OMAP1610_DMA_LCD_BASE (0xfffee300)
#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
#define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca)
#define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc)
#define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce)
#define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0)
#define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2)
#define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4)
#define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6)
#define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8)
#define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda)
#define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0)
#define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4)
#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
/* LCD DMA block numbers */
enum {
OMAP_LCD_DMA_B1_TOP,
OMAP_LCD_DMA_B1_BOTTOM,
OMAP_LCD_DMA_B2_TOP,
OMAP_LCD_DMA_B2_BOTTOM
};
/* LCD DMA functions */
extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
void *data);
extern void omap_free_lcd_dma(void);
extern void omap_setup_lcd_dma(void);
extern void omap_enable_lcd_dma(void);
extern void omap_stop_lcd_dma(void);
extern void omap_set_lcd_dma_ext_controller(int external);
extern void omap_set_lcd_dma_single_transfer(int single);
extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
int data_type);
extern void omap_set_lcd_dma_b1_rotation(int rotate);
extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
extern void omap_set_lcd_dma_b1_mirror(int mirror);
extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
extern int omap_lcd_dma_running(void);
#endif /* __MACH_OMAP1_LCD_DMA_H__ */
arch/arm/mach-omap1/include/mach/lcdc.h 0 → 100644
View file @ 5ccf1978
/*
* arch/arm/mach-omap1/include/mach/lcdc.h
*
* Extracted from drivers/video/omap/lcdc.c
* Copyright (C) 2004 Nokia Corporation
* Author: Imre Deak <imre.deak@nokia.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef __MACH_LCDC_H__
#define __MACH_LCDC_H__
#define OMAP_LCDC_BASE 0xfffec000
#define OMAP_LCDC_SIZE 256
#define OMAP_LCDC_IRQ INT_LCD_CTRL
#define OMAP_LCDC_CONTROL (OMAP_LCDC_BASE + 0x00)
#define OMAP_LCDC_TIMING0 (OMAP_LCDC_BASE + 0x04)
#define OMAP_LCDC_TIMING1 (OMAP_LCDC_BASE + 0x08)
#define OMAP_LCDC_TIMING2 (OMAP_LCDC_BASE + 0x0c)
#define OMAP_LCDC_STATUS (OMAP_LCDC_BASE + 0x10)
#define OMAP_LCDC_SUBPANEL (OMAP_LCDC_BASE + 0x14)
#define OMAP_LCDC_LINE_INT (OMAP_LCDC_BASE + 0x18)
#define OMAP_LCDC_DISPLAY_STATUS (OMAP_LCDC_BASE + 0x1c)
#define OMAP_LCDC_STAT_DONE (1 << 0)
#define OMAP_LCDC_STAT_VSYNC (1 << 1)
#define OMAP_LCDC_STAT_SYNC_LOST (1 << 2)
#define OMAP_LCDC_STAT_ABC (1 << 3)
#define OMAP_LCDC_STAT_LINE_INT (1 << 4)
#define OMAP_LCDC_STAT_FUF (1 << 5)
#define OMAP_LCDC_STAT_LOADED_PALETTE (1 << 6)
#define OMAP_LCDC_CTRL_LCD_EN (1 << 0)
#define OMAP_LCDC_CTRL_LCD_TFT (1 << 7)
#define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10)
#define OMAP_LCDC_IRQ_VSYNC (1 << 2)
#define OMAP_LCDC_IRQ_DONE (1 << 3)
#define OMAP_LCDC_IRQ_LOADED_PALETTE (1 << 4)
#define OMAP_LCDC_IRQ_LINE_NIRQ (1 << 5)
#define OMAP_LCDC_IRQ_LINE (1 << 6)
#define OMAP_LCDC_IRQ_MASK (((1 << 5) - 1) << 2)
#endif /* __MACH_LCDC_H__ */
arch/arm/mach-omap1/lcd_dma.c 0 → 100644
View file @ 5ccf1978
/*
* linux/arch/arm/mach-omap1/lcd_dma.c
*
* Extracted from arch/arm/plat-omap/dma.c
* Copyright (C) 2003 - 2008 Nokia Corporation
* Author: Juha Yrjölä <juha.yrjola@nokia.com>
* DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
* Graphics DMA and LCD DMA graphics tranformations
* by Imre Deak <imre.deak@nokia.com>
* OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
* Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
* Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
*
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* Support functions for the OMAP internal DMA channels.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <mach/hardware.h>
#include <mach/lcdc.h>
#include <plat/dma.h>
int omap_lcd_dma_running(void)
{
/*
* On OMAP1510, internal LCD controller will start the transfer
* when it gets enabled, so assume DMA running if LCD enabled.
*/
if (cpu_is_omap1510())
if (omap_readw(OMAP_LCDC_CONTROL) & OMAP_LCDC_CTRL_LCD_EN)
return 1;
/* Check if LCD DMA is running */
if (cpu_is_omap16xx())
if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
return 1;
return 0;
}
static struct lcd_dma_info {
spinlock_t lock;
int reserved;
void (*callback)(u16 status, void *data);
void *cb_data;
int active;
unsigned long addr, size;
int rotate, data_type, xres, yres;
int vxres;
int mirror;
int xscale, yscale;
int ext_ctrl;
int src_port;
int single_transfer;
} lcd_dma;
void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
int data_type)
{
lcd_dma.addr = addr;
lcd_dma.data_type = data_type;
lcd_dma.xres = fb_xres;
lcd_dma.yres = fb_yres;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1);
void omap_set_lcd_dma_src_port(int port)
{
lcd_dma.src_port = port;
}
void omap_set_lcd_dma_ext_controller(int external)
{
lcd_dma.ext_ctrl = external;
}
EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
void omap_set_lcd_dma_single_transfer(int single)
{
lcd_dma.single_transfer = single;
}
EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
void omap_set_lcd_dma_b1_rotation(int rotate)
{
if (cpu_is_omap1510()) {
printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
BUG();
return;
}
lcd_dma.rotate = rotate;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
void omap_set_lcd_dma_b1_mirror(int mirror)
{
if (cpu_is_omap1510()) {
printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
BUG();
}
lcd_dma.mirror = mirror;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
{
if (cpu_is_omap1510()) {
printk(KERN_ERR "DMA virtual resulotion is not supported "
"in 1510 mode\n");
BUG();
}
lcd_dma.vxres = vxres;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
{
if (cpu_is_omap1510()) {
printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
BUG();
}
lcd_dma.xscale = xscale;
lcd_dma.yscale = yscale;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
static void set_b1_regs(void)
{
unsigned long top, bottom;
int es;
u16 w;
unsigned long en, fn;
long ei, fi;
unsigned long vxres;
unsigned int xscale, yscale;
switch (lcd_dma.data_type) {
case OMAP_DMA_DATA_TYPE_S8:
es = 1;
break;
case OMAP_DMA_DATA_TYPE_S16:
es = 2;
break;
case OMAP_DMA_DATA_TYPE_S32:
es = 4;
break;
default:
BUG();
return;
}
vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
BUG_ON(vxres < lcd_dma.xres);
#define PIXADDR(x, y) (lcd_dma.addr + \
((y) * vxres * yscale + (x) * xscale) * es)
#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
switch (lcd_dma.rotate) {
case 0:
if (!lcd_dma.mirror) {
top = PIXADDR(0, 0);
bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
/* 1510 DMA requires the bottom address to be 2 more
* than the actual last memory access location. */
if (cpu_is_omap1510() &&
lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
bottom += 2;
ei = PIXSTEP(0, 0, 1, 0);
fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
} else {
top = PIXADDR(lcd_dma.xres - 1, 0);
bottom = PIXADDR(0, lcd_dma.yres - 1);
ei = PIXSTEP(1, 0, 0, 0);
fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
}
en = lcd_dma.xres;
fn = lcd_dma.yres;
break;
case 90:
if (!lcd_dma.mirror) {
top = PIXADDR(0, lcd_dma.yres - 1);
bottom = PIXADDR(lcd_dma.xres - 1, 0);
ei = PIXSTEP(0, 1, 0, 0);
fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
} else {
top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
bottom = PIXADDR(0, 0);
ei = PIXSTEP(0, 1, 0, 0);
fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
}
en = lcd_dma.yres;
fn = lcd_dma.xres;
break;
case 180:
if (!lcd_dma.mirror) {
top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
bottom = PIXADDR(0, 0);
ei = PIXSTEP(1, 0, 0, 0);
fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
} else {
top = PIXADDR(0, lcd_dma.yres - 1);
bottom = PIXADDR(lcd_dma.xres - 1, 0);
ei = PIXSTEP(0, 0, 1, 0);
fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
}
en = lcd_dma.xres;
fn = lcd_dma.yres;
break;
case 270:
if (!lcd_dma.mirror) {
top = PIXADDR(lcd_dma.xres - 1, 0);
bottom = PIXADDR(0, lcd_dma.yres - 1);
ei = PIXSTEP(0, 0, 0, 1);
fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
} else {
top = PIXADDR(0, 0);
bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
ei = PIXSTEP(0, 0, 0, 1);
fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
}
en = lcd_dma.yres;
fn = lcd_dma.xres;
break;
default:
BUG();
return; /* Suppress warning about uninitialized vars */
}
if (cpu_is_omap1510()) {
omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
return;
}
/* 1610 regs */
omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
w = omap_readw(OMAP1610_DMA_LCD_CSDP);
w &= ~0x03;
w |= lcd_dma.data_type;
omap_writew(w, OMAP1610_DMA_LCD_CSDP);
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
/* Always set the source port as SDRAM for now*/
w &= ~(0x03 << 6);
if (lcd_dma.callback != NULL)
w |= 1 << 1; /* Block interrupt enable */
else
w &= ~(1 << 1);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
if (!(lcd_dma.rotate || lcd_dma.mirror ||
lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
return;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
/* Set the double-indexed addressing mode */
w |= (0x03 << 12);
omap_writew(w, OMAP1610_DMA_LCD_CCR);
omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
}
static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
{
u16 w;
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
if (unlikely(!(w & (1 << 3)))) {
printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
return IRQ_NONE;
}
/* Ack the IRQ */
w |= (1 << 3);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
lcd_dma.active = 0;
if (lcd_dma.callback != NULL)
lcd_dma.callback(w, lcd_dma.cb_data);
return IRQ_HANDLED;
}
int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
void *data)
{
spin_lock_irq(&lcd_dma.lock);
if (lcd_dma.reserved) {
spin_unlock_irq(&lcd_dma.lock);
printk(KERN_ERR "LCD DMA channel already reserved\n");
BUG();
return -EBUSY;
}
lcd_dma.reserved = 1;
spin_unlock_irq(&lcd_dma.lock);
lcd_dma.callback = callback;
lcd_dma.cb_data = data;
lcd_dma.active = 0;
lcd_dma.single_transfer = 0;
lcd_dma.rotate = 0;
lcd_dma.vxres = 0;
lcd_dma.mirror = 0;
lcd_dma.xscale = 0;
lcd_dma.yscale = 0;
lcd_dma.ext_ctrl = 0;
lcd_dma.src_port = 0;
return 0;
}
EXPORT_SYMBOL(omap_request_lcd_dma);
void omap_free_lcd_dma(void)
{
spin_lock(&lcd_dma.lock);
if (!lcd_dma.reserved) {
spin_unlock(&lcd_dma.lock);
printk(KERN_ERR "LCD DMA is not reserved\n");
BUG();
return;
}
if (!cpu_is_omap1510())
omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
OMAP1610_DMA_LCD_CCR);
lcd_dma.reserved = 0;
spin_unlock(&lcd_dma.lock);
}
EXPORT_SYMBOL(omap_free_lcd_dma);
void omap_enable_lcd_dma(void)
{
u16 w;
/*
* Set the Enable bit only if an external controller is
* connected. Otherwise the OMAP internal controller will
* start the transfer when it gets enabled.
*/
if (cpu_is_omap1510() || !lcd_dma.ext_ctrl)
return;
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w |= 1 << 8;
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
lcd_dma.active = 1;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
w |= 1 << 7;
omap_writew(w, OMAP1610_DMA_LCD_CCR);
}
EXPORT_SYMBOL(omap_enable_lcd_dma);
void omap_setup_lcd_dma(void)
{
BUG_ON(lcd_dma.active);
if (!cpu_is_omap1510()) {
/* Set some reasonable defaults */
omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
}
set_b1_regs();
if (!cpu_is_omap1510()) {
u16 w;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
/*
* If DMA was already active set the end_prog bit to have
* the programmed register set loaded into the active
* register set.
*/
w |= 1 << 11; /* End_prog */
if (!lcd_dma.single_transfer)
w |= (3 << 8); /* Auto_init, repeat */
omap_writew(w, OMAP1610_DMA_LCD_CCR);
}
}
EXPORT_SYMBOL(omap_setup_lcd_dma);
void omap_stop_lcd_dma(void)
{
u16 w;
lcd_dma.active = 0;
if (cpu_is_omap1510() || !lcd_dma.ext_ctrl)
return;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
w &= ~(1 << 7);
omap_writew(w, OMAP1610_DMA_LCD_CCR);
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w &= ~(1 << 8);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
}
EXPORT_SYMBOL(omap_stop_lcd_dma);
static int __init omap_init_lcd_dma(void)
{
int r;
if (cpu_is_omap16xx()) {
u16 w;
/* this would prevent OMAP sleep */
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w &= ~(1 << 8);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
}
spin_lock_init(&lcd_dma.lock);
r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
"LCD DMA", NULL);
if (r != 0)
printk(KERN_ERR "unable to request IRQ for LCD DMA "
"(error %d)\n", r);
return r;
}
arch_initcall(omap_init_lcd_dma);
arch/arm/mach-omap1/mux.c
View file @ 5ccf1978
......@@ -50,12 +50,18 @@ MUX_CFG_7XX("E3_7XX_KBC4", 13, 25, 0, 24, 1, 0)
MUX_CFG_7XX("AA17_7XX_USB_DM", 2, 21, 0, 20, 0, 0)
MUX_CFG_7XX("W16_7XX_USB_PU_EN", 2, 25, 0, 24, 0, 0)
MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 0, 28, 0, 0)
MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 6, 28, 1, 0)
MUX_CFG_7XX("W18_7XX_USB_DMCK_OUT",3, 3, 1, 2, 0, 0)
MUX_CFG_7XX("W19_7XX_USB_DCRST", 3, 7, 1, 6, 0, 0)
/* MMC Pins */
MUX_CFG_7XX("MMC_7XX_CMD", 2, 9, 0, 8, 1, 0)
MUX_CFG_7XX("MMC_7XX_CLK", 2, 13, 0, 12, 1, 0)
MUX_CFG_7XX("MMC_7XX_DAT0", 2, 17, 0, 16, 1, 0)
/* I2C interface */
MUX_CFG_7XX("I2C_7XX_SCL", 5, 1, 0, 0, 1, 0)
MUX_CFG_7XX("I2C_7XX_SDA", 5, 5, 0, 0, 1, 0)
};
#define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins)
#else
......
arch/arm/mach-omap2/Kconfig
View file @ 5ccf1978
......@@ -24,6 +24,18 @@ config ARCH_OMAP3430
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select ARCH_OMAP_OTG
config OMAP_PACKAGE_CBC
bool
config OMAP_PACKAGE_CBB
bool
config OMAP_PACKAGE_CUS
bool
config OMAP_PACKAGE_CBP
bool
comment "OMAP Board Type"
depends on ARCH_OMAP2 || ARCH_OMAP3 || ARCH_OMAP4
......@@ -52,14 +64,17 @@ config MACH_OMAP_2430SDP
config MACH_OMAP3_BEAGLE
bool "OMAP3 BEAGLE board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBB
config MACH_OMAP_LDP
bool "OMAP3 LDP board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBB
config MACH_OVERO
bool "Gumstix Overo board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBB
config MACH_OMAP3EVM
bool "OMAP 3530 EVM board"
......@@ -68,14 +83,22 @@ config MACH_OMAP3EVM
config MACH_OMAP3517EVM
bool "OMAP3517/ AM3517 EVM board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBB
config MACH_OMAP3_PANDORA
bool "OMAP3 Pandora"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBB
config MACH_OMAP3_TOUCHBOOK
bool "OMAP3 Touch Book"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select BACKLIGHT_CLASS_DEVICE
config MACH_OMAP_3430SDP
bool "OMAP 3430 SDP board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBB
config MACH_NOKIA_N800
bool
......@@ -96,26 +119,33 @@ config MACH_NOKIA_N8X0
config MACH_NOKIA_RX51
bool "Nokia RX-51 board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBB
config MACH_OMAP_ZOOM2
bool "OMAP3 Zoom2 board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBB
config MACH_OMAP_ZOOM3
bool "OMAP3630 Zoom3 board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBP
config MACH_CM_T35
bool "CompuLab CM-T35 module"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CUS
select OMAP_MUX
config MACH_IGEP0020
bool "IGEP0020"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBB
config MACH_OMAP_3630SDP
bool "OMAP3630 SDP board"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
select OMAP_PACKAGE_CBP
config MACH_OMAP_4430SDP
bool "OMAP 4430 SDP board"
......
arch/arm/mach-omap2/Makefile
View file @ 5ccf1978
......@@ -26,6 +26,9 @@ obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o
obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o
obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o
# Pin multiplexing
obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o
# SMS/SDRC
obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o
......@@ -61,6 +64,9 @@ iommu-$(CONFIG_ARCH_OMAP3) += omap3-iommu.o
obj-$(CONFIG_OMAP_IOMMU) += $(iommu-y)
i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o
obj-y += $(i2c-omap-m) $(i2c-omap-y)
# Specific board support
obj-$(CONFIG_MACH_OMAP_GENERIC) += board-generic.o
obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
......@@ -99,7 +105,8 @@ obj-$(CONFIG_MACH_CM_T35) += board-cm-t35.o \
mmc-twl4030.o
obj-$(CONFIG_MACH_IGEP0020) += board-igep0020.o \
mmc-twl4030.o
obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK) += board-omap3touchbook.o \
mmc-twl4030.o
obj-$(CONFIG_MACH_OMAP_4430SDP) += board-4430sdp.o
obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o
......
arch/arm/mach-omap2/board-3430sdp.c
View file @ 5ccf1978
......@@ -31,7 +31,6 @@
#include <asm/mach/map.h>
#include <plat/mcspi.h>
#include <plat/mux.h>
#include <plat/board.h>
#include <plat/usb.h>
#include <plat/common.h>
......@@ -42,6 +41,7 @@
#include <plat/control.h>
#include <plat/gpmc-smc91x.h>
#include "mux.h"
#include "sdram-qimonda-hyb18m512160af-6.h"
#include "mmc-twl4030.h"
......@@ -625,7 +625,9 @@ static inline void board_smc91x_init(void)
static void enable_board_wakeup_source(void)
{
omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */
/* T2 interrupt line (keypad) */
omap_mux_init_signal("sys_nirq",
OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
}
static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
......@@ -640,8 +642,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
.reset_gpio_port[2] = -EINVAL
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init omap_3430sdp_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap3430_i2c_init();
platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices));
if (omap_rev() > OMAP3430_REV_ES1_0)
......
arch/arm/mach-omap2/board-3630sdp.c
View file @ 5ccf1978
......@@ -23,6 +23,7 @@
#include <mach/board-zoom.h>
#include "mux.h"
#include "sdram-hynix-h8mbx00u0mer-0em.h"
#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
......@@ -48,7 +49,9 @@ static inline void board_smc91x_init(void)
static void enable_board_wakeup_source(void)
{
omap_cfg_reg(AF26_34XX_SYS_NIRQ); /* T2 interrupt line (keypad) */
/* T2 interrupt line (keypad) */
omap_mux_init_signal("sys_nirq",
OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
}
static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
......@@ -82,8 +85,17 @@ static void __init omap_sdp_init_irq(void)
omap_gpio_init();
}
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init omap_sdp_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
zoom_peripherals_init();
board_smc91x_init();
enable_board_wakeup_source();
......
arch/arm/mach-omap2/board-am3517evm.c
View file @ 5ccf1978
......@@ -30,6 +30,8 @@
#include <plat/common.h>
#include <plat/usb.h>
#include "mux.h"
/*
* Board initialization
*/
......@@ -60,8 +62,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
.reset_gpio_port[2] = -EINVAL
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init am3517_evm_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
platform_add_devices(am3517_evm_devices,
ARRAY_SIZE(am3517_evm_devices));
......
arch/arm/mach-omap2/board-apollon.c
View file @ 5ccf1978
......@@ -26,6 +26,7 @@
#include <linux/leds.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/smc91x.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
......@@ -120,6 +121,12 @@ static void __init apollon_flash_init(void)
apollon_flash_resource[0].end = base + SZ_128K - 1;
}
static struct smc91x_platdata appolon_smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource apollon_smc91x_resources[] = {
[0] = {
.flags = IORESOURCE_MEM,
......@@ -134,6 +141,9 @@ static struct resource apollon_smc91x_resources[] = {
static struct platform_device apollon_smc91x_device = {
.name = "smc91x",
.id = -1,
.dev = {
.platform_data = &appolon_smc91x_info,
},
.num_resources = ARRAY_SIZE(apollon_smc91x_resources),
.resource = apollon_smc91x_resources,
};
......
arch/arm/mach-omap2/board-cm-t35.c
View file @ 5ccf1978
......@@ -38,13 +38,13 @@
#include <plat/board.h>
#include <plat/common.h>
#include <plat/mux.h>
#include <plat/nand.h>
#include <plat/gpmc.h>
#include <plat/usb.h>
#include <mach/hardware.h>
#include "mux.h"
#include "sdram-micron-mt46h32m32lf-6.h"
#include "mmc-twl4030.h"
......@@ -482,8 +482,102 @@ static void __init cm_t35_map_io(void)
omap2_map_common_io();
}
static struct omap_board_mux board_mux[] __initdata = {
/* nCS and IRQ for CM-T35 ethernet */
OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0),
OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
/* nCS and IRQ for SB-T35 ethernet */
OMAP3_MUX(GPMC_NCS4, OMAP_MUX_MODE0),
OMAP3_MUX(GPMC_WAIT3, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP),
/* PENDOWN GPIO */
OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
/* mUSB */
OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
/* MMC 2 */
OMAP3_MUX(SDMMC2_DAT4, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
OMAP3_MUX(SDMMC2_DAT5, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
OMAP3_MUX(SDMMC2_DAT6, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
OMAP3_MUX(SDMMC2_DAT7, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
/* McSPI 1 */
OMAP3_MUX(MCSPI1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(MCSPI1_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(MCSPI1_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(MCSPI1_CS0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
/* McSPI 4 */
OMAP3_MUX(MCBSP1_CLKR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
OMAP3_MUX(MCBSP1_DX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
OMAP3_MUX(MCBSP1_DR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
OMAP3_MUX(MCBSP1_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP),
/* McBSP 2 */
OMAP3_MUX(MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
OMAP3_MUX(MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
/* serial ports */
OMAP3_MUX(MCBSP3_CLKX, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT),
OMAP3_MUX(MCBSP3_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT),
OMAP3_MUX(UART1_TX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(UART1_RX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
/* DSS */
OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA20, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
/* TPS IRQ */
OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \
OMAP_PIN_INPUT_PULLUP),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
static void __init cm_t35_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
omap_serial_init();
cm_t35_init_i2c();
cm_t35_init_nand();
......@@ -492,8 +586,6 @@ static void __init cm_t35_init(void)
cm_t35_init_led();
usb_musb_init();
omap_cfg_reg(AF26_34XX_SYS_NIRQ);
}
MACHINE_START(CM_T35, "Compulab CM-T35")
......
arch/arm/mach-omap2/board-igep0020.c
View file @ 5ccf1978
......@@ -27,9 +27,9 @@
#include <plat/board.h>
#include <plat/common.h>
#include <plat/gpmc.h>
#include <plat/mux.h>
#include <plat/usb.h>
#include "mux.h"
#include "mmc-twl4030.h"
#define IGEP2_SMSC911X_CS 5
......@@ -203,8 +203,17 @@ static int __init igep2_i2c_init(void)
return 0;
}
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init igep2_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
igep2_i2c_init();
omap_serial_init();
usb_musb_init();
......
arch/arm/mach-omap2/board-ldp.c
View file @ 5ccf1978
......@@ -43,6 +43,7 @@
#include <plat/control.h>
#include <plat/usb.h>
#include "mux.h"
#include "mmc-twl4030.h"
#define LDP_SMSC911X_CS 1
......@@ -374,8 +375,17 @@ static struct platform_device *ldp_devices[] __initdata = {
&ldp_gpio_keys_device,
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init omap_ldp_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_i2c_init();
platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
ts_gpio = 54;
......
arch/arm/mach-omap2/board-omap3beagle.c
View file @ 5ccf1978
......@@ -41,10 +41,10 @@
#include <plat/common.h>
#include <plat/gpmc.h>
#include <plat/nand.h>
#include <plat/mux.h>
#include <plat/usb.h>
#include <plat/timer-gp.h>
#include "mux.h"
#include "mmc-twl4030.h"
#define GPMC_CS0_BASE 0x60
......@@ -140,10 +140,10 @@ static int beagle_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
if (system_rev >= 0x20 && system_rev <= 0x34301000) {
omap_cfg_reg(AG9_34XX_GPIO23);
omap_mux_init_gpio(23, OMAP_PIN_INPUT);
mmc[0].gpio_wp = 23;
} else {
omap_cfg_reg(AH8_34XX_GPIO29);
omap_mux_init_gpio(29, OMAP_PIN_INPUT);
}
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
......@@ -422,14 +422,23 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
.reset_gpio_port[2] = -EINVAL
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init omap3_beagle_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap3_beagle_i2c_init();
platform_add_devices(omap3_beagle_devices,
ARRAY_SIZE(omap3_beagle_devices));
omap_serial_init();
omap_cfg_reg(J25_34XX_GPIO170);
omap_mux_init_gpio(170, OMAP_PIN_INPUT);
gpio_request(170, "DVI_nPD");
/* REVISIT leave DVI powered down until it's needed ... */
gpio_direction_output(170, true);
......@@ -439,8 +448,8 @@ static void __init omap3_beagle_init(void)
omap3beagle_flash_init();
/* Ensure SDRC pins are mux'd for self-refresh */
omap_cfg_reg(H16_34XX_SDRC_CKE0);
omap_cfg_reg(H17_34XX_SDRC_CKE1);
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
}
static void __init omap3_beagle_map_io(void)
......
arch/arm/mach-omap2/board-omap3evm.c
View file @ 5ccf1978
......@@ -38,11 +38,11 @@
#include <asm/mach/map.h>
#include <plat/board.h>
#include <plat/mux.h>
#include <plat/usb.h>
#include <plat/common.h>
#include <plat/mcspi.h>
#include "mux.h"
#include "sdram-micron-mt46h32m32lf-6.h"
#include "mmc-twl4030.h"
......@@ -223,7 +223,7 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
omap_cfg_reg(L8_34XX_GPIO63);
omap_mux_init_gpio(63, OMAP_PIN_INPUT);
mmc[0].gpio_cd = gpio + 0;
twl4030_mmc_init(mmc);
......@@ -422,9 +422,18 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
.reset_gpio_port[2] = -EINVAL
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init omap3_evm_init(void)
{
omap3_evm_get_revision();
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap3_evm_i2c_init();
......@@ -440,24 +449,24 @@ static void __init omap3_evm_init(void)
#endif
if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
/* enable EHCI VBUS using GPIO22 */
omap_cfg_reg(AF9_34XX_GPIO22);
omap_mux_init_gpio(22, OMAP_PIN_INPUT_PULLUP);
gpio_request(OMAP3_EVM_EHCI_VBUS, "enable EHCI VBUS");
gpio_direction_output(OMAP3_EVM_EHCI_VBUS, 0);
gpio_set_value(OMAP3_EVM_EHCI_VBUS, 1);
/* Select EHCI port on main board */
omap_cfg_reg(U3_34XX_GPIO61);
omap_mux_init_gpio(61, OMAP_PIN_INPUT_PULLUP);
gpio_request(OMAP3_EVM_EHCI_SELECT, "select EHCI port");
gpio_direction_output(OMAP3_EVM_EHCI_SELECT, 0);
gpio_set_value(OMAP3_EVM_EHCI_SELECT, 0);
/* setup EHCI phy reset config */
omap_cfg_reg(AH14_34XX_GPIO21);
omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
ehci_pdata.reset_gpio_port[1] = 21;
} else {
/* setup EHCI phy reset on MDC */
omap_cfg_reg(AF4_34XX_GPIO135_OUT);
omap_mux_init_gpio(135, OMAP_PIN_OUTPUT);
ehci_pdata.reset_gpio_port[1] = 135;
}
usb_musb_init();
......
arch/arm/mach-omap2/board-omap3pandora.c
View file @ 5ccf1978
......@@ -40,8 +40,8 @@
#include <mach/hardware.h>
#include <plat/mcspi.h>
#include <plat/usb.h>
#include <plat/mux.h>
#include "mux.h"
#include "sdram-micron-mt46h32m32lf-6.h"
#include "mmc-twl4030.h"
......@@ -98,10 +98,10 @@ static struct gpio_keys_button pandora_gpio_keys[] = {
GPIO_BUTTON_LOW(103, KEY_DOWN, "down"),
GPIO_BUTTON_LOW(96, KEY_LEFT, "left"),
GPIO_BUTTON_LOW(98, KEY_RIGHT, "right"),
GPIO_BUTTON_LOW(111, BTN_A, "a"),
GPIO_BUTTON_LOW(106, BTN_B, "b"),
GPIO_BUTTON_LOW(109, BTN_X, "x"),
GPIO_BUTTON_LOW(101, BTN_Y, "y"),
GPIO_BUTTON_LOW(109, KEY_KP1, "game 1"),
GPIO_BUTTON_LOW(111, KEY_KP2, "game 2"),
GPIO_BUTTON_LOW(106, KEY_KP3, "game 3"),
GPIO_BUTTON_LOW(101, KEY_KP4, "game 4"),
GPIO_BUTTON_LOW(102, BTN_TL, "l"),
GPIO_BUTTON_LOW(97, BTN_TL2, "l2"),
GPIO_BUTTON_LOW(105, BTN_TR, "r"),
......@@ -315,7 +315,7 @@ static int __init omap3pandora_i2c_init(void)
omap_register_i2c_bus(1, 2600, omap3pandora_i2c_boardinfo,
ARRAY_SIZE(omap3pandora_i2c_boardinfo));
/* i2c2 pins are not connected */
omap_register_i2c_bus(3, 400, NULL, 0);
omap_register_i2c_bus(3, 100, NULL, 0);
return 0;
}
......@@ -368,23 +368,8 @@ static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
}
};
static struct platform_device omap3pandora_lcd_device = {
.name = "pandora_lcd",
.id = -1,
};
static struct omap_lcd_config omap3pandora_lcd_config __initdata = {
.ctrl_name = "internal",
};
static struct omap_board_config_kernel omap3pandora_config[] __initdata = {
{ OMAP_TAG_LCD, &omap3pandora_lcd_config },
};
static void __init omap3pandora_init_irq(void)
{
omap_board_config = omap3pandora_config;
omap_board_config_size = ARRAY_SIZE(omap3pandora_config);
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
......@@ -392,7 +377,6 @@ static void __init omap3pandora_init_irq(void)
}
static struct platform_device *omap3pandora_devices[] __initdata = {
&omap3pandora_lcd_device,
&pandora_leds_gpio,
&pandora_keys_gpio,
};
......@@ -409,8 +393,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
.reset_gpio_port[2] = -EINVAL
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init omap3pandora_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap3pandora_i2c_init();
platform_add_devices(omap3pandora_devices,
ARRAY_SIZE(omap3pandora_devices));
......@@ -423,8 +416,8 @@ static void __init omap3pandora_init(void)
usb_musb_init();
/* Ensure SDRC pins are mux'd for self-refresh */
omap_cfg_reg(H16_34XX_SDRC_CKE0);
omap_cfg_reg(H17_34XX_SDRC_CKE1);
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
}
static void __init omap3pandora_map_io(void)
......
arch/arm/mach-omap2/board-omap3touchbook.c 0 → 100644
View file @ 5ccf1978
/*
* linux/arch/arm/mach-omap2/board-omap3touchbook.c
*
* Copyright (C) 2009 Always Innovating
*
* Modified from mach-omap2/board-omap3beagleboard.c
*
* Initial code: Grégoire Gentil, Tim Yamin
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/leds.h>
#include <linux/gpio.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/nand.h>
#include <plat/mcspi.h>
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
#include <linux/regulator/machine.h>
#include <linux/i2c/twl4030.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <plat/board.h>
#include <plat/common.h>
#include <plat/gpmc.h>
#include <plat/nand.h>
#include <plat/usb.h>
#include <plat/timer-gp.h>
#include "mux.h"
#include "mmc-twl4030.h"
#include <asm/setup.h>
#define GPMC_CS0_BASE 0x60
#define GPMC_CS_SIZE 0x30
#define NAND_BLOCK_SIZE SZ_128K
#define OMAP3_AC_GPIO 136
#define OMAP3_TS_GPIO 162
#define TB_BL_PWM_TIMER 9
#define TB_KILL_POWER_GPIO 168
unsigned long touchbook_revision;
static struct mtd_partition omap3touchbook_nand_partitions[] = {
/* All the partition sizes are listed in terms of NAND block size */
{
.name = "X-Loader",
.offset = 0,
.size = 4 * NAND_BLOCK_SIZE,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
{
.name = "U-Boot",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
.size = 15 * NAND_BLOCK_SIZE,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
{
.name = "U-Boot Env",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */
.size = 1 * NAND_BLOCK_SIZE,
},
{
.name = "Kernel",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
.size = 32 * NAND_BLOCK_SIZE,
},
{
.name = "File System",
.offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */
.size = MTDPART_SIZ_FULL,
},
};
static struct omap_nand_platform_data omap3touchbook_nand_data = {
.options = NAND_BUSWIDTH_16,
.parts = omap3touchbook_nand_partitions,
.nr_parts = ARRAY_SIZE(omap3touchbook_nand_partitions),
.dma_channel = -1, /* disable DMA in OMAP NAND driver */
.nand_setup = NULL,
.dev_ready = NULL,
};
static struct resource omap3touchbook_nand_resource = {
.flags = IORESOURCE_MEM,
};
static struct platform_device omap3touchbook_nand_device = {
.name = "omap2-nand",
.id = -1,
.dev = {
.platform_data = &omap3touchbook_nand_data,
},
.num_resources = 1,
.resource = &omap3touchbook_nand_resource,
};
#include "sdram-micron-mt46h32m32lf-6.h"
static struct twl4030_hsmmc_info mmc[] = {
{
.mmc = 1,
.wires = 8,
.gpio_wp = 29,
},
{} /* Terminator */
};
static struct platform_device omap3_touchbook_lcd_device = {
.name = "omap3touchbook_lcd",
.id = -1,
};
static struct omap_lcd_config omap3_touchbook_lcd_config __initdata = {
.ctrl_name = "internal",
};
static struct regulator_consumer_supply touchbook_vmmc1_supply = {
.supply = "vmmc",
};
static struct regulator_consumer_supply touchbook_vsim_supply = {
.supply = "vmmc_aux",
};
static struct gpio_led gpio_leds[];
static int touchbook_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
if (system_rev >= 0x20 && system_rev <= 0x34301000) {
omap_mux_init_gpio(23, OMAP_PIN_INPUT);
mmc[0].gpio_wp = 23;
} else {
omap_mux_init_gpio(29, OMAP_PIN_INPUT);
}
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
twl4030_mmc_init(mmc);
/* link regulators to MMC adapters */
touchbook_vmmc1_supply.dev = mmc[0].dev;
touchbook_vsim_supply.dev = mmc[0].dev;
/* REVISIT: need ehci-omap hooks for external VBUS
* power switch and overcurrent detect
*/
gpio_request(gpio + 1, "EHCI_nOC");
gpio_direction_input(gpio + 1);
/* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */
gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR");
gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0);
/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
return 0;
}
static struct twl4030_gpio_platform_data touchbook_gpio_data = {
.gpio_base = OMAP_MAX_GPIO_LINES,
.irq_base = TWL4030_GPIO_IRQ_BASE,
.irq_end = TWL4030_GPIO_IRQ_END,
.use_leds = true,
.pullups = BIT(1),
.pulldowns = BIT(2) | BIT(6) | BIT(7) | BIT(8) | BIT(13)
| BIT(15) | BIT(16) | BIT(17),
.setup = touchbook_twl_gpio_setup,
};
static struct regulator_consumer_supply touchbook_vdac_supply = {
.supply = "vdac",
.dev = &omap3_touchbook_lcd_device.dev,
};
static struct regulator_consumer_supply touchbook_vdvi_supply = {
.supply = "vdvi",
.dev = &omap3_touchbook_lcd_device.dev,
};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
static struct regulator_init_data touchbook_vmmc1 = {
.constraints = {
.min_uV = 1850000,
.max_uV = 3150000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &touchbook_vmmc1_supply,
};
/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
static struct regulator_init_data touchbook_vsim = {
.constraints = {
.min_uV = 1800000,
.max_uV = 3000000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &touchbook_vsim_supply,
};
/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
static struct regulator_init_data touchbook_vdac = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &touchbook_vdac_supply,
};
/* VPLL2 for digital video outputs */
static struct regulator_init_data touchbook_vpll2 = {
.constraints = {
.name = "VDVI",
.min_uV = 1800000,
.max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = &touchbook_vdvi_supply,
};
static struct twl4030_usb_data touchbook_usb_data = {
.usb_mode = T2_USB_MODE_ULPI,
};
static struct twl4030_codec_audio_data touchbook_audio_data = {
.audio_mclk = 26000000,
};
static struct twl4030_codec_data touchbook_codec_data = {
.audio_mclk = 26000000,
.audio = &touchbook_audio_data,
};
static struct twl4030_platform_data touchbook_twldata = {
.irq_base = TWL4030_IRQ_BASE,
.irq_end = TWL4030_IRQ_END,
/* platform_data for children goes here */
.usb = &touchbook_usb_data,
.gpio = &touchbook_gpio_data,
.codec = &touchbook_codec_data,
.vmmc1 = &touchbook_vmmc1,
.vsim = &touchbook_vsim,
.vdac = &touchbook_vdac,
.vpll2 = &touchbook_vpll2,
};
static struct i2c_board_info __initdata touchbook_i2c_boardinfo[] = {
{
I2C_BOARD_INFO("twl4030", 0x48),
.flags = I2C_CLIENT_WAKE,
.irq = INT_34XX_SYS_NIRQ,
.platform_data = &touchbook_twldata,
},
};
static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
{
I2C_BOARD_INFO("bq27200", 0x55),
},
};
static int __init omap3_touchbook_i2c_init(void)
{
/* Standard TouchBook bus */
omap_register_i2c_bus(1, 2600, touchbook_i2c_boardinfo,
ARRAY_SIZE(touchbook_i2c_boardinfo));
/* Additional TouchBook bus */
omap_register_i2c_bus(3, 100, touchBook_i2c_boardinfo,
ARRAY_SIZE(touchBook_i2c_boardinfo));
return 0;
}
static void __init omap3_ads7846_init(void)
{
if (gpio_request(OMAP3_TS_GPIO, "ads7846_pen_down")) {
printk(KERN_ERR "Failed to request GPIO %d for "
"ads7846 pen down IRQ\n", OMAP3_TS_GPIO);
return;
}
gpio_direction_input(OMAP3_TS_GPIO);
omap_set_gpio_debounce(OMAP3_TS_GPIO, 1);
omap_set_gpio_debounce_time(OMAP3_TS_GPIO, 0xa);
}
static struct ads7846_platform_data ads7846_config = {
.x_min = 100,
.y_min = 265,
.x_max = 3950,
.y_max = 3750,
.x_plate_ohms = 40,
.pressure_max = 255,
.debounce_max = 10,
.debounce_tol = 5,
.debounce_rep = 1,
.gpio_pendown = OMAP3_TS_GPIO,
.keep_vref_on = 1,
};
static struct omap2_mcspi_device_config ads7846_mcspi_config = {
.turbo_mode = 0,
.single_channel = 1, /* 0: slave, 1: master */
};
static struct spi_board_info omap3_ads7846_spi_board_info[] __initdata = {
{
.modalias = "ads7846",
.bus_num = 4,
.chip_select = 0,
.max_speed_hz = 1500000,
.controller_data = &ads7846_mcspi_config,
.irq = OMAP_GPIO_IRQ(OMAP3_TS_GPIO),
.platform_data = &ads7846_config,
}
};
static struct gpio_led gpio_leds[] = {
{
.name = "touchbook::usr0",
.default_trigger = "heartbeat",
.gpio = 150,
},
{
.name = "touchbook::usr1",
.default_trigger = "mmc0",
.gpio = 149,
},
{
.name = "touchbook::pmu_stat",
.gpio = -EINVAL, /* gets replaced */
.active_low = true,
},
};
static struct gpio_led_platform_data gpio_led_info = {
.leds = gpio_leds,
.num_leds = ARRAY_SIZE(gpio_leds),
};
static struct platform_device leds_gpio = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &gpio_led_info,
},
};
static struct gpio_keys_button gpio_buttons[] = {
{
.code = BTN_EXTRA,
.gpio = 7,
.desc = "user",
.wakeup = 1,
},
{
.code = KEY_POWER,
.gpio = 183,
.desc = "power",
.wakeup = 1,
},
};
static struct gpio_keys_platform_data gpio_key_info = {
.buttons = gpio_buttons,
.nbuttons = ARRAY_SIZE(gpio_buttons),
};
static struct platform_device keys_gpio = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &gpio_key_info,
},
};
static struct omap_board_config_kernel omap3_touchbook_config[] __initdata = {
{ OMAP_TAG_LCD, &omap3_touchbook_lcd_config },
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init omap3_touchbook_init_irq(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_board_config = omap3_touchbook_config;
omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config);
omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
mt46h32m32lf6_sdrc_params);
omap_init_irq();
#ifdef CONFIG_OMAP_32K_TIMER
omap2_gp_clockevent_set_gptimer(12);
#endif
omap_gpio_init();
}
static struct platform_device *omap3_touchbook_devices[] __initdata = {
&omap3_touchbook_lcd_device,
&leds_gpio,
&keys_gpio,
};
static void __init omap3touchbook_flash_init(void)
{
u8 cs = 0;
u8 nandcs = GPMC_CS_NUM + 1;
u32 gpmc_base_add = OMAP34XX_GPMC_VIRT;
/* find out the chip-select on which NAND exists */
while (cs < GPMC_CS_NUM) {
u32 ret = 0;
ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
if ((ret & 0xC00) == 0x800) {
printk(KERN_INFO "Found NAND on CS%d\n", cs);
if (nandcs > GPMC_CS_NUM)
nandcs = cs;
}
cs++;
}
if (nandcs > GPMC_CS_NUM) {
printk(KERN_INFO "NAND: Unable to find configuration "
"in GPMC\n ");
return;
}
if (nandcs < GPMC_CS_NUM) {
omap3touchbook_nand_data.cs = nandcs;
omap3touchbook_nand_data.gpmc_cs_baseaddr = (void *)
(gpmc_base_add + GPMC_CS0_BASE + nandcs * GPMC_CS_SIZE);
omap3touchbook_nand_data.gpmc_baseaddr =
(void *) (gpmc_base_add);
printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
if (platform_device_register(&omap3touchbook_nand_device) < 0)
printk(KERN_ERR "Unable to register NAND device\n");
}
}
static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
.port_mode[0] = EHCI_HCD_OMAP_MODE_PHY,
.port_mode[1] = EHCI_HCD_OMAP_MODE_PHY,
.port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN,
.phy_reset = true,
.reset_gpio_port[0] = -EINVAL,
.reset_gpio_port[1] = 147,
.reset_gpio_port[2] = -EINVAL
};
static void omap3_touchbook_poweroff(void)
{
int r;
r = gpio_request(TB_KILL_POWER_GPIO, "DVI reset");
if (r < 0) {
printk(KERN_ERR "Unable to get kill power GPIO\n");
return;
}
gpio_direction_output(TB_KILL_POWER_GPIO, 0);
}
static void __init early_touchbook_revision(char **p)
{
if (!*p)
return;
strict_strtoul(*p, 10, &touchbook_revision);
}
__early_param("tbr=", early_touchbook_revision);
static void __init omap3_touchbook_init(void)
{
pm_power_off = omap3_touchbook_poweroff;
omap3_touchbook_i2c_init();
platform_add_devices(omap3_touchbook_devices,
ARRAY_SIZE(omap3_touchbook_devices));
omap_serial_init();
omap_mux_init_gpio(170, OMAP_PIN_INPUT);
gpio_request(176, "DVI_nPD");
/* REVISIT leave DVI powered down until it's needed ... */
gpio_direction_output(176, true);
/* Touchscreen and accelerometer */
spi_register_board_info(omap3_ads7846_spi_board_info,
ARRAY_SIZE(omap3_ads7846_spi_board_info));
omap3_ads7846_init();
usb_musb_init();
usb_ehci_init(&ehci_pdata);
omap3touchbook_flash_init();
/* Ensure SDRC pins are mux'd for self-refresh */
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
}
static void __init omap3_touchbook_map_io(void)
{
omap2_set_globals_343x();
omap2_map_common_io();
}
MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
/* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */
.phys_io = 0x48000000,
.io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
.boot_params = 0x80000100,
.map_io = omap3_touchbook_map_io,
.init_irq = omap3_touchbook_init_irq,
.init_machine = omap3_touchbook_init,
.timer = &omap_timer,
MACHINE_END
arch/arm/mach-omap2/board-overo.c
View file @ 5ccf1978
......@@ -44,9 +44,9 @@
#include <plat/gpmc.h>
#include <mach/hardware.h>
#include <plat/nand.h>
#include <plat/mux.h>
#include <plat/usb.h>
#include "mux.h"
#include "sdram-micron-mt46h32m32lf-6.h"
#include "mmc-twl4030.h"
......@@ -405,9 +405,17 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initconst = {
.reset_gpio_port[2] = -EINVAL
};
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init overo_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
overo_i2c_init();
platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices));
omap_serial_init();
......@@ -418,8 +426,8 @@ static void __init overo_init(void)
overo_init_smsc911x();
/* Ensure SDRC pins are mux'd for self-refresh */
omap_cfg_reg(H16_34XX_SDRC_CKE0);
omap_cfg_reg(H17_34XX_SDRC_CKE1);
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
if ((gpio_request(OVERO_GPIO_W2W_NRESET,
"OVERO_GPIO_W2W_NRESET") == 0) &&
......
arch/arm/mach-omap2/board-rx51-peripherals.c
View file @ 5ccf1978
......@@ -33,6 +33,7 @@
#include <plat/onenand.h>
#include <plat/gpmc-smc91x.h>
#include "mux.h"
#include "mmc-twl4030.h"
#define SYSTEM_REV_B_USES_VAUX3 0x1699
......@@ -59,7 +60,7 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
.bus_num = 4,
.chip_select = 0,
.max_speed_hz = 48000000,
.mode = SPI_MODE_2,
.mode = SPI_MODE_3,
.controller_data = &wl1251_mcspi_config,
.platform_data = &wl1251_pdata,
},
......@@ -630,9 +631,9 @@ static struct omap_smc91x_platform_data board_smc91x_data = {
static void __init board_smc91x_init(void)
{
omap_cfg_reg(U8_34XX_GPIO54_DOWN);
omap_cfg_reg(G25_34XX_GPIO86_OUT);
omap_cfg_reg(H19_34XX_GPIO164_OUT);
omap_mux_init_gpio(54, OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_gpio(86, OMAP_PIN_OUTPUT);
omap_mux_init_gpio(164, OMAP_PIN_OUTPUT);
gpmc_smc91x_init(&board_smc91x_data);
}
......
arch/arm/mach-omap2/board-rx51.c
View file @ 5ccf1978
......@@ -23,13 +23,14 @@
#include <asm/mach/map.h>
#include <plat/mcspi.h>
#include <plat/mux.h>
#include <plat/board.h>
#include <plat/common.h>
#include <plat/dma.h>
#include <plat/gpmc.h>
#include <plat/usb.h>
#include "mux.h"
struct omap_sdrc_params *rx51_get_sdram_timings(void);
static struct omap_lcd_config rx51_lcd_config = {
......@@ -69,15 +70,24 @@ static void __init rx51_init_irq(void)
extern void __init rx51_peripherals_init(void);
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init rx51_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap_serial_init();
usb_musb_init();
rx51_peripherals_init();
/* Ensure SDRC pins are mux'd for self-refresh */
omap_cfg_reg(H16_34XX_SDRC_CKE0);
omap_cfg_reg(H17_34XX_SDRC_CKE1);
omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
}
static void __init rx51_map_io(void)
......
arch/arm/mach-omap2/board-zoom-peripherals.c
View file @ 5ccf1978
......@@ -152,14 +152,20 @@ static struct regulator_init_data zoom_vsim = {
static struct twl4030_hsmmc_info mmc[] __initdata = {
{
.name = "external",
.mmc = 1,
.wires = 4,
.gpio_wp = -EINVAL,
.power_saving = true,
},
{
.name = "internal",
.mmc = 2,
.wires = 4,
.wires = 8,
.gpio_cd = -EINVAL,
.gpio_wp = -EINVAL,
.nonremovable = true,
.power_saving = true,
},
{} /* Terminator */
};
......@@ -167,11 +173,8 @@ static struct twl4030_hsmmc_info mmc[] __initdata = {
static int zoom_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
/* gpio + 0 is "mmc0_cd" (input/IRQ),
* gpio + 1 is "mmc1_cd" (input/IRQ)
*/
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
mmc[1].gpio_cd = gpio + 1;
twl4030_mmc_init(mmc);
/* link regulators to MMC adapters ... we "know" the
......@@ -236,6 +239,7 @@ static struct twl4030_platform_data zoom_twldata = {
.gpio = &zoom_gpio_data,
.keypad = &zoom_kp_twl4030_data,
.codec = &zoom_codec_data,
.vmmc1 = &zoom_vmmc1,
.vmmc2 = &zoom_vmmc2,
.vsim = &zoom_vsim,
......
arch/arm/mach-omap2/board-zoom2.c
View file @ 5ccf1978
......@@ -23,6 +23,7 @@
#include <mach/board-zoom.h>
#include "mux.h"
#include "sdram-micron-mt46h32m32lf-6.h"
static void __init omap_zoom2_init_irq(void)
......@@ -68,8 +69,17 @@ static struct twl4030_platform_data zoom2_twldata = {
#endif
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init omap_zoom2_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
zoom_peripherals_init();
zoom_debugboard_init();
}
......
arch/arm/mach-omap2/board-zoom3.c
View file @ 5ccf1978
......@@ -21,6 +21,7 @@
#include <plat/common.h>
#include <plat/board.h>
#include "mux.h"
#include "sdram-hynix-h8mbx00u0mer-0em.h"
static void __init omap_zoom_map_io(void)
......@@ -42,8 +43,17 @@ static void __init omap_zoom_init_irq(void)
omap_gpio_init();
}
#ifdef CONFIG_OMAP_MUX
static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define board_mux NULL
#endif
static void __init omap_zoom_init(void)
{
omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
zoom_peripherals_init();
zoom_debugboard_init();
}
......
arch/arm/mach-omap2/devices.c
View file @ 5ccf1978
......@@ -27,6 +27,8 @@
#include <mach/gpio.h>
#include <plat/mmc.h>
#include "mux.h"
#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
static struct resource cam_resources[] = {
......@@ -595,27 +597,40 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
if (cpu_is_omap34xx()) {
if (controller_nr == 0) {
omap_cfg_reg(N28_3430_MMC1_CLK);
omap_cfg_reg(M27_3430_MMC1_CMD);
omap_cfg_reg(N27_3430_MMC1_DAT0);
omap_mux_init_signal("sdmmc1_clk",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_cmd",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat0",
OMAP_PIN_INPUT_PULLUP);
if (mmc_controller->slots[0].wires == 4 ||
mmc_controller->slots[0].wires == 8) {
omap_cfg_reg(N26_3430_MMC1_DAT1);
omap_cfg_reg(N25_3430_MMC1_DAT2);
omap_cfg_reg(P28_3430_MMC1_DAT3);
omap_mux_init_signal("sdmmc1_dat1",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat2",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat3",
OMAP_PIN_INPUT_PULLUP);
}
if (mmc_controller->slots[0].wires == 8) {
omap_cfg_reg(P27_3430_MMC1_DAT4);
omap_cfg_reg(P26_3430_MMC1_DAT5);
omap_cfg_reg(R27_3430_MMC1_DAT6);
omap_cfg_reg(R25_3430_MMC1_DAT7);
omap_mux_init_signal("sdmmc1_dat4",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat5",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat6",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc1_dat7",
OMAP_PIN_INPUT_PULLUP);
}
}
if (controller_nr == 1) {
/* MMC2 */
omap_cfg_reg(AE2_3430_MMC2_CLK);
omap_cfg_reg(AG5_3430_MMC2_CMD);
omap_cfg_reg(AH5_3430_MMC2_DAT0);
omap_mux_init_signal("sdmmc2_clk",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_cmd",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat0",
OMAP_PIN_INPUT_PULLUP);
/*
* For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
......@@ -623,15 +638,22 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
*/
if (mmc_controller->slots[0].wires == 4 ||
mmc_controller->slots[0].wires == 8) {
omap_cfg_reg(AH4_3430_MMC2_DAT1);
omap_cfg_reg(AG4_3430_MMC2_DAT2);
omap_cfg_reg(AF4_3430_MMC2_DAT3);
omap_mux_init_signal("sdmmc2_dat1",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat2",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat3",
OMAP_PIN_INPUT_PULLUP);
}
if (mmc_controller->slots[0].wires == 8) {
omap_cfg_reg(AE4_3430_MMC2_DAT4);
omap_cfg_reg(AH3_3430_MMC2_DAT5);
omap_cfg_reg(AF3_3430_MMC2_DAT6);
omap_cfg_reg(AE3_3430_MMC2_DAT7);
omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
OMAP_PIN_INPUT_PULLUP);
}
}
......
arch/arm/mach-omap2/gpmc-smc91x.c
View file @ 5ccf1978
......@@ -33,17 +33,19 @@ static struct resource gpmc_smc91x_resources[] = {
};
static struct smc91x_platdata gpmc_smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_0,
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_0,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct platform_device gpmc_smc91x_device = {
.name = "smc91x",
.id = -1,
.num_resources = ARRAY_SIZE(gpmc_smc91x_resources),
.resource = gpmc_smc91x_resources,
.dev = {
.platform_data = &gpmc_smc91x_info,
},
.num_resources = ARRAY_SIZE(gpmc_smc91x_resources),
.resource = gpmc_smc91x_resources,
};
/*
......
arch/arm/mach-omap2/i2c.c 0 → 100644
View file @ 5ccf1978
/*
* Helper module for board specific I2C bus registration
*
* Copyright (C) 2009 Nokia Corporation.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#include <plat/cpu.h>
#include <plat/i2c.h>
#include <plat/mux.h>
#include "mux.h"
int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len)
{
if (cpu_is_omap24xx()) {
const int omap24xx_pins[][2] = {
{ M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA },
{ J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA },
};
int scl, sda;
scl = omap24xx_pins[bus_id - 1][0];
sda = omap24xx_pins[bus_id - 1][1];
omap_cfg_reg(sda);
omap_cfg_reg(scl);
}
/* First I2C bus is not muxable */
if (cpu_is_omap34xx() && bus_id > 1) {
char mux_name[sizeof("i2c2_scl.i2c2_scl")];
sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id);
omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
}
return omap_plat_register_i2c_bus(bus_id, clkrate, info, len);
}
arch/arm/mach-omap2/id.c
View file @ 5ccf1978
......@@ -246,6 +246,31 @@ void __init omap3_check_revision(void)
}
}
void __init omap4_check_revision(void)
{
u32 idcode;
u16 hawkeye;
u8 rev;
char *rev_name = "ES1.0";
/*
* The IC rev detection is done with hawkeye and rev.
* Note that rev does not map directly to defined processor
* revision numbers as ES1.0 uses value 0.
*/
idcode = read_tap_reg(OMAP_TAP_IDCODE);
hawkeye = (idcode >> 12) & 0xffff;
rev = (idcode >> 28) & 0xff;
if ((hawkeye == 0xb852) && (rev == 0x0)) {
omap_revision = OMAP4430_REV_ES1_0;
pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
return;
}
pr_err("Unknown OMAP4 CPU id\n");
}
#define OMAP3_SHOW_FEATURE(feat) \
if (omap3_has_ ##feat()) \
printk(#feat" ");
......@@ -277,10 +302,10 @@ void __init omap3_cpuinfo(void)
} else if (omap3_has_iva() && omap3_has_sgx()) {
/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
strcpy(cpu_name, "OMAP3430/3530");
} else if (omap3_has_sgx()) {
} else if (omap3_has_iva()) {
omap_revision = OMAP3525_REV(rev);
strcpy(cpu_name, "OMAP3525");
} else if (omap3_has_iva()) {
} else if (omap3_has_sgx()) {
omap_revision = OMAP3515_REV(rev);
strcpy(cpu_name, "OMAP3515");
} else {
......@@ -336,7 +361,7 @@ void __init omap2_check_revision(void)
omap3_check_features();
omap3_cpuinfo();
} else if (cpu_is_omap44xx()) {
printk(KERN_INFO "FIXME: CPU revision = OMAP4430\n");
omap4_check_revision();
return;
} else {
pr_err("OMAP revision unknown, please fix!\n");
......
arch/arm/mach-omap2/io.c
View file @ 5ccf1978
......@@ -33,6 +33,7 @@
#include <plat/sdrc.h>
#include <plat/gpmc.h>
#include <plat/serial.h>
#include <plat/mux.h>
#include <plat/vram.h>
#include "clock.h"
......
arch/arm/mach-omap2/mux.c
View file @ 5ccf1978
......@@ -27,19 +27,52 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/list.h>
#include <linux/ctype.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/uaccess.h>
#include <asm/system.h>
#include <plat/control.h>
#include <plat/mux.h>
#ifdef CONFIG_OMAP_MUX
#include "mux.h"
#define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */
#define OMAP_MUX_BASE_SZ 0x5ca
struct omap_mux_entry {
struct omap_mux mux;
struct list_head node;
};
static unsigned long mux_phys;
static void __iomem *mux_base;
static inline u16 omap_mux_read(u16 reg)
{
if (cpu_is_omap24xx())
return __raw_readb(mux_base + reg);
else
return __raw_readw(mux_base + reg);
}
static inline void omap_mux_write(u16 val, u16 reg)
{
if (cpu_is_omap24xx())
__raw_writeb(val, mux_base + reg);
else
__raw_writew(val, mux_base + reg);
}
#if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_OMAP_MUX)
static struct omap_mux_cfg arch_mux_cfg;
/* NOTE: See mux.h for the enumeration */
#ifdef CONFIG_ARCH_OMAP24XX
static struct pin_config __initdata_or_module omap24xx_pins[] = {
/*
* description mux mux pull pull debug
......@@ -249,342 +282,14 @@ MUX_CFG_24XX("AF19_2430_GPIO_85", 0x0113, 3, 0, 0, 1)
#define OMAP24XX_PINS_SZ ARRAY_SIZE(omap24xx_pins)
#else
#define omap24xx_pins NULL
#define OMAP24XX_PINS_SZ 0
#endif /* CONFIG_ARCH_OMAP24XX */
#ifdef CONFIG_ARCH_OMAP34XX
static struct pin_config __initdata_or_module omap34xx_pins[] = {
/*
* Name, reg-offset,
* mux-mode | [active-mode | off-mode]
*/
/* 34xx I2C */
MUX_CFG_34XX("K21_34XX_I2C1_SCL", 0x1ba,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("J21_34XX_I2C1_SDA", 0x1bc,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AF15_34XX_I2C2_SCL", 0x1be,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AE15_34XX_I2C2_SDA", 0x1c0,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AF14_34XX_I2C3_SCL", 0x1c2,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AG14_34XX_I2C3_SDA", 0x1c4,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AD26_34XX_I2C4_SCL", 0xa00,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AE26_34XX_I2C4_SDA", 0xa02,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
MUX_CFG_34XX("Y8_3430_USB1HS_PHY_CLK", 0x5da,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX("AA14_3430_USB1HS_PHY_DIR", 0x5ec,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AA11_3430_USB1HS_PHY_NXT", 0x5ee,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("W13_3430_USB1HS_PHY_D0", 0x5dc,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("W12_3430_USB1HS_PHY_D1", 0x5de,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("W11_3430_USB1HS_PHY_D2", 0x5e0,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("Y11_3430_USB1HS_PHY_D3", 0x5ea,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("W9_3430_USB1HS_PHY_D4", 0x5e4,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("Y12_3430_USB1HS_PHY_D5", 0x5e6,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("W8_3430_USB1HS_PHY_D6", 0x5e8,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("Y13_3430_USB1HS_PHY_D7", 0x5e2,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
/* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
MUX_CFG_34XX("AA8_3430_USB2HS_PHY_CLK", 0x5f0,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX("AA10_3430_USB2HS_PHY_STP", 0x5f2,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX("AA9_3430_USB2HS_PHY_DIR", 0x5f4,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AB11_3430_USB2HS_PHY_NXT", 0x5f6,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AB10_3430_USB2HS_PHY_D0", 0x5f8,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AB9_3430_USB2HS_PHY_D1", 0x5fa,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("W3_3430_USB2HS_PHY_D2", 0x1d4,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("T4_3430_USB2HS_PHY_D3", 0x1de,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("T3_3430_USB2HS_PHY_D4", 0x1d8,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("R3_3430_USB2HS_PHY_D5", 0x1da,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("R4_3430_USB2HS_PHY_D6", 0x1dc,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("T2_3430_USB2HS_PHY_D7", 0x1d6,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
/* TLL - HSUSB: 12-pin TLL Port 1*/
MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR", 0x5ec,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT", 0x5ee,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("W11_3430_USB1HS_TLL_D2", 0x5e0,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("Y11_3430_USB1HS_TLL_D3", 0x5ea,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("W9_3430_USB1HS_TLL_D4", 0x5e4,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("Y12_3430_USB1HS_TLL_D5", 0x5e6,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("W8_3430_USB1HS_TLL_D6", 0x5e8,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("Y13_3430_USB1HS_TLL_D7", 0x5e2,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
/* TLL - HSUSB: 12-pin TLL Port 2*/
MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP", 0x5f2,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT", 0x5f6,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("W3_3430_USB2HS_TLL_D2", 0x1d4,
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("T4_3430_USB2HS_TLL_D3", 0x1de,
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("T3_3430_USB2HS_TLL_D4", 0x1d8,
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("R3_3430_USB2HS_TLL_D5", 0x1da,
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("R4_3430_USB2HS_TLL_D6", 0x1dc,
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("T2_3430_USB2HS_TLL_D7", 0x1d6,
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
/* TLL - HSUSB: 12-pin TLL Port 3*/
MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("Y5_3430_USB3HS_TLL_D2", 0x188,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("W5_3430_USB3HS_TLL_D3", 0x18a,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AB12_3430_USB3HS_TLL_D4", 0x16c,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AB13_3430_USB3HS_TLL_D5", 0x16e,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AA13_3430_USB3HS_TLL_D6", 0x170,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
/* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
MUX_CFG_34XX("AF10_3430_USB1FS_PHY_MM1_RXDP", 0x5d8,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AG9_3430_USB1FS_PHY_MM1_RXDM", 0x5ee,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("W13_3430_USB1FS_PHY_MM1_RXRCV", 0x5dc,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("W12_3430_USB1FS_PHY_MM1_TXSE0", 0x5de,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("W11_3430_USB1FS_PHY_MM1_TXDAT", 0x5e0,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("Y11_3430_USB1FS_PHY_MM1_TXEN_N", 0x5ea,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
/* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
MUX_CFG_34XX("AF7_3430_USB2FS_PHY_MM2_RXDP", 0x5f2,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AH7_3430_USB2FS_PHY_MM2_RXDM", 0x5f6,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AB10_3430_USB2FS_PHY_MM2_RXRCV", 0x5f8,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AB9_3430_USB2FS_PHY_MM2_TXSE0", 0x5fa,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("W3_3430_USB2FS_PHY_MM2_TXDAT", 0x1d4,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("T4_3430_USB2FS_PHY_MM2_TXEN_N", 0x1de,
OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
/* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
MUX_CFG_34XX("AH3_3430_USB3FS_PHY_MM3_RXDP", 0x166,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AE3_3430_USB3FS_PHY_MM3_RXDM", 0x16a,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AD1_3430_USB3FS_PHY_MM3_RXRCV", 0x186,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AE1_3430_USB3FS_PHY_MM3_TXSE0", 0x184,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AD2_3430_USB3FS_PHY_MM3_TXDAT", 0x188,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a,
OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
/* 34XX GPIO - bidirectional, unless the name has an "_OUT" suffix.
* (Always specify PIN_INPUT, except for names suffixed by "_OUT".)
* No internal pullup/pulldown without "_UP" or "_DOWN" suffix.
*/
MUX_CFG_34XX("AF26_34XX_GPIO0", 0x1e0,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
MUX_CFG_34XX("AF22_34XX_GPIO9", 0xa18,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
MUX_CFG_34XX("AG9_34XX_GPIO23", 0x5ee,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
MUX_CFG_34XX("AH8_34XX_GPIO29", 0x5fa,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
MUX_CFG_34XX("U8_34XX_GPIO54_OUT", 0x0b4,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX("U8_34XX_GPIO54_DOWN", 0x0b4,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN)
MUX_CFG_34XX("L8_34XX_GPIO63", 0x0ce,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
MUX_CFG_34XX("G25_34XX_GPIO86_OUT", 0x0fc,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX("AG4_34XX_GPIO134_OUT", 0x160,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX("AF4_34XX_GPIO135_OUT", 0x162,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX("AE4_34XX_GPIO136_OUT", 0x164,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX("AF6_34XX_GPIO140_UP", 0x16c,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AE6_34XX_GPIO141", 0x16e,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
MUX_CFG_34XX("AF5_34XX_GPIO142", 0x170,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
MUX_CFG_34XX("AE5_34XX_GPIO143", 0x172,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT)
/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
MUX_CFG_34XX("H16_34XX_SDRC_CKE0", 0x262,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
MUX_CFG_34XX("H17_34XX_SDRC_CKE1", 0x264,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_OUTPUT)
/* MMC1 */
MUX_CFG_34XX("N28_3430_MMC1_CLK", 0x144,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("M27_3430_MMC1_CMD", 0x146,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("N27_3430_MMC1_DAT0", 0x148,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("N26_3430_MMC1_DAT1", 0x14a,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("N25_3430_MMC1_DAT2", 0x14c,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("P28_3430_MMC1_DAT3", 0x14e,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("P27_3430_MMC1_DAT4", 0x150,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("P26_3430_MMC1_DAT5", 0x152,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("R27_3430_MMC1_DAT6", 0x154,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("R25_3430_MMC1_DAT7", 0x156,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
/* MMC2 */
MUX_CFG_34XX("AE2_3430_MMC2_CLK", 0x158,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AG5_3430_MMC2_CMD", 0x15A,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AH5_3430_MMC2_DAT0", 0x15c,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AH4_3430_MMC2_DAT1", 0x15e,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AG4_3430_MMC2_DAT2", 0x160,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AF4_3430_MMC2_DAT3", 0x162,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AE4_3430_MMC2_DAT4", 0x164,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AH3_3430_MMC2_DAT5", 0x166,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AF3_3430_MMC2_DAT6", 0x168,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AE3_3430_MMC2_DAT7", 0x16A,
OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
/* MMC3 */
MUX_CFG_34XX("AF10_3430_MMC3_CLK", 0x5d8,
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AC3_3430_MMC3_CMD", 0x1d0,
OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AE11_3430_MMC3_DAT0", 0x5e4,
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AH9_3430_MMC3_DAT1", 0x5e6,
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AF13_3430_MMC3_DAT2", 0x5e8,
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AF13_3430_MMC3_DAT3", 0x5e2,
OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLUP)
/* SYS_NIRQ T2 INT1 */
MUX_CFG_34XX("AF26_34XX_SYS_NIRQ", 0x1E0,
OMAP3_WAKEUP_EN | OMAP34XX_PIN_INPUT_PULLUP |
OMAP34XX_MUX_MODE0)
/* EHCI GPIO's on OMAP3EVM (Rev >= E) */
MUX_CFG_34XX("AH14_34XX_GPIO21", 0x5ea,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("AF9_34XX_GPIO22", 0x5ec,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP)
MUX_CFG_34XX("U3_34XX_GPIO61", 0x0c8,
OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP)
};
#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
#else
#define omap34xx_pins NULL
#define OMAP34XX_PINS_SZ 0
#endif /* CONFIG_ARCH_OMAP34XX */
#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg)
{
u16 orig;
u8 warn = 0, debug = 0;
if (cpu_is_omap24xx())
orig = omap_ctrl_readb(cfg->mux_reg);
else
orig = omap_ctrl_readw(cfg->mux_reg);
orig = omap_mux_read(cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
#ifdef CONFIG_OMAP_MUX_DEBUG
debug = cfg->debug;
......@@ -600,7 +305,6 @@ static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 r
#define omap2_cfg_debug(x, y) do {} while (0)
#endif
#ifdef CONFIG_ARCH_OMAP24XX
static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
{
static DEFINE_SPINLOCK(mux_spin_lock);
......@@ -614,47 +318,692 @@ static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
if (cfg->pu_pd_val)
reg |= OMAP2_PULL_UP;
omap2_cfg_debug(cfg, reg);
omap_ctrl_writeb(reg, cfg->mux_reg);
omap_mux_write(reg, cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
spin_unlock_irqrestore(&mux_spin_lock, flags);
return 0;
}
int __init omap2_mux_init(void)
{
u32 mux_pbase;
if (cpu_is_omap2420())
mux_pbase = OMAP2420_CTRL_BASE + OMAP_MUX_BASE_OFFSET;
else if (cpu_is_omap2430())
mux_pbase = OMAP243X_CTRL_BASE + OMAP_MUX_BASE_OFFSET;
else
return -ENODEV;
mux_base = ioremap(mux_pbase, OMAP_MUX_BASE_SZ);
if (!mux_base) {
printk(KERN_ERR "mux: Could not ioremap\n");
return -ENODEV;
}
if (cpu_is_omap24xx()) {
arch_mux_cfg.pins = omap24xx_pins;
arch_mux_cfg.size = OMAP24XX_PINS_SZ;
arch_mux_cfg.cfg_reg = omap24xx_cfg_reg;
return omap_mux_register(&arch_mux_cfg);
}
return 0;
}
#else
#define omap24xx_cfg_reg NULL
#endif
int __init omap2_mux_init(void)
{
return 0;
}
#endif /* CONFIG_OMAP_MUX */
/*----------------------------------------------------------------------------*/
#ifdef CONFIG_ARCH_OMAP34XX
static int __init_or_module omap34xx_cfg_reg(const struct pin_config *cfg)
static LIST_HEAD(muxmodes);
static DEFINE_MUTEX(muxmode_mutex);
#ifdef CONFIG_OMAP_MUX
static char *omap_mux_options;
int __init omap_mux_init_gpio(int gpio, int val)
{
static DEFINE_SPINLOCK(mux_spin_lock);
unsigned long flags;
u16 reg = 0;
struct omap_mux_entry *e;
int found = 0;
if (!gpio)
return -EINVAL;
list_for_each_entry(e, &muxmodes, node) {
struct omap_mux *m = &e->mux;
if (gpio == m->gpio) {
u16 old_mode;
u16 mux_mode;
old_mode = omap_mux_read(m->reg_offset);
mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
mux_mode |= OMAP_MUX_MODE4;
printk(KERN_DEBUG "mux: Setting signal "
"%s.gpio%i 0x%04x -> 0x%04x\n",
m->muxnames[0], gpio, old_mode, mux_mode);
omap_mux_write(mux_mode, m->reg_offset);
found++;
}
}
spin_lock_irqsave(&mux_spin_lock, flags);
reg |= cfg->mux_val;
omap2_cfg_debug(cfg, reg);
omap_ctrl_writew(reg, cfg->mux_reg);
spin_unlock_irqrestore(&mux_spin_lock, flags);
if (found == 1)
return 0;
if (found > 1) {
printk(KERN_ERR "mux: Multiple gpio paths for gpio%i\n", gpio);
return -EINVAL;
}
printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
return -ENODEV;
}
int __init omap_mux_init_signal(char *muxname, int val)
{
struct omap_mux_entry *e;
char *m0_name = NULL, *mode_name = NULL;
int found = 0;
mode_name = strchr(muxname, '.');
if (mode_name) {
*mode_name = '\0';
mode_name++;
m0_name = muxname;
} else {
mode_name = muxname;
}
list_for_each_entry(e, &muxmodes, node) {
struct omap_mux *m = &e->mux;
char *m0_entry = m->muxnames[0];
int i;
if (m0_name && strcmp(m0_name, m0_entry))
continue;
for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
char *mode_cur = m->muxnames[i];
if (!mode_cur)
continue;
if (!strcmp(mode_name, mode_cur)) {
u16 old_mode;
u16 mux_mode;
old_mode = omap_mux_read(m->reg_offset);
mux_mode = val | i;
printk(KERN_DEBUG "mux: Setting signal "
"%s.%s 0x%04x -> 0x%04x\n",
m0_entry, muxname, old_mode, mux_mode);
omap_mux_write(mux_mode, m->reg_offset);
found++;
}
}
}
if (found == 1)
return 0;
if (found > 1) {
printk(KERN_ERR "mux: Multiple signal paths (%i) for %s\n",
found, muxname);
return -EINVAL;
}
printk(KERN_ERR "mux: Could not set signal %s\n", muxname);
return -ENODEV;
}
#ifdef CONFIG_DEBUG_FS
#define OMAP_MUX_MAX_NR_FLAGS 10
#define OMAP_MUX_TEST_FLAG(val, mask) \
if (((val) & (mask)) == (mask)) { \
i++; \
flags[i] = #mask; \
}
/* REVISIT: Add checking for non-optimal mux settings */
static inline void omap_mux_decode(struct seq_file *s, u16 val)
{
char *flags[OMAP_MUX_MAX_NR_FLAGS];
char mode[14];
int i = -1;
sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
i++;
flags[i] = mode;
OMAP_MUX_TEST_FLAG(val, OMAP_PIN_OFF_WAKEUPENABLE);
if (val & OMAP_OFF_EN) {
if (!(val & OMAP_OFFOUT_EN)) {
if (!(val & OMAP_OFF_PULL_UP)) {
OMAP_MUX_TEST_FLAG(val,
OMAP_PIN_OFF_INPUT_PULLDOWN);
} else {
OMAP_MUX_TEST_FLAG(val,
OMAP_PIN_OFF_INPUT_PULLUP);
}
} else {
if (!(val & OMAP_OFFOUT_VAL)) {
OMAP_MUX_TEST_FLAG(val,
OMAP_PIN_OFF_OUTPUT_LOW);
} else {
OMAP_MUX_TEST_FLAG(val,
OMAP_PIN_OFF_OUTPUT_HIGH);
}
}
}
if (val & OMAP_INPUT_EN) {
if (val & OMAP_PULL_ENA) {
if (!(val & OMAP_PULL_UP)) {
OMAP_MUX_TEST_FLAG(val,
OMAP_PIN_INPUT_PULLDOWN);
} else {
OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT_PULLUP);
}
} else {
OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT);
}
} else {
i++;
flags[i] = "OMAP_PIN_OUTPUT";
}
do {
seq_printf(s, "%s", flags[i]);
if (i > 0)
seq_printf(s, " | ");
} while (i-- > 0);
}
#define OMAP_MUX_DEFNAME_LEN 16
static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
{
struct omap_mux_entry *e;
list_for_each_entry(e, &muxmodes, node) {
struct omap_mux *m = &e->mux;
char m0_def[OMAP_MUX_DEFNAME_LEN];
char *m0_name = m->muxnames[0];
u16 val;
int i, mode;
if (!m0_name)
continue;
for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) {
if (m0_name[i] == '\0') {
m0_def[i] = m0_name[i];
break;
}
m0_def[i] = toupper(m0_name[i]);
}
val = omap_mux_read(m->reg_offset);
mode = val & OMAP_MUX_MODE7;
seq_printf(s, "OMAP%i_MUX(%s, ",
cpu_is_omap34xx() ? 3 : 0, m0_def);
omap_mux_decode(s, val);
seq_printf(s, "),\n");
}
return 0;
}
static int omap_mux_dbg_board_open(struct inode *inode, struct file *file)
{
return single_open(file, omap_mux_dbg_board_show, &inode->i_private);
}
static const struct file_operations omap_mux_dbg_board_fops = {
.open = omap_mux_dbg_board_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
{
struct omap_mux *m = s->private;
const char *none = "NA";
u16 val;
int mode;
val = omap_mux_read(m->reg_offset);
mode = val & OMAP_MUX_MODE7;
seq_printf(s, "name: %s.%s (0x%08lx/0x%03x = 0x%04x), b %s, t %s\n",
m->muxnames[0], m->muxnames[mode],
mux_phys + m->reg_offset, m->reg_offset, val,
m->balls[0] ? m->balls[0] : none,
m->balls[1] ? m->balls[1] : none);
seq_printf(s, "mode: ");
omap_mux_decode(s, val);
seq_printf(s, "\n");
seq_printf(s, "signals: %s | %s | %s | %s | %s | %s | %s | %s\n",
m->muxnames[0] ? m->muxnames[0] : none,
m->muxnames[1] ? m->muxnames[1] : none,
m->muxnames[2] ? m->muxnames[2] : none,
m->muxnames[3] ? m->muxnames[3] : none,
m->muxnames[4] ? m->muxnames[4] : none,
m->muxnames[5] ? m->muxnames[5] : none,
m->muxnames[6] ? m->muxnames[6] : none,
m->muxnames[7] ? m->muxnames[7] : none);
return 0;
}
#define OMAP_MUX_MAX_ARG_CHAR 7
static ssize_t omap_mux_dbg_signal_write(struct file *file,
const char __user *user_buf,
size_t count, loff_t *ppos)
{
char buf[OMAP_MUX_MAX_ARG_CHAR];
struct seq_file *seqf;
struct omap_mux *m;
unsigned long val;
int buf_size, ret;
if (count > OMAP_MUX_MAX_ARG_CHAR)
return -EINVAL;
memset(buf, 0, sizeof(buf));
buf_size = min(count, sizeof(buf) - 1);
if (copy_from_user(buf, user_buf, buf_size))
return -EFAULT;
ret = strict_strtoul(buf, 0x10, &val);
if (ret < 0)
return ret;
if (val > 0xffff)
return -EINVAL;
seqf = file->private_data;
m = seqf->private;
omap_mux_write((u16)val, m->reg_offset);
*ppos += count;
return count;
}
static int omap_mux_dbg_signal_open(struct inode *inode, struct file *file)
{
return single_open(file, omap_mux_dbg_signal_show, inode->i_private);
}
static const struct file_operations omap_mux_dbg_signal_fops = {
.open = omap_mux_dbg_signal_open,
.read = seq_read,
.write = omap_mux_dbg_signal_write,
.llseek = seq_lseek,
.release = single_release,
};
static struct dentry *mux_dbg_dir;
static void __init omap_mux_dbg_init(void)
{
struct omap_mux_entry *e;
mux_dbg_dir = debugfs_create_dir("omap_mux", NULL);
if (!mux_dbg_dir)
return;
(void)debugfs_create_file("board", S_IRUGO, mux_dbg_dir,
NULL, &omap_mux_dbg_board_fops);
list_for_each_entry(e, &muxmodes, node) {
struct omap_mux *m = &e->mux;
(void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
m, &omap_mux_dbg_signal_fops);
}
}
#else
#define omap34xx_cfg_reg NULL
static inline void omap_mux_dbg_init(void)
{
}
#endif /* CONFIG_DEBUG_FS */
static void __init omap_mux_free_names(struct omap_mux *m)
{
int i;
for (i = 0; i < OMAP_MUX_NR_MODES; i++)
kfree(m->muxnames[i]);
#ifdef CONFIG_DEBUG_FS
for (i = 0; i < OMAP_MUX_NR_SIDES; i++)
kfree(m->balls[i]);
#endif
int __init omap2_mux_init(void)
}
/* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */
static int __init omap_mux_late_init(void)
{
if (cpu_is_omap24xx()) {
arch_mux_cfg.pins = omap24xx_pins;
arch_mux_cfg.size = OMAP24XX_PINS_SZ;
arch_mux_cfg.cfg_reg = omap24xx_cfg_reg;
} else if (cpu_is_omap34xx()) {
arch_mux_cfg.pins = omap34xx_pins;
arch_mux_cfg.size = OMAP34XX_PINS_SZ;
arch_mux_cfg.cfg_reg = omap34xx_cfg_reg;
struct omap_mux_entry *e, *tmp;
list_for_each_entry_safe(e, tmp, &muxmodes, node) {
struct omap_mux *m = &e->mux;
u16 mode = omap_mux_read(m->reg_offset);
if (OMAP_MODE_GPIO(mode))
continue;
#ifndef CONFIG_DEBUG_FS
mutex_lock(&muxmode_mutex);
list_del(&e->node);
mutex_unlock(&muxmode_mutex);
omap_mux_free_names(m);
kfree(m);
#endif
}
omap_mux_dbg_init();
return 0;
}
late_initcall(omap_mux_late_init);
static void __init omap_mux_package_fixup(struct omap_mux *p,
struct omap_mux *superset)
{
while (p->reg_offset != OMAP_MUX_TERMINATOR) {
struct omap_mux *s = superset;
int found = 0;
while (s->reg_offset != OMAP_MUX_TERMINATOR) {
if (s->reg_offset == p->reg_offset) {
*s = *p;
found++;
break;
}
s++;
}
if (!found)
printk(KERN_ERR "mux: Unknown entry offset 0x%x\n",
p->reg_offset);
p++;
}
}
#ifdef CONFIG_DEBUG_FS
static void __init omap_mux_package_init_balls(struct omap_ball *b,
struct omap_mux *superset)
{
while (b->reg_offset != OMAP_MUX_TERMINATOR) {
struct omap_mux *s = superset;
int found = 0;
while (s->reg_offset != OMAP_MUX_TERMINATOR) {
if (s->reg_offset == b->reg_offset) {
s->balls[0] = b->balls[0];
s->balls[1] = b->balls[1];
found++;
break;
}
s++;
}
if (!found)
printk(KERN_ERR "mux: Unknown ball offset 0x%x\n",
b->reg_offset);
b++;
}
}
#else /* CONFIG_DEBUG_FS */
static inline void omap_mux_package_init_balls(struct omap_ball *b,
struct omap_mux *superset)
{
}
#endif /* CONFIG_DEBUG_FS */
static int __init omap_mux_setup(char *options)
{
if (!options)
return 0;
omap_mux_options = options;
return 1;
}
__setup("omap_mux=", omap_mux_setup);
/*
* Note that the omap_mux=some.signal1=0x1234,some.signal2=0x1234
* cmdline options only override the bootloader values.
* During development, please enable CONFIG_DEBUG_FS, and use the
* signal specific entries under debugfs.
*/
static void __init omap_mux_set_cmdline_signals(void)
{
char *options, *next_opt, *token;
if (!omap_mux_options)
return;
options = kmalloc(strlen(omap_mux_options) + 1, GFP_KERNEL);
if (!options)
return;
strcpy(options, omap_mux_options);
next_opt = options;
while ((token = strsep(&next_opt, ",")) != NULL) {
char *keyval, *name;
unsigned long val;
keyval = token;
name = strsep(&keyval, "=");
if (name) {
int res;
res = strict_strtoul(keyval, 0x10, &val);
if (res < 0)
continue;
omap_mux_init_signal(name, (u16)val);
}
}
kfree(options);
}
static void __init omap_mux_set_board_signals(struct omap_board_mux *board_mux)
{
while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
omap_mux_write(board_mux->value, board_mux->reg_offset);
board_mux++;
}
}
static int __init omap_mux_copy_names(struct omap_mux *src,
struct omap_mux *dst)
{
int i;
for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
if (src->muxnames[i]) {
dst->muxnames[i] =
kmalloc(strlen(src->muxnames[i]) + 1,
GFP_KERNEL);
if (!dst->muxnames[i])
goto free;
strcpy(dst->muxnames[i], src->muxnames[i]);
}
}
#ifdef CONFIG_DEBUG_FS
for (i = 0; i < OMAP_MUX_NR_SIDES; i++) {
if (src->balls[i]) {
dst->balls[i] =
kmalloc(strlen(src->balls[i]) + 1,
GFP_KERNEL);
if (!dst->balls[i])
goto free;
strcpy(dst->balls[i], src->balls[i]);
}
}
#endif
return 0;
free:
omap_mux_free_names(dst);
return -ENOMEM;
}
#endif /* CONFIG_OMAP_MUX */
static u16 omap_mux_get_by_gpio(int gpio)
{
struct omap_mux_entry *e;
u16 offset = OMAP_MUX_TERMINATOR;
list_for_each_entry(e, &muxmodes, node) {
struct omap_mux *m = &e->mux;
if (m->gpio == gpio) {
offset = m->reg_offset;
break;
}
}
return offset;
}
/* Needed for dynamic muxing of GPIO pins for off-idle */
u16 omap_mux_get_gpio(int gpio)
{
u16 offset;
offset = omap_mux_get_by_gpio(gpio);
if (offset == OMAP_MUX_TERMINATOR) {
printk(KERN_ERR "mux: Could not get gpio%i\n", gpio);
return offset;
}
return omap_mux_read(offset);
}
/* Needed for dynamic muxing of GPIO pins for off-idle */
void omap_mux_set_gpio(u16 val, int gpio)
{
u16 offset;
offset = omap_mux_get_by_gpio(gpio);
if (offset == OMAP_MUX_TERMINATOR) {
printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
return;
}
omap_mux_write(val, offset);
}
static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src)
{
struct omap_mux_entry *entry;
struct omap_mux *m;
entry = kzalloc(sizeof(struct omap_mux_entry), GFP_KERNEL);
if (!entry)
return NULL;
m = &entry->mux;
memcpy(m, src, sizeof(struct omap_mux_entry));
#ifdef CONFIG_OMAP_MUX
if (omap_mux_copy_names(src, m)) {
kfree(entry);
return NULL;
}
#endif
mutex_lock(&muxmode_mutex);
list_add_tail(&entry->node, &muxmodes);
mutex_unlock(&muxmode_mutex);
return omap_mux_register(&arch_mux_cfg);
return m;
}
/*
* Note if CONFIG_OMAP_MUX is not selected, we will only initialize
* the GPIO to mux offset mapping that is needed for dynamic muxing
* of GPIO pins for off-idle.
*/
static void __init omap_mux_init_list(struct omap_mux *superset)
{
while (superset->reg_offset != OMAP_MUX_TERMINATOR) {
struct omap_mux *entry;
#ifndef CONFIG_OMAP_MUX
/* Skip pins that are not muxed as GPIO by bootloader */
if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) {
superset++;
continue;
}
#endif
entry = omap_mux_list_add(superset);
if (!entry) {
printk(KERN_ERR "mux: Could not add entry\n");
return;
}
superset++;
}
}
int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
struct omap_mux *superset,
struct omap_mux *package_subset,
struct omap_board_mux *board_mux,
struct omap_ball *package_balls)
{
if (mux_base)
return -EBUSY;
mux_phys = mux_pbase;
mux_base = ioremap(mux_pbase, mux_size);
if (!mux_base) {
printk(KERN_ERR "mux: Could not ioremap\n");
return -ENODEV;
}
#ifdef CONFIG_OMAP_MUX
omap_mux_package_fixup(package_subset, superset);
omap_mux_package_init_balls(package_balls, superset);
omap_mux_set_cmdline_signals();
omap_mux_set_board_signals(board_mux);
#endif
omap_mux_init_list(superset);
return 0;
}
#endif /* CONFIG_ARCH_OMAP34XX */
arch/arm/mach-omap2/mux.h 0 → 100644
View file @ 5ccf1978
/*
* Copyright (C) 2009 Nokia
* Copyright (C) 2009 Texas Instruments
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "mux34xx.h"
#define OMAP_MUX_TERMINATOR 0xffff
/* 34xx mux mode options for each pin. See TRM for options */
#define OMAP_MUX_MODE0 0
#define OMAP_MUX_MODE1 1
#define OMAP_MUX_MODE2 2
#define OMAP_MUX_MODE3 3
#define OMAP_MUX_MODE4 4
#define OMAP_MUX_MODE5 5
#define OMAP_MUX_MODE6 6
#define OMAP_MUX_MODE7 7
/* 24xx/34xx mux bit defines */
#define OMAP_PULL_ENA (1 << 3)
#define OMAP_PULL_UP (1 << 4)
#define OMAP_ALTELECTRICALSEL (1 << 5)
/* 34xx specific mux bit defines */
#define OMAP_INPUT_EN (1 << 8)
#define OMAP_OFF_EN (1 << 9)
#define OMAP_OFFOUT_EN (1 << 10)
#define OMAP_OFFOUT_VAL (1 << 11)
#define OMAP_OFF_PULL_EN (1 << 12)
#define OMAP_OFF_PULL_UP (1 << 13)
#define OMAP_WAKEUP_EN (1 << 14)
/* Active pin states */
#define OMAP_PIN_OUTPUT 0
#define OMAP_PIN_INPUT OMAP_INPUT_EN
#define OMAP_PIN_INPUT_PULLUP (OMAP_PULL_ENA | OMAP_INPUT_EN \
| OMAP_PULL_UP)
#define OMAP_PIN_INPUT_PULLDOWN (OMAP_PULL_ENA | OMAP_INPUT_EN)
/* Off mode states */
#define OMAP_PIN_OFF_NONE 0
#define OMAP_PIN_OFF_OUTPUT_HIGH (OMAP_OFF_EN | OMAP_OFFOUT_EN \
| OMAP_OFFOUT_VAL)
#define OMAP_PIN_OFF_OUTPUT_LOW (OMAP_OFF_EN | OMAP_OFFOUT_EN)
#define OMAP_PIN_OFF_INPUT_PULLUP (OMAP_OFF_EN | OMAP_OFF_PULL_EN \
| OMAP_OFF_PULL_UP)
#define OMAP_PIN_OFF_INPUT_PULLDOWN (OMAP_OFF_EN | OMAP_OFF_PULL_EN)
#define OMAP_PIN_OFF_WAKEUPENABLE OMAP_WAKEUP_EN
#define OMAP_MODE_GPIO(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4)
/* Flags for omap_mux_init */
#define OMAP_PACKAGE_MASK 0xffff
#define OMAP_PACKAGE_CBP 4 /* 515-pin 0.40 0.50 */
#define OMAP_PACKAGE_CUS 3 /* 423-pin 0.65 */
#define OMAP_PACKAGE_CBB 2 /* 515-pin 0.40 0.50 */
#define OMAP_PACKAGE_CBC 1 /* 515-pin 0.50 0.65 */
#define OMAP_MUX_NR_MODES 8 /* Available modes */
#define OMAP_MUX_NR_SIDES 2 /* Bottom & top */
/**
* struct omap_mux - data for omap mux register offset and it's value
* @reg_offset: mux register offset from the mux base
* @gpio: GPIO number
* @muxnames: available signal modes for a ball
*/
struct omap_mux {
u16 reg_offset;
u16 gpio;
#ifdef CONFIG_OMAP_MUX
char *muxnames[OMAP_MUX_NR_MODES];
#ifdef CONFIG_DEBUG_FS
char *balls[OMAP_MUX_NR_SIDES];
#endif
#endif
};
/**
* struct omap_ball - data for balls on omap package
* @reg_offset: mux register offset from the mux base
* @balls: available balls on the package
*/
struct omap_ball {
u16 reg_offset;
char *balls[OMAP_MUX_NR_SIDES];
};
/**
* struct omap_board_mux - data for initializing mux registers
* @reg_offset: mux register offset from the mux base
* @mux_value: desired mux value to set
*/
struct omap_board_mux {
u16 reg_offset;
u16 value;
};
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_ARCH_OMAP34XX)
/**
* omap_mux_init_gpio - initialize a signal based on the GPIO number
* @gpio: GPIO number
* @val: Options for the mux register value
*/
int omap_mux_init_gpio(int gpio, int val);
/**
* omap_mux_init_signal - initialize a signal based on the signal name
* @muxname: Mux name in mode0_name.signal_name format
* @val: Options for the mux register value
*/
int omap_mux_init_signal(char *muxname, int val);
#else
static inline int omap_mux_init_gpio(int gpio, int val)
{
return 0;
}
static inline int omap_mux_init_signal(char *muxname, int val)
{
return 0;
}
#endif
/**
* omap_mux_get_gpio() - get mux register value based on GPIO number
* @gpio: GPIO number
*
*/
u16 omap_mux_get_gpio(int gpio);
/**
* omap_mux_set_gpio() - set mux register value based on GPIO number
* @val: New mux register value
* @gpio: GPIO number
*
*/
void omap_mux_set_gpio(u16 val, int gpio);
/**
* omap3_mux_init() - initialize mux system with board specific set
* @board_mux: Board specific mux table
* @flags: OMAP package type used for the board
*/
int omap3_mux_init(struct omap_board_mux *board_mux, int flags);
/**
* omap_mux_init - private mux init function, do not call
*/
int omap_mux_init(u32 mux_pbase, u32 mux_size,
struct omap_mux *superset,
struct omap_mux *package_subset,
struct omap_board_mux *board_mux,
struct omap_ball *package_balls);
arch/arm/mach-omap2/mux34xx.c 0 → 100644
View file @ 5ccf1978
/*
* Copyright (C) 2009 Nokia
* Copyright (C) 2009 Texas Instruments
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/init.h>
#include "mux.h"
#ifdef CONFIG_OMAP_MUX
#define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
{ \
.reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
.gpio = (g), \
.muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \
}
#else
#define _OMAP3_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \
{ \
.reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
.gpio = (g), \
}
#endif
#define _OMAP3_BALLENTRY(M0, bb, bt) \
{ \
.reg_offset = (OMAP3_CONTROL_PADCONF_##M0##_OFFSET), \
.balls = { bb, bt }, \
}
/*
* Superset of all mux modes for omap3
*/
static struct omap_mux __initdata omap3_muxmodes[] = {
_OMAP3_MUXENTRY(CAM_D0, 99,
"cam_d0", NULL, NULL, NULL,
"gpio_99", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D1, 100,
"cam_d1", NULL, NULL, NULL,
"gpio_100", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D10, 109,
"cam_d10", NULL, NULL, NULL,
"gpio_109", "hw_dbg8", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D11, 110,
"cam_d11", NULL, NULL, NULL,
"gpio_110", "hw_dbg9", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D2, 101,
"cam_d2", NULL, NULL, NULL,
"gpio_101", "hw_dbg4", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D3, 102,
"cam_d3", NULL, NULL, NULL,
"gpio_102", "hw_dbg5", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D4, 103,
"cam_d4", NULL, NULL, NULL,
"gpio_103", "hw_dbg6", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D5, 104,
"cam_d5", NULL, NULL, NULL,
"gpio_104", "hw_dbg7", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D6, 105,
"cam_d6", NULL, NULL, NULL,
"gpio_105", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D7, 106,
"cam_d7", NULL, NULL, NULL,
"gpio_106", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D8, 107,
"cam_d8", NULL, NULL, NULL,
"gpio_107", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D9, 108,
"cam_d9", NULL, NULL, NULL,
"gpio_108", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_FLD, 98,
"cam_fld", NULL, "cam_global_reset", NULL,
"gpio_98", "hw_dbg3", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_HS, 94,
"cam_hs", NULL, NULL, NULL,
"gpio_94", "hw_dbg0", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_PCLK, 97,
"cam_pclk", NULL, NULL, NULL,
"gpio_97", "hw_dbg2", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_STROBE, 126,
"cam_strobe", NULL, NULL, NULL,
"gpio_126", "hw_dbg11", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_VS, 95,
"cam_vs", NULL, NULL, NULL,
"gpio_95", "hw_dbg1", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_WEN, 167,
"cam_wen", NULL, "cam_shutter", NULL,
"gpio_167", "hw_dbg10", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_XCLKA, 96,
"cam_xclka", NULL, NULL, NULL,
"gpio_96", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_XCLKB, 111,
"cam_xclkb", NULL, NULL, NULL,
"gpio_111", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CSI2_DX0, 112,
"csi2_dx0", NULL, NULL, NULL,
"gpio_112", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CSI2_DX1, 114,
"csi2_dx1", NULL, NULL, NULL,
"gpio_114", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CSI2_DY0, 113,
"csi2_dy0", NULL, NULL, NULL,
"gpio_113", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CSI2_DY1, 115,
"csi2_dy1", NULL, NULL, NULL,
"gpio_115", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_ACBIAS, 69,
"dss_acbias", NULL, NULL, NULL,
"gpio_69", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA0, 70,
"dss_data0", NULL, "uart1_cts", NULL,
"gpio_70", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA1, 71,
"dss_data1", NULL, "uart1_rts", NULL,
"gpio_71", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA10, 80,
"dss_data10", NULL, NULL, NULL,
"gpio_80", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA11, 81,
"dss_data11", NULL, NULL, NULL,
"gpio_81", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA12, 82,
"dss_data12", NULL, NULL, NULL,
"gpio_82", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA13, 83,
"dss_data13", NULL, NULL, NULL,
"gpio_83", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA14, 84,
"dss_data14", NULL, NULL, NULL,
"gpio_84", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA15, 85,
"dss_data15", NULL, NULL, NULL,
"gpio_85", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA16, 86,
"dss_data16", NULL, NULL, NULL,
"gpio_86", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA17, 87,
"dss_data17", NULL, NULL, NULL,
"gpio_87", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA18, 88,
"dss_data18", NULL, "mcspi3_clk", "dss_data0",
"gpio_88", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA19, 89,
"dss_data19", NULL, "mcspi3_simo", "dss_data1",
"gpio_89", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA20, 90,
"dss_data20", NULL, "mcspi3_somi", "dss_data2",
"gpio_90", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA21, 91,
"dss_data21", NULL, "mcspi3_cs0", "dss_data3",
"gpio_91", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA22, 92,
"dss_data22", NULL, "mcspi3_cs1", "dss_data4",
"gpio_92", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA23, 93,
"dss_data23", NULL, NULL, "dss_data5",
"gpio_93", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA2, 72,
"dss_data2", NULL, NULL, NULL,
"gpio_72", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA3, 73,
"dss_data3", NULL, NULL, NULL,
"gpio_73", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA4, 74,
"dss_data4", NULL, "uart3_rx_irrx", NULL,
"gpio_74", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA5, 75,
"dss_data5", NULL, "uart3_tx_irtx", NULL,
"gpio_75", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA6, 76,
"dss_data6", NULL, "uart1_tx", NULL,
"gpio_76", "hw_dbg14", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA7, 77,
"dss_data7", NULL, "uart1_rx", NULL,
"gpio_77", "hw_dbg15", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA8, 78,
"dss_data8", NULL, NULL, NULL,
"gpio_78", "hw_dbg16", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA9, 79,
"dss_data9", NULL, NULL, NULL,
"gpio_79", "hw_dbg17", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_HSYNC, 67,
"dss_hsync", NULL, NULL, NULL,
"gpio_67", "hw_dbg13", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_PCLK, 66,
"dss_pclk", NULL, NULL, NULL,
"gpio_66", "hw_dbg12", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_VSYNC, 68,
"dss_vsync", NULL, NULL, NULL,
"gpio_68", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(ETK_CLK, 12,
"etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
"gpio_12", "mm1_rxdp", "hsusb1_tll_stp", "hw_dbg0"),
_OMAP3_MUXENTRY(ETK_CTL, 13,
"etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
"gpio_13", NULL, "hsusb1_tll_clk", "hw_dbg1"),
_OMAP3_MUXENTRY(ETK_D0, 14,
"etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
"gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", "hw_dbg2"),
_OMAP3_MUXENTRY(ETK_D1, 15,
"etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
"gpio_15", "mm1_txse0", "hsusb1_tll_data1", "hw_dbg3"),
_OMAP3_MUXENTRY(ETK_D10, 24,
"etk_d10", NULL, "uart1_rx", "hsusb2_clk",
"gpio_24", NULL, "hsusb2_tll_clk", "hw_dbg12"),
_OMAP3_MUXENTRY(ETK_D11, 25,
"etk_d11", NULL, NULL, "hsusb2_stp",
"gpio_25", "mm2_rxdp", "hsusb2_tll_stp", "hw_dbg13"),
_OMAP3_MUXENTRY(ETK_D12, 26,
"etk_d12", NULL, NULL, "hsusb2_dir",
"gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"),
_OMAP3_MUXENTRY(ETK_D13, 27,
"etk_d13", NULL, NULL, "hsusb2_nxt",
"gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", "hw_dbg15"),
_OMAP3_MUXENTRY(ETK_D14, 28,
"etk_d14", NULL, NULL, "hsusb2_data0",
"gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", "hw_dbg16"),
_OMAP3_MUXENTRY(ETK_D15, 29,
"etk_d15", NULL, NULL, "hsusb2_data1",
"gpio_29", "mm2_txse0", "hsusb2_tll_data1", "hw_dbg17"),
_OMAP3_MUXENTRY(ETK_D2, 16,
"etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
"gpio_16", "mm1_txdat", "hsusb1_tll_data2", "hw_dbg4"),
_OMAP3_MUXENTRY(ETK_D3, 17,
"etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
"gpio_17", NULL, "hsusb1_tll_data7", "hw_dbg5"),
_OMAP3_MUXENTRY(ETK_D4, 18,
"etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
"gpio_18", NULL, "hsusb1_tll_data4", "hw_dbg6"),
_OMAP3_MUXENTRY(ETK_D5, 19,
"etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
"gpio_19", NULL, "hsusb1_tll_data5", "hw_dbg7"),
_OMAP3_MUXENTRY(ETK_D6, 20,
"etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
"gpio_20", NULL, "hsusb1_tll_data6", "hw_dbg8"),
_OMAP3_MUXENTRY(ETK_D7, 21,
"etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
"gpio_21", "mm1_txen_n", "hsusb1_tll_data3", "hw_dbg9"),
_OMAP3_MUXENTRY(ETK_D8, 22,
"etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
"gpio_22", NULL, "hsusb1_tll_dir", "hw_dbg10"),
_OMAP3_MUXENTRY(ETK_D9, 23,
"etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
"gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", "hw_dbg11"),
_OMAP3_MUXENTRY(GPMC_A1, 34,
"gpmc_a1", NULL, NULL, NULL,
"gpio_34", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A10, 43,
"gpmc_a10", "sys_ndmareq3", NULL, NULL,
"gpio_43", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A2, 35,
"gpmc_a2", NULL, NULL, NULL,
"gpio_35", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A3, 36,
"gpmc_a3", NULL, NULL, NULL,
"gpio_36", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A4, 37,
"gpmc_a4", NULL, NULL, NULL,
"gpio_37", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A5, 38,
"gpmc_a5", NULL, NULL, NULL,
"gpio_38", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A6, 39,
"gpmc_a6", NULL, NULL, NULL,
"gpio_39", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A7, 40,
"gpmc_a7", NULL, NULL, NULL,
"gpio_40", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A8, 41,
"gpmc_a8", NULL, NULL, NULL,
"gpio_41", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_A9, 42,
"gpmc_a9", "sys_ndmareq2", NULL, NULL,
"gpio_42", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_CLK, 59,
"gpmc_clk", NULL, NULL, NULL,
"gpio_59", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D10, 46,
"gpmc_d10", NULL, NULL, NULL,
"gpio_46", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D11, 47,
"gpmc_d11", NULL, NULL, NULL,
"gpio_47", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D12, 48,
"gpmc_d12", NULL, NULL, NULL,
"gpio_48", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D13, 49,
"gpmc_d13", NULL, NULL, NULL,
"gpio_49", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D14, 50,
"gpmc_d14", NULL, NULL, NULL,
"gpio_50", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D15, 51,
"gpmc_d15", NULL, NULL, NULL,
"gpio_51", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D8, 44,
"gpmc_d8", NULL, NULL, NULL,
"gpio_44", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_D9, 45,
"gpmc_d9", NULL, NULL, NULL,
"gpio_45", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NBE0_CLE, 60,
"gpmc_nbe0_cle", NULL, NULL, NULL,
"gpio_60", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NBE1, 61,
"gpmc_nbe1", NULL, NULL, NULL,
"gpio_61", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS1, 52,
"gpmc_ncs1", NULL, NULL, NULL,
"gpio_52", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS2, 53,
"gpmc_ncs2", NULL, NULL, NULL,
"gpio_53", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS3, 54,
"gpmc_ncs3", "sys_ndmareq0", NULL, NULL,
"gpio_54", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS4, 55,
"gpmc_ncs4", "sys_ndmareq1", "mcbsp4_clkx", "gpt9_pwm_evt",
"gpio_55", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS5, 56,
"gpmc_ncs5", "sys_ndmareq2", "mcbsp4_dr", "gpt10_pwm_evt",
"gpio_56", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS6, 57,
"gpmc_ncs6", "sys_ndmareq3", "mcbsp4_dx", "gpt11_pwm_evt",
"gpio_57", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NCS7, 58,
"gpmc_ncs7", "gpmc_io_dir", "mcbsp4_fsx", "gpt8_pwm_evt",
"gpio_58", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_NWP, 62,
"gpmc_nwp", NULL, NULL, NULL,
"gpio_62", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_WAIT1, 63,
"gpmc_wait1", NULL, NULL, NULL,
"gpio_63", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_WAIT2, 64,
"gpmc_wait2", NULL, NULL, NULL,
"gpio_64", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_WAIT3, 65,
"gpmc_wait3", "sys_ndmareq1", NULL, NULL,
"gpio_65", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HDQ_SIO, 170,
"hdq_sio", "sys_altclk", "i2c2_sccbe", "i2c3_sccbe",
"gpio_170", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_CLK, 120,
"hsusb0_clk", NULL, NULL, NULL,
"gpio_120", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA0, 125,
"hsusb0_data0", NULL, "uart3_tx_irtx", NULL,
"gpio_125", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA1, 130,
"hsusb0_data1", NULL, "uart3_rx_irrx", NULL,
"gpio_130", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA2, 131,
"hsusb0_data2", NULL, "uart3_rts_sd", NULL,
"gpio_131", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA3, 169,
"hsusb0_data3", NULL, "uart3_cts_rctx", NULL,
"gpio_169", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA4, 188,
"hsusb0_data4", NULL, NULL, NULL,
"gpio_188", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA5, 189,
"hsusb0_data5", NULL, NULL, NULL,
"gpio_189", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA6, 190,
"hsusb0_data6", NULL, NULL, NULL,
"gpio_190", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA7, 191,
"hsusb0_data7", NULL, NULL, NULL,
"gpio_191", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DIR, 122,
"hsusb0_dir", NULL, NULL, NULL,
"gpio_122", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_NXT, 124,
"hsusb0_nxt", NULL, NULL, NULL,
"gpio_124", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_STP, 121,
"hsusb0_stp", NULL, NULL, NULL,
"gpio_121", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(I2C2_SCL, 168,
"i2c2_scl", NULL, NULL, NULL,
"gpio_168", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(I2C2_SDA, 183,
"i2c2_sda", NULL, NULL, NULL,
"gpio_183", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(I2C3_SCL, 184,
"i2c3_scl", NULL, NULL, NULL,
"gpio_184", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(I2C3_SDA, 185,
"i2c3_sda", NULL, NULL, NULL,
"gpio_185", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(I2C4_SCL, 0,
"i2c4_scl", "sys_nvmode1", NULL, NULL,
NULL, NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(I2C4_SDA, 0,
"i2c4_sda", "sys_nvmode2", NULL, NULL,
NULL, NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(JTAG_EMU0, 11,
"jtag_emu0", NULL, NULL, NULL,
"gpio_11", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(JTAG_EMU1, 31,
"jtag_emu1", NULL, NULL, NULL,
"gpio_31", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_CLKR, 156,
"mcbsp1_clkr", "mcspi4_clk", NULL, NULL,
"gpio_156", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_CLKX, 162,
"mcbsp1_clkx", NULL, "mcbsp3_clkx", NULL,
"gpio_162", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_DR, 159,
"mcbsp1_dr", "mcspi4_somi", "mcbsp3_dr", NULL,
"gpio_159", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_DX, 158,
"mcbsp1_dx", "mcspi4_simo", "mcbsp3_dx", NULL,
"gpio_158", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_FSR, 157,
"mcbsp1_fsr", NULL, "cam_global_reset", NULL,
"gpio_157", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_FSX, 161,
"mcbsp1_fsx", "mcspi4_cs0", "mcbsp3_fsx", NULL,
"gpio_161", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP2_CLKX, 117,
"mcbsp2_clkx", NULL, NULL, NULL,
"gpio_117", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP2_DR, 118,
"mcbsp2_dr", NULL, NULL, NULL,
"gpio_118", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP2_DX, 119,
"mcbsp2_dx", NULL, NULL, NULL,
"gpio_119", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP2_FSX, 116,
"mcbsp2_fsx", NULL, NULL, NULL,
"gpio_116", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_CLKX, 142,
"mcbsp3_clkx", "uart2_tx", NULL, NULL,
"gpio_142", "hsusb3_tll_data6", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_DR, 141,
"mcbsp3_dr", "uart2_rts", NULL, NULL,
"gpio_141", "hsusb3_tll_data5", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_DX, 140,
"mcbsp3_dx", "uart2_cts", NULL, NULL,
"gpio_140", "hsusb3_tll_data4", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_FSX, 143,
"mcbsp3_fsx", "uart2_rx", NULL, NULL,
"gpio_143", "hsusb3_tll_data7", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_CLKX, 152,
"mcbsp4_clkx", NULL, NULL, NULL,
"gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_DR, 153,
"mcbsp4_dr", NULL, NULL, NULL,
"gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_DX, 154,
"mcbsp4_dx", NULL, NULL, NULL,
"gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_FSX, 155,
"mcbsp4_fsx", NULL, NULL, NULL,
"gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP_CLKS, 160,
"mcbsp_clks", NULL, "cam_shutter", NULL,
"gpio_160", "uart1_cts", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_CLK, 171,
"mcspi1_clk", "sdmmc2_dat4", NULL, NULL,
"gpio_171", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_CS0, 174,
"mcspi1_cs0", "sdmmc2_dat7", NULL, NULL,
"gpio_174", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_CS1, 175,
"mcspi1_cs1", NULL, NULL, "sdmmc3_cmd",
"gpio_175", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_CS2, 176,
"mcspi1_cs2", NULL, NULL, "sdmmc3_clk",
"gpio_176", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_CS3, 177,
"mcspi1_cs3", NULL, "hsusb2_tll_data2", "hsusb2_data2",
"gpio_177", "mm2_txdat", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_SIMO, 172,
"mcspi1_simo", "sdmmc2_dat5", NULL, NULL,
"gpio_172", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_SOMI, 173,
"mcspi1_somi", "sdmmc2_dat6", NULL, NULL,
"gpio_173", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI2_CLK, 178,
"mcspi2_clk", NULL, "hsusb2_tll_data7", "hsusb2_data7",
"gpio_178", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI2_CS0, 181,
"mcspi2_cs0", "gpt11_pwm_evt",
"hsusb2_tll_data6", "hsusb2_data6",
"gpio_181", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI2_CS1, 182,
"mcspi2_cs1", "gpt8_pwm_evt",
"hsusb2_tll_data3", "hsusb2_data3",
"gpio_182", "mm2_txen_n", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI2_SIMO, 179,
"mcspi2_simo", "gpt9_pwm_evt",
"hsusb2_tll_data4", "hsusb2_data4",
"gpio_179", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCSPI2_SOMI, 180,
"mcspi2_somi", "gpt10_pwm_evt",
"hsusb2_tll_data5", "hsusb2_data5",
"gpio_180", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_CLK, 120,
"sdmmc1_clk", NULL, NULL, NULL,
"gpio_120", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_CMD, 121,
"sdmmc1_cmd", NULL, NULL, NULL,
"gpio_121", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT0, 122,
"sdmmc1_dat0", NULL, NULL, NULL,
"gpio_122", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT1, 123,
"sdmmc1_dat1", NULL, NULL, NULL,
"gpio_123", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT2, 124,
"sdmmc1_dat2", NULL, NULL, NULL,
"gpio_124", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT3, 125,
"sdmmc1_dat3", NULL, NULL, NULL,
"gpio_125", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT4, 126,
"sdmmc1_dat4", NULL, "sim_io", NULL,
"gpio_126", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT5, 127,
"sdmmc1_dat5", NULL, "sim_clk", NULL,
"gpio_127", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT6, 128,
"sdmmc1_dat6", NULL, "sim_pwrctrl", NULL,
"gpio_128", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT7, 129,
"sdmmc1_dat7", NULL, "sim_rst", NULL,
"gpio_129", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_CLK, 130,
"sdmmc2_clk", "mcspi3_clk", NULL, NULL,
"gpio_130", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_CMD, 131,
"sdmmc2_cmd", "mcspi3_simo", NULL, NULL,
"gpio_131", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT0, 132,
"sdmmc2_dat0", "mcspi3_somi", NULL, NULL,
"gpio_132", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT1, 133,
"sdmmc2_dat1", NULL, NULL, NULL,
"gpio_133", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT2, 134,
"sdmmc2_dat2", "mcspi3_cs1", NULL, NULL,
"gpio_134", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT3, 135,
"sdmmc2_dat3", "mcspi3_cs0", NULL, NULL,
"gpio_135", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT4, 136,
"sdmmc2_dat4", "sdmmc2_dir_dat0", NULL, "sdmmc3_dat0",
"gpio_136", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT5, 137,
"sdmmc2_dat5", "sdmmc2_dir_dat1",
"cam_global_reset", "sdmmc3_dat1",
"gpio_137", "hsusb3_tll_stp", "mm3_rxdp", "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT6, 138,
"sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2",
"gpio_138", "hsusb3_tll_dir", NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT7, 139,
"sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3",
"gpio_139", "hsusb3_tll_nxt", "mm3_rxdm", "safe_mode"),
_OMAP3_MUXENTRY(SDRC_CKE0, 0,
"sdrc_cke0", NULL, NULL, NULL,
NULL, NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDRC_CKE1, 0,
"sdrc_cke1", NULL, NULL, NULL,
NULL, NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT0, 2,
"sys_boot0", NULL, NULL, NULL,
"gpio_2", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT1, 3,
"sys_boot1", NULL, NULL, NULL,
"gpio_3", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT2, 4,
"sys_boot2", NULL, NULL, NULL,
"gpio_4", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT3, 5,
"sys_boot3", NULL, NULL, NULL,
"gpio_5", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT4, 6,
"sys_boot4", "sdmmc2_dir_dat2", NULL, NULL,
"gpio_6", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT5, 7,
"sys_boot5", "sdmmc2_dir_dat3", NULL, NULL,
"gpio_7", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT6, 8,
"sys_boot6", NULL, NULL, NULL,
"gpio_8", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_CLKOUT1, 10,
"sys_clkout1", NULL, NULL, NULL,
"gpio_10", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_CLKOUT2, 186,
"sys_clkout2", NULL, NULL, NULL,
"gpio_186", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_CLKREQ, 1,
"sys_clkreq", NULL, NULL, NULL,
"gpio_1", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_NIRQ, 0,
"sys_nirq", NULL, NULL, NULL,
"gpio_0", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_NRESWARM, 30,
"sys_nreswarm", NULL, NULL, NULL,
"gpio_30", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_OFF_MODE, 9,
"sys_off_mode", NULL, NULL, NULL,
"gpio_9", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_CTS, 150,
"uart1_cts", NULL, NULL, NULL,
"gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_RTS, 149,
"uart1_rts", NULL, NULL, NULL,
"gpio_149", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_RX, 151,
"uart1_rx", NULL, "mcbsp1_clkr", "mcspi4_clk",
"gpio_151", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_TX, 148,
"uart1_tx", NULL, NULL, NULL,
"gpio_148", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART2_CTS, 144,
"uart2_cts", "mcbsp3_dx", "gpt9_pwm_evt", NULL,
"gpio_144", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART2_RTS, 145,
"uart2_rts", "mcbsp3_dr", "gpt10_pwm_evt", NULL,
"gpio_145", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART2_RX, 147,
"uart2_rx", "mcbsp3_fsx", "gpt8_pwm_evt", NULL,
"gpio_147", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART2_TX, 146,
"uart2_tx", "mcbsp3_clkx", "gpt11_pwm_evt", NULL,
"gpio_146", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART3_CTS_RCTX, 163,
"uart3_cts_rctx", NULL, NULL, NULL,
"gpio_163", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART3_RTS_SD, 164,
"uart3_rts_sd", NULL, NULL, NULL,
"gpio_164", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART3_RX_IRRX, 165,
"uart3_rx_irrx", NULL, NULL, NULL,
"gpio_165", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART3_TX_IRTX, 166,
"uart3_tx_irtx", NULL, NULL, NULL,
"gpio_166", NULL, NULL, "safe_mode"),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
/*
* Signals different on CBC package compared to the superset
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBC)
struct omap_mux __initdata omap3_cbc_subset[] = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap3_cbc_subset NULL
#endif
/*
* Balls for CBC package
* 515-pin s-PBGA Package, 0.65mm Ball Pitch (Top), 0.50mm Ball Pitch (Bottom)
*
* FIXME: What's up with the outdated TI documentation? See:
*
* http://wiki.davincidsp.com/index.php/Datasheet_Errata_for_OMAP35x_CBC_Package
* http://community.ti.com/forums/t/10982.aspx
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
&& defined(CONFIG_OMAP_PACKAGE_CBC)
struct omap_ball __initdata omap3_cbc_ball[] = {
_OMAP3_BALLENTRY(CAM_D0, "ae16", NULL),
_OMAP3_BALLENTRY(CAM_D1, "ae15", NULL),
_OMAP3_BALLENTRY(CAM_D10, "d25", NULL),
_OMAP3_BALLENTRY(CAM_D11, "e26", NULL),
_OMAP3_BALLENTRY(CAM_D2, "a24", NULL),
_OMAP3_BALLENTRY(CAM_D3, "b24", NULL),
_OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
_OMAP3_BALLENTRY(CAM_D5, "c24", NULL),
_OMAP3_BALLENTRY(CAM_D6, "p25", NULL),
_OMAP3_BALLENTRY(CAM_D7, "p26", NULL),
_OMAP3_BALLENTRY(CAM_D8, "n25", NULL),
_OMAP3_BALLENTRY(CAM_D9, "n26", NULL),
_OMAP3_BALLENTRY(CAM_FLD, "b23", NULL),
_OMAP3_BALLENTRY(CAM_HS, "c23", NULL),
_OMAP3_BALLENTRY(CAM_PCLK, "c26", NULL),
_OMAP3_BALLENTRY(CAM_STROBE, "d26", NULL),
_OMAP3_BALLENTRY(CAM_VS, "d23", NULL),
_OMAP3_BALLENTRY(CAM_WEN, "a23", NULL),
_OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
_OMAP3_BALLENTRY(CAM_XCLKB, "e25", NULL),
_OMAP3_BALLENTRY(CSI2_DX0, "ad17", NULL),
_OMAP3_BALLENTRY(CSI2_DX1, "ae18", NULL),
_OMAP3_BALLENTRY(CSI2_DY0, "ad16", NULL),
_OMAP3_BALLENTRY(CSI2_DY1, "ae17", NULL),
_OMAP3_BALLENTRY(DSS_ACBIAS, "f26", NULL),
_OMAP3_BALLENTRY(DSS_DATA0, "ae21", NULL),
_OMAP3_BALLENTRY(DSS_DATA1, "ae22", NULL),
_OMAP3_BALLENTRY(DSS_DATA10, "ac26", NULL),
_OMAP3_BALLENTRY(DSS_DATA11, "ad26", NULL),
_OMAP3_BALLENTRY(DSS_DATA12, "aa25", NULL),
_OMAP3_BALLENTRY(DSS_DATA13, "y25", NULL),
_OMAP3_BALLENTRY(DSS_DATA14, "aa26", NULL),
_OMAP3_BALLENTRY(DSS_DATA15, "ab26", NULL),
_OMAP3_BALLENTRY(DSS_DATA16, "l25", NULL),
_OMAP3_BALLENTRY(DSS_DATA17, "l26", NULL),
_OMAP3_BALLENTRY(DSS_DATA18, "m24", NULL),
_OMAP3_BALLENTRY(DSS_DATA19, "m26", NULL),
_OMAP3_BALLENTRY(DSS_DATA2, "ae23", NULL),
_OMAP3_BALLENTRY(DSS_DATA20, "f25", NULL),
_OMAP3_BALLENTRY(DSS_DATA21, "n24", NULL),
_OMAP3_BALLENTRY(DSS_DATA22, "ac25", NULL),
_OMAP3_BALLENTRY(DSS_DATA23, "ab25", NULL),
_OMAP3_BALLENTRY(DSS_DATA3, "ae24", NULL),
_OMAP3_BALLENTRY(DSS_DATA4, "ad23", NULL),
_OMAP3_BALLENTRY(DSS_DATA5, "ad24", NULL),
_OMAP3_BALLENTRY(DSS_DATA6, "g26", NULL),
_OMAP3_BALLENTRY(DSS_DATA7, "h25", NULL),
_OMAP3_BALLENTRY(DSS_DATA8, "h26", NULL),
_OMAP3_BALLENTRY(DSS_DATA9, "j26", NULL),
_OMAP3_BALLENTRY(DSS_HSYNC, "k24", NULL),
_OMAP3_BALLENTRY(DSS_PCLK, "g25", NULL),
_OMAP3_BALLENTRY(DSS_VSYNC, "m25", NULL),
_OMAP3_BALLENTRY(ETK_CLK, "ab2", NULL),
_OMAP3_BALLENTRY(ETK_CTL, "ab3", NULL),
_OMAP3_BALLENTRY(ETK_D0, "ac3", NULL),
_OMAP3_BALLENTRY(ETK_D1, "ad4", NULL),
_OMAP3_BALLENTRY(ETK_D10, "ae4", NULL),
_OMAP3_BALLENTRY(ETK_D11, "af6", NULL),
_OMAP3_BALLENTRY(ETK_D12, "ae6", NULL),
_OMAP3_BALLENTRY(ETK_D13, "af7", NULL),
_OMAP3_BALLENTRY(ETK_D14, "af9", NULL),
_OMAP3_BALLENTRY(ETK_D15, "ae9", NULL),
_OMAP3_BALLENTRY(ETK_D2, "ad3", NULL),
_OMAP3_BALLENTRY(ETK_D3, "aa3", NULL),
_OMAP3_BALLENTRY(ETK_D4, "y3", NULL),
_OMAP3_BALLENTRY(ETK_D5, "ab1", NULL),
_OMAP3_BALLENTRY(ETK_D6, "ae3", NULL),
_OMAP3_BALLENTRY(ETK_D7, "ad2", NULL),
_OMAP3_BALLENTRY(ETK_D8, "aa4", NULL),
_OMAP3_BALLENTRY(ETK_D9, "v2", NULL),
_OMAP3_BALLENTRY(GPMC_A1, "j2", NULL),
_OMAP3_BALLENTRY(GPMC_A10, "d2", NULL),
_OMAP3_BALLENTRY(GPMC_A2, "h1", NULL),
_OMAP3_BALLENTRY(GPMC_A3, "h2", NULL),
_OMAP3_BALLENTRY(GPMC_A4, "g2", NULL),
_OMAP3_BALLENTRY(GPMC_A5, "f1", NULL),
_OMAP3_BALLENTRY(GPMC_A6, "f2", NULL),
_OMAP3_BALLENTRY(GPMC_A7, "e1", NULL),
_OMAP3_BALLENTRY(GPMC_A8, "e2", NULL),
_OMAP3_BALLENTRY(GPMC_A9, "d1", NULL),
_OMAP3_BALLENTRY(GPMC_CLK, "n1", "l1"),
_OMAP3_BALLENTRY(GPMC_D10, "t1", "n1"),
_OMAP3_BALLENTRY(GPMC_D11, "u2", "p2"),
_OMAP3_BALLENTRY(GPMC_D12, "u1", "p1"),
_OMAP3_BALLENTRY(GPMC_D13, "p1", "m1"),
_OMAP3_BALLENTRY(GPMC_D14, "l2", "j2"),
_OMAP3_BALLENTRY(GPMC_D15, "m2", "k2"),
_OMAP3_BALLENTRY(GPMC_D8, "v1", "r1"),
_OMAP3_BALLENTRY(GPMC_D9, "y1", "t1"),
_OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k2", NULL),
_OMAP3_BALLENTRY(GPMC_NBE1, "j1", NULL),
_OMAP3_BALLENTRY(GPMC_NCS1, "ad1", "w1"),
_OMAP3_BALLENTRY(GPMC_NCS2, "a3", NULL),
_OMAP3_BALLENTRY(GPMC_NCS3, "b6", NULL),
_OMAP3_BALLENTRY(GPMC_NCS4, "b4", NULL),
_OMAP3_BALLENTRY(GPMC_NCS5, "c4", NULL),
_OMAP3_BALLENTRY(GPMC_NCS6, "b5", NULL),
_OMAP3_BALLENTRY(GPMC_NCS7, "c5", NULL),
_OMAP3_BALLENTRY(GPMC_NWP, "ac6", "y5"),
_OMAP3_BALLENTRY(GPMC_WAIT1, "ac8", "y8"),
_OMAP3_BALLENTRY(GPMC_WAIT2, "b3", NULL),
_OMAP3_BALLENTRY(GPMC_WAIT3, "c6", NULL),
_OMAP3_BALLENTRY(HDQ_SIO, "j23", NULL),
_OMAP3_BALLENTRY(HSUSB0_CLK, "w19", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA0, "v20", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA1, "y20", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA2, "v18", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA3, "w20", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA4, "w17", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA5, "y18", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA6, "y19", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA7, "y17", NULL),
_OMAP3_BALLENTRY(HSUSB0_DIR, "v19", NULL),
_OMAP3_BALLENTRY(HSUSB0_NXT, "w18", NULL),
_OMAP3_BALLENTRY(HSUSB0_STP, "u20", NULL),
_OMAP3_BALLENTRY(I2C2_SCL, "c2", NULL),
_OMAP3_BALLENTRY(I2C2_SDA, "c1", NULL),
_OMAP3_BALLENTRY(I2C3_SCL, "ab4", NULL),
_OMAP3_BALLENTRY(I2C3_SDA, "ac4", NULL),
_OMAP3_BALLENTRY(I2C4_SCL, "ad15", NULL),
_OMAP3_BALLENTRY(I2C4_SDA, "w16", NULL),
_OMAP3_BALLENTRY(JTAG_EMU0, "y15", NULL),
_OMAP3_BALLENTRY(JTAG_EMU1, "y14", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKR, "u19", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKX, "t17", NULL),
_OMAP3_BALLENTRY(MCBSP1_DR, "t20", NULL),
_OMAP3_BALLENTRY(MCBSP1_DX, "u17", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSR, "v17", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSX, "p20", NULL),
_OMAP3_BALLENTRY(MCBSP2_CLKX, "r18", NULL),
_OMAP3_BALLENTRY(MCBSP2_DR, "t18", NULL),
_OMAP3_BALLENTRY(MCBSP2_DX, "r19", NULL),
_OMAP3_BALLENTRY(MCBSP2_FSX, "u18", NULL),
_OMAP3_BALLENTRY(MCBSP3_CLKX, "u3", NULL),
_OMAP3_BALLENTRY(MCBSP3_DR, "n3", NULL),
_OMAP3_BALLENTRY(MCBSP3_DX, "p3", NULL),
_OMAP3_BALLENTRY(MCBSP3_FSX, "w3", NULL),
_OMAP3_BALLENTRY(MCBSP4_CLKX, "v3", NULL),
_OMAP3_BALLENTRY(MCBSP4_DR, "u4", NULL),
_OMAP3_BALLENTRY(MCBSP4_DX, "r3", NULL),
_OMAP3_BALLENTRY(MCBSP4_FSX, "t3", NULL),
_OMAP3_BALLENTRY(MCBSP_CLKS, "t19", NULL),
_OMAP3_BALLENTRY(MCSPI1_CLK, "p9", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS0, "r7", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS1, "r8", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS2, "r9", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS3, "t8", NULL),
_OMAP3_BALLENTRY(MCSPI1_SIMO, "p8", NULL),
_OMAP3_BALLENTRY(MCSPI1_SOMI, "p7", NULL),
_OMAP3_BALLENTRY(MCSPI2_CLK, "w7", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS0, "v8", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS1, "v9", NULL),
_OMAP3_BALLENTRY(MCSPI2_SIMO, "w8", NULL),
_OMAP3_BALLENTRY(MCSPI2_SOMI, "u8", NULL),
_OMAP3_BALLENTRY(SDMMC1_CLK, "n19", NULL),
_OMAP3_BALLENTRY(SDMMC1_CMD, "l18", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT0, "m19", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT1, "m18", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT2, "k18", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT3, "n20", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT4, "m20", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT5, "p17", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT6, "p18", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT7, "p19", NULL),
_OMAP3_BALLENTRY(SDMMC2_CLK, "w10", NULL),
_OMAP3_BALLENTRY(SDMMC2_CMD, "r10", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT0, "t10", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT1, "t9", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT2, "u10", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT3, "u9", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT4, "v10", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT5, "m3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT6, "l3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT7, "k3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT0, "f3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT1, "d3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT2, "c3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT3, "e3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT4, "e4", NULL),
_OMAP3_BALLENTRY(SYS_BOOT5, "g3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT6, "d4", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT1, "ae14", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT2, "w11", NULL),
_OMAP3_BALLENTRY(SYS_CLKREQ, "w15", NULL),
_OMAP3_BALLENTRY(SYS_NIRQ, "v16", NULL),
_OMAP3_BALLENTRY(SYS_NRESWARM, "ad7", "aa5"),
_OMAP3_BALLENTRY(SYS_OFF_MODE, "v12", NULL),
_OMAP3_BALLENTRY(UART1_CTS, "w2", NULL),
_OMAP3_BALLENTRY(UART1_RTS, "r2", NULL),
_OMAP3_BALLENTRY(UART1_RX, "h3", NULL),
_OMAP3_BALLENTRY(UART1_TX, "l4", NULL),
_OMAP3_BALLENTRY(UART2_CTS, "y24", NULL),
_OMAP3_BALLENTRY(UART2_RTS, "aa24", NULL),
_OMAP3_BALLENTRY(UART2_RX, "ad21", NULL),
_OMAP3_BALLENTRY(UART2_TX, "ad22", NULL),
_OMAP3_BALLENTRY(UART3_CTS_RCTX, "f23", NULL),
_OMAP3_BALLENTRY(UART3_RTS_SD, "f24", NULL),
_OMAP3_BALLENTRY(UART3_RX_IRRX, "h24", NULL),
_OMAP3_BALLENTRY(UART3_TX_IRTX, "g24", NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap3_cbc_ball NULL
#endif
/*
* Signals different on CUS package compared to superset
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CUS)
struct omap_mux __initdata omap3_cus_subset[] = {
_OMAP3_MUXENTRY(CAM_D10, 109,
"cam_d10", NULL, NULL, NULL,
"gpio_109", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D11, 110,
"cam_d11", NULL, NULL, NULL,
"gpio_110", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D2, 101,
"cam_d2", NULL, NULL, NULL,
"gpio_101", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D3, 102,
"cam_d3", NULL, NULL, NULL,
"gpio_102", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D4, 103,
"cam_d4", NULL, NULL, NULL,
"gpio_103", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D5, 104,
"cam_d5", NULL, NULL, NULL,
"gpio_104", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_FLD, 98,
"cam_fld", NULL, "cam_global_reset", NULL,
"gpio_98", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_HS, 94,
"cam_hs", NULL, NULL, NULL,
"gpio_94", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_PCLK, 97,
"cam_pclk", NULL, NULL, NULL,
"gpio_97", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_STROBE, 126,
"cam_strobe", NULL, NULL, NULL,
"gpio_126", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_VS, 95,
"cam_vs", NULL, NULL, NULL,
"gpio_95", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_WEN, 167,
"cam_wen", NULL, "cam_shutter", NULL,
"gpio_167", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA6, 76,
"dss_data6", NULL, "uart1_tx", NULL,
"gpio_76", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA7, 77,
"dss_data7", NULL, "uart1_rx", NULL,
"gpio_77", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA8, 78,
"dss_data8", NULL, NULL, NULL,
"gpio_78", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA9, 79,
"dss_data9", NULL, NULL, NULL,
"gpio_79", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_HSYNC, 67,
"dss_hsync", NULL, NULL, NULL,
"gpio_67", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_PCLK, 66,
"dss_pclk", NULL, NULL, NULL,
"gpio_66", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(ETK_CLK, 12,
"etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
"gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL),
_OMAP3_MUXENTRY(ETK_CTL, 13,
"etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
"gpio_13", NULL, "hsusb1_tll_clk", NULL),
_OMAP3_MUXENTRY(ETK_D0, 14,
"etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
"gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL),
_OMAP3_MUXENTRY(ETK_D1, 15,
"etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
"gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL),
_OMAP3_MUXENTRY(ETK_D10, 24,
"etk_d10", NULL, "uart1_rx", "hsusb2_clk",
"gpio_24", NULL, "hsusb2_tll_clk", NULL),
_OMAP3_MUXENTRY(ETK_D11, 25,
"etk_d11", NULL, NULL, "hsusb2_stp",
"gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL),
_OMAP3_MUXENTRY(ETK_D12, 26,
"etk_d12", NULL, NULL, "hsusb2_dir",
"gpio_26", NULL, "hsusb2_tll_dir", NULL),
_OMAP3_MUXENTRY(ETK_D13, 27,
"etk_d13", NULL, NULL, "hsusb2_nxt",
"gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL),
_OMAP3_MUXENTRY(ETK_D14, 28,
"etk_d14", NULL, NULL, "hsusb2_data0",
"gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL),
_OMAP3_MUXENTRY(ETK_D15, 29,
"etk_d15", NULL, NULL, "hsusb2_data1",
"gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL),
_OMAP3_MUXENTRY(ETK_D2, 16,
"etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
"gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL),
_OMAP3_MUXENTRY(ETK_D3, 17,
"etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
"gpio_17", NULL, "hsusb1_tll_data7", NULL),
_OMAP3_MUXENTRY(ETK_D4, 18,
"etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
"gpio_18", NULL, "hsusb1_tll_data4", NULL),
_OMAP3_MUXENTRY(ETK_D5, 19,
"etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
"gpio_19", NULL, "hsusb1_tll_data5", NULL),
_OMAP3_MUXENTRY(ETK_D6, 20,
"etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
"gpio_20", NULL, "hsusb1_tll_data6", NULL),
_OMAP3_MUXENTRY(ETK_D7, 21,
"etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
"gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL),
_OMAP3_MUXENTRY(ETK_D8, 22,
"etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
"gpio_22", NULL, "hsusb1_tll_dir", NULL),
_OMAP3_MUXENTRY(ETK_D9, 23,
"etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
"gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL),
_OMAP3_MUXENTRY(MCBSP3_CLKX, 142,
"mcbsp3_clkx", "uart2_tx", NULL, NULL,
"gpio_142", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_DR, 141,
"mcbsp3_dr", "uart2_rts", NULL, NULL,
"gpio_141", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_DX, 140,
"mcbsp3_dx", "uart2_cts", NULL, NULL,
"gpio_140", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP3_FSX, 143,
"mcbsp3_fsx", "uart2_rx", NULL, NULL,
"gpio_143", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT5, 137,
"sdmmc2_dat5", "sdmmc2_dir_dat1",
"cam_global_reset", "sdmmc3_dat1",
"gpio_137", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT6, 138,
"sdmmc2_dat6", "sdmmc2_dir_cmd", "cam_shutter", "sdmmc3_dat2",
"gpio_138", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC2_DAT7, 139,
"sdmmc2_dat7", "sdmmc2_clkin", NULL, "sdmmc3_dat3",
"gpio_139", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_CTS, 150,
"uart1_cts", NULL, NULL, NULL,
"gpio_150", NULL, NULL, "safe_mode"),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap3_cus_subset NULL
#endif
/*
* Balls for CUS package
* 423-pin s-PBGA Package, 0.65mm Ball Pitch (Bottom)
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
&& defined(CONFIG_OMAP_PACKAGE_CUS)
struct omap_ball __initdata omap3_cus_ball[] = {
_OMAP3_BALLENTRY(CAM_D0, "ab18", NULL),
_OMAP3_BALLENTRY(CAM_D1, "ac18", NULL),
_OMAP3_BALLENTRY(CAM_D10, "f21", NULL),
_OMAP3_BALLENTRY(CAM_D11, "g21", NULL),
_OMAP3_BALLENTRY(CAM_D2, "g19", NULL),
_OMAP3_BALLENTRY(CAM_D3, "f19", NULL),
_OMAP3_BALLENTRY(CAM_D4, "g20", NULL),
_OMAP3_BALLENTRY(CAM_D5, "b21", NULL),
_OMAP3_BALLENTRY(CAM_D6, "l24", NULL),
_OMAP3_BALLENTRY(CAM_D7, "k24", NULL),
_OMAP3_BALLENTRY(CAM_D8, "j23", NULL),
_OMAP3_BALLENTRY(CAM_D9, "k23", NULL),
_OMAP3_BALLENTRY(CAM_FLD, "h24", NULL),
_OMAP3_BALLENTRY(CAM_HS, "a22", NULL),
_OMAP3_BALLENTRY(CAM_PCLK, "j19", NULL),
_OMAP3_BALLENTRY(CAM_STROBE, "j20", NULL),
_OMAP3_BALLENTRY(CAM_VS, "e18", NULL),
_OMAP3_BALLENTRY(CAM_WEN, "f18", NULL),
_OMAP3_BALLENTRY(CAM_XCLKA, "b22", NULL),
_OMAP3_BALLENTRY(CAM_XCLKB, "c22", NULL),
_OMAP3_BALLENTRY(DSS_ACBIAS, "j21", NULL),
_OMAP3_BALLENTRY(DSS_DATA0, "ac19", NULL),
_OMAP3_BALLENTRY(DSS_DATA1, "ab19", NULL),
_OMAP3_BALLENTRY(DSS_DATA10, "ac22", NULL),
_OMAP3_BALLENTRY(DSS_DATA11, "ac23", NULL),
_OMAP3_BALLENTRY(DSS_DATA12, "ab22", NULL),
_OMAP3_BALLENTRY(DSS_DATA13, "y22", NULL),
_OMAP3_BALLENTRY(DSS_DATA14, "w22", NULL),
_OMAP3_BALLENTRY(DSS_DATA15, "v22", NULL),
_OMAP3_BALLENTRY(DSS_DATA16, "j22", NULL),
_OMAP3_BALLENTRY(DSS_DATA17, "g23", NULL),
_OMAP3_BALLENTRY(DSS_DATA18, "g24", NULL),
_OMAP3_BALLENTRY(DSS_DATA19, "h23", NULL),
_OMAP3_BALLENTRY(DSS_DATA2, "ad20", NULL),
_OMAP3_BALLENTRY(DSS_DATA20, "d23", NULL),
_OMAP3_BALLENTRY(DSS_DATA21, "k22", NULL),
_OMAP3_BALLENTRY(DSS_DATA22, "v21", NULL),
_OMAP3_BALLENTRY(DSS_DATA23, "w21", NULL),
_OMAP3_BALLENTRY(DSS_DATA3, "ac20", NULL),
_OMAP3_BALLENTRY(DSS_DATA4, "ad21", NULL),
_OMAP3_BALLENTRY(DSS_DATA5, "ac21", NULL),
_OMAP3_BALLENTRY(DSS_DATA6, "d24", NULL),
_OMAP3_BALLENTRY(DSS_DATA7, "e23", NULL),
_OMAP3_BALLENTRY(DSS_DATA8, "e24", NULL),
_OMAP3_BALLENTRY(DSS_DATA9, "f23", NULL),
_OMAP3_BALLENTRY(DSS_HSYNC, "e22", NULL),
_OMAP3_BALLENTRY(DSS_PCLK, "g22", NULL),
_OMAP3_BALLENTRY(DSS_VSYNC, "f22", NULL),
_OMAP3_BALLENTRY(ETK_CLK, "ac1", NULL),
_OMAP3_BALLENTRY(ETK_CTL, "ad3", NULL),
_OMAP3_BALLENTRY(ETK_D0, "ad6", NULL),
_OMAP3_BALLENTRY(ETK_D1, "ac6", NULL),
_OMAP3_BALLENTRY(ETK_D10, "ac3", NULL),
_OMAP3_BALLENTRY(ETK_D11, "ac9", NULL),
_OMAP3_BALLENTRY(ETK_D12, "ac10", NULL),
_OMAP3_BALLENTRY(ETK_D13, "ad11", NULL),
_OMAP3_BALLENTRY(ETK_D14, "ac11", NULL),
_OMAP3_BALLENTRY(ETK_D15, "ad12", NULL),
_OMAP3_BALLENTRY(ETK_D2, "ac7", NULL),
_OMAP3_BALLENTRY(ETK_D3, "ad8", NULL),
_OMAP3_BALLENTRY(ETK_D4, "ac5", NULL),
_OMAP3_BALLENTRY(ETK_D5, "ad2", NULL),
_OMAP3_BALLENTRY(ETK_D6, "ac8", NULL),
_OMAP3_BALLENTRY(ETK_D7, "ad9", NULL),
_OMAP3_BALLENTRY(ETK_D8, "ac4", NULL),
_OMAP3_BALLENTRY(ETK_D9, "ad5", NULL),
_OMAP3_BALLENTRY(GPMC_A1, "k4", NULL),
_OMAP3_BALLENTRY(GPMC_A10, "g2", NULL),
_OMAP3_BALLENTRY(GPMC_A2, "k3", NULL),
_OMAP3_BALLENTRY(GPMC_A3, "k2", NULL),
_OMAP3_BALLENTRY(GPMC_A4, "j4", NULL),
_OMAP3_BALLENTRY(GPMC_A5, "j3", NULL),
_OMAP3_BALLENTRY(GPMC_A6, "j2", NULL),
_OMAP3_BALLENTRY(GPMC_A7, "j1", NULL),
_OMAP3_BALLENTRY(GPMC_A8, "h1", NULL),
_OMAP3_BALLENTRY(GPMC_A9, "h2", NULL),
_OMAP3_BALLENTRY(GPMC_CLK, "w2", NULL),
_OMAP3_BALLENTRY(GPMC_D10, "u1", NULL),
_OMAP3_BALLENTRY(GPMC_D11, "r3", NULL),
_OMAP3_BALLENTRY(GPMC_D12, "t3", NULL),
_OMAP3_BALLENTRY(GPMC_D13, "u2", NULL),
_OMAP3_BALLENTRY(GPMC_D14, "v1", NULL),
_OMAP3_BALLENTRY(GPMC_D15, "v2", NULL),
_OMAP3_BALLENTRY(GPMC_D8, "r2", NULL),
_OMAP3_BALLENTRY(GPMC_D9, "t2", NULL),
_OMAP3_BALLENTRY(GPMC_NBE0_CLE, "k5", NULL),
_OMAP3_BALLENTRY(GPMC_NBE1, "l1", NULL),
_OMAP3_BALLENTRY(GPMC_NCS3, "d2", NULL),
_OMAP3_BALLENTRY(GPMC_NCS4, "f4", NULL),
_OMAP3_BALLENTRY(GPMC_NCS5, "g5", NULL),
_OMAP3_BALLENTRY(GPMC_NCS6, "f3", NULL),
_OMAP3_BALLENTRY(GPMC_NCS7, "g4", NULL),
_OMAP3_BALLENTRY(GPMC_NWP, "e1", NULL),
_OMAP3_BALLENTRY(GPMC_WAIT3, "c2", NULL),
_OMAP3_BALLENTRY(HDQ_SIO, "a24", NULL),
_OMAP3_BALLENTRY(HSUSB0_CLK, "r21", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA0, "t24", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA1, "t23", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA2, "u24", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA3, "u23", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA4, "w24", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA5, "v23", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA6, "w23", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA7, "t22", NULL),
_OMAP3_BALLENTRY(HSUSB0_DIR, "p23", NULL),
_OMAP3_BALLENTRY(HSUSB0_NXT, "r22", NULL),
_OMAP3_BALLENTRY(HSUSB0_STP, "r23", NULL),
_OMAP3_BALLENTRY(I2C2_SCL, "ac15", NULL),
_OMAP3_BALLENTRY(I2C2_SDA, "ac14", NULL),
_OMAP3_BALLENTRY(I2C3_SCL, "ac13", NULL),
_OMAP3_BALLENTRY(I2C3_SDA, "ac12", NULL),
_OMAP3_BALLENTRY(I2C4_SCL, "y16", NULL),
_OMAP3_BALLENTRY(I2C4_SDA, "y15", NULL),
_OMAP3_BALLENTRY(JTAG_EMU0, "ac24", NULL),
_OMAP3_BALLENTRY(JTAG_EMU1, "ad24", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKR, "w19", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKX, "v18", NULL),
_OMAP3_BALLENTRY(MCBSP1_DR, "y18", NULL),
_OMAP3_BALLENTRY(MCBSP1_DX, "w18", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSR, "ab20", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSX, "aa19", NULL),
_OMAP3_BALLENTRY(MCBSP2_CLKX, "t21", NULL),
_OMAP3_BALLENTRY(MCBSP2_DR, "v19", NULL),
_OMAP3_BALLENTRY(MCBSP2_DX, "r20", NULL),
_OMAP3_BALLENTRY(MCBSP2_FSX, "v20", NULL),
_OMAP3_BALLENTRY(MCBSP3_CLKX, "w4", NULL),
_OMAP3_BALLENTRY(MCBSP3_DR, "v5", NULL),
_OMAP3_BALLENTRY(MCBSP3_DX, "v6", NULL),
_OMAP3_BALLENTRY(MCBSP3_FSX, "v4", NULL),
_OMAP3_BALLENTRY(MCBSP_CLKS, "aa18", NULL),
_OMAP3_BALLENTRY(MCSPI1_CLK, "t5", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS0, "t6", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS3, "r5", NULL),
_OMAP3_BALLENTRY(MCSPI1_SIMO, "r4", NULL),
_OMAP3_BALLENTRY(MCSPI1_SOMI, "t4", NULL),
_OMAP3_BALLENTRY(MCSPI2_CLK, "n5", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS0, "m5", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS1, "m4", NULL),
_OMAP3_BALLENTRY(MCSPI2_SIMO, "n4", NULL),
_OMAP3_BALLENTRY(MCSPI2_SOMI, "n3", NULL),
_OMAP3_BALLENTRY(SDMMC1_CLK, "m23", NULL),
_OMAP3_BALLENTRY(SDMMC1_CMD, "l23", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT0, "m22", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT1, "m21", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT2, "m20", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT3, "n23", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT4, "n22", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT5, "n21", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT6, "n20", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT7, "p24", NULL),
_OMAP3_BALLENTRY(SDMMC2_CLK, "y1", NULL),
_OMAP3_BALLENTRY(SDMMC2_CMD, "ab5", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT0, "ab3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT1, "y3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT2, "w3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT3, "v3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT4, "ab2", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT5, "aa2", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT6, "y2", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT7, "aa1", NULL),
_OMAP3_BALLENTRY(SYS_BOOT0, "ab12", NULL),
_OMAP3_BALLENTRY(SYS_BOOT1, "ac16", NULL),
_OMAP3_BALLENTRY(SYS_BOOT2, "ad17", NULL),
_OMAP3_BALLENTRY(SYS_BOOT3, "ad18", NULL),
_OMAP3_BALLENTRY(SYS_BOOT4, "ac17", NULL),
_OMAP3_BALLENTRY(SYS_BOOT5, "ab16", NULL),
_OMAP3_BALLENTRY(SYS_BOOT6, "aa15", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT1, "y7", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT2, "aa6", NULL),
_OMAP3_BALLENTRY(SYS_CLKREQ, "y13", NULL),
_OMAP3_BALLENTRY(SYS_NIRQ, "w16", NULL),
_OMAP3_BALLENTRY(SYS_NRESWARM, "y10", NULL),
_OMAP3_BALLENTRY(SYS_OFF_MODE, "ad23", NULL),
_OMAP3_BALLENTRY(UART1_CTS, "ac2", NULL),
_OMAP3_BALLENTRY(UART1_RTS, "w6", NULL),
_OMAP3_BALLENTRY(UART1_RX, "v7", NULL),
_OMAP3_BALLENTRY(UART1_TX, "w7", NULL),
_OMAP3_BALLENTRY(UART3_CTS_RCTX, "a23", NULL),
_OMAP3_BALLENTRY(UART3_RTS_SD, "b23", NULL),
_OMAP3_BALLENTRY(UART3_RX_IRRX, "b24", NULL),
_OMAP3_BALLENTRY(UART3_TX_IRTX, "c23", NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap3_cus_ball NULL
#endif
/*
* Signals different on CBB package comapared to superset
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBB)
struct omap_mux __initdata omap3_cbb_subset[] = {
_OMAP3_MUXENTRY(CAM_D10, 109,
"cam_d10", NULL, NULL, NULL,
"gpio_109", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D11, 110,
"cam_d11", NULL, NULL, NULL,
"gpio_110", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D2, 101,
"cam_d2", NULL, NULL, NULL,
"gpio_101", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D3, 102,
"cam_d3", NULL, NULL, NULL,
"gpio_102", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D4, 103,
"cam_d4", NULL, NULL, NULL,
"gpio_103", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D5, 104,
"cam_d5", NULL, NULL, NULL,
"gpio_104", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_FLD, 98,
"cam_fld", NULL, "cam_global_reset", NULL,
"gpio_98", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_HS, 94,
"cam_hs", NULL, NULL, NULL,
"gpio_94", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_PCLK, 97,
"cam_pclk", NULL, NULL, NULL,
"gpio_97", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_STROBE, 126,
"cam_strobe", NULL, NULL, NULL,
"gpio_126", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_VS, 95,
"cam_vs", NULL, NULL, NULL,
"gpio_95", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_WEN, 167,
"cam_wen", NULL, "cam_shutter", NULL,
"gpio_167", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA6, 76,
"dss_data6", NULL, "uart1_tx", NULL,
"gpio_76", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA7, 77,
"dss_data7", NULL, "uart1_rx", NULL,
"gpio_77", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA8, 78,
"dss_data8", NULL, NULL, NULL,
"gpio_78", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA9, 79,
"dss_data9", NULL, NULL, NULL,
"gpio_79", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_HSYNC, 67,
"dss_hsync", NULL, NULL, NULL,
"gpio_67", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_PCLK, 66,
"dss_pclk", NULL, NULL, NULL,
"gpio_66", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(ETK_CLK, 12,
"etk_clk", "mcbsp5_clkx", "sdmmc3_clk", "hsusb1_stp",
"gpio_12", "mm1_rxdp", "hsusb1_tll_stp", NULL),
_OMAP3_MUXENTRY(ETK_CTL, 13,
"etk_ctl", NULL, "sdmmc3_cmd", "hsusb1_clk",
"gpio_13", NULL, "hsusb1_tll_clk", NULL),
_OMAP3_MUXENTRY(ETK_D0, 14,
"etk_d0", "mcspi3_simo", "sdmmc3_dat4", "hsusb1_data0",
"gpio_14", "mm1_rxrcv", "hsusb1_tll_data0", NULL),
_OMAP3_MUXENTRY(ETK_D1, 15,
"etk_d1", "mcspi3_somi", NULL, "hsusb1_data1",
"gpio_15", "mm1_txse0", "hsusb1_tll_data1", NULL),
_OMAP3_MUXENTRY(ETK_D10, 24,
"etk_d10", NULL, "uart1_rx", "hsusb2_clk",
"gpio_24", NULL, "hsusb2_tll_clk", NULL),
_OMAP3_MUXENTRY(ETK_D11, 25,
"etk_d11", NULL, NULL, "hsusb2_stp",
"gpio_25", "mm2_rxdp", "hsusb2_tll_stp", NULL),
_OMAP3_MUXENTRY(ETK_D12, 26,
"etk_d12", NULL, NULL, "hsusb2_dir",
"gpio_26", NULL, "hsusb2_tll_dir", NULL),
_OMAP3_MUXENTRY(ETK_D13, 27,
"etk_d13", NULL, NULL, "hsusb2_nxt",
"gpio_27", "mm2_rxdm", "hsusb2_tll_nxt", NULL),
_OMAP3_MUXENTRY(ETK_D14, 28,
"etk_d14", NULL, NULL, "hsusb2_data0",
"gpio_28", "mm2_rxrcv", "hsusb2_tll_data0", NULL),
_OMAP3_MUXENTRY(ETK_D15, 29,
"etk_d15", NULL, NULL, "hsusb2_data1",
"gpio_29", "mm2_txse0", "hsusb2_tll_data1", NULL),
_OMAP3_MUXENTRY(ETK_D2, 16,
"etk_d2", "mcspi3_cs0", NULL, "hsusb1_data2",
"gpio_16", "mm1_txdat", "hsusb1_tll_data2", NULL),
_OMAP3_MUXENTRY(ETK_D3, 17,
"etk_d3", "mcspi3_clk", "sdmmc3_dat3", "hsusb1_data7",
"gpio_17", NULL, "hsusb1_tll_data7", NULL),
_OMAP3_MUXENTRY(ETK_D4, 18,
"etk_d4", "mcbsp5_dr", "sdmmc3_dat0", "hsusb1_data4",
"gpio_18", NULL, "hsusb1_tll_data4", NULL),
_OMAP3_MUXENTRY(ETK_D5, 19,
"etk_d5", "mcbsp5_fsx", "sdmmc3_dat1", "hsusb1_data5",
"gpio_19", NULL, "hsusb1_tll_data5", NULL),
_OMAP3_MUXENTRY(ETK_D6, 20,
"etk_d6", "mcbsp5_dx", "sdmmc3_dat2", "hsusb1_data6",
"gpio_20", NULL, "hsusb1_tll_data6", NULL),
_OMAP3_MUXENTRY(ETK_D7, 21,
"etk_d7", "mcspi3_cs1", "sdmmc3_dat7", "hsusb1_data3",
"gpio_21", "mm1_txen_n", "hsusb1_tll_data3", NULL),
_OMAP3_MUXENTRY(ETK_D8, 22,
"etk_d8", "sys_drm_msecure", "sdmmc3_dat6", "hsusb1_dir",
"gpio_22", NULL, "hsusb1_tll_dir", NULL),
_OMAP3_MUXENTRY(ETK_D9, 23,
"etk_d9", "sys_secure_indicator", "sdmmc3_dat5", "hsusb1_nxt",
"gpio_23", "mm1_rxdm", "hsusb1_tll_nxt", NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap3_cbb_subset NULL
#endif
/*
* Balls for CBB package
* 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom)
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
&& defined(CONFIG_OMAP_PACKAGE_CBB)
struct omap_ball __initdata omap3_cbb_ball[] = {
_OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
_OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
_OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
_OMAP3_BALLENTRY(CAM_D11, "c26", NULL),
_OMAP3_BALLENTRY(CAM_D2, "b24", NULL),
_OMAP3_BALLENTRY(CAM_D3, "c24", NULL),
_OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
_OMAP3_BALLENTRY(CAM_D5, "a25", NULL),
_OMAP3_BALLENTRY(CAM_D6, "k28", NULL),
_OMAP3_BALLENTRY(CAM_D7, "l28", NULL),
_OMAP3_BALLENTRY(CAM_D8, "k27", NULL),
_OMAP3_BALLENTRY(CAM_D9, "l27", NULL),
_OMAP3_BALLENTRY(CAM_FLD, "c23", NULL),
_OMAP3_BALLENTRY(CAM_HS, "a24", NULL),
_OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL),
_OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL),
_OMAP3_BALLENTRY(CAM_VS, "a23", NULL),
_OMAP3_BALLENTRY(CAM_WEN, "b23", NULL),
_OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
_OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL),
_OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL),
_OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL),
_OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL),
_OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL),
_OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL),
_OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL),
_OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL),
_OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL),
_OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL),
_OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL),
_OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL),
_OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL),
_OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL),
_OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL),
_OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL),
_OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL),
_OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL),
_OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL),
_OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL),
_OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL),
_OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL),
_OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL),
_OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL),
_OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL),
_OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL),
_OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL),
_OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL),
_OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL),
_OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL),
_OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL),
_OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL),
_OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL),
_OMAP3_BALLENTRY(ETK_CLK, "af10", NULL),
_OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL),
_OMAP3_BALLENTRY(ETK_D0, "af11", NULL),
_OMAP3_BALLENTRY(ETK_D1, "ag12", NULL),
_OMAP3_BALLENTRY(ETK_D10, "ae7", NULL),
_OMAP3_BALLENTRY(ETK_D11, "af7", NULL),
_OMAP3_BALLENTRY(ETK_D12, "ag7", NULL),
_OMAP3_BALLENTRY(ETK_D13, "ah7", NULL),
_OMAP3_BALLENTRY(ETK_D14, "ag8", NULL),
_OMAP3_BALLENTRY(ETK_D15, "ah8", NULL),
_OMAP3_BALLENTRY(ETK_D2, "ah12", NULL),
_OMAP3_BALLENTRY(ETK_D3, "ae13", NULL),
_OMAP3_BALLENTRY(ETK_D4, "ae11", NULL),
_OMAP3_BALLENTRY(ETK_D5, "ah9", NULL),
_OMAP3_BALLENTRY(ETK_D6, "af13", NULL),
_OMAP3_BALLENTRY(ETK_D7, "ah14", NULL),
_OMAP3_BALLENTRY(ETK_D8, "af9", NULL),
_OMAP3_BALLENTRY(ETK_D9, "ag9", NULL),
_OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"),
_OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"),
_OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"),
_OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"),
_OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"),
_OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"),
_OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"),
_OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"),
_OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"),
_OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"),
_OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"),
_OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"),
_OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"),
_OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"),
_OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"),
_OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"),
_OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"),
_OMAP3_BALLENTRY(GPMC_D8, "h2", "ab3"),
_OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"),
_OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"),
_OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL),
_OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"),
_OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL),
_OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"),
_OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"),
_OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL),
_OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL),
_OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL),
_OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL),
_OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL),
_OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL),
_OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL),
_OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL),
_OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL),
_OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL),
_OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL),
_OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL),
_OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL),
_OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL),
_OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL),
_OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL),
_OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL),
_OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL),
_OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL),
_OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL),
_OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL),
_OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL),
_OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL),
_OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL),
_OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL),
_OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL),
_OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL),
_OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL),
_OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL),
_OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL),
_OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL),
_OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL),
_OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL),
_OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL),
_OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL),
_OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL),
_OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL),
_OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT4, "p27", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT5, "p26", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT6, "r27", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT7, "r25", NULL),
_OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL),
_OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL),
_OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL),
_OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL),
_OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL),
_OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL),
_OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL),
_OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL),
_OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL),
_OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL),
_OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL),
_OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL),
_OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL),
_OMAP3_BALLENTRY(UART1_CTS, "w8", NULL),
_OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL),
_OMAP3_BALLENTRY(UART1_RX, "y8", NULL),
_OMAP3_BALLENTRY(UART1_TX, "aa8", NULL),
_OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL),
_OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL),
_OMAP3_BALLENTRY(UART2_RX, "ad25", NULL),
_OMAP3_BALLENTRY(UART2_TX, "aa25", NULL),
_OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL),
_OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL),
_OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL),
_OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap3_cbb_ball NULL
#endif
/*
* Signals different on 36XX CBP package comapared to 34XX CBC package
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_OMAP_PACKAGE_CBP)
struct omap_mux __initdata omap36xx_cbp_subset[] = {
_OMAP3_MUXENTRY(CAM_D0, 99,
"cam_d0", NULL, "csi2_dx2", NULL,
"gpio_99", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D1, 100,
"cam_d1", NULL, "csi2_dy2", NULL,
"gpio_100", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D10, 109,
"cam_d10", "ssi2_wake", NULL, NULL,
"gpio_109", "hw_dbg8", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D2, 101,
"cam_d2", "ssi2_rdy_tx", NULL, NULL,
"gpio_101", "hw_dbg4", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D3, 102,
"cam_d3", "ssi2_dat_rx", NULL, NULL,
"gpio_102", "hw_dbg5", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D4, 103,
"cam_d4", "ssi2_flag_rx", NULL, NULL,
"gpio_103", "hw_dbg6", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_D5, 104,
"cam_d5", "ssi2_rdy_rx", NULL, NULL,
"gpio_104", "hw_dbg7", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_HS, 94,
"cam_hs", "ssi2_dat_tx", NULL, NULL,
"gpio_94", "hw_dbg0", NULL, "safe_mode"),
_OMAP3_MUXENTRY(CAM_VS, 95,
"cam_vs", "ssi2_flag_tx", NULL, NULL,
"gpio_95", "hw_dbg1", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA0, 70,
"dss_data0", "dsi_dx0", "uart1_cts", NULL,
"gpio_70", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA1, 71,
"dss_data1", "dsi_dy0", "uart1_rts", NULL,
"gpio_71", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA2, 72,
"dss_data2", "dsi_dx1", NULL, NULL,
"gpio_72", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA3, 73,
"dss_data3", "dsi_dy1", NULL, NULL,
"gpio_73", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA4, 74,
"dss_data4", "dsi_dx2", "uart3_rx_irrx", NULL,
"gpio_74", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA5, 75,
"dss_data5", "dsi_dy2", "uart3_tx_irtx", NULL,
"gpio_75", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA6, 76,
"dss_data6", NULL, "uart1_tx", "dssvenc656_data6",
"gpio_76", "hw_dbg14", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA7, 77,
"dss_data7", NULL, "uart1_rx", "dssvenc656_data7",
"gpio_77", "hw_dbg15", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA8, 78,
"dss_data8", NULL, "uart3_rx_irrx", NULL,
"gpio_78", "hw_dbg16", NULL, "safe_mode"),
_OMAP3_MUXENTRY(DSS_DATA9, 79,
"dss_data9", NULL, "uart3_tx_irtx", NULL,
"gpio_79", "hw_dbg17", NULL, "safe_mode"),
_OMAP3_MUXENTRY(ETK_D12, 26,
"etk_d12", "sys_drm_msecure", NULL, "hsusb2_dir",
"gpio_26", NULL, "hsusb2_tll_dir", "hw_dbg14"),
_OMAP3_MUXENTRY(GPMC_A11, 0,
"gpmc_a11", NULL, NULL, NULL,
NULL, NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_WAIT2, 64,
"gpmc_wait2", NULL, "uart4_tx", NULL,
"gpio_64", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(GPMC_WAIT3, 65,
"gpmc_wait3", "sys_ndmareq1", "uart4_rx", NULL,
"gpio_65", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA0, 125,
"hsusb0_data0", NULL, "uart3_tx_irtx", NULL,
"gpio_125", "uart2_tx", NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA1, 130,
"hsusb0_data1", NULL, "uart3_rx_irrx", NULL,
"gpio_130", "uart2_rx", NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA2, 131,
"hsusb0_data2", NULL, "uart3_rts_sd", NULL,
"gpio_131", "uart2_rts", NULL, "safe_mode"),
_OMAP3_MUXENTRY(HSUSB0_DATA3, 169,
"hsusb0_data3", NULL, "uart3_cts_rctx", NULL,
"gpio_169", "uart2_cts", NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_CLKR, 156,
"mcbsp1_clkr", "mcspi4_clk", "sim_cd", NULL,
"gpio_156", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP1_FSR, 157,
"mcbsp1_fsr", "adpllv2d_dithering_en1",
"cam_global_reset", NULL,
"gpio_157", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_CLKX, 152,
"mcbsp4_clkx", "ssi1_dat_rx", NULL, NULL,
"gpio_152", "hsusb3_tll_data1", "mm3_txse0", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_DR, 153,
"mcbsp4_dr", "ssi1_flag_rx", NULL, NULL,
"gpio_153", "hsusb3_tll_data0", "mm3_rxrcv", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_DX, 154,
"mcbsp4_dx", "ssi1_rdy_rx", NULL, NULL,
"gpio_154", "hsusb3_tll_data2", "mm3_txdat", "safe_mode"),
_OMAP3_MUXENTRY(MCBSP4_FSX, 155,
"mcbsp4_fsx", "ssi1_wake", NULL, NULL,
"gpio_155", "hsusb3_tll_data3", "mm3_txen_n", "safe_mode"),
_OMAP3_MUXENTRY(MCSPI1_CS1, 175,
"mcspi1_cs1", "adpllv2d_dithering_en2", NULL, "sdmmc3_cmd",
"gpio_175", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SAD2D_MBUSFLAG, 0,
"sad2d_mbusflag", "mad2d_sbusflag", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD28, 0,
"sad2d_mcad28", "mad2d_mcad28", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD29, 0,
"sad2d_mcad29", "mad2d_mcad29", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD32, 0,
"sad2d_mcad32", "mad2d_mcad32", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD33, 0,
"sad2d_mcad33", "mad2d_mcad33", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD34, 0,
"sad2d_mcad34", "mad2d_mcad34", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD35, 0,
"sad2d_mcad35", "mad2d_mcad35", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MCAD36, 0,
"sad2d_mcad36", "mad2d_mcad36", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MREAD, 0,
"sad2d_mread", "mad2d_sread", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_MWRITE, 0,
"sad2d_mwrite", "mad2d_swrite", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_SBUSFLAG, 0,
"sad2d_sbusflag", "mad2d_mbusflag", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_SREAD, 0,
"sad2d_sread", "mad2d_mread", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SAD2D_SWRITE, 0,
"sad2d_swrite", "mad2d_mwrite", NULL, NULL,
NULL, NULL, NULL, NULL),
_OMAP3_MUXENTRY(SDMMC1_CLK, 120,
"sdmmc1_clk", "ms_clk", NULL, NULL,
"gpio_120", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_CMD, 121,
"sdmmc1_cmd", "ms_bs", NULL, NULL,
"gpio_121", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT0, 122,
"sdmmc1_dat0", "ms_dat0", NULL, NULL,
"gpio_122", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT1, 123,
"sdmmc1_dat1", "ms_dat1", NULL, NULL,
"gpio_123", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT2, 124,
"sdmmc1_dat2", "ms_dat2", NULL, NULL,
"gpio_124", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDMMC1_DAT3, 125,
"sdmmc1_dat3", "ms_dat3", NULL, NULL,
"gpio_125", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SDRC_CKE0, 0,
"sdrc_cke0", NULL, NULL, NULL,
NULL, NULL, NULL, "safe_mode_out1"),
_OMAP3_MUXENTRY(SDRC_CKE1, 0,
"sdrc_cke1", NULL, NULL, NULL,
NULL, NULL, NULL, "safe_mode_out1"),
_OMAP3_MUXENTRY(SIM_IO, 126,
"sim_io", "sim_io_low_impedance", NULL, NULL,
"gpio_126", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SIM_CLK, 127,
"sim_clk", NULL, NULL, NULL,
"gpio_127", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SIM_PWRCTRL, 128,
"sim_pwrctrl", NULL, NULL, NULL,
"gpio_128", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SIM_RST, 129,
"sim_rst", NULL, NULL, NULL,
"gpio_129", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT0, 2,
"sys_boot0", NULL, NULL, "dss_data18",
"gpio_2", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT1, 3,
"sys_boot1", NULL, NULL, "dss_data19",
"gpio_3", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT3, 5,
"sys_boot3", NULL, NULL, "dss_data20",
"gpio_5", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT4, 6,
"sys_boot4", "sdmmc2_dir_dat2", NULL, "dss_data21",
"gpio_6", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT5, 7,
"sys_boot5", "sdmmc2_dir_dat3", NULL, "dss_data22",
"gpio_7", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(SYS_BOOT6, 8,
"sys_boot6", NULL, NULL, "dss_data23",
"gpio_8", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_CTS, 150,
"uart1_cts", "ssi1_rdy_tx", NULL, NULL,
"gpio_150", "hsusb3_tll_clk", NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_RTS, 149,
"uart1_rts", "ssi1_flag_tx", NULL, NULL,
"gpio_149", NULL, NULL, "safe_mode"),
_OMAP3_MUXENTRY(UART1_TX, 148,
"uart1_tx", "ssi1_dat_tx", NULL, NULL,
"gpio_148", NULL, NULL, "safe_mode"),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap36xx_cbp_subset NULL
#endif
/*
* Balls for 36XX CBP package
* 515-pin s-PBGA Package, 0.50mm Ball Pitch (Top), 0.40mm Ball Pitch (Bottom)
*/
#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \
&& defined (CONFIG_OMAP_PACKAGE_CBP)
struct omap_ball __initdata omap36xx_cbp_ball[] = {
_OMAP3_BALLENTRY(CAM_D0, "ag17", NULL),
_OMAP3_BALLENTRY(CAM_D1, "ah17", NULL),
_OMAP3_BALLENTRY(CAM_D10, "b25", NULL),
_OMAP3_BALLENTRY(CAM_D11, "c26", NULL),
_OMAP3_BALLENTRY(CAM_D2, "b24", NULL),
_OMAP3_BALLENTRY(CAM_D3, "c24", NULL),
_OMAP3_BALLENTRY(CAM_D4, "d24", NULL),
_OMAP3_BALLENTRY(CAM_D5, "a25", NULL),
_OMAP3_BALLENTRY(CAM_D6, "k28", NULL),
_OMAP3_BALLENTRY(CAM_D7, "l28", NULL),
_OMAP3_BALLENTRY(CAM_D8, "k27", NULL),
_OMAP3_BALLENTRY(CAM_D9, "l27", NULL),
_OMAP3_BALLENTRY(CAM_FLD, "c23", NULL),
_OMAP3_BALLENTRY(CAM_HS, "a24", NULL),
_OMAP3_BALLENTRY(CAM_PCLK, "c27", NULL),
_OMAP3_BALLENTRY(CAM_STROBE, "d25", NULL),
_OMAP3_BALLENTRY(CAM_VS, "a23", NULL),
_OMAP3_BALLENTRY(CAM_WEN, "b23", NULL),
_OMAP3_BALLENTRY(CAM_XCLKA, "c25", NULL),
_OMAP3_BALLENTRY(CAM_XCLKB, "b26", NULL),
_OMAP3_BALLENTRY(CSI2_DX0, "ag19", NULL),
_OMAP3_BALLENTRY(CSI2_DX1, "ag18", NULL),
_OMAP3_BALLENTRY(CSI2_DY0, "ah19", NULL),
_OMAP3_BALLENTRY(CSI2_DY1, "ah18", NULL),
_OMAP3_BALLENTRY(DSS_ACBIAS, "e27", NULL),
_OMAP3_BALLENTRY(DSS_DATA0, "ag22", NULL),
_OMAP3_BALLENTRY(DSS_DATA1, "ah22", NULL),
_OMAP3_BALLENTRY(DSS_DATA10, "ad28", NULL),
_OMAP3_BALLENTRY(DSS_DATA11, "ad27", NULL),
_OMAP3_BALLENTRY(DSS_DATA12, "ab28", NULL),
_OMAP3_BALLENTRY(DSS_DATA13, "ab27", NULL),
_OMAP3_BALLENTRY(DSS_DATA14, "aa28", NULL),
_OMAP3_BALLENTRY(DSS_DATA15, "aa27", NULL),
_OMAP3_BALLENTRY(DSS_DATA16, "g25", NULL),
_OMAP3_BALLENTRY(DSS_DATA17, "h27", NULL),
_OMAP3_BALLENTRY(DSS_DATA18, "h26", NULL),
_OMAP3_BALLENTRY(DSS_DATA19, "h25", NULL),
_OMAP3_BALLENTRY(DSS_DATA2, "ag23", NULL),
_OMAP3_BALLENTRY(DSS_DATA20, "e28", NULL),
_OMAP3_BALLENTRY(DSS_DATA21, "j26", NULL),
_OMAP3_BALLENTRY(DSS_DATA22, "ac27", NULL),
_OMAP3_BALLENTRY(DSS_DATA23, "ac28", NULL),
_OMAP3_BALLENTRY(DSS_DATA3, "ah23", NULL),
_OMAP3_BALLENTRY(DSS_DATA4, "ag24", NULL),
_OMAP3_BALLENTRY(DSS_DATA5, "ah24", NULL),
_OMAP3_BALLENTRY(DSS_DATA6, "e26", NULL),
_OMAP3_BALLENTRY(DSS_DATA7, "f28", NULL),
_OMAP3_BALLENTRY(DSS_DATA8, "f27", NULL),
_OMAP3_BALLENTRY(DSS_DATA9, "g26", NULL),
_OMAP3_BALLENTRY(DSS_HSYNC, "d26", NULL),
_OMAP3_BALLENTRY(DSS_PCLK, "d28", NULL),
_OMAP3_BALLENTRY(DSS_VSYNC, "d27", NULL),
_OMAP3_BALLENTRY(ETK_CLK, "af10", NULL),
_OMAP3_BALLENTRY(ETK_CTL, "ae10", NULL),
_OMAP3_BALLENTRY(ETK_D0, "af11", NULL),
_OMAP3_BALLENTRY(ETK_D1, "ag12", NULL),
_OMAP3_BALLENTRY(ETK_D10, "ae7", NULL),
_OMAP3_BALLENTRY(ETK_D11, "af7", NULL),
_OMAP3_BALLENTRY(ETK_D12, "ag7", NULL),
_OMAP3_BALLENTRY(ETK_D13, "ah7", NULL),
_OMAP3_BALLENTRY(ETK_D14, "ag8", NULL),
_OMAP3_BALLENTRY(ETK_D15, "ah8", NULL),
_OMAP3_BALLENTRY(ETK_D2, "ah12", NULL),
_OMAP3_BALLENTRY(ETK_D3, "ae13", NULL),
_OMAP3_BALLENTRY(ETK_D4, "ae11", NULL),
_OMAP3_BALLENTRY(ETK_D5, "ah9", NULL),
_OMAP3_BALLENTRY(ETK_D6, "af13", NULL),
_OMAP3_BALLENTRY(ETK_D7, "ah14", NULL),
_OMAP3_BALLENTRY(ETK_D8, "af9", NULL),
_OMAP3_BALLENTRY(ETK_D9, "ag9", NULL),
_OMAP3_BALLENTRY(GPMC_A1, "n4", "ac15"),
_OMAP3_BALLENTRY(GPMC_A10, "k3", "ab19"),
_OMAP3_BALLENTRY(GPMC_A11, NULL, "ac20"),
_OMAP3_BALLENTRY(GPMC_A2, "m4", "ab15"),
_OMAP3_BALLENTRY(GPMC_A3, "l4", "ac16"),
_OMAP3_BALLENTRY(GPMC_A4, "k4", "ab16"),
_OMAP3_BALLENTRY(GPMC_A5, "t3", "ac17"),
_OMAP3_BALLENTRY(GPMC_A6, "r3", "ab17"),
_OMAP3_BALLENTRY(GPMC_A7, "n3", "ac18"),
_OMAP3_BALLENTRY(GPMC_A8, "m3", "ab18"),
_OMAP3_BALLENTRY(GPMC_A9, "l3", "ac19"),
_OMAP3_BALLENTRY(GPMC_CLK, "t4", "w2"),
_OMAP3_BALLENTRY(GPMC_D0, "k1", "m2"),
_OMAP3_BALLENTRY(GPMC_D1, "l1", "m1"),
_OMAP3_BALLENTRY(GPMC_D10, "p1", "ab4"),
_OMAP3_BALLENTRY(GPMC_D11, "r1", "ac4"),
_OMAP3_BALLENTRY(GPMC_D12, "r2", "ab6"),
_OMAP3_BALLENTRY(GPMC_D13, "t2", "ac6"),
_OMAP3_BALLENTRY(GPMC_D14, "w1", "ab7"),
_OMAP3_BALLENTRY(GPMC_D15, "y1", "ac7"),
_OMAP3_BALLENTRY(GPMC_D2, "l2", "n2"),
_OMAP3_BALLENTRY(GPMC_D3, "p2", "n1"),
_OMAP3_BALLENTRY(GPMC_D4, "t1", "r2"),
_OMAP3_BALLENTRY(GPMC_D5, "v1", "r1"),
_OMAP3_BALLENTRY(GPMC_D6, "v2", "t2"),
_OMAP3_BALLENTRY(GPMC_D7, "w2", "t1"),
_OMAP3_BALLENTRY(GPMC_D8, "h2", "ab3"),
_OMAP3_BALLENTRY(GPMC_D9, "k2", "ac3"),
_OMAP3_BALLENTRY(GPMC_NADV_ALE, "f3", "w1"),
_OMAP3_BALLENTRY(GPMC_NBE0_CLE, "g3", "ac12"),
_OMAP3_BALLENTRY(GPMC_NBE1, "u3", NULL),
_OMAP3_BALLENTRY(GPMC_NCS0, "g4", "y2"),
_OMAP3_BALLENTRY(GPMC_NCS1, "h3", "y1"),
_OMAP3_BALLENTRY(GPMC_NCS2, "v8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS3, "u8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS4, "t8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS5, "r8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS6, "p8", NULL),
_OMAP3_BALLENTRY(GPMC_NCS7, "n8", NULL),
_OMAP3_BALLENTRY(GPMC_NOE, "g2", "v2"),
_OMAP3_BALLENTRY(GPMC_NWE, "f4", "v1"),
_OMAP3_BALLENTRY(GPMC_NWP, "h1", "ab10"),
_OMAP3_BALLENTRY(GPMC_WAIT0, "m8", "ab12"),
_OMAP3_BALLENTRY(GPMC_WAIT1, "l8", "ac10"),
_OMAP3_BALLENTRY(GPMC_WAIT2, "k8", NULL),
_OMAP3_BALLENTRY(GPMC_WAIT3, "j8", NULL),
_OMAP3_BALLENTRY(HDQ_SIO, "j25", NULL),
_OMAP3_BALLENTRY(HSUSB0_CLK, "t28", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA0, "t27", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA1, "u28", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA2, "u27", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA3, "u26", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA4, "u25", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA5, "v28", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA6, "v27", NULL),
_OMAP3_BALLENTRY(HSUSB0_DATA7, "v26", NULL),
_OMAP3_BALLENTRY(HSUSB0_DIR, "r28", NULL),
_OMAP3_BALLENTRY(HSUSB0_NXT, "t26", NULL),
_OMAP3_BALLENTRY(HSUSB0_STP, "t25", NULL),
_OMAP3_BALLENTRY(I2C1_SCL, "k21", NULL),
_OMAP3_BALLENTRY(I2C1_SDA, "j21", NULL),
_OMAP3_BALLENTRY(I2C2_SCL, "af15", NULL),
_OMAP3_BALLENTRY(I2C2_SDA, "ae15", NULL),
_OMAP3_BALLENTRY(I2C3_SCL, "af14", NULL),
_OMAP3_BALLENTRY(I2C3_SDA, "ag14", NULL),
_OMAP3_BALLENTRY(I2C4_SCL, "ad26", NULL),
_OMAP3_BALLENTRY(I2C4_SDA, "ae26", NULL),
_OMAP3_BALLENTRY(JTAG_EMU0, "aa11", NULL),
_OMAP3_BALLENTRY(JTAG_EMU1, "aa10", NULL),
_OMAP3_BALLENTRY(JTAG_RTCK, "aa12", NULL),
_OMAP3_BALLENTRY(JTAG_TCK, "aa13", NULL),
_OMAP3_BALLENTRY(JTAG_TDI, "aa20", NULL),
_OMAP3_BALLENTRY(JTAG_TDO, "aa19", NULL),
_OMAP3_BALLENTRY(JTAG_TMS_TMSC, "aa18", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKR, "y21", NULL),
_OMAP3_BALLENTRY(MCBSP1_CLKX, "w21", NULL),
_OMAP3_BALLENTRY(MCBSP1_DR, "u21", NULL),
_OMAP3_BALLENTRY(MCBSP1_DX, "v21", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSR, "aa21", NULL),
_OMAP3_BALLENTRY(MCBSP1_FSX, "k26", NULL),
_OMAP3_BALLENTRY(MCBSP2_CLKX, "n21", NULL),
_OMAP3_BALLENTRY(MCBSP2_DR, "r21", NULL),
_OMAP3_BALLENTRY(MCBSP2_DX, "m21", NULL),
_OMAP3_BALLENTRY(MCBSP2_FSX, "p21", NULL),
_OMAP3_BALLENTRY(MCBSP3_CLKX, "af5", NULL),
_OMAP3_BALLENTRY(MCBSP3_DR, "ae6", NULL),
_OMAP3_BALLENTRY(MCBSP3_DX, "af6", NULL),
_OMAP3_BALLENTRY(MCBSP3_FSX, "ae5", NULL),
_OMAP3_BALLENTRY(MCBSP4_CLKX, "ae1", NULL),
_OMAP3_BALLENTRY(MCBSP4_DR, "ad1", NULL),
_OMAP3_BALLENTRY(MCBSP4_DX, "ad2", NULL),
_OMAP3_BALLENTRY(MCBSP4_FSX, "ac1", NULL),
_OMAP3_BALLENTRY(MCBSP_CLKS, "t21", NULL),
_OMAP3_BALLENTRY(MCSPI1_CLK, "ab3", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS0, "ac2", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS1, "ac3", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS2, "ab1", NULL),
_OMAP3_BALLENTRY(MCSPI1_CS3, "ab2", NULL),
_OMAP3_BALLENTRY(MCSPI1_SIMO, "ab4", NULL),
_OMAP3_BALLENTRY(MCSPI1_SOMI, "aa4", NULL),
_OMAP3_BALLENTRY(MCSPI2_CLK, "aa3", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS0, "y4", NULL),
_OMAP3_BALLENTRY(MCSPI2_CS1, "v3", NULL),
_OMAP3_BALLENTRY(MCSPI2_SIMO, "y2", NULL),
_OMAP3_BALLENTRY(MCSPI2_SOMI, "y3", NULL),
_OMAP3_BALLENTRY(SDMMC1_CLK, "n28", NULL),
_OMAP3_BALLENTRY(SDMMC1_CMD, "m27", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT0, "n27", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT1, "n26", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT2, "n25", NULL),
_OMAP3_BALLENTRY(SDMMC1_DAT3, "p28", NULL),
_OMAP3_BALLENTRY(SDMMC2_CLK, "ae2", NULL),
_OMAP3_BALLENTRY(SDMMC2_CMD, "ag5", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT0, "ah5", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT1, "ah4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT2, "ag4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT3, "af4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT4, "ae4", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT5, "ah3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT6, "af3", NULL),
_OMAP3_BALLENTRY(SDMMC2_DAT7, "ae3", NULL),
_OMAP3_BALLENTRY(SDRC_A0, NULL, "n22"),
_OMAP3_BALLENTRY(SDRC_A1, NULL, "n23"),
_OMAP3_BALLENTRY(SDRC_A10, NULL, "v22"),
_OMAP3_BALLENTRY(SDRC_A11, NULL, "v23"),
_OMAP3_BALLENTRY(SDRC_A12, NULL, "w22"),
_OMAP3_BALLENTRY(SDRC_A13, NULL, "w23"),
_OMAP3_BALLENTRY(SDRC_A14, NULL, "y22"),
_OMAP3_BALLENTRY(SDRC_A2, NULL, "p22"),
_OMAP3_BALLENTRY(SDRC_A3, NULL, "p23"),
_OMAP3_BALLENTRY(SDRC_A4, NULL, "r22"),
_OMAP3_BALLENTRY(SDRC_A5, NULL, "r23"),
_OMAP3_BALLENTRY(SDRC_A6, NULL, "t22"),
_OMAP3_BALLENTRY(SDRC_A7, NULL, "t23"),
_OMAP3_BALLENTRY(SDRC_A8, NULL, "u22"),
_OMAP3_BALLENTRY(SDRC_A9, NULL, "u23"),
_OMAP3_BALLENTRY(SDRC_BA0, "h9", "ab21"),
_OMAP3_BALLENTRY(SDRC_BA1, "h10", "ac21"),
_OMAP3_BALLENTRY(SDRC_CKE0, "h16", "j22"),
_OMAP3_BALLENTRY(SDRC_CKE1, "h17", "j23"),
_OMAP3_BALLENTRY(SDRC_CLK, "a13", "a11"),
_OMAP3_BALLENTRY(SDRC_D0, NULL, "j2"),
_OMAP3_BALLENTRY(SDRC_D1, NULL, "j1"),
_OMAP3_BALLENTRY(SDRC_D10, "c15", "b14"),
_OMAP3_BALLENTRY(SDRC_D11, "b16", "a14"),
_OMAP3_BALLENTRY(SDRC_D12, "d17", "b16"),
_OMAP3_BALLENTRY(SDRC_D13, "c17", "a16"),
_OMAP3_BALLENTRY(SDRC_D14, "b17", "b19"),
_OMAP3_BALLENTRY(SDRC_D15, "d18", "a19"),
_OMAP3_BALLENTRY(SDRC_D16, NULL, "b3"),
_OMAP3_BALLENTRY(SDRC_D17, NULL, "a3"),
_OMAP3_BALLENTRY(SDRC_D18, NULL, "b5"),
_OMAP3_BALLENTRY(SDRC_D19, NULL, "a5"),
_OMAP3_BALLENTRY(SDRC_D2, NULL, "g2"),
_OMAP3_BALLENTRY(SDRC_D20, NULL, "b8"),
_OMAP3_BALLENTRY(SDRC_D21, NULL, "a8"),
_OMAP3_BALLENTRY(SDRC_D22, NULL, "b9"),
_OMAP3_BALLENTRY(SDRC_D23, NULL, "a9"),
_OMAP3_BALLENTRY(SDRC_D24, NULL, "b21"),
_OMAP3_BALLENTRY(SDRC_D25, NULL, "a21"),
_OMAP3_BALLENTRY(SDRC_D26, NULL, "d22"),
_OMAP3_BALLENTRY(SDRC_D27, NULL, "d23"),
_OMAP3_BALLENTRY(SDRC_D28, NULL, "e22"),
_OMAP3_BALLENTRY(SDRC_D29, NULL, "e23"),
_OMAP3_BALLENTRY(SDRC_D3, NULL, "g1"),
_OMAP3_BALLENTRY(SDRC_D30, NULL, "g22"),
_OMAP3_BALLENTRY(SDRC_D31, NULL, "g23"),
_OMAP3_BALLENTRY(SDRC_D4, NULL, "f2"),
_OMAP3_BALLENTRY(SDRC_D5, NULL, "f1"),
_OMAP3_BALLENTRY(SDRC_D6, NULL, "d2"),
_OMAP3_BALLENTRY(SDRC_D7, NULL, "d1"),
_OMAP3_BALLENTRY(SDRC_D8, "c14", "b13"),
_OMAP3_BALLENTRY(SDRC_D9, "b14", "a13"),
_OMAP3_BALLENTRY(SDRC_DM0, NULL, "c1"),
_OMAP3_BALLENTRY(SDRC_DM1, "a16", "a17"),
_OMAP3_BALLENTRY(SDRC_DM2, NULL, "a6"),
_OMAP3_BALLENTRY(SDRC_DM3, NULL, "a20"),
_OMAP3_BALLENTRY(SDRC_DQS0, NULL, "c2"),
_OMAP3_BALLENTRY(SDRC_DQS1, "a17", "b17"),
_OMAP3_BALLENTRY(SDRC_DQS2, NULL, "b6"),
_OMAP3_BALLENTRY(SDRC_DQS3, NULL, "b20"),
_OMAP3_BALLENTRY(SDRC_NCAS, "h13", "l22"),
_OMAP3_BALLENTRY(SDRC_NCLK, "a14", "b11"),
_OMAP3_BALLENTRY(SDRC_NCS0, "h11", "m22"),
_OMAP3_BALLENTRY(SDRC_NCS1, "h12", "m23"),
_OMAP3_BALLENTRY(SDRC_NRAS, "h14", "l23"),
_OMAP3_BALLENTRY(SDRC_NWE, "h15", "k23"),
_OMAP3_BALLENTRY(SIM_CLK, "p26", NULL),
_OMAP3_BALLENTRY(SIM_IO, "p27", NULL),
_OMAP3_BALLENTRY(SIM_PWRCTRL, "r27", NULL),
_OMAP3_BALLENTRY(SIM_RST, "r25", NULL),
_OMAP3_BALLENTRY(SYS_32K, "ae25", NULL),
_OMAP3_BALLENTRY(SYS_BOOT0, "ah26", NULL),
_OMAP3_BALLENTRY(SYS_BOOT1, "ag26", NULL),
_OMAP3_BALLENTRY(SYS_BOOT2, "ae14", NULL),
_OMAP3_BALLENTRY(SYS_BOOT3, "af18", NULL),
_OMAP3_BALLENTRY(SYS_BOOT4, "af19", NULL),
_OMAP3_BALLENTRY(SYS_BOOT5, "ae21", NULL),
_OMAP3_BALLENTRY(SYS_BOOT6, "af21", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT1, "ag25", NULL),
_OMAP3_BALLENTRY(SYS_CLKOUT2, "ae22", NULL),
_OMAP3_BALLENTRY(SYS_CLKREQ, "af25", NULL),
_OMAP3_BALLENTRY(SYS_NIRQ, "af26", NULL),
_OMAP3_BALLENTRY(SYS_NRESWARM, "af24", NULL),
_OMAP3_BALLENTRY(SYS_OFF_MODE, "af22", NULL),
_OMAP3_BALLENTRY(UART1_CTS, "w8", NULL),
_OMAP3_BALLENTRY(UART1_RTS, "aa9", NULL),
_OMAP3_BALLENTRY(UART1_RX, "y8", NULL),
_OMAP3_BALLENTRY(UART1_TX, "aa8", NULL),
_OMAP3_BALLENTRY(UART2_CTS, "ab26", NULL),
_OMAP3_BALLENTRY(UART2_RTS, "ab25", NULL),
_OMAP3_BALLENTRY(UART2_RX, "ad25", NULL),
_OMAP3_BALLENTRY(UART2_TX, "aa25", NULL),
_OMAP3_BALLENTRY(UART3_CTS_RCTX, "h18", NULL),
_OMAP3_BALLENTRY(UART3_RTS_SD, "h19", NULL),
_OMAP3_BALLENTRY(UART3_RX_IRRX, "h20", NULL),
_OMAP3_BALLENTRY(UART3_TX_IRTX, "h21", NULL),
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
#else
#define omap36xx_cbp_ball NULL
#endif
int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags)
{
struct omap_mux *package_subset;
struct omap_ball *package_balls;
switch (flags & OMAP_PACKAGE_MASK) {
case (OMAP_PACKAGE_CBC):
package_subset = omap3_cbc_subset;
package_balls = omap3_cbc_ball;
break;
case (OMAP_PACKAGE_CBB):
package_subset = omap3_cbb_subset;
package_balls = omap3_cbb_ball;
break;
case (OMAP_PACKAGE_CUS):
package_subset = omap3_cus_subset;
package_balls = omap3_cus_ball;
break;
case (OMAP_PACKAGE_CBP):
package_subset = omap36xx_cbp_subset;
package_balls = omap36xx_cbp_ball;
break;
default:
printk(KERN_ERR "mux: Unknown omap package, mux disabled\n");
return -EINVAL;
}
return omap_mux_init(OMAP3_CONTROL_PADCONF_MUX_PBASE,
OMAP3_CONTROL_PADCONF_MUX_SIZE,
omap3_muxmodes, package_subset, board_subset,
package_balls);
}
arch/arm/mach-omap2/mux34xx.h 0 → 100644
View file @ 5ccf1978
/*
* Copyright (C) 2009 Nokia
* Copyright (C) 2009 Texas Instruments
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define OMAP3_CONTROL_PADCONF_MUX_PBASE 0x48002030LU
#define OMAP3_MUX(mode0, mux_value) \
{ \
.reg_offset = (OMAP3_CONTROL_PADCONF_##mode0##_OFFSET), \
.value = (mux_value), \
}
/*
* OMAP3 CONTROL_PADCONF* register offsets for pin-muxing
*
* Extracted from the TRM. Add 0x48002030 to these values to get the
* absolute addresses. The name in the macro is the mode-0 name of
* the pin. NOTE: These registers are 16-bits wide.
*
* Note that 34XX TRM uses MMC instead of SDMMC and SAD2D instead
* of CHASSIS for some registers. For the defines, we follow the
* 36XX naming, and use SDMMC and CHASSIS.
*/
#define OMAP3_CONTROL_PADCONF_SDRC_D0_OFFSET 0x000
#define OMAP3_CONTROL_PADCONF_SDRC_D1_OFFSET 0x002
#define OMAP3_CONTROL_PADCONF_SDRC_D2_OFFSET 0x004
#define OMAP3_CONTROL_PADCONF_SDRC_D3_OFFSET 0x006
#define OMAP3_CONTROL_PADCONF_SDRC_D4_OFFSET 0x008
#define OMAP3_CONTROL_PADCONF_SDRC_D5_OFFSET 0x00a
#define OMAP3_CONTROL_PADCONF_SDRC_D6_OFFSET 0x00c
#define OMAP3_CONTROL_PADCONF_SDRC_D7_OFFSET 0x00e
#define OMAP3_CONTROL_PADCONF_SDRC_D8_OFFSET 0x010
#define OMAP3_CONTROL_PADCONF_SDRC_D9_OFFSET 0x012
#define OMAP3_CONTROL_PADCONF_SDRC_D10_OFFSET 0x014
#define OMAP3_CONTROL_PADCONF_SDRC_D11_OFFSET 0x016
#define OMAP3_CONTROL_PADCONF_SDRC_D12_OFFSET 0x018
#define OMAP3_CONTROL_PADCONF_SDRC_D13_OFFSET 0x01a
#define OMAP3_CONTROL_PADCONF_SDRC_D14_OFFSET 0x01c
#define OMAP3_CONTROL_PADCONF_SDRC_D15_OFFSET 0x01e
#define OMAP3_CONTROL_PADCONF_SDRC_D16_OFFSET 0x020
#define OMAP3_CONTROL_PADCONF_SDRC_D17_OFFSET 0x022
#define OMAP3_CONTROL_PADCONF_SDRC_D18_OFFSET 0x024
#define OMAP3_CONTROL_PADCONF_SDRC_D19_OFFSET 0x026
#define OMAP3_CONTROL_PADCONF_SDRC_D20_OFFSET 0x028
#define OMAP3_CONTROL_PADCONF_SDRC_D21_OFFSET 0x02a
#define OMAP3_CONTROL_PADCONF_SDRC_D22_OFFSET 0x02c
#define OMAP3_CONTROL_PADCONF_SDRC_D23_OFFSET 0x02e
#define OMAP3_CONTROL_PADCONF_SDRC_D24_OFFSET 0x030
#define OMAP3_CONTROL_PADCONF_SDRC_D25_OFFSET 0x032
#define OMAP3_CONTROL_PADCONF_SDRC_D26_OFFSET 0x034
#define OMAP3_CONTROL_PADCONF_SDRC_D27_OFFSET 0x036
#define OMAP3_CONTROL_PADCONF_SDRC_D28_OFFSET 0x038
#define OMAP3_CONTROL_PADCONF_SDRC_D29_OFFSET 0x03a
#define OMAP3_CONTROL_PADCONF_SDRC_D30_OFFSET 0x03c
#define OMAP3_CONTROL_PADCONF_SDRC_D31_OFFSET 0x03e
#define OMAP3_CONTROL_PADCONF_SDRC_CLK_OFFSET 0x040
#define OMAP3_CONTROL_PADCONF_SDRC_DQS0_OFFSET 0x042
#define OMAP3_CONTROL_PADCONF_SDRC_DQS1_OFFSET 0x044
#define OMAP3_CONTROL_PADCONF_SDRC_DQS2_OFFSET 0x046
#define OMAP3_CONTROL_PADCONF_SDRC_DQS3_OFFSET 0x048
#define OMAP3_CONTROL_PADCONF_GPMC_A1_OFFSET 0x04a
#define OMAP3_CONTROL_PADCONF_GPMC_A2_OFFSET 0x04c
#define OMAP3_CONTROL_PADCONF_GPMC_A3_OFFSET 0x04e
#define OMAP3_CONTROL_PADCONF_GPMC_A4_OFFSET 0x050
#define OMAP3_CONTROL_PADCONF_GPMC_A5_OFFSET 0x052
#define OMAP3_CONTROL_PADCONF_GPMC_A6_OFFSET 0x054
#define OMAP3_CONTROL_PADCONF_GPMC_A7_OFFSET 0x056
#define OMAP3_CONTROL_PADCONF_GPMC_A8_OFFSET 0x058
#define OMAP3_CONTROL_PADCONF_GPMC_A9_OFFSET 0x05a
#define OMAP3_CONTROL_PADCONF_GPMC_A10_OFFSET 0x05c
#define OMAP3_CONTROL_PADCONF_GPMC_D0_OFFSET 0x05e
#define OMAP3_CONTROL_PADCONF_GPMC_D1_OFFSET 0x060
#define OMAP3_CONTROL_PADCONF_GPMC_D2_OFFSET 0x062
#define OMAP3_CONTROL_PADCONF_GPMC_D3_OFFSET 0x064
#define OMAP3_CONTROL_PADCONF_GPMC_D4_OFFSET 0x066
#define OMAP3_CONTROL_PADCONF_GPMC_D5_OFFSET 0x068
#define OMAP3_CONTROL_PADCONF_GPMC_D6_OFFSET 0x06a
#define OMAP3_CONTROL_PADCONF_GPMC_D7_OFFSET 0x06c
#define OMAP3_CONTROL_PADCONF_GPMC_D8_OFFSET 0x06e
#define OMAP3_CONTROL_PADCONF_GPMC_D9_OFFSET 0x070
#define OMAP3_CONTROL_PADCONF_GPMC_D10_OFFSET 0x072
#define OMAP3_CONTROL_PADCONF_GPMC_D11_OFFSET 0x074
#define OMAP3_CONTROL_PADCONF_GPMC_D12_OFFSET 0x076
#define OMAP3_CONTROL_PADCONF_GPMC_D13_OFFSET 0x078
#define OMAP3_CONTROL_PADCONF_GPMC_D14_OFFSET 0x07a
#define OMAP3_CONTROL_PADCONF_GPMC_D15_OFFSET 0x07c
#define OMAP3_CONTROL_PADCONF_GPMC_NCS0_OFFSET 0x07e
#define OMAP3_CONTROL_PADCONF_GPMC_NCS1_OFFSET 0x080
#define OMAP3_CONTROL_PADCONF_GPMC_NCS2_OFFSET 0x082
#define OMAP3_CONTROL_PADCONF_GPMC_NCS3_OFFSET 0x084
#define OMAP3_CONTROL_PADCONF_GPMC_NCS4_OFFSET 0x086
#define OMAP3_CONTROL_PADCONF_GPMC_NCS5_OFFSET 0x088
#define OMAP3_CONTROL_PADCONF_GPMC_NCS6_OFFSET 0x08a
#define OMAP3_CONTROL_PADCONF_GPMC_NCS7_OFFSET 0x08c
#define OMAP3_CONTROL_PADCONF_GPMC_CLK_OFFSET 0x08e
#define OMAP3_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET 0x090
#define OMAP3_CONTROL_PADCONF_GPMC_NOE_OFFSET 0x092
#define OMAP3_CONTROL_PADCONF_GPMC_NWE_OFFSET 0x094
#define OMAP3_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET 0x096
#define OMAP3_CONTROL_PADCONF_GPMC_NBE1_OFFSET 0x098
#define OMAP3_CONTROL_PADCONF_GPMC_NWP_OFFSET 0x09a
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT0_OFFSET 0x09c
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT1_OFFSET 0x09e
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT2_OFFSET 0x0a0
#define OMAP3_CONTROL_PADCONF_GPMC_WAIT3_OFFSET 0x0a2
#define OMAP3_CONTROL_PADCONF_DSS_PCLK_OFFSET 0x0a4
#define OMAP3_CONTROL_PADCONF_DSS_HSYNC_OFFSET 0x0a6
#define OMAP3_CONTROL_PADCONF_DSS_VSYNC_OFFSET 0x0a8
#define OMAP3_CONTROL_PADCONF_DSS_ACBIAS_OFFSET 0x0aa
#define OMAP3_CONTROL_PADCONF_DSS_DATA0_OFFSET 0x0ac
#define OMAP3_CONTROL_PADCONF_DSS_DATA1_OFFSET 0x0ae
#define OMAP3_CONTROL_PADCONF_DSS_DATA2_OFFSET 0x0b0
#define OMAP3_CONTROL_PADCONF_DSS_DATA3_OFFSET 0x0b2
#define OMAP3_CONTROL_PADCONF_DSS_DATA4_OFFSET 0x0b4
#define OMAP3_CONTROL_PADCONF_DSS_DATA5_OFFSET 0x0b6
#define OMAP3_CONTROL_PADCONF_DSS_DATA6_OFFSET 0x0b8
#define OMAP3_CONTROL_PADCONF_DSS_DATA7_OFFSET 0x0ba
#define OMAP3_CONTROL_PADCONF_DSS_DATA8_OFFSET 0x0bc
#define OMAP3_CONTROL_PADCONF_DSS_DATA9_OFFSET 0x0be
#define OMAP3_CONTROL_PADCONF_DSS_DATA10_OFFSET 0x0c0
#define OMAP3_CONTROL_PADCONF_DSS_DATA11_OFFSET 0x0c2
#define OMAP3_CONTROL_PADCONF_DSS_DATA12_OFFSET 0x0c4
#define OMAP3_CONTROL_PADCONF_DSS_DATA13_OFFSET 0x0c6
#define OMAP3_CONTROL_PADCONF_DSS_DATA14_OFFSET 0x0c8
#define OMAP3_CONTROL_PADCONF_DSS_DATA15_OFFSET 0x0ca
#define OMAP3_CONTROL_PADCONF_DSS_DATA16_OFFSET 0x0cc
#define OMAP3_CONTROL_PADCONF_DSS_DATA17_OFFSET 0x0ce
#define OMAP3_CONTROL_PADCONF_DSS_DATA18_OFFSET 0x0d0
#define OMAP3_CONTROL_PADCONF_DSS_DATA19_OFFSET 0x0d2
#define OMAP3_CONTROL_PADCONF_DSS_DATA20_OFFSET 0x0d4
#define OMAP3_CONTROL_PADCONF_DSS_DATA21_OFFSET 0x0d6
#define OMAP3_CONTROL_PADCONF_DSS_DATA22_OFFSET 0x0d8
#define OMAP3_CONTROL_PADCONF_DSS_DATA23_OFFSET 0x0da
#define OMAP3_CONTROL_PADCONF_CAM_HS_OFFSET 0x0dc
#define OMAP3_CONTROL_PADCONF_CAM_VS_OFFSET 0x0de
#define OMAP3_CONTROL_PADCONF_CAM_XCLKA_OFFSET 0x0e0
#define OMAP3_CONTROL_PADCONF_CAM_PCLK_OFFSET 0x0e2
#define OMAP3_CONTROL_PADCONF_CAM_FLD_OFFSET 0x0e4
#define OMAP3_CONTROL_PADCONF_CAM_D0_OFFSET 0x0e6
#define OMAP3_CONTROL_PADCONF_CAM_D1_OFFSET 0x0e8
#define OMAP3_CONTROL_PADCONF_CAM_D2_OFFSET 0x0ea
#define OMAP3_CONTROL_PADCONF_CAM_D3_OFFSET 0x0ec
#define OMAP3_CONTROL_PADCONF_CAM_D4_OFFSET 0x0ee
#define OMAP3_CONTROL_PADCONF_CAM_D5_OFFSET 0x0f0
#define OMAP3_CONTROL_PADCONF_CAM_D6_OFFSET 0x0f2
#define OMAP3_CONTROL_PADCONF_CAM_D7_OFFSET 0x0f4
#define OMAP3_CONTROL_PADCONF_CAM_D8_OFFSET 0x0f6
#define OMAP3_CONTROL_PADCONF_CAM_D9_OFFSET 0x0f8
#define OMAP3_CONTROL_PADCONF_CAM_D10_OFFSET 0x0fa
#define OMAP3_CONTROL_PADCONF_CAM_D11_OFFSET 0x0fc
#define OMAP3_CONTROL_PADCONF_CAM_XCLKB_OFFSET 0x0fe
#define OMAP3_CONTROL_PADCONF_CAM_WEN_OFFSET 0x100
#define OMAP3_CONTROL_PADCONF_CAM_STROBE_OFFSET 0x102
#define OMAP3_CONTROL_PADCONF_CSI2_DX0_OFFSET 0x104
#define OMAP3_CONTROL_PADCONF_CSI2_DY0_OFFSET 0x106
#define OMAP3_CONTROL_PADCONF_CSI2_DX1_OFFSET 0x108
#define OMAP3_CONTROL_PADCONF_CSI2_DY1_OFFSET 0x10a
#define OMAP3_CONTROL_PADCONF_MCBSP2_FSX_OFFSET 0x10c
#define OMAP3_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET 0x10e
#define OMAP3_CONTROL_PADCONF_MCBSP2_DR_OFFSET 0x110
#define OMAP3_CONTROL_PADCONF_MCBSP2_DX_OFFSET 0x112
#define OMAP3_CONTROL_PADCONF_SDMMC1_CLK_OFFSET 0x114
#define OMAP3_CONTROL_PADCONF_SDMMC1_CMD_OFFSET 0x116
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET 0x118
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET 0x11a
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET 0x11c
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET 0x11e
/* SDMMC1_DAT4 - DAT7 are SIM_IO SIM_CLK SIM_PWRCTRL and SIM_RST on 36xx */
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT4_OFFSET 0x120
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT5_OFFSET 0x122
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT6_OFFSET 0x124
#define OMAP3_CONTROL_PADCONF_SDMMC1_DAT7_OFFSET 0x126
#define OMAP3_CONTROL_PADCONF_SDMMC2_CLK_OFFSET 0x128
#define OMAP3_CONTROL_PADCONF_SDMMC2_CMD_OFFSET 0x12a
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET 0x12c
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET 0x12e
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET 0x130
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET 0x132
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT4_OFFSET 0x134
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT5_OFFSET 0x136
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT6_OFFSET 0x138
#define OMAP3_CONTROL_PADCONF_SDMMC2_DAT7_OFFSET 0x13a
#define OMAP3_CONTROL_PADCONF_MCBSP3_DX_OFFSET 0x13c
#define OMAP3_CONTROL_PADCONF_MCBSP3_DR_OFFSET 0x13e
#define OMAP3_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET 0x140
#define OMAP3_CONTROL_PADCONF_MCBSP3_FSX_OFFSET 0x142
#define OMAP3_CONTROL_PADCONF_UART2_CTS_OFFSET 0x144
#define OMAP3_CONTROL_PADCONF_UART2_RTS_OFFSET 0x146
#define OMAP3_CONTROL_PADCONF_UART2_TX_OFFSET 0x148
#define OMAP3_CONTROL_PADCONF_UART2_RX_OFFSET 0x14a
#define OMAP3_CONTROL_PADCONF_UART1_TX_OFFSET 0x14c
#define OMAP3_CONTROL_PADCONF_UART1_RTS_OFFSET 0x14e
#define OMAP3_CONTROL_PADCONF_UART1_CTS_OFFSET 0x150
#define OMAP3_CONTROL_PADCONF_UART1_RX_OFFSET 0x152
#define OMAP3_CONTROL_PADCONF_MCBSP4_CLKX_OFFSET 0x154
#define OMAP3_CONTROL_PADCONF_MCBSP4_DR_OFFSET 0x156
#define OMAP3_CONTROL_PADCONF_MCBSP4_DX_OFFSET 0x158
#define OMAP3_CONTROL_PADCONF_MCBSP4_FSX_OFFSET 0x15a
#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET 0x15c
#define OMAP3_CONTROL_PADCONF_MCBSP1_FSR_OFFSET 0x15e
#define OMAP3_CONTROL_PADCONF_MCBSP1_DX_OFFSET 0x160
#define OMAP3_CONTROL_PADCONF_MCBSP1_DR_OFFSET 0x162
#define OMAP3_CONTROL_PADCONF_MCBSP_CLKS_OFFSET 0x164
#define OMAP3_CONTROL_PADCONF_MCBSP1_FSX_OFFSET 0x166
#define OMAP3_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET 0x168
#define OMAP3_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET 0x16a
#define OMAP3_CONTROL_PADCONF_UART3_RTS_SD_OFFSET 0x16c
#define OMAP3_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET 0x16e
#define OMAP3_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET 0x170
#define OMAP3_CONTROL_PADCONF_HSUSB0_CLK_OFFSET 0x172
#define OMAP3_CONTROL_PADCONF_HSUSB0_STP_OFFSET 0x174
#define OMAP3_CONTROL_PADCONF_HSUSB0_DIR_OFFSET 0x176
#define OMAP3_CONTROL_PADCONF_HSUSB0_NXT_OFFSET 0x178
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA0_OFFSET 0x17a
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA1_OFFSET 0x17c
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA2_OFFSET 0x17e
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA3_OFFSET 0x180
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA4_OFFSET 0x182
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA5_OFFSET 0x184
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA6_OFFSET 0x186
#define OMAP3_CONTROL_PADCONF_HSUSB0_DATA7_OFFSET 0x188
#define OMAP3_CONTROL_PADCONF_I2C1_SCL_OFFSET 0x18a
#define OMAP3_CONTROL_PADCONF_I2C1_SDA_OFFSET 0x18c
#define OMAP3_CONTROL_PADCONF_I2C2_SCL_OFFSET 0x18e
#define OMAP3_CONTROL_PADCONF_I2C2_SDA_OFFSET 0x190
#define OMAP3_CONTROL_PADCONF_I2C3_SCL_OFFSET 0x192
#define OMAP3_CONTROL_PADCONF_I2C3_SDA_OFFSET 0x194
#define OMAP3_CONTROL_PADCONF_HDQ_SIO_OFFSET 0x196
#define OMAP3_CONTROL_PADCONF_MCSPI1_CLK_OFFSET 0x198
#define OMAP3_CONTROL_PADCONF_MCSPI1_SIMO_OFFSET 0x19a
#define OMAP3_CONTROL_PADCONF_MCSPI1_SOMI_OFFSET 0x19c
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS0_OFFSET 0x19e
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS1_OFFSET 0x1a0
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS2_OFFSET 0x1a2
#define OMAP3_CONTROL_PADCONF_MCSPI1_CS3_OFFSET 0x1a4
#define OMAP3_CONTROL_PADCONF_MCSPI2_CLK_OFFSET 0x1a6
#define OMAP3_CONTROL_PADCONF_MCSPI2_SIMO_OFFSET 0x1a8
#define OMAP3_CONTROL_PADCONF_MCSPI2_SOMI_OFFSET 0x1aa
#define OMAP3_CONTROL_PADCONF_MCSPI2_CS0_OFFSET 0x1ac
#define OMAP3_CONTROL_PADCONF_MCSPI2_CS1_OFFSET 0x1ae
#define OMAP3_CONTROL_PADCONF_SYS_NIRQ_OFFSET 0x1b0
#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT2_OFFSET 0x1b2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD0_OFFSET 0x1b4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD1_OFFSET 0x1b6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD2_OFFSET 0x1b8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD3_OFFSET 0x1ba
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD4_OFFSET 0x1bc
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD5_OFFSET 0x1be
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD6_OFFSET 0x1c0
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD7_OFFSET 0x1c2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD8_OFFSET 0x1c4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD9_OFFSET 0x1c6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD10_OFFSET 0x1c8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD11_OFFSET 0x1ca
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD12_OFFSET 0x1cc
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD13_OFFSET 0x1ce
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD14_OFFSET 0x1d0
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD15_OFFSET 0x1d2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD16_OFFSET 0x1d4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD17_OFFSET 0x1d6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD18_OFFSET 0x1d8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD19_OFFSET 0x1da
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD20_OFFSET 0x1dc
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD21_OFFSET 0x1de
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD22_OFFSET 0x1e0
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD23_OFFSET 0x1e2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD24_OFFSET 0x1e4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD25_OFFSET 0x1e6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD26_OFFSET 0x1e8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD27_OFFSET 0x1ea
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD28_OFFSET 0x1ec
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD29_OFFSET 0x1ee
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD30_OFFSET 0x1f0
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD31_OFFSET 0x1f2
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD32_OFFSET 0x1f4
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD33_OFFSET 0x1f6
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD34_OFFSET 0x1f8
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD35_OFFSET 0x1fa
#define OMAP3_CONTROL_PADCONF_SAD2D_MCAD36_OFFSET 0x1fc
/* Note that 34xx TRM has SAD2D instead of CHASSIS for these */
#define OMAP3_CONTROL_PADCONF_CHASSIS_CLK26MI_OFFSET 0x1fe
#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESPWRON_OFFSET 0x200
#define OMAP3_CONTROL_PADCONF_CHASSIS_NRESWARW_OFFSET 0x202
#define OMAP3_CONTROL_PADCONF_CHASSIS_NIRQ_OFFSET 0x204
#define OMAP3_CONTROL_PADCONF_CHASSIS_FIQ_OFFSET 0x206
#define OMAP3_CONTROL_PADCONF_CHASSIS_ARMIRQ_OFFSET 0x208
#define OMAP3_CONTROL_PADCONF_CHASSIS_IVAIRQ_OFFSET 0x20a
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ0_OFFSET 0x20c
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ1_OFFSET 0x20e
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ2_OFFSET 0x210
#define OMAP3_CONTROL_PADCONF_CHASSIS_DMAREQ3_OFFSET 0x212
#define OMAP3_CONTROL_PADCONF_CHASSIS_NTRST_OFFSET 0x214
#define OMAP3_CONTROL_PADCONF_CHASSIS_TDI_OFFSET 0x216
#define OMAP3_CONTROL_PADCONF_CHASSIS_TDO_OFFSET 0x218
#define OMAP3_CONTROL_PADCONF_CHASSIS_TMS_OFFSET 0x21a
#define OMAP3_CONTROL_PADCONF_CHASSIS_TCK_OFFSET 0x21c
#define OMAP3_CONTROL_PADCONF_CHASSIS_RTCK_OFFSET 0x21e
#define OMAP3_CONTROL_PADCONF_CHASSIS_MSTDBY_OFFSET 0x220
#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEREQ_OFFSET 0x222
#define OMAP3_CONTROL_PADCONF_CHASSIS_IDLEACK_OFFSET 0x224
#define OMAP3_CONTROL_PADCONF_SAD2D_MWRITE_OFFSET 0x226
#define OMAP3_CONTROL_PADCONF_SAD2D_SWRITE_OFFSET 0x228
#define OMAP3_CONTROL_PADCONF_SAD2D_MREAD_OFFSET 0x22a
#define OMAP3_CONTROL_PADCONF_SAD2D_SREAD_OFFSET 0x22c
#define OMAP3_CONTROL_PADCONF_SAD2D_MBUSFLAG_OFFSET 0x22e
#define OMAP3_CONTROL_PADCONF_SAD2D_SBUSFLAG_OFFSET 0x230
#define OMAP3_CONTROL_PADCONF_SDRC_CKE0_OFFSET 0x232
#define OMAP3_CONTROL_PADCONF_SDRC_CKE1_OFFSET 0x234
/* 36xx only */
#define OMAP3_CONTROL_PADCONF_GPMC_A11_OFFSET 0x236
#define OMAP3_CONTROL_PADCONF_SDRC_BA0_OFFSET 0x570
#define OMAP3_CONTROL_PADCONF_SDRC_BA1_OFFSET 0x572
#define OMAP3_CONTROL_PADCONF_SDRC_A0_OFFSET 0x574
#define OMAP3_CONTROL_PADCONF_SDRC_A1_OFFSET 0x576
#define OMAP3_CONTROL_PADCONF_SDRC_A2_OFFSET 0x578
#define OMAP3_CONTROL_PADCONF_SDRC_A3_OFFSET 0x57a
#define OMAP3_CONTROL_PADCONF_SDRC_A4_OFFSET 0x57c
#define OMAP3_CONTROL_PADCONF_SDRC_A5_OFFSET 0x57e
#define OMAP3_CONTROL_PADCONF_SDRC_A6_OFFSET 0x580
#define OMAP3_CONTROL_PADCONF_SDRC_A7_OFFSET 0x582
#define OMAP3_CONTROL_PADCONF_SDRC_A8_OFFSET 0x584
#define OMAP3_CONTROL_PADCONF_SDRC_A9_OFFSET 0x586
#define OMAP3_CONTROL_PADCONF_SDRC_A10_OFFSET 0x588
#define OMAP3_CONTROL_PADCONF_SDRC_A11_OFFSET 0x58a
#define OMAP3_CONTROL_PADCONF_SDRC_A12_OFFSET 0x58c
#define OMAP3_CONTROL_PADCONF_SDRC_A13_OFFSET 0x58e
#define OMAP3_CONTROL_PADCONF_SDRC_A14_OFFSET 0x590
#define OMAP3_CONTROL_PADCONF_SDRC_NCS0_OFFSET 0x592
#define OMAP3_CONTROL_PADCONF_SDRC_NCS1_OFFSET 0x594
#define OMAP3_CONTROL_PADCONF_SDRC_NCLK_OFFSET 0x596
#define OMAP3_CONTROL_PADCONF_SDRC_NRAS_OFFSET 0x598
#define OMAP3_CONTROL_PADCONF_SDRC_NCAS_OFFSET 0x59a
#define OMAP3_CONTROL_PADCONF_SDRC_NWE_OFFSET 0x59c
#define OMAP3_CONTROL_PADCONF_SDRC_DM0_OFFSET 0x59e
#define OMAP3_CONTROL_PADCONF_SDRC_DM1_OFFSET 0x5a0
#define OMAP3_CONTROL_PADCONF_SDRC_DM2_OFFSET 0x5a2
#define OMAP3_CONTROL_PADCONF_SDRC_DM3_OFFSET 0x5a4
/* 36xx only, these are SDMMC1_DAT4 - DAT7 on 34xx */
#define OMAP3_CONTROL_PADCONF_SIM_IO_OFFSET 0x120
#define OMAP3_CONTROL_PADCONF_SIM_CLK_OFFSET 0x122
#define OMAP3_CONTROL_PADCONF_SIM_PWRCTRL_OFFSET 0x124
#define OMAP3_CONTROL_PADCONF_SIM_RST_OFFSET 0x126
#define OMAP3_CONTROL_PADCONF_ETK_CLK_OFFSET 0x5a8
#define OMAP3_CONTROL_PADCONF_ETK_CTL_OFFSET 0x5aa
#define OMAP3_CONTROL_PADCONF_ETK_D0_OFFSET 0x5ac
#define OMAP3_CONTROL_PADCONF_ETK_D1_OFFSET 0x5ae
#define OMAP3_CONTROL_PADCONF_ETK_D2_OFFSET 0x5b0
#define OMAP3_CONTROL_PADCONF_ETK_D3_OFFSET 0x5b2
#define OMAP3_CONTROL_PADCONF_ETK_D4_OFFSET 0x5b4
#define OMAP3_CONTROL_PADCONF_ETK_D5_OFFSET 0x5b6
#define OMAP3_CONTROL_PADCONF_ETK_D6_OFFSET 0x5b8
#define OMAP3_CONTROL_PADCONF_ETK_D7_OFFSET 0x5ba
#define OMAP3_CONTROL_PADCONF_ETK_D8_OFFSET 0x5bc
#define OMAP3_CONTROL_PADCONF_ETK_D9_OFFSET 0x5be
#define OMAP3_CONTROL_PADCONF_ETK_D10_OFFSET 0x5c0
#define OMAP3_CONTROL_PADCONF_ETK_D11_OFFSET 0x5c2
#define OMAP3_CONTROL_PADCONF_ETK_D12_OFFSET 0x5c4
#define OMAP3_CONTROL_PADCONF_ETK_D13_OFFSET 0x5c6
#define OMAP3_CONTROL_PADCONF_ETK_D14_OFFSET 0x5c8
#define OMAP3_CONTROL_PADCONF_ETK_D15_OFFSET 0x5ca
#define OMAP3_CONTROL_PADCONF_I2C4_SCL_OFFSET 0x9d0
#define OMAP3_CONTROL_PADCONF_I2C4_SDA_OFFSET 0x9d2
#define OMAP3_CONTROL_PADCONF_SYS_32K_OFFSET 0x9d4
#define OMAP3_CONTROL_PADCONF_SYS_CLKREQ_OFFSET 0x9d6
#define OMAP3_CONTROL_PADCONF_SYS_NRESWARM_OFFSET 0x9d8
#define OMAP3_CONTROL_PADCONF_SYS_BOOT0_OFFSET 0x9da
#define OMAP3_CONTROL_PADCONF_SYS_BOOT1_OFFSET 0x9dc
#define OMAP3_CONTROL_PADCONF_SYS_BOOT2_OFFSET 0x9de
#define OMAP3_CONTROL_PADCONF_SYS_BOOT3_OFFSET 0x9e0
#define OMAP3_CONTROL_PADCONF_SYS_BOOT4_OFFSET 0x9e2
#define OMAP3_CONTROL_PADCONF_SYS_BOOT5_OFFSET 0x9e4
#define OMAP3_CONTROL_PADCONF_SYS_BOOT6_OFFSET 0x9e6
#define OMAP3_CONTROL_PADCONF_SYS_OFF_MODE_OFFSET 0x9e8
#define OMAP3_CONTROL_PADCONF_SYS_CLKOUT1_OFFSET 0x9ea
#define OMAP3_CONTROL_PADCONF_JTAG_NTRST_OFFSET 0x9ec
#define OMAP3_CONTROL_PADCONF_JTAG_TCK_OFFSET 0x9ee
#define OMAP3_CONTROL_PADCONF_JTAG_TMS_TMSC_OFFSET 0x9f0
#define OMAP3_CONTROL_PADCONF_JTAG_TDI_OFFSET 0x9f2
#define OMAP3_CONTROL_PADCONF_JTAG_EMU0_OFFSET 0x9f4
#define OMAP3_CONTROL_PADCONF_JTAG_EMU1_OFFSET 0x9f6
#define OMAP3_CONTROL_PADCONF_SAD2D_SWAKEUP_OFFSET 0xa1c
#define OMAP3_CONTROL_PADCONF_JTAG_RTCK_OFFSET 0xa1e
#define OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET 0xa20
#define OMAP3_CONTROL_PADCONF_MUX_SIZE \
(OMAP3_CONTROL_PADCONF_JTAG_TDO_OFFSET + 0x2)
arch/arm/mach-omap2/omap-headsmp.S
View file @ 5ccf1978
......@@ -27,20 +27,39 @@
* OMAP4 specific entry point for secondary CPU to jump from ROM
* code. This routine also provides a holding flag into which
* secondary core is held until we're ready for it to initialise.
* The primary core will update the this flag using a hardware
* register AuxCoreBoot1.
* The primary core will update this flag using a hardware
* register AuxCoreBoot0.
*/
ENTRY(omap_secondary_startup)
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #0x0f
hold: ldr r1, =OMAP4_AUX_CORE_BOOT1_PA @ read from AuxCoreBoot1
ldr r2, [r1]
cmp r2, r0
hold: ldr r12,=0x103
dsb
smc @ read from AuxCoreBoot0
mov r0, r0, lsr #9
mrc p15, 0, r4, c0, c0, 5
and r4, r4, #0x0f
cmp r0, r4
bne hold
/*
* we've been released from the cpu_release,secondary_stack
* we've been released from the wait loop,secondary_stack
* should now contain the SVC stack for this core
*/
b secondary_startup
END(omap_secondary_startup)
ENTRY(omap_modify_auxcoreboot0)
stmfd sp!, {r1-r12, lr}
ldr r12, =0x104
dsb
smc
ldmfd sp!, {r1-r12, pc}
END(omap_modify_auxcoreboot0)
ENTRY(omap_auxcoreboot_addr)
stmfd sp!, {r2-r12, lr}
ldr r12, =0x105
dsb
smc
ldmfd sp!, {r2-r12, pc}
END(omap_auxcoreboot_addr)
arch/arm/mach-omap2/omap-smp.c
View file @ 5ccf1978
......@@ -17,19 +17,15 @@
*/
#include <linux/init.h>
#include <linux/device.h>
#include <linux/jiffies.h>
#include <linux/smp.h>
#include <linux/io.h>
#include <asm/cacheflush.h>
#include <asm/localtimer.h>
#include <asm/smp_scu.h>
#include <mach/hardware.h>
#include <plat/common.h>
/* Registers used for communicating startup information */
static void __iomem *omap4_auxcoreboot_reg0;
static void __iomem *omap4_auxcoreboot_reg1;
/* SCU base address */
static void __iomem *scu_base;
......@@ -65,8 +61,6 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
/*
* Set synchronisation state between this boot processor
* and the secondary one
......@@ -74,18 +68,15 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
spin_lock(&boot_lock);
/*
* Update the AuxCoreBoot1 with boot state for secondary core.
* Update the AuxCoreBoot0 with boot state for secondary core.
* omap_secondary_startup() routine will hold the secondary core till
* the AuxCoreBoot1 register is updated with cpu state
* A barrier is added to ensure that write buffer is drained
*/
__raw_writel(cpu, omap4_auxcoreboot_reg1);
omap_modify_auxcoreboot0(0x200, 0x0);
flush_cache_all();
smp_wmb();
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout))
;
/*
* Now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
......@@ -99,17 +90,18 @@ static void __init wakeup_secondary(void)
{
/*
* Write the address of secondary startup routine into the
* AuxCoreBoot0 where ROM code will jump and start executing
* AuxCoreBoot1 where ROM code will jump and start executing
* on secondary core once out of WFE
* A barrier is added to ensure that write buffer is drained
*/
__raw_writel(virt_to_phys(omap_secondary_startup), \
omap4_auxcoreboot_reg0);
omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
smp_wmb();
/*
* Send a 'sev' to wake the secondary core from WFE.
* Drain the outstanding writes to memory
*/
dsb();
set_event();
mb();
}
......@@ -136,7 +128,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
{
unsigned int ncores = get_core_count();
unsigned int cpu = smp_processor_id();
void __iomem *omap4_wkupgen_base;
int i;
/* sanity check */
......@@ -168,12 +159,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
for (i = 0; i < max_cpus; i++)
set_cpu_present(i, true);
/* Never released */
omap4_wkupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
BUG_ON(!omap4_wkupgen_base);
omap4_auxcoreboot_reg0 = omap4_wkupgen_base + 0x800;
omap4_auxcoreboot_reg1 = omap4_wkupgen_base + 0x804;
if (max_cpus > 1) {
/*
* Enable the local timer or broadcast device for the
......
arch/arm/mach-omap2/serial.c
View file @ 5ccf1978
......@@ -33,6 +33,7 @@
#include "pm.h"
#include "prm-regbits-34xx.h"
#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV 0x52
#define UART_OMAP_WER 0x17 /* Wake-up enable register */
#define DEFAULT_TIMEOUT (5 * HZ)
......@@ -572,6 +573,23 @@ static struct omap_uart_state omap_uart[] = {
#endif
};
/*
* Override the default 8250 read handler: mem_serial_in()
* Empty RX fifo read causes an abort on omap3630 and omap4
* This function makes sure that an empty rx fifo is not read on these silicons
* (OMAP1/2/3430 are not affected)
*/
static unsigned int serial_in_override(struct uart_port *up, int offset)
{
if (UART_RX == offset) {
unsigned int lsr;
lsr = serial_read_reg(omap_uart[up->line].p, UART_LSR);
if (!(lsr & UART_LSR_DR))
return -EPERM;
}
return serial_read_reg(omap_uart[up->line].p, offset);
}
void __init omap_serial_early_init(void)
{
int i;
......@@ -631,24 +649,64 @@ void __init omap_serial_early_init(void)
}
}
void __init omap_serial_init(void)
/**
* omap_serial_init_port() - initialize single serial port
* @port: serial port number (0-3)
*
* This function initialies serial driver for given @port only.
* Platforms can call this function instead of omap_serial_init()
* if they don't plan to use all available UARTs as serial ports.
*
* Don't mix calls to omap_serial_init_port() and omap_serial_init(),
* use only one of the two.
*/
void __init omap_serial_init_port(int port)
{
int i;
struct omap_uart_state *uart;
struct platform_device *pdev;
struct device *dev;
for (i = 0; i < ARRAY_SIZE(omap_uart); i++) {
struct omap_uart_state *uart = &omap_uart[i];
struct platform_device *pdev = &uart->pdev;
struct device *dev = &pdev->dev;
BUG_ON(port < 0);
BUG_ON(port >= ARRAY_SIZE(omap_uart));
omap_uart_reset(uart);
omap_uart_idle_init(uart);
uart = &omap_uart[port];
pdev = &uart->pdev;
dev = &pdev->dev;
if (WARN_ON(platform_device_register(pdev)))
continue;
if ((cpu_is_omap34xx() && uart->padconf) ||
(uart->wk_en && uart->wk_mask)) {
device_init_wakeup(dev, true);
DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
}
omap_uart_reset(uart);
omap_uart_idle_init(uart);
if (WARN_ON(platform_device_register(pdev)))
return;
if ((cpu_is_omap34xx() && uart->padconf) ||
(uart->wk_en && uart->wk_mask)) {
device_init_wakeup(dev, true);
DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
}
/* omap44xx: Never read empty UART fifo
* omap3xxx: Never read empty UART fifo on UARTs
* with IP rev >=0x52
*/
if (cpu_is_omap44xx())
uart->p->serial_in = serial_in_override;
else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
>= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
uart->p->serial_in = serial_in_override;
}
/**
* omap_serial_init() - intialize all supported serial ports
*
* Initializes all available UARTs as serial ports. Platforms
* can call this function when they want to have default behaviour
* for serial ports (e.g initialize them all as serial ports).
*/
void __init omap_serial_init(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(omap_uart); i++)
omap_serial_init_port(i);
}
arch/arm/mach-omap2/usb-ehci.c
View file @ 5ccf1978
......@@ -27,6 +27,8 @@
#include <mach/irqs.h>
#include <plat/usb.h>
#include "mux.h"
#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
static struct resource ehci_resources[] = {
......@@ -72,32 +74,44 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
{
switch (port_mode[0]) {
case EHCI_HCD_OMAP_MODE_PHY:
omap_cfg_reg(Y9_3430_USB1HS_PHY_STP);
omap_cfg_reg(Y8_3430_USB1HS_PHY_CLK);
omap_cfg_reg(AA14_3430_USB1HS_PHY_DIR);
omap_cfg_reg(AA11_3430_USB1HS_PHY_NXT);
omap_cfg_reg(W13_3430_USB1HS_PHY_DATA0);
omap_cfg_reg(W12_3430_USB1HS_PHY_DATA1);
omap_cfg_reg(W11_3430_USB1HS_PHY_DATA2);
omap_cfg_reg(Y11_3430_USB1HS_PHY_DATA3);
omap_cfg_reg(W9_3430_USB1HS_PHY_DATA4);
omap_cfg_reg(Y12_3430_USB1HS_PHY_DATA5);
omap_cfg_reg(W8_3430_USB1HS_PHY_DATA6);
omap_cfg_reg(Y13_3430_USB1HS_PHY_DATA7);
omap_mux_init_signal("hsusb1_stp", OMAP_PIN_OUTPUT);
omap_mux_init_signal("hsusb1_clk", OMAP_PIN_OUTPUT);
omap_mux_init_signal("hsusb1_dir", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_nxt", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data0", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data1", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data2", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data3", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data4", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data5", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data6", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_data7", OMAP_PIN_INPUT_PULLDOWN);
break;
case EHCI_HCD_OMAP_MODE_TLL:
omap_cfg_reg(Y9_3430_USB1HS_TLL_STP);
omap_cfg_reg(Y8_3430_USB1HS_TLL_CLK);
omap_cfg_reg(AA14_3430_USB1HS_TLL_DIR);
omap_cfg_reg(AA11_3430_USB1HS_TLL_NXT);
omap_cfg_reg(W13_3430_USB1HS_TLL_DATA0);
omap_cfg_reg(W12_3430_USB1HS_TLL_DATA1);
omap_cfg_reg(W11_3430_USB1HS_TLL_DATA2);
omap_cfg_reg(Y11_3430_USB1HS_TLL_DATA3);
omap_cfg_reg(W9_3430_USB1HS_TLL_DATA4);
omap_cfg_reg(Y12_3430_USB1HS_TLL_DATA5);
omap_cfg_reg(W8_3430_USB1HS_TLL_DATA6);
omap_cfg_reg(Y13_3430_USB1HS_TLL_DATA7);
omap_mux_init_signal("hsusb1_tll_stp",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("hsusb1_tll_clk",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_dir",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_nxt",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb1_tll_data7",
OMAP_PIN_INPUT_PULLDOWN);
break;
case EHCI_HCD_OMAP_MODE_UNKNOWN:
/* FALLTHROUGH */
......@@ -107,32 +121,52 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
switch (port_mode[1]) {
case EHCI_HCD_OMAP_MODE_PHY:
omap_cfg_reg(AA10_3430_USB2HS_PHY_STP);
omap_cfg_reg(AA8_3430_USB2HS_PHY_CLK);
omap_cfg_reg(AA9_3430_USB2HS_PHY_DIR);
omap_cfg_reg(AB11_3430_USB2HS_PHY_NXT);
omap_cfg_reg(AB10_3430_USB2HS_PHY_DATA0);
omap_cfg_reg(AB9_3430_USB2HS_PHY_DATA1);
omap_cfg_reg(W3_3430_USB2HS_PHY_DATA2);
omap_cfg_reg(T4_3430_USB2HS_PHY_DATA3);
omap_cfg_reg(T3_3430_USB2HS_PHY_DATA4);
omap_cfg_reg(R3_3430_USB2HS_PHY_DATA5);
omap_cfg_reg(R4_3430_USB2HS_PHY_DATA6);
omap_cfg_reg(T2_3430_USB2HS_PHY_DATA7);
omap_mux_init_signal("hsusb2_stp", OMAP_PIN_OUTPUT);
omap_mux_init_signal("hsusb2_clk", OMAP_PIN_OUTPUT);
omap_mux_init_signal("hsusb2_dir", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_nxt", OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_data7",
OMAP_PIN_INPUT_PULLDOWN);
break;
case EHCI_HCD_OMAP_MODE_TLL:
omap_cfg_reg(AA10_3430_USB2HS_TLL_STP);
omap_cfg_reg(AA8_3430_USB2HS_TLL_CLK);
omap_cfg_reg(AA9_3430_USB2HS_TLL_DIR);
omap_cfg_reg(AB11_3430_USB2HS_TLL_NXT);
omap_cfg_reg(AB10_3430_USB2HS_TLL_DATA0);
omap_cfg_reg(AB9_3430_USB2HS_TLL_DATA1);
omap_cfg_reg(W3_3430_USB2HS_TLL_DATA2);
omap_cfg_reg(T4_3430_USB2HS_TLL_DATA3);
omap_cfg_reg(T3_3430_USB2HS_TLL_DATA4);
omap_cfg_reg(R3_3430_USB2HS_TLL_DATA5);
omap_cfg_reg(R4_3430_USB2HS_TLL_DATA6);
omap_cfg_reg(T2_3430_USB2HS_TLL_DATA7);
omap_mux_init_signal("hsusb2_tll_stp",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("hsusb2_tll_clk",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_dir",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_nxt",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb2_tll_data7",
OMAP_PIN_INPUT_PULLDOWN);
break;
case EHCI_HCD_OMAP_MODE_UNKNOWN:
/* FALLTHROUGH */
......@@ -145,18 +179,30 @@ static void setup_ehci_io_mux(enum ehci_hcd_omap_mode *port_mode)
printk(KERN_WARNING "Port3 can't be used in PHY mode\n");
break;
case EHCI_HCD_OMAP_MODE_TLL:
omap_cfg_reg(AB3_3430_USB3HS_TLL_STP);
omap_cfg_reg(AA6_3430_USB3HS_TLL_CLK);
omap_cfg_reg(AA3_3430_USB3HS_TLL_DIR);
omap_cfg_reg(Y3_3430_USB3HS_TLL_NXT);
omap_cfg_reg(AA5_3430_USB3HS_TLL_DATA0);
omap_cfg_reg(Y4_3430_USB3HS_TLL_DATA1);
omap_cfg_reg(Y5_3430_USB3HS_TLL_DATA2);
omap_cfg_reg(W5_3430_USB3HS_TLL_DATA3);
omap_cfg_reg(AB12_3430_USB3HS_TLL_DATA4);
omap_cfg_reg(AB13_3430_USB3HS_TLL_DATA5);
omap_cfg_reg(AA13_3430_USB3HS_TLL_DATA6);
omap_cfg_reg(AA12_3430_USB3HS_TLL_DATA7);
omap_mux_init_signal("hsusb3_tll_stp",
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("hsusb3_tll_clk",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_dir",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_nxt",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data0",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data1",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data2",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data3",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data4",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data5",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data6",
OMAP_PIN_INPUT_PULLDOWN);
omap_mux_init_signal("hsusb3_tll_data7",
OMAP_PIN_INPUT_PULLDOWN);
break;
case EHCI_HCD_OMAP_MODE_UNKNOWN:
/* FALLTHROUGH */
......
arch/arm/plat-omap/common.c
View file @ 5ccf1978
......@@ -280,7 +280,7 @@ void __init omap2_set_globals_343x(void)
#if defined(CONFIG_ARCH_OMAP4)
static struct omap_globals omap4_globals = {
.class = OMAP443X_CLASS,
.tap = OMAP2_L4_IO_ADDRESS(0x4830a000),
.tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
.ctrl = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE),
.prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
.cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
......
arch/arm/plat-omap/debug-devices.c
View file @ 5ccf1978
......@@ -13,6 +13,7 @@
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/smc91x.h>
#include <mach/hardware.h>
......@@ -24,6 +25,12 @@
* platforms include H2, H3, H4, and Perseus2.
*/
static struct smc91x_platdata smc91x_info = {
.flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
.leda = RPC_LED_100_10,
.ledb = RPC_LED_TX_RX,
};
static struct resource smc91x_resources[] = {
[0] = {
.flags = IORESOURCE_MEM,
......@@ -36,6 +43,9 @@ static struct resource smc91x_resources[] = {
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = -1,
.dev = {
.platform_data = &smc91x_info,
},
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
......
arch/arm/plat-omap/devices.c
View file @ 5ccf1978
......@@ -242,6 +242,39 @@ int __init omap_mmc_add(const char *name, int id, unsigned long base,
/*-------------------------------------------------------------------------*/
#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
#ifdef CONFIG_ARCH_OMAP24XX
#define OMAP_RNG_BASE 0x480A0000
#else
#define OMAP_RNG_BASE 0xfffe5000
#endif
static struct resource rng_resources[] = {
{
.start = OMAP_RNG_BASE,
.end = OMAP_RNG_BASE + 0x4f,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device omap_rng_device = {
.name = "omap_rng",
.id = -1,
.num_resources = ARRAY_SIZE(rng_resources),
.resource = rng_resources,
};
static void omap_init_rng(void)
{
(void) platform_device_register(&omap_rng_device);
}
#else
static inline void omap_init_rng(void) {}
#endif
/*-------------------------------------------------------------------------*/
/* Numbering for the SPI-capable controllers when used for SPI:
* spi = 1
* uwire = 2
......@@ -324,39 +357,6 @@ static void omap_init_wdt(void)
static inline void omap_init_wdt(void) {}
#endif
/*-------------------------------------------------------------------------*/
#if defined(CONFIG_HW_RANDOM_OMAP) || defined(CONFIG_HW_RANDOM_OMAP_MODULE)
#ifdef CONFIG_ARCH_OMAP24XX
#define OMAP_RNG_BASE 0x480A0000
#else
#define OMAP_RNG_BASE 0xfffe5000
#endif
static struct resource rng_resources[] = {
{
.start = OMAP_RNG_BASE,
.end = OMAP_RNG_BASE + 0x4f,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device omap_rng_device = {
.name = "omap_rng",
.id = -1,
.num_resources = ARRAY_SIZE(rng_resources),
.resource = rng_resources,
};
static void omap_init_rng(void)
{
(void) platform_device_register(&omap_rng_device);
}
#else
static inline void omap_init_rng(void) {}
#endif
/*
* This gets called after board-specific INIT_MACHINE, and initializes most
* on-chip peripherals accessible on this board (except for few like USB):
......@@ -384,9 +384,9 @@ static int __init omap_init_devices(void)
*/
omap_init_dsp();
omap_init_kp();
omap_init_rng();
omap_init_uwire();
omap_init_wdt();
omap_init_rng();
return 0;
}
arch_initcall(omap_init_devices);
arch/arm/plat-omap/dma.c
View file @ 5ccf1978
......@@ -47,7 +47,6 @@ enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
#endif
#define OMAP_DMA_ACTIVE 0x01
#define OMAP_DMA_CCR_EN (1 << 7)
#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
......@@ -1120,17 +1119,8 @@ int omap_dma_running(void)
{
int lch;
/*
* On OMAP1510, internal LCD controller will start the transfer
* when it gets enabled, so assume DMA running if LCD enabled.
*/
if (cpu_is_omap1510())
if (omap_readw(0xfffec000 + 0x00) & (1 << 0))
return 1;
/* Check if LCD DMA is running */
if (cpu_is_omap16xx())
if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
if (cpu_class_is_omap1())
if (omap_lcd_dma_running())
return 1;
for (lch = 0; lch < dma_chan_count; lch++)
......@@ -1990,377 +1980,6 @@ static struct irqaction omap24xx_dma_irq;
/*----------------------------------------------------------------------------*/
static struct lcd_dma_info {
spinlock_t lock;
int reserved;
void (*callback)(u16 status, void *data);
void *cb_data;
int active;
unsigned long addr, size;
int rotate, data_type, xres, yres;
int vxres;
int mirror;
int xscale, yscale;
int ext_ctrl;
int src_port;
int single_transfer;
} lcd_dma;
void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
int data_type)
{
lcd_dma.addr = addr;
lcd_dma.data_type = data_type;
lcd_dma.xres = fb_xres;
lcd_dma.yres = fb_yres;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1);
void omap_set_lcd_dma_src_port(int port)
{
lcd_dma.src_port = port;
}
void omap_set_lcd_dma_ext_controller(int external)
{
lcd_dma.ext_ctrl = external;
}
EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
void omap_set_lcd_dma_single_transfer(int single)
{
lcd_dma.single_transfer = single;
}
EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
void omap_set_lcd_dma_b1_rotation(int rotate)
{
if (omap_dma_in_1510_mode()) {
printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
BUG();
return;
}
lcd_dma.rotate = rotate;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
void omap_set_lcd_dma_b1_mirror(int mirror)
{
if (omap_dma_in_1510_mode()) {
printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
BUG();
}
lcd_dma.mirror = mirror;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
{
if (omap_dma_in_1510_mode()) {
printk(KERN_ERR "DMA virtual resulotion is not supported "
"in 1510 mode\n");
BUG();
}
lcd_dma.vxres = vxres;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
{
if (omap_dma_in_1510_mode()) {
printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
BUG();
}
lcd_dma.xscale = xscale;
lcd_dma.yscale = yscale;
}
EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
static void set_b1_regs(void)
{
unsigned long top, bottom;
int es;
u16 w;
unsigned long en, fn;
long ei, fi;
unsigned long vxres;
unsigned int xscale, yscale;
switch (lcd_dma.data_type) {
case OMAP_DMA_DATA_TYPE_S8:
es = 1;
break;
case OMAP_DMA_DATA_TYPE_S16:
es = 2;
break;
case OMAP_DMA_DATA_TYPE_S32:
es = 4;
break;
default:
BUG();
return;
}
vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
BUG_ON(vxres < lcd_dma.xres);
#define PIXADDR(x, y) (lcd_dma.addr + \
((y) * vxres * yscale + (x) * xscale) * es)
#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
switch (lcd_dma.rotate) {
case 0:
if (!lcd_dma.mirror) {
top = PIXADDR(0, 0);
bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
/* 1510 DMA requires the bottom address to be 2 more
* than the actual last memory access location. */
if (omap_dma_in_1510_mode() &&
lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
bottom += 2;
ei = PIXSTEP(0, 0, 1, 0);
fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
} else {
top = PIXADDR(lcd_dma.xres - 1, 0);
bottom = PIXADDR(0, lcd_dma.yres - 1);
ei = PIXSTEP(1, 0, 0, 0);
fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
}
en = lcd_dma.xres;
fn = lcd_dma.yres;
break;
case 90:
if (!lcd_dma.mirror) {
top = PIXADDR(0, lcd_dma.yres - 1);
bottom = PIXADDR(lcd_dma.xres - 1, 0);
ei = PIXSTEP(0, 1, 0, 0);
fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
} else {
top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
bottom = PIXADDR(0, 0);
ei = PIXSTEP(0, 1, 0, 0);
fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
}
en = lcd_dma.yres;
fn = lcd_dma.xres;
break;
case 180:
if (!lcd_dma.mirror) {
top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
bottom = PIXADDR(0, 0);
ei = PIXSTEP(1, 0, 0, 0);
fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
} else {
top = PIXADDR(0, lcd_dma.yres - 1);
bottom = PIXADDR(lcd_dma.xres - 1, 0);
ei = PIXSTEP(0, 0, 1, 0);
fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
}
en = lcd_dma.xres;
fn = lcd_dma.yres;
break;
case 270:
if (!lcd_dma.mirror) {
top = PIXADDR(lcd_dma.xres - 1, 0);
bottom = PIXADDR(0, lcd_dma.yres - 1);
ei = PIXSTEP(0, 0, 0, 1);
fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
} else {
top = PIXADDR(0, 0);
bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
ei = PIXSTEP(0, 0, 0, 1);
fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
}
en = lcd_dma.yres;
fn = lcd_dma.xres;
break;
default:
BUG();
return; /* Suppress warning about uninitialized vars */
}
if (omap_dma_in_1510_mode()) {
omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
return;
}
/* 1610 regs */
omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
w = omap_readw(OMAP1610_DMA_LCD_CSDP);
w &= ~0x03;
w |= lcd_dma.data_type;
omap_writew(w, OMAP1610_DMA_LCD_CSDP);
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
/* Always set the source port as SDRAM for now*/
w &= ~(0x03 << 6);
if (lcd_dma.callback != NULL)
w |= 1 << 1; /* Block interrupt enable */
else
w &= ~(1 << 1);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
if (!(lcd_dma.rotate || lcd_dma.mirror ||
lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
return;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
/* Set the double-indexed addressing mode */
w |= (0x03 << 12);
omap_writew(w, OMAP1610_DMA_LCD_CCR);
omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
}
static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
{
u16 w;
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
if (unlikely(!(w & (1 << 3)))) {
printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
return IRQ_NONE;
}
/* Ack the IRQ */
w |= (1 << 3);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
lcd_dma.active = 0;
if (lcd_dma.callback != NULL)
lcd_dma.callback(w, lcd_dma.cb_data);
return IRQ_HANDLED;
}
int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
void *data)
{
spin_lock_irq(&lcd_dma.lock);
if (lcd_dma.reserved) {
spin_unlock_irq(&lcd_dma.lock);
printk(KERN_ERR "LCD DMA channel already reserved\n");
BUG();
return -EBUSY;
}
lcd_dma.reserved = 1;
spin_unlock_irq(&lcd_dma.lock);
lcd_dma.callback = callback;
lcd_dma.cb_data = data;
lcd_dma.active = 0;
lcd_dma.single_transfer = 0;
lcd_dma.rotate = 0;
lcd_dma.vxres = 0;
lcd_dma.mirror = 0;
lcd_dma.xscale = 0;
lcd_dma.yscale = 0;
lcd_dma.ext_ctrl = 0;
lcd_dma.src_port = 0;
return 0;
}
EXPORT_SYMBOL(omap_request_lcd_dma);
void omap_free_lcd_dma(void)
{
spin_lock(&lcd_dma.lock);
if (!lcd_dma.reserved) {
spin_unlock(&lcd_dma.lock);
printk(KERN_ERR "LCD DMA is not reserved\n");
BUG();
return;
}
if (!enable_1510_mode)
omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
OMAP1610_DMA_LCD_CCR);
lcd_dma.reserved = 0;
spin_unlock(&lcd_dma.lock);
}
EXPORT_SYMBOL(omap_free_lcd_dma);
void omap_enable_lcd_dma(void)
{
u16 w;
/*
* Set the Enable bit only if an external controller is
* connected. Otherwise the OMAP internal controller will
* start the transfer when it gets enabled.
*/
if (enable_1510_mode || !lcd_dma.ext_ctrl)
return;
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w |= 1 << 8;
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
lcd_dma.active = 1;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
w |= 1 << 7;
omap_writew(w, OMAP1610_DMA_LCD_CCR);
}
EXPORT_SYMBOL(omap_enable_lcd_dma);
void omap_setup_lcd_dma(void)
{
BUG_ON(lcd_dma.active);
if (!enable_1510_mode) {
/* Set some reasonable defaults */
omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
}
set_b1_regs();
if (!enable_1510_mode) {
u16 w;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
/*
* If DMA was already active set the end_prog bit to have
* the programmed register set loaded into the active
* register set.
*/
w |= 1 << 11; /* End_prog */
if (!lcd_dma.single_transfer)
w |= (3 << 8); /* Auto_init, repeat */
omap_writew(w, OMAP1610_DMA_LCD_CCR);
}
}
EXPORT_SYMBOL(omap_setup_lcd_dma);
void omap_stop_lcd_dma(void)
{
u16 w;
lcd_dma.active = 0;
if (enable_1510_mode || !lcd_dma.ext_ctrl)
return;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
w &= ~(1 << 7);
omap_writew(w, OMAP1610_DMA_LCD_CCR);
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w &= ~(1 << 8);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
}
EXPORT_SYMBOL(omap_stop_lcd_dma);
void omap_dma_global_context_save(void)
{
omap_dma_global_context.dma_irqenable_l0 =
......@@ -2465,14 +2084,6 @@ static int __init omap_init_dma(void)
dma_chan_count = 16;
} else
dma_chan_count = 9;
if (cpu_is_omap16xx()) {
u16 w;
/* this would prevent OMAP sleep */
w = omap_readw(OMAP1610_DMA_LCD_CTRL);
w &= ~(1 << 8);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
}
} else if (cpu_class_is_omap2()) {
u8 revision = dma_read(REVISION) & 0xff;
printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
......@@ -2483,7 +2094,6 @@ static int __init omap_init_dma(void)
return 0;
}
spin_lock_init(&lcd_dma.lock);
spin_lock_init(&dma_chan_lock);
for (ch = 0; ch < dma_chan_count; ch++) {
......@@ -2548,22 +2158,6 @@ static int __init omap_init_dma(void)
}
}
/* FIXME: Update LCD DMA to work on 24xx */
if (cpu_class_is_omap1()) {
r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
"LCD DMA", NULL);
if (r != 0) {
int i;
printk(KERN_ERR "unable to request IRQ for LCD DMA "
"(error %d)\n", r);
for (i = 0; i < dma_chan_count; i++)
free_irq(omap1_dma_irq[i], (void *) (i + 1));
goto out_free;
}
}
return 0;
out_free:
......
arch/arm/plat-omap/i2c.c
View file @ 5ccf1978
......@@ -80,47 +80,8 @@ static struct platform_device omap_i2c_devices[] = {
#endif
};
#if defined(CONFIG_ARCH_OMAP24XX)
static const int omap24xx_pins[][2] = {
{ M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA },
{ J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA },
};
#else
static const int omap24xx_pins[][2] = {};
#endif
#if defined(CONFIG_ARCH_OMAP34XX)
static const int omap34xx_pins[][2] = {
{ K21_34XX_I2C1_SCL, J21_34XX_I2C1_SDA},
{ AF15_34XX_I2C2_SCL, AE15_34XX_I2C2_SDA},
{ AF14_34XX_I2C3_SCL, AG14_34XX_I2C3_SDA},
};
#else
static const int omap34xx_pins[][2] = {};
#endif
#define OMAP_I2C_CMDLINE_SETUP (BIT(31))
static void __init omap_i2c_mux_pins(int bus)
{
int scl, sda;
if (cpu_class_is_omap1()) {
scl = I2C_SCL;
sda = I2C_SDA;
} else if (cpu_is_omap24xx()) {
scl = omap24xx_pins[bus][0];
sda = omap24xx_pins[bus][1];
} else if (cpu_is_omap34xx()) {
scl = omap34xx_pins[bus][0];
sda = omap34xx_pins[bus][1];
} else {
return;
}
omap_cfg_reg(sda);
omap_cfg_reg(scl);
}
static int __init omap_i2c_nr_ports(void)
{
int ports = 0;
......@@ -156,7 +117,6 @@ static int __init omap_i2c_add_bus(int bus_id)
res[1].start = irq;
}
omap_i2c_mux_pins(bus_id - 1);
return platform_device_register(pdev);
}
......@@ -209,7 +169,7 @@ static int __init omap_register_i2c_bus_cmdline(void)
subsys_initcall(omap_register_i2c_bus_cmdline);
/**
* omap_register_i2c_bus - register I2C bus with device descriptors
* omap_plat_register_i2c_bus - register I2C bus with device descriptors
* @bus_id: bus id counting from number 1
* @clkrate: clock rate of the bus in kHz
* @info: pointer into I2C device descriptor table or NULL
......@@ -217,7 +177,7 @@ subsys_initcall(omap_register_i2c_bus_cmdline);
*
* Returns 0 on success or an error code.
*/
int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
int __init omap_plat_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len)
{
......
arch/arm/plat-omap/include/plat/board.h
View file @ 5ccf1978
......@@ -114,15 +114,6 @@ struct omap_pwm_led_platform_data {
void (*set_power)(struct omap_pwm_led_platform_data *self, int on_off);
};
/* See arch/arm/plat-omap/include/mach/gpio-switch.h for definitions */
struct omap_gpio_switch_config {
char name[12];
u16 gpio;
int flags:4;
int type:4;
int key_code:24; /* Linux key code */
};
struct omap_uart_config {
/* Bit field of UARTs present; bit 0 --> UART1 */
unsigned int enabled_uarts;
......
arch/arm/plat-omap/include/plat/common.h
View file @ 5ccf1978
......@@ -27,7 +27,7 @@
#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
#define __ARCH_ARM_MACH_OMAP_COMMON_H
#include <linux/i2c.h>
#include <plat/i2c.h>
struct sys_timer;
......@@ -36,18 +36,6 @@ extern void __iomem *gic_cpu_base_addr;
extern void omap_map_common_io(void);
extern struct sys_timer omap_timer;
#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len);
#else
static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len)
{
return 0;
}
#endif
/* IO bases for various OMAP processors */
struct omap_globals {
......
arch/arm/plat-omap/include/plat/cpu.h
View file @ 5ccf1978
......@@ -176,11 +176,13 @@ IS_OMAP_CLASS(15xx, 0x15)
IS_OMAP_CLASS(16xx, 0x16)
IS_OMAP_CLASS(24xx, 0x24)
IS_OMAP_CLASS(34xx, 0x34)
IS_OMAP_CLASS(44xx, 0x44)
IS_OMAP_SUBCLASS(242x, 0x242)
IS_OMAP_SUBCLASS(243x, 0x243)
IS_OMAP_SUBCLASS(343x, 0x343)
IS_OMAP_SUBCLASS(363x, 0x363)
IS_OMAP_SUBCLASS(443x, 0x443)
#define cpu_is_omap7xx() 0
#define cpu_is_omap15xx() 0
......@@ -393,11 +395,11 @@ IS_OMAP_TYPE(3517, 0x3517)
(!omap3_has_iva()) && \
(!omap3_has_sgx()))
# define cpu_is_omap3515() (cpu_is_omap3430() && \
(omap3_has_iva()) && \
(!omap3_has_sgx()))
(!omap3_has_iva()) && \
(omap3_has_sgx()))
# define cpu_is_omap3525() (cpu_is_omap3430() && \
(omap3_has_sgx()) && \
(!omap3_has_iva()))
(!omap3_has_sgx()) && \
(omap3_has_iva()))
# define cpu_is_omap3530() (cpu_is_omap3430())
# define cpu_is_omap3505() is_omap3505()
# define cpu_is_omap3517() is_omap3517()
......@@ -408,8 +410,8 @@ IS_OMAP_TYPE(3517, 0x3517)
# if defined(CONFIG_ARCH_OMAP4)
# undef cpu_is_omap44xx
# undef cpu_is_omap443x
# define cpu_is_omap44xx() 1
# define cpu_is_omap443x() 1
# define cpu_is_omap44xx() is_omap44xx()
# define cpu_is_omap443x() is_omap443x()
# endif
/* Macros to detect if we have OMAP1 or OMAP2 */
......@@ -436,14 +438,15 @@ IS_OMAP_TYPE(3517, 0x3517)
#define OMAP3630_REV_ES1_0 0x36300034
#define OMAP35XX_CLASS 0x35000034
#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 12))
#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 12))
#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 12))
#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 12))
#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 12))
#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 12))
#define OMAP443X_CLASS 0x44300034
#define OMAP3503_REV(v) (OMAP35XX_CLASS | (0x3503 << 16) | (v << 8))
#define OMAP3515_REV(v) (OMAP35XX_CLASS | (0x3515 << 16) | (v << 8))
#define OMAP3525_REV(v) (OMAP35XX_CLASS | (0x3525 << 16) | (v << 8))
#define OMAP3530_REV(v) (OMAP35XX_CLASS | (0x3530 << 16) | (v << 8))
#define OMAP3505_REV(v) (OMAP35XX_CLASS | (0x3505 << 16) | (v << 8))
#define OMAP3517_REV(v) (OMAP35XX_CLASS | (0x3517 << 16) | (v << 8))
#define OMAP443X_CLASS 0x44300044
#define OMAP4430_REV_ES1_0 0x44300044
/*
* omap_chip bits
......
arch/arm/plat-omap/include/plat/dma.h
View file @ 5ccf1978
......@@ -401,33 +401,6 @@
/*----------------------------------------------------------------------------*/
/* Hardware registers for LCD DMA */
#define OMAP1510_DMA_LCD_BASE (0xfffedb00)
#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
#define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04)
#define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06)
#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
#define OMAP1610_DMA_LCD_BASE (0xfffee300)
#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
#define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca)
#define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc)
#define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce)
#define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0)
#define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2)
#define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4)
#define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6)
#define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8)
#define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda)
#define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0)
#define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4)
#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
#define OMAP1_DMA_TOUT_IRQ (1 << 0)
#define OMAP_DMA_DROP_IRQ (1 << 1)
#define OMAP_DMA_HALF_IRQ (1 << 2)
......@@ -441,6 +414,8 @@
#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
#define OMAP_DMA_CCR_EN (1 << 7)
#define OMAP_DMA_DATA_TYPE_S8 0x00
#define OMAP_DMA_DATA_TYPE_S16 0x01
#define OMAP_DMA_DATA_TYPE_S32 0x02
......@@ -503,14 +478,6 @@
#define DMA_CH_PRIO_HIGH 0x1
#define DMA_CH_PRIO_LOW 0x0 /* Def */
/* LCD DMA block numbers */
enum {
OMAP_LCD_DMA_B1_TOP,
OMAP_LCD_DMA_B1_BOTTOM,
OMAP_LCD_DMA_B2_TOP,
OMAP_LCD_DMA_B2_BOTTOM
};
enum omap_dma_burst_mode {
OMAP_DMA_DATA_BURST_DIS = 0,
OMAP_DMA_DATA_BURST_4,
......@@ -661,20 +628,13 @@ extern int omap_modify_dma_chain_params(int chain_id,
extern int omap_dma_chain_status(int chain_id);
#endif
/* LCD DMA functions */
extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
void *data);
extern void omap_free_lcd_dma(void);
extern void omap_setup_lcd_dma(void);
extern void omap_enable_lcd_dma(void);
extern void omap_stop_lcd_dma(void);
extern void omap_set_lcd_dma_ext_controller(int external);
extern void omap_set_lcd_dma_single_transfer(int single);
extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
int data_type);
extern void omap_set_lcd_dma_b1_rotation(int rotate);
extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
extern void omap_set_lcd_dma_b1_mirror(int mirror);
extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_FB_OMAP)
#include <mach/lcd_dma.h>
#else
static inline int omap_lcd_dma_running(void)
{
return 0;
}
#endif
#endif /* __ASM_ARCH_DMA_H */
arch/arm/plat-omap/include/plat/gpmc.h
View file @ 5ccf1978
......@@ -45,7 +45,7 @@
#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(1)
#define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(2)
#define GPMC_CONFIG1_MUXADDDATA (1 << 9)
#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
......
arch/arm/plat-omap/include/plat/i2c.h 0 → 100644
View file @ 5ccf1978
/*
* Helper module for board specific I2C bus registration
*
* Copyright (C) 2009 Nokia Corporation.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#include <linux/i2c.h>
#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len);
#else
static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len)
{
return 0;
}
#endif
int omap_plat_register_i2c_bus(int bus_id, u32 clkrate,
struct i2c_board_info const *info,
unsigned len);
arch/arm/plat-omap/include/plat/mux.h
View file @ 5ccf1978
......@@ -130,58 +130,11 @@
#define OMAP2_PULL_UP (1 << 4)
#define OMAP2_ALTELECTRICALSEL (1 << 5)
/* 34xx specific mux bit defines */
#define OMAP3_INPUT_EN (1 << 8)
#define OMAP3_OFF_EN (1 << 9)
#define OMAP3_OFFOUT_EN (1 << 10)
#define OMAP3_OFFOUT_VAL (1 << 11)
#define OMAP3_OFF_PULL_EN (1 << 12)
#define OMAP3_OFF_PULL_UP (1 << 13)
#define OMAP3_WAKEUP_EN (1 << 14)
/* 34xx mux mode options for each pin. See TRM for options */
#define OMAP34XX_MUX_MODE0 0
#define OMAP34XX_MUX_MODE1 1
#define OMAP34XX_MUX_MODE2 2
#define OMAP34XX_MUX_MODE3 3
#define OMAP34XX_MUX_MODE4 4
#define OMAP34XX_MUX_MODE5 5
#define OMAP34XX_MUX_MODE6 6
#define OMAP34XX_MUX_MODE7 7
/* 34xx active pin states */
#define OMAP34XX_PIN_OUTPUT 0
#define OMAP34XX_PIN_INPUT OMAP3_INPUT_EN
#define OMAP34XX_PIN_INPUT_PULLUP (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
| OMAP2_PULL_UP)
#define OMAP34XX_PIN_INPUT_PULLDOWN (OMAP2_PULL_ENA | OMAP3_INPUT_EN)
/* 34xx off mode states */
#define OMAP34XX_PIN_OFF_NONE 0
#define OMAP34XX_PIN_OFF_OUTPUT_HIGH (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
| OMAP3_OFFOUT_VAL)
#define OMAP34XX_PIN_OFF_OUTPUT_LOW (OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
#define OMAP34XX_PIN_OFF_INPUT_PULLUP (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
| OMAP3_OFF_PULL_UP)
#define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
#define OMAP34XX_PIN_OFF_WAKEUPENABLE OMAP3_WAKEUP_EN
#define MUX_CFG_34XX(desc, reg_offset, mux_value) { \
.name = desc, \
.debug = 0, \
.mux_reg = reg_offset, \
.mux_val = mux_value \
},
struct pin_config {
char *name;
const unsigned int mux_reg;
unsigned char debug;
#if defined(CONFIG_ARCH_OMAP34XX)
u16 mux_val; /* Wake-up, off mode, pull, mux mode */
#endif
#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
const unsigned char mask_offset;
const unsigned char mask;
......@@ -219,11 +172,17 @@ enum omap7xx_index {
AA17_7XX_USB_DM,
W16_7XX_USB_PU_EN,
W17_7XX_USB_VBUSI,
W18_7XX_USB_DMCK_OUT,
W19_7XX_USB_DCRST,
/* MMC */
MMC_7XX_CMD,
MMC_7XX_CLK,
MMC_7XX_DAT0,
/* I2C */
I2C_7XX_SCL,
I2C_7XX_SDA,
};
enum omap1xxx_index {
......@@ -681,181 +640,6 @@ enum omap24xx_index {
};
enum omap34xx_index {
/* 34xx I2C */
K21_34XX_I2C1_SCL,
J21_34XX_I2C1_SDA,
AF15_34XX_I2C2_SCL,
AE15_34XX_I2C2_SDA,
AF14_34XX_I2C3_SCL,
AG14_34XX_I2C3_SDA,
AD26_34XX_I2C4_SCL,
AE26_34XX_I2C4_SDA,
/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
Y8_3430_USB1HS_PHY_CLK,
Y9_3430_USB1HS_PHY_STP,
AA14_3430_USB1HS_PHY_DIR,
AA11_3430_USB1HS_PHY_NXT,
W13_3430_USB1HS_PHY_DATA0,
W12_3430_USB1HS_PHY_DATA1,
W11_3430_USB1HS_PHY_DATA2,
Y11_3430_USB1HS_PHY_DATA3,
W9_3430_USB1HS_PHY_DATA4,
Y12_3430_USB1HS_PHY_DATA5,
W8_3430_USB1HS_PHY_DATA6,
Y13_3430_USB1HS_PHY_DATA7,
/* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
AA8_3430_USB2HS_PHY_CLK,
AA10_3430_USB2HS_PHY_STP,
AA9_3430_USB2HS_PHY_DIR,
AB11_3430_USB2HS_PHY_NXT,
AB10_3430_USB2HS_PHY_DATA0,
AB9_3430_USB2HS_PHY_DATA1,
W3_3430_USB2HS_PHY_DATA2,
T4_3430_USB2HS_PHY_DATA3,
T3_3430_USB2HS_PHY_DATA4,
R3_3430_USB2HS_PHY_DATA5,
R4_3430_USB2HS_PHY_DATA6,
T2_3430_USB2HS_PHY_DATA7,
/* TLL - HSUSB: 12-pin TLL Port 1*/
Y8_3430_USB1HS_TLL_CLK,
Y9_3430_USB1HS_TLL_STP,
AA14_3430_USB1HS_TLL_DIR,
AA11_3430_USB1HS_TLL_NXT,
W13_3430_USB1HS_TLL_DATA0,
W12_3430_USB1HS_TLL_DATA1,
W11_3430_USB1HS_TLL_DATA2,
Y11_3430_USB1HS_TLL_DATA3,
W9_3430_USB1HS_TLL_DATA4,
Y12_3430_USB1HS_TLL_DATA5,
W8_3430_USB1HS_TLL_DATA6,
Y13_3430_USB1HS_TLL_DATA7,
/* TLL - HSUSB: 12-pin TLL Port 2*/
AA8_3430_USB2HS_TLL_CLK,
AA10_3430_USB2HS_TLL_STP,
AA9_3430_USB2HS_TLL_DIR,
AB11_3430_USB2HS_TLL_NXT,
AB10_3430_USB2HS_TLL_DATA0,
AB9_3430_USB2HS_TLL_DATA1,
W3_3430_USB2HS_TLL_DATA2,
T4_3430_USB2HS_TLL_DATA3,
T3_3430_USB2HS_TLL_DATA4,
R3_3430_USB2HS_TLL_DATA5,
R4_3430_USB2HS_TLL_DATA6,
T2_3430_USB2HS_TLL_DATA7,
/* TLL - HSUSB: 12-pin TLL Port 3*/
AA6_3430_USB3HS_TLL_CLK,
AB3_3430_USB3HS_TLL_STP,
AA3_3430_USB3HS_TLL_DIR,
Y3_3430_USB3HS_TLL_NXT,
AA5_3430_USB3HS_TLL_DATA0,
Y4_3430_USB3HS_TLL_DATA1,
Y5_3430_USB3HS_TLL_DATA2,
W5_3430_USB3HS_TLL_DATA3,
AB12_3430_USB3HS_TLL_DATA4,
AB13_3430_USB3HS_TLL_DATA5,
AA13_3430_USB3HS_TLL_DATA6,
AA12_3430_USB3HS_TLL_DATA7,
/* PHY FSUSB: FS Serial for Port 1 (multiple PHY modes supported) */
AF10_3430_USB1FS_PHY_MM1_RXDP,
AG9_3430_USB1FS_PHY_MM1_RXDM,
W13_3430_USB1FS_PHY_MM1_RXRCV,
W12_3430_USB1FS_PHY_MM1_TXSE0,
W11_3430_USB1FS_PHY_MM1_TXDAT,
Y11_3430_USB1FS_PHY_MM1_TXEN_N,
/* PHY FSUSB: FS Serial for Port 2 (multiple PHY modes supported) */
AF7_3430_USB2FS_PHY_MM2_RXDP,
AH7_3430_USB2FS_PHY_MM2_RXDM,
AB10_3430_USB2FS_PHY_MM2_RXRCV,
AB9_3430_USB2FS_PHY_MM2_TXSE0,
W3_3430_USB2FS_PHY_MM2_TXDAT,
T4_3430_USB2FS_PHY_MM2_TXEN_N,
/* PHY FSUSB: FS Serial for Port 3 (multiple PHY modes supported) */
AH3_3430_USB3FS_PHY_MM3_RXDP,
AE3_3430_USB3FS_PHY_MM3_RXDM,
AD1_3430_USB3FS_PHY_MM3_RXRCV,
AE1_3430_USB3FS_PHY_MM3_TXSE0,
AD2_3430_USB3FS_PHY_MM3_TXDAT,
AC1_3430_USB3FS_PHY_MM3_TXEN_N,
/* 34xx GPIO
* - normally these are bidirectional, no internal pullup/pulldown
* - "_UP" suffix (GPIO3_UP) if internal pullup is configured
* - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown
* - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx)
*/
AF26_34XX_GPIO0,
AF22_34XX_GPIO9,
AG9_34XX_GPIO23,
AH8_34XX_GPIO29,
U8_34XX_GPIO54_OUT,
U8_34XX_GPIO54_DOWN,
L8_34XX_GPIO63,
G25_34XX_GPIO86_OUT,
AG4_34XX_GPIO134_OUT,
AF4_34XX_GPIO135_OUT,
AE4_34XX_GPIO136_OUT,
AF6_34XX_GPIO140_UP,
AE6_34XX_GPIO141,
AF5_34XX_GPIO142,
AE5_34XX_GPIO143,
H19_34XX_GPIO164_OUT,
J25_34XX_GPIO170,
/* OMAP3 SDRC CKE signals to SDR/DDR ram chips */
H16_34XX_SDRC_CKE0,
H17_34XX_SDRC_CKE1,
/* MMC1 */
N28_3430_MMC1_CLK,
M27_3430_MMC1_CMD,
N27_3430_MMC1_DAT0,
N26_3430_MMC1_DAT1,
N25_3430_MMC1_DAT2,
P28_3430_MMC1_DAT3,
P27_3430_MMC1_DAT4,
P26_3430_MMC1_DAT5,
R27_3430_MMC1_DAT6,
R25_3430_MMC1_DAT7,
/* MMC2 */
AE2_3430_MMC2_CLK,
AG5_3430_MMC2_CMD,
AH5_3430_MMC2_DAT0,
AH4_3430_MMC2_DAT1,
AG4_3430_MMC2_DAT2,
AF4_3430_MMC2_DAT3,
AE4_3430_MMC2_DAT4,
AH3_3430_MMC2_DAT5,
AF3_3430_MMC2_DAT6,
AE3_3430_MMC2_DAT7,
/* MMC3 */
AF10_3430_MMC3_CLK,
AC3_3430_MMC3_CMD,
AE11_3430_MMC3_DAT0,
AH9_3430_MMC3_DAT1,
AF13_3430_MMC3_DAT2,
AF13_3430_MMC3_DAT3,
/* SYS_NIRQ T2 INT1 */
AF26_34XX_SYS_NIRQ,
/* EHCI GPIO's for OMAP3EVM (Rev >= E) */
AH14_34XX_GPIO21,
AF9_34XX_GPIO22,
U3_34XX_GPIO61,
};
struct omap_mux_cfg {
struct pin_config *pins;
unsigned long size;
......@@ -865,14 +649,14 @@ struct omap_mux_cfg {
#ifdef CONFIG_OMAP_MUX
/* setup pin muxing in Linux */
extern int omap1_mux_init(void);
extern int omap2_mux_init(void);
extern int omap_mux_register(struct omap_mux_cfg *);
extern int omap_cfg_reg(unsigned long reg_cfg);
#else
/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
static inline int omap1_mux_init(void) { return 0; }
static inline int omap2_mux_init(void) { return 0; }
static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
#endif
extern int omap2_mux_init(void);
#endif
arch/arm/plat-omap/include/plat/serial.h
View file @ 5ccf1978
......@@ -53,6 +53,7 @@
#ifndef __ASSEMBLER__
extern void __init omap_serial_early_init(void);
extern void omap_serial_init(void);
extern void omap_serial_init_port(int port);
extern int omap_uart_can_sleep(void);
extern void omap_uart_check_wakeup(void);
extern void omap_uart_prepare_suspend(void);
......
arch/arm/plat-omap/include/plat/smp.h
View file @ 5ccf1978
......@@ -28,6 +28,8 @@
/* Needed for secondary core boot */
extern void omap_secondary_startup(void);
extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
extern void omap_auxcoreboot_addr(u32 cpu_addr);
/*
* We use Soft IRQ1 as the IPI
......
arch/arm/plat-omap/mux.c
View file @ 5ccf1978
......@@ -54,8 +54,12 @@ int __init_or_module omap_cfg_reg(const unsigned long index)
{
struct pin_config *reg;
if (cpu_is_omap44xx())
return 0;
if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
index);
WARN_ON(1);
return -EINVAL;
}
if (mux_cfg == NULL) {
printk(KERN_ERR "Pin mux table not initialized\n");
......
arch/arm/plat-omap/sram.c
View file @ 5ccf1978
......@@ -48,8 +48,10 @@
#define OMAP3_SRAM_VA 0xfe400000
#define OMAP3_SRAM_PUB_PA 0x40208000
#define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000)
#define OMAP4_SRAM_PA 0x40200000 /*0x402f0000*/
#define OMAP4_SRAM_VA 0xfe400000 /*0xfe4f0000*/
#define OMAP4_SRAM_PA 0x40300000
#define OMAP4_SRAM_VA 0xfe400000
#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
#define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000)
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
#define SRAM_BOOTLOADER_SZ 0x00
......@@ -140,6 +142,10 @@ void __init omap_detect_sram(void)
} else {
omap_sram_size = 0x8000; /* 32K */
}
} else if (cpu_is_omap44xx()) {
omap_sram_base = OMAP4_SRAM_PUB_VA;
omap_sram_start = OMAP4_SRAM_PUB_PA;
omap_sram_size = 0xa000; /* 40K */
} else {
omap_sram_base = OMAP2_SRAM_PUB_VA;
omap_sram_start = OMAP2_SRAM_PUB_PA;
......@@ -153,7 +159,7 @@ void __init omap_detect_sram(void)
} else if (cpu_is_omap44xx()) {
omap_sram_base = OMAP4_SRAM_VA;
omap_sram_start = OMAP4_SRAM_PA;
omap_sram_size = 0x8000; /* 32K */
omap_sram_size = 0xe000; /* 56K */
} else {
omap_sram_base = OMAP2_SRAM_VA;
omap_sram_start = OMAP2_SRAM_PA;
......
arch/arm/plat-omap/usb.c
View file @ 5ccf1978
......@@ -137,7 +137,13 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
if (is_device) {
if (cpu_is_omap24xx())
omap_cfg_reg(J20_24XX_USB0_PUEN);
else
else if (cpu_is_omap7xx()) {
omap_cfg_reg(AA17_7XX_USB_DM);
omap_cfg_reg(W16_7XX_USB_PU_EN);
omap_cfg_reg(W17_7XX_USB_VBUSI);
omap_cfg_reg(W18_7XX_USB_DMCK_OUT);
omap_cfg_reg(W19_7XX_USB_DCRST);
} else
omap_cfg_reg(W4_USB_PUEN);
}
......
drivers/net/smc91x.h
View file @ 5ccf1978
......@@ -206,21 +206,6 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
}
}
#elif defined(CONFIG_ARCH_OMAP)
/* We can only do 16-bit reads and writes in the static memory space. */
#define SMC_CAN_USE_8BIT 0
#define SMC_CAN_USE_16BIT 1
#define SMC_CAN_USE_32BIT 0
#define SMC_IO_SHIFT 0
#define SMC_NOWAIT 1
#define SMC_inw(a, r) readw((a) + (r))
#define SMC_outw(v, a, r) writew(v, (a) + (r))
#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
#define SMC_IRQ_FLAGS (-1) /* from resource */
#elif defined(CONFIG_SH_SH4202_MICRODEV)
#define SMC_CAN_USE_8BIT 0
......
drivers/video/omap/lcdc.c
View file @ 5ccf1978
......@@ -29,6 +29,7 @@
#include <linux/vmalloc.h>
#include <linux/clk.h>
#include <mach/lcdc.h>
#include <plat/dma.h>
#include <asm/mach-types.h>
......@@ -39,38 +40,6 @@
#define MODULE_NAME "lcdc"
#define OMAP_LCDC_BASE 0xfffec000
#define OMAP_LCDC_SIZE 256
#define OMAP_LCDC_IRQ INT_LCD_CTRL
#define OMAP_LCDC_CONTROL (OMAP_LCDC_BASE + 0x00)
#define OMAP_LCDC_TIMING0 (OMAP_LCDC_BASE + 0x04)
#define OMAP_LCDC_TIMING1 (OMAP_LCDC_BASE + 0x08)
#define OMAP_LCDC_TIMING2 (OMAP_LCDC_BASE + 0x0c)
#define OMAP_LCDC_STATUS (OMAP_LCDC_BASE + 0x10)
#define OMAP_LCDC_SUBPANEL (OMAP_LCDC_BASE + 0x14)
#define OMAP_LCDC_LINE_INT (OMAP_LCDC_BASE + 0x18)
#define OMAP_LCDC_DISPLAY_STATUS (OMAP_LCDC_BASE + 0x1c)
#define OMAP_LCDC_STAT_DONE (1 << 0)
#define OMAP_LCDC_STAT_VSYNC (1 << 1)
#define OMAP_LCDC_STAT_SYNC_LOST (1 << 2)
#define OMAP_LCDC_STAT_ABC (1 << 3)
#define OMAP_LCDC_STAT_LINE_INT (1 << 4)
#define OMAP_LCDC_STAT_FUF (1 << 5)
#define OMAP_LCDC_STAT_LOADED_PALETTE (1 << 6)
#define OMAP_LCDC_CTRL_LCD_EN (1 << 0)
#define OMAP_LCDC_CTRL_LCD_TFT (1 << 7)
#define OMAP_LCDC_CTRL_LINE_IRQ_CLR_SEL (1 << 10)
#define OMAP_LCDC_IRQ_VSYNC (1 << 2)
#define OMAP_LCDC_IRQ_DONE (1 << 3)
#define OMAP_LCDC_IRQ_LOADED_PALETTE (1 << 4)
#define OMAP_LCDC_IRQ_LINE_NIRQ (1 << 5)
#define OMAP_LCDC_IRQ_LINE (1 << 6)
#define OMAP_LCDC_IRQ_MASK (((1 << 5) - 1) << 2)
#define MAX_PALETTE_SIZE PAGE_SIZE
enum lcdc_load_mode {
......
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