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Commit 5d3adbe2 authored by Ralf Bächle's avatar Ralf Bächle Committed by Linus Torvalds
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[PATCH] Update for MIPS Inc's eval boards. 

This is an update for MIPS Inc's evaluation boards in all their ugly
versions ...
parent a85be436
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Showing with 4834 additions and 4120 deletions
arch/mips/defconfig-atlas
View file @ 5d3adbe2
......@@ -2,90 +2,125 @@
# Automatically generated make config: don't edit
#
CONFIG_MIPS=y
# CONFIG_SMP is not set
CONFIG_MIPS32=y
# CONFIG_MIPS64 is not set
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
#
# General setup
#
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_EMBEDDED is not set
CONFIG_FUTEX=y
CONFIG_EPOLL=y
#
# Loadable module support
#
# CONFIG_MODULES is not set
#
# Machine selection
#
# CONFIG_ACER_PICA_61 is not set
# CONFIG_ALGOR_P4032 is not set
# CONFIG_BAGET_MIPS is not set
# CONFIG_CASIO_E55 is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_DECSTATION is not set
# CONFIG_DDB5074 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_LASAT is not set
# CONFIG_HP_LASERJET is not set
# CONFIG_IBM_WORKPAD is not set
# CONFIG_MIPS_ITE8172 is not set
CONFIG_MIPS_ATLAS=y
# CONFIG_MIPS_MALTA is not set
# CONFIG_NINO is not set
# CONFIG_MIPS_MAGNUM_4000 is not set
# CONFIG_MIPS_MALTA is not set
# CONFIG_MIPS_SEAD is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_DDB5074 is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_NEC_OSPREY is not set
# CONFIG_NEC_EAGLE is not set
# CONFIG_OLIVETTI_M700 is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SOC_AU1X00 is not set
# CONFIG_SIBYTE_SB1xxx_SOC is not set
# CONFIG_SNI_RM200_PCI is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_PB1000 is not set
# CONFIG_TANBAC_TB0226 is not set
# CONFIG_TANBAC_TB0229 is not set
# CONFIG_TOSHIBA_JMR3927 is not set
# CONFIG_TOSHIBA_RBTX4927 is not set
# CONFIG_VICTOR_MPC30X is not set
# CONFIG_ZAO_CAPCELLA is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
# CONFIG_MCA is not set
# CONFIG_SBUS is not set
CONFIG_PCI=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_NONCOHERENT_IO=y
# CONFIG_CPU_LITTLE_ENDIAN is not set
CONFIG_MIPS_BOARDS_GEN=y
CONFIG_SWAP_IO_SPACE=y
# CONFIG_ISA is not set
# CONFIG_EISA is not set
# CONFIG_I8259 is not set
#
# Loadable module support
#
# CONFIG_MODULES is not set
CONFIG_BOOT_ELF32=y
CONFIG_L1_CACHE_SHIFT=5
# CONFIG_FB is not set
#
# CPU selection
#
CONFIG_CPU_MIPS32=y
# CONFIG_CPU_MIPS64 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
CONFIG_CPU_R5000=y
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_SB1 is not set
# CONFIG_CPU_MIPS32 is not set
# CONFIG_CPU_MIPS64 is not set
CONFIG_CPU_HAS_PREFETCH=y
# CONFIG_VTAG_ICACHE is not set
# CONFIG_64BIT_PHYS_ADDR is not set
# CONFIG_CPU_ADVANCED is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_LLDSCD=y
# CONFIG_CPU_HAS_WB is not set
CONFIG_CPU_HAS_SYNC=y
# CONFIG_PREEMPT is not set
CONFIG_KALLSYMS=y
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
#
# General setup
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
#
CONFIG_PCI=y
CONFIG_PCI_LEGACY_PROC=y
CONFIG_PCI_NAMES=y
CONFIG_MMU=y
# CONFIG_HOTPLUG is not set
#
# Executable file formats
#
# CONFIG_CPU_LITTLE_ENDIAN is not set
CONFIG_KCORE_ELF=y
CONFIG_ELF_KERNEL=y
CONFIG_BINFMT_IRIX=y
# CONFIG_FORWARD_KEYBOARD is not set
# CONFIG_BINFMT_AOUT is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_NET=y
# CONFIG_PCI_NAMES is not set
# CONFIG_HOTPLUG is not set
# CONFIG_PCMCIA is not set
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_SYSCTL is not set
# CONFIG_BINFMT_IRIX is not set
#
# Memory Technology Devices (MTD)
......@@ -97,92 +132,37 @@ CONFIG_SYSVIPC=y
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNP is not set
#
# Generic Driver Options
#
# CONFIG_FW_LOADER is not set
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_DEV_XD is not set
# CONFIG_PARIDE is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_UMEM is not set
CONFIG_BLK_DEV_LOOP=y
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_BLK_DEV_INITRD is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
# CONFIG_BLK_DEV_MD is not set
# CONFIG_MD_LINEAR is not set
# CONFIG_MD_RAID0 is not set
# CONFIG_MD_RAID1 is not set
# CONFIG_MD_RAID5 is not set
# CONFIG_BLK_DEV_LVM is not set
#
# Networking options
#
# CONFIG_PACKET is not set
# CONFIG_NETLINK is not set
# CONFIG_NETFILTER is not set
# CONFIG_FILTER is not set
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
# CONFIG_IP_PNP_DHCP is not set
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_INET_ECN is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_IPV6 is not set
# CONFIG_KHTTPD is not set
# CONFIG_ATM is not set
#
#
#
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_LLC is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_FASTROUTE is not set
# CONFIG_NET_HW_FLOWCONTROL is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
# CONFIG_PHONE_IXJ is not set
# CONFIG_PHONE_IXJ_PCMCIA is not set
#
# ATA/IDE/MFM/RLL support
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_IDE is not set
# CONFIG_BLK_DEV_IDE_MODES is not set
# CONFIG_BLK_DEV_HD is not set
#
# SCSI support
# SCSI device support
#
CONFIG_SCSI=y
......@@ -190,7 +170,6 @@ CONFIG_SCSI=y
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
CONFIG_SD_EXTRA_DEVS=40
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
# CONFIG_BLK_DEV_SR is not set
......@@ -199,8 +178,8 @@ CONFIG_SD_EXTRA_DEVS=40
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_DEBUG_QUEUES is not set
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_REPORT_LUNS is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
......@@ -208,53 +187,115 @@ CONFIG_SD_EXTRA_DEVS=40
# SCSI low-level drivers
#
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_7000FASST is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AHA152X is not set
# CONFIG_SCSI_AHA1542 is not set
# CONFIG_SCSI_AHA1740 is not set
# CONFIG_SCSI_AACRAID is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_AIC79XX is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_IN2000 is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_MEGARAID is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_CPQFCTS is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_DTC3280 is not set
# CONFIG_SCSI_EATA is not set
# CONFIG_SCSI_EATA_DMA is not set
# CONFIG_SCSI_EATA_PIO is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_GDTH is not set
# CONFIG_SCSI_GENERIC_NCR5380 is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_NCR53C406A is not set
# CONFIG_SCSI_NCR_D700 is not set
# CONFIG_SCSI_NCR53C7xx is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_NCR53C8XX is not set
# CONFIG_SCSI_SYM53C8XX is not set
# CONFIG_SCSI_PAS16 is not set
# CONFIG_SCSI_PCI2000 is not set
# CONFIG_SCSI_PCI2220I is not set
# CONFIG_SCSI_PSI240I is not set
# CONFIG_SCSI_QLOGIC_FAS is not set
# CONFIG_SCSI_QLOGIC_ISP is not set
# CONFIG_SCSI_QLOGIC_FC is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_SIM710 is not set
# CONFIG_SCSI_SYM53C416 is not set
# CONFIG_SCSI_DC395x is not set
# CONFIG_SCSI_DC390T is not set
# CONFIG_SCSI_T128 is not set
# CONFIG_SCSI_U14_34F is not set
# CONFIG_SCSI_NSP32 is not set
# CONFIG_SCSI_DEBUG is not set
#
# Network device support
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
#
# IEEE 1394 (FireWire) support (EXPERIMENTAL)
#
# CONFIG_IEEE1394 is not set
#
# I2O device support
#
# CONFIG_I2O is not set
#
# Networking support
#
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_NETLINK_DEV=y
# CONFIG_NETFILTER is not set
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
# CONFIG_IP_PNP_DHCP is not set
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_INET_ECN is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_IPV6 is not set
# CONFIG_XFRM_USER is not set
#
# SCTP Configuration (EXPERIMENTAL)
#
CONFIG_IPV6_SCTP__=y
# CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_LLC is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_FASTROUTE is not set
# CONFIG_NET_HW_FLOWCONTROL is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
CONFIG_NETDEVICES=y
#
......@@ -265,39 +306,43 @@ CONFIG_NETDEVICES=y
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_ETHERTAP is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
# CONFIG_SUNLANCE is not set
# CONFIG_MII is not set
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNBMAC is not set
# CONFIG_SUNQE is not set
# CONFIG_SUNLANCE is not set
# CONFIG_SUNGEM is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_LANCE is not set
# CONFIG_NET_VENDOR_SMC is not set
# CONFIG_NET_VENDOR_RACAL is not set
#
# Tulip family network device support
#
# CONFIG_NET_TULIP is not set
# CONFIG_HP100 is not set
# CONFIG_NET_ISA is not set
# CONFIG_NET_PCI is not set
# CONFIG_NET_POCKET is not set
#
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_MYRI_SBUS is not set
# CONFIG_E1000 is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_R8169 is not set
# CONFIG_SK98LIN is not set
# CONFIG_TIGON3 is not set
#
# Ethernet (10000 Mbit)
#
# CONFIG_IXGB is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PLIP is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
......@@ -307,9 +352,8 @@ CONFIG_NET_ETHERNET=y
# CONFIG_NET_RADIO is not set
#
# Token Ring devices
# Token Ring devices (depends on LLC=y)
#
# CONFIG_TR is not set
# CONFIG_NET_FC is not set
# CONFIG_RCPCI is not set
# CONFIG_SHAPER is not set
......@@ -332,21 +376,65 @@ CONFIG_NET_ETHERNET=y
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
# CONFIG_ISDN_BOOL is not set
#
# Old CD-ROM drivers (not SCSI, not IDE)
# Telephony Support
#
# CONFIG_CD_NO_IDESCSI is not set
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input I/O drivers
#
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
# CONFIG_SERIO_PCIPS2 is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Character devices
#
# CONFIG_VT is not set
CONFIG_SERIAL=y
CONFIG_SERIAL_CONSOLE=y
# CONFIG_SERIAL_EXTENDED is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_EXTENDED is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
......@@ -356,36 +444,35 @@ CONFIG_UNIX98_PTY_COUNT=256
# CONFIG_I2C is not set
#
# Mice
# I2C Hardware Sensors Mainboard support
#
# CONFIG_BUSMOUSE is not set
# CONFIG_MOUSE is not set
#
# Joysticks
# I2C Hardware Sensors Chip support
#
# CONFIG_INPUT_GAMEPORT is not set
# CONFIG_I2C_SENSOR is not set
#
# Input core support is needed for gameports
# Mice
#
# CONFIG_BUSMOUSE is not set
# CONFIG_QIC02_TAPE is not set
#
# Input core support is needed for joysticks
# IPMI
#
# CONFIG_QIC02_TAPE is not set
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_INTEL_RNG is not set
# CONFIG_NVRAM is not set
CONFIG_RTC=y
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
# CONFIG_SONYPI is not set
#
# Ftape, the floppy tape device driver
......@@ -393,93 +480,103 @@ CONFIG_RTC=y
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_HANGCHECK_TIMER is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_QUOTA is not set
CONFIG_AUTOFS_FS=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_REISERFS_CHECK is not set
# CONFIG_REISERFS_PROC_INFO is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_FAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
CONFIG_DEVPTS_FS=y
CONFIG_DEVPTS_FS_XATTR=y
CONFIG_DEVPTS_FS_SECURITY=y
# CONFIG_TMPFS is not set
CONFIG_RAMFS=y
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_ADFS_FS_RW is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_CMS_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_JBD_DEBUG is not set
# CONFIG_FAT_FS is not set
# CONFIG_MSDOS_FS is not set
# CONFIG_UMSDOS_FS is not set
# CONFIG_VFAT_FS is not set
CONFIG_EFS_FS=y
# CONFIG_JFFS_FS is not set
# CONFIG_JFFS2_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_TMPFS is not set
# CONFIG_RAMFS is not set
# CONFIG_ISO9660_FS is not set
# CONFIG_JOLIET is not set
# CONFIG_MINIX_FS is not set
# CONFIG_FREEVXFS_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS_DEBUG is not set
# CONFIG_NTFS_RW is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
# CONFIG_DEVFS_MOUNT is not set
# CONFIG_DEVFS_DEBUG is not set
CONFIG_DEVPTS_FS=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX4FS_RW is not set
# CONFIG_ROMFS_FS is not set
CONFIG_EXT2_FS=y
# CONFIG_SYSV_FS is not set
# CONFIG_UDF_FS is not set
# CONFIG_UDF_RW is not set
# CONFIG_UFS_FS is not set
# CONFIG_UFS_FS_WRITE is not set
#
# Network File Systems
#
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
CONFIG_ROOT_NFS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V4 is not set
# CONFIG_NFSD is not set
# CONFIG_NFSD_V3 is not set
CONFIG_SUNRPC=y
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
# CONFIG_EXPORTFS is not set
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_GSS is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_NCPFS_PACKET_SIGNING is not set
# CONFIG_NCPFS_IOCTL_LOCKING is not set
# CONFIG_NCPFS_STRONG is not set
# CONFIG_NCPFS_NFS_NS is not set
# CONFIG_NCPFS_OS2_NS is not set
# CONFIG_NCPFS_SMALLDOS is not set
# CONFIG_NCPFS_NLS is not set
# CONFIG_NCPFS_EXTRAS is not set
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_SMB_NLS is not set
# CONFIG_NLS is not set
#
# Graphics support
#
#
# Sound
......@@ -490,116 +587,30 @@ CONFIG_MSDOS_PARTITION=y
# USB support
#
# CONFIG_USB is not set
# CONFIG_USB_GADGET is not set
#
# USB Controllers
#
# CONFIG_USB_UHCI is not set
# CONFIG_USB_UHCI_ALT is not set
# CONFIG_USB_OHCI is not set
#
# USB Device Class drivers
#
# CONFIG_USB_AUDIO is not set
# CONFIG_USB_BLUETOOTH is not set
# CONFIG_USB_STORAGE is not set
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_DPCM is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
#
# USB Human Interface Devices (HID)
#
#
# Input core support is needed for USB HID
#
#
# USB Imaging devices
#
# CONFIG_USB_DC2XX is not set
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_SCANNER is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USB_HPUSBSCSI is not set
#
# USB Multimedia devices
# Bluetooth support
#
# CONFIG_BT is not set
#
# Video4Linux support is needed for USB Multimedia device support
#
# CONFIG_USB_DABUSB is not set
#
# USB Network adaptors
#
# CONFIG_USB_PLUSB is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_CATC is not set
# CONFIG_USB_CDCETHER is not set
# CONFIG_USB_USBNET is not set
#
# USB port drivers
#
# CONFIG_USB_USS720 is not set
#
# USB Serial Converter support
# Kernel hacking
#
# CONFIG_USB_SERIAL is not set
# CONFIG_USB_SERIAL_GENERIC is not set
# CONFIG_USB_SERIAL_BELKIN is not set
# CONFIG_USB_SERIAL_WHITEHEAT is not set
# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
# CONFIG_USB_SERIAL_EMPEG is not set
# CONFIG_USB_SERIAL_FTDI_SIO is not set
# CONFIG_USB_SERIAL_VISOR is not set
# CONFIG_USB_SERIAL_EDGEPORT is not set
# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
# CONFIG_USB_SERIAL_KEYSPAN is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
# CONFIG_USB_SERIAL_MCT_U232 is not set
# CONFIG_USB_SERIAL_PL2303 is not set
# CONFIG_USB_SERIAL_CYBERJACK is not set
# CONFIG_USB_SERIAL_OMNINET is not set
CONFIG_CROSSCOMPILE=y
# CONFIG_DEBUG_KERNEL is not set
#
# Miscellaneous USB drivers
# Security options
#
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_ID75 is not set
# CONFIG_SECURITY is not set
#
# Input core support
# Cryptographic options
#
# CONFIG_INPUT is not set
# CONFIG_INPUT_KEYBDEV is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_CRYPTO is not set
#
# Kernel hacking
# Library routines
#
CONFIG_CROSSCOMPILE=y
# CONFIG_REMOTE_DEBUG is not set
# CONFIG_GDB_CONSOLE is not set
# CONFIG_LL_DEBUG is not set
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_MIPS_UNCACHED is not set
# CONFIG_CRC32 is not set
arch/mips/defconfig-malta
View file @ 5d3adbe2
......@@ -2,90 +2,129 @@
# Automatically generated make config: don't edit
#
CONFIG_MIPS=y
# CONFIG_SMP is not set
CONFIG_MIPS32=y
# CONFIG_MIPS64 is not set
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
#
# General setup
#
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_EMBEDDED is not set
CONFIG_FUTEX=y
CONFIG_EPOLL=y
#
# Loadable module support
#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
CONFIG_OBSOLETE_MODPARM=y
CONFIG_MODVERSIONS=y
CONFIG_KMOD=y
#
# Machine selection
#
# CONFIG_ACER_PICA_61 is not set
# CONFIG_ALGOR_P4032 is not set
# CONFIG_BAGET_MIPS is not set
# CONFIG_CASIO_E55 is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_DECSTATION is not set
# CONFIG_DDB5074 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_LASAT is not set
# CONFIG_HP_LASERJET is not set
# CONFIG_IBM_WORKPAD is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MIPS_ATLAS is not set
CONFIG_MIPS_MALTA=y
# CONFIG_NINO is not set
# CONFIG_MIPS_MAGNUM_4000 is not set
CONFIG_MIPS_MALTA=y
# CONFIG_MIPS_SEAD is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_DDB5074 is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_NEC_OSPREY is not set
# CONFIG_NEC_EAGLE is not set
# CONFIG_OLIVETTI_M700 is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SOC_AU1X00 is not set
# CONFIG_SIBYTE_SB1xxx_SOC is not set
# CONFIG_SNI_RM200_PCI is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_MIPS_PB1000 is not set
# CONFIG_TANBAC_TB0226 is not set
# CONFIG_TANBAC_TB0229 is not set
# CONFIG_TOSHIBA_JMR3927 is not set
# CONFIG_TOSHIBA_RBTX4927 is not set
# CONFIG_VICTOR_MPC30X is not set
# CONFIG_ZAO_CAPCELLA is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
# CONFIG_MCA is not set
# CONFIG_SBUS is not set
CONFIG_GENERIC_ISA_DMA=y
CONFIG_I8259=y
CONFIG_PCI=y
CONFIG_HAVE_STD_PC_SERIAL_PORT=y
CONFIG_NEW_IRQ=y
CONFIG_NONCOHERENT_IO=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_MIPS_BOARDS_GEN=y
CONFIG_SWAP_IO_SPACE=y
# CONFIG_ISA is not set
# CONFIG_EISA is not set
#
# Loadable module support
#
# CONFIG_MODULES is not set
CONFIG_BOOT_ELF32=y
CONFIG_L1_CACHE_SHIFT=5
# CONFIG_FB is not set
CONFIG_HAVE_STD_PC_SERIAL_PORT=y
#
# CPU selection
#
CONFIG_CPU_MIPS32=y
# CONFIG_CPU_MIPS64 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_CPU_MIPS32=y
# CONFIG_CPU_MIPS64 is not set
CONFIG_CPU_HAS_PREFETCH=y
# CONFIG_VTAG_ICACHE is not set
# CONFIG_64BIT_PHYS_ADDR is not set
# CONFIG_CPU_ADVANCED is not set
CONFIG_CPU_HAS_LLSC=y
# CONFIG_CPU_HAS_LLDSCD is not set
# CONFIG_CPU_HAS_WB is not set
CONFIG_CPU_HAS_SYNC=y
# CONFIG_PREEMPT is not set
CONFIG_KALLSYMS=y
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
#
# General setup
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
#
# CONFIG_PCI is not set
CONFIG_MMU=y
# CONFIG_HOTPLUG is not set
#
# Executable file formats
#
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_KCORE_ELF=y
CONFIG_ELF_KERNEL=y
# CONFIG_BINFMT_AOUT is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_NET=y
# CONFIG_PCI_NAMES is not set
# CONFIG_HOTPLUG is not set
# CONFIG_PCMCIA is not set
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_SYSCTL is not set
#
# Memory Technology Devices (MTD)
......@@ -97,65 +136,119 @@ CONFIG_SYSVIPC=y
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNP is not set
#
# Generic Driver Options
#
# CONFIG_FW_LOADER is not set
#
# Block devices
#
CONFIG_BLK_DEV_FD=y
# CONFIG_BLK_DEV_XD is not set
# CONFIG_PARIDE is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_BLK_DEV_INITRD is not set
#
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_IDE is not set
#
# SCSI device support
#
CONFIG_SCSI=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
# CONFIG_BLK_DEV_SR is not set
# CONFIG_CHR_DEV_SG is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_REPORT_LUNS is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
#
# SCSI low-level drivers
#
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_EATA_PIO is not set
# CONFIG_SCSI_DEBUG is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
# CONFIG_BLK_DEV_MD is not set
# CONFIG_MD_LINEAR is not set
# CONFIG_MD_RAID0 is not set
# CONFIG_MD_RAID1 is not set
# CONFIG_MD_RAID5 is not set
# CONFIG_BLK_DEV_LVM is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
#
# I2O device support
#
#
# Networking support
#
CONFIG_NET=y
#
# Networking options
#
# CONFIG_PACKET is not set
# CONFIG_NETLINK is not set
CONFIG_NETLINK_DEV=y
# CONFIG_NETFILTER is not set
# CONFIG_FILTER is not set
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
# CONFIG_IP_PNP_DHCP is not set
# CONFIG_IP_PNP_BOOTP is not set
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_INET_ECN is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_IPV6 is not set
# CONFIG_KHTTPD is not set
# CONFIG_ATM is not set
# CONFIG_XFRM_USER is not set
#
# SCTP Configuration (EXPERIMENTAL)
#
#
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
CONFIG_IPV6_SCTP__=y
# CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_LLC is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_LLC is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
......@@ -168,162 +261,29 @@ CONFIG_IP_PNP=y
# CONFIG_NET_SCHED is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
# CONFIG_PHONE_IXJ is not set
# CONFIG_PHONE_IXJ_PCMCIA is not set
#
# ATA/IDE/MFM/RLL support
#
# CONFIG_IDE is not set
# CONFIG_BLK_DEV_IDE_MODES is not set
# CONFIG_BLK_DEV_HD is not set
#
# SCSI support
#
CONFIG_SCSI=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
CONFIG_SD_EXTRA_DEVS=40
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
# CONFIG_BLK_DEV_SR is not set
# CONFIG_CHR_DEV_SG is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_DEBUG_QUEUES is not set
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
#
# SCSI low-level drivers
#
# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
# CONFIG_SCSI_7000FASST is not set
# CONFIG_SCSI_ACARD is not set
# CONFIG_SCSI_AHA152X is not set
# CONFIG_SCSI_AHA1542 is not set
# CONFIG_SCSI_AHA1740 is not set
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_ADVANSYS is not set
# CONFIG_SCSI_IN2000 is not set
# CONFIG_SCSI_AM53C974 is not set
# CONFIG_SCSI_MEGARAID is not set
# CONFIG_SCSI_BUSLOGIC is not set
# CONFIG_SCSI_CPQFCTS is not set
# CONFIG_SCSI_DMX3191D is not set
# CONFIG_SCSI_DTC3280 is not set
# CONFIG_SCSI_EATA is not set
# CONFIG_SCSI_EATA_DMA is not set
# CONFIG_SCSI_EATA_PIO is not set
# CONFIG_SCSI_FUTURE_DOMAIN is not set
# CONFIG_SCSI_GDTH is not set
# CONFIG_SCSI_GENERIC_NCR5380 is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_NCR53C406A is not set
# CONFIG_SCSI_NCR_D700 is not set
# CONFIG_SCSI_NCR53C7xx is not set
# CONFIG_SCSI_NCR53C8XX is not set
# CONFIG_SCSI_SYM53C8XX is not set
# CONFIG_SCSI_PAS16 is not set
# CONFIG_SCSI_PCI2000 is not set
# CONFIG_SCSI_PCI2220I is not set
# CONFIG_SCSI_PSI240I is not set
# CONFIG_SCSI_QLOGIC_FAS is not set
# CONFIG_SCSI_QLOGIC_ISP is not set
# CONFIG_SCSI_QLOGIC_FC is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_SIM710 is not set
# CONFIG_SCSI_SYM53C416 is not set
# CONFIG_SCSI_DC390T is not set
# CONFIG_SCSI_T128 is not set
# CONFIG_SCSI_U14_34F is not set
# CONFIG_SCSI_DEBUG is not set
#
# Network device support
# Network testing
#
# CONFIG_NET_PKTGEN is not set
CONFIG_NETDEVICES=y
#
# ARCnet devices
#
# CONFIG_ARCNET is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_ETHERTAP is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
# CONFIG_SUNLANCE is not set
# CONFIG_HAPPYMEAL is not set
# CONFIG_SUNBMAC is not set
# CONFIG_SUNQE is not set
# CONFIG_SUNLANCE is not set
# CONFIG_SUNGEM is not set
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_LANCE is not set
# CONFIG_NET_VENDOR_SMC is not set
# CONFIG_NET_VENDOR_RACAL is not set
# CONFIG_HP100 is not set
# CONFIG_NET_ISA is not set
CONFIG_NET_PCI=y
CONFIG_PCNET32=y
# CONFIG_ADAPTEC_STARFIRE is not set
# CONFIG_APRICOT is not set
# CONFIG_CS89x0 is not set
# CONFIG_TULIP is not set
# CONFIG_DE4X5 is not set
# CONFIG_DGRS is not set
# CONFIG_DM9102 is not set
# CONFIG_EEPRO100 is not set
# CONFIG_LNE390 is not set
# CONFIG_FEALNX is not set
# CONFIG_NATSEMI is not set
# CONFIG_NE2K_PCI is not set
# CONFIG_NE3210 is not set
# CONFIG_ES3210 is not set
# CONFIG_8139TOO is not set
# CONFIG_8139TOO_PIO is not set
# CONFIG_8139TOO_TUNE_TWISTER is not set
# CONFIG_8139TOO_8129 is not set
# CONFIG_SIS900 is not set
# CONFIG_EPIC100 is not set
# CONFIG_SUNDANCE is not set
# CONFIG_TLAN is not set
# CONFIG_VIA_RHINE is not set
# CONFIG_WINBOND_840 is not set
# CONFIG_LAN_SAA9730 is not set
# CONFIG_NET_POCKET is not set
# CONFIG_MII is not set
#
# Ethernet (1000 Mbit)
#
# CONFIG_ACENIC is not set
# CONFIG_DL2K is not set
# CONFIG_MYRI_SBUS is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_SK98LIN is not set
# CONFIG_FDDI is not set
# CONFIG_HIPPI is not set
# CONFIG_PLIP is not set
#
# Ethernet (10000 Mbit)
#
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
......@@ -333,11 +293,8 @@ CONFIG_PCNET32=y
# CONFIG_NET_RADIO is not set
#
# Token Ring devices
# Token Ring devices (depends on LLC=y)
#
# CONFIG_TR is not set
# CONFIG_NET_FC is not set
# CONFIG_RCPCI is not set
# CONFIG_SHAPER is not set
#
......@@ -358,21 +315,64 @@ CONFIG_PCNET32=y
#
# ISDN subsystem
#
# CONFIG_ISDN is not set
# CONFIG_ISDN_BOOL is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input I/O drivers
#
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
#
# Old CD-ROM drivers (not SCSI, not IDE)
# Input Device Drivers
#
# CONFIG_CD_NO_IDESCSI is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Character devices
#
# CONFIG_VT is not set
CONFIG_SERIAL=y
CONFIG_SERIAL_CONSOLE=y
# CONFIG_SERIAL_EXTENDED is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_EXTENDED is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
......@@ -382,36 +382,34 @@ CONFIG_UNIX98_PTY_COUNT=256
# CONFIG_I2C is not set
#
# Mice
# I2C Hardware Sensors Mainboard support
#
# CONFIG_BUSMOUSE is not set
# CONFIG_MOUSE is not set
#
# Joysticks
# I2C Hardware Sensors Chip support
#
# CONFIG_INPUT_GAMEPORT is not set
# CONFIG_I2C_SENSOR is not set
#
# Input core support is needed for gameports
# Mice
#
# CONFIG_BUSMOUSE is not set
# CONFIG_QIC02_TAPE is not set
#
# Input core support is needed for joysticks
# IPMI
#
# CONFIG_QIC02_TAPE is not set
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_INTEL_RNG is not set
# CONFIG_NVRAM is not set
CONFIG_RTC=y
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
# CONFIG_SONYPI is not set
#
# Ftape, the floppy tape device driver
......@@ -419,213 +417,139 @@ CONFIG_RTC=y
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_HANGCHECK_TIMER is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_QUOTA is not set
CONFIG_AUTOFS_FS=y
# CONFIG_AUTOFS4_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_REISERFS_CHECK is not set
# CONFIG_REISERFS_PROC_INFO is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_FAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
CONFIG_DEVPTS_FS=y
CONFIG_DEVPTS_FS_XATTR=y
CONFIG_DEVPTS_FS_SECURITY=y
# CONFIG_TMPFS is not set
CONFIG_RAMFS=y
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_ADFS_FS_RW is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_CMS_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_JBD_DEBUG is not set
# CONFIG_FAT_FS is not set
# CONFIG_MSDOS_FS is not set
# CONFIG_UMSDOS_FS is not set
# CONFIG_VFAT_FS is not set
CONFIG_EFS_FS=y
# CONFIG_JFFS_FS is not set
# CONFIG_JFFS2_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_TMPFS is not set
# CONFIG_RAMFS is not set
# CONFIG_ISO9660_FS is not set
# CONFIG_JOLIET is not set
# CONFIG_MINIX_FS is not set
# CONFIG_FREEVXFS_FS is not set
# CONFIG_NTFS_FS is not set
# CONFIG_NTFS_DEBUG is not set
# CONFIG_NTFS_RW is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
# CONFIG_DEVFS_MOUNT is not set
# CONFIG_DEVFS_DEBUG is not set
CONFIG_DEVPTS_FS=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX4FS_RW is not set
# CONFIG_ROMFS_FS is not set
CONFIG_EXT2_FS=y
# CONFIG_SYSV_FS is not set
# CONFIG_UDF_FS is not set
# CONFIG_UDF_RW is not set
# CONFIG_UFS_FS is not set
# CONFIG_UFS_FS_WRITE is not set
#
# Network File Systems
#
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
CONFIG_NFS_V3=y
# CONFIG_NFS_V4 is not set
CONFIG_NFSD=y
CONFIG_NFSD_V3=y
# CONFIG_NFSD_V4 is not set
# CONFIG_NFSD_TCP is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFSD is not set
# CONFIG_NFSD_V3 is not set
CONFIG_SUNRPC=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_EXPORTFS=y
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_GSS is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_NCPFS_PACKET_SIGNING is not set
# CONFIG_NCPFS_IOCTL_LOCKING is not set
# CONFIG_NCPFS_STRONG is not set
# CONFIG_NCPFS_NFS_NS is not set
# CONFIG_NCPFS_OS2_NS is not set
# CONFIG_NCPFS_SMALLDOS is not set
# CONFIG_NCPFS_NLS is not set
# CONFIG_NCPFS_EXTRAS is not set
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_SMB_NLS is not set
# CONFIG_NLS is not set
#
# Sound
# Graphics support
#
# CONFIG_SOUND is not set
#
# USB support
#
# CONFIG_USB is not set
#
# USB Controllers
#
# CONFIG_USB_UHCI is not set
# CONFIG_USB_UHCI_ALT is not set
# CONFIG_USB_OHCI is not set
#
# USB Device Class drivers
#
# CONFIG_USB_AUDIO is not set
# CONFIG_USB_BLUETOOTH is not set
# CONFIG_USB_STORAGE is not set
# CONFIG_USB_STORAGE_DEBUG is not set
# CONFIG_USB_STORAGE_DATAFAB is not set
# CONFIG_USB_STORAGE_FREECOM is not set
# CONFIG_USB_STORAGE_JUMPSHOT is not set
# CONFIG_USB_STORAGE_DPCM is not set
# CONFIG_USB_STORAGE_SDDR09 is not set
# CONFIG_USB_ACM is not set
# CONFIG_USB_PRINTER is not set
#
# USB Human Interface Devices (HID)
#
#
# Input core support is needed for USB HID
#
#
# USB Imaging devices
#
# CONFIG_USB_DC2XX is not set
# CONFIG_USB_MDC800 is not set
# CONFIG_USB_SCANNER is not set
# CONFIG_USB_MICROTEK is not set
# CONFIG_USB_HPUSBSCSI is not set
#
# USB Multimedia devices
#
#
# Video4Linux support is needed for USB Multimedia device support
# Sound
#
# CONFIG_USB_DABUSB is not set
# CONFIG_SOUND is not set
#
# USB Network adaptors
# USB support
#
# CONFIG_USB_PLUSB is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_CATC is not set
# CONFIG_USB_CDCETHER is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB_GADGET is not set
#
# USB port drivers
# Bluetooth support
#
# CONFIG_USB_USS720 is not set
# CONFIG_BT is not set
#
# USB Serial Converter support
# Kernel hacking
#
# CONFIG_USB_SERIAL is not set
# CONFIG_USB_SERIAL_GENERIC is not set
# CONFIG_USB_SERIAL_BELKIN is not set
# CONFIG_USB_SERIAL_WHITEHEAT is not set
# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
# CONFIG_USB_SERIAL_EMPEG is not set
# CONFIG_USB_SERIAL_FTDI_SIO is not set
# CONFIG_USB_SERIAL_VISOR is not set
# CONFIG_USB_SERIAL_EDGEPORT is not set
# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
# CONFIG_USB_SERIAL_KEYSPAN is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
# CONFIG_USB_SERIAL_MCT_U232 is not set
# CONFIG_USB_SERIAL_PL2303 is not set
# CONFIG_USB_SERIAL_CYBERJACK is not set
# CONFIG_USB_SERIAL_OMNINET is not set
CONFIG_CROSSCOMPILE=y
# CONFIG_DEBUG_KERNEL is not set
#
# Miscellaneous USB drivers
# Security options
#
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_ID75 is not set
# CONFIG_SECURITY is not set
#
# Input core support
# Cryptographic options
#
# CONFIG_INPUT is not set
# CONFIG_INPUT_KEYBDEV is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_CRYPTO is not set
#
# Kernel hacking
# Library routines
#
CONFIG_CROSSCOMPILE=y
# CONFIG_REMOTE_DEBUG is not set
# CONFIG_GDB_CONSOLE is not set
# CONFIG_LL_DEBUG is not set
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_MIPS_UNCACHED is not set
# CONFIG_CRC32 is not set
arch/mips/defconfig-sead 0 → 100644
View file @ 5d3adbe2
#
# Automatically generated make config: don't edit
#
CONFIG_MIPS=y
CONFIG_MIPS32=y
# CONFIG_MIPS64 is not set
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
#
# General setup
#
CONFIG_SWAP=y
# CONFIG_SYSVIPC is not set
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_EMBEDDED is not set
CONFIG_FUTEX=y
CONFIG_EPOLL=y
#
# Loadable module support
#
# CONFIG_MODULES is not set
#
# Machine selection
#
# CONFIG_ACER_PICA_61 is not set
# CONFIG_BAGET_MIPS is not set
# CONFIG_CASIO_E55 is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_LASAT is not set
# CONFIG_HP_LASERJET is not set
# CONFIG_IBM_WORKPAD is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MIPS_ATLAS is not set
# CONFIG_MIPS_MAGNUM_4000 is not set
# CONFIG_MIPS_MALTA is not set
CONFIG_MIPS_SEAD=y
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_DDB5074 is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_NEC_OSPREY is not set
# CONFIG_NEC_EAGLE is not set
# CONFIG_OLIVETTI_M700 is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SOC_AU1X00 is not set
# CONFIG_SIBYTE_SB1xxx_SOC is not set
# CONFIG_SNI_RM200_PCI is not set
# CONFIG_TANBAC_TB0226 is not set
# CONFIG_TANBAC_TB0229 is not set
# CONFIG_TOSHIBA_JMR3927 is not set
# CONFIG_TOSHIBA_RBTX4927 is not set
# CONFIG_VICTOR_MPC30X is not set
# CONFIG_ZAO_CAPCELLA is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_NONCOHERENT_IO=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_MIPS_BOARDS_GEN=y
CONFIG_L1_CACHE_SHIFT=5
# CONFIG_FB is not set
#
# CPU selection
#
CONFIG_CPU_MIPS32=y
# CONFIG_CPU_MIPS64 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_CPU_HAS_PREFETCH=y
# CONFIG_VTAG_ICACHE is not set
# CONFIG_64BIT_PHYS_ADDR is not set
# CONFIG_CPU_ADVANCED is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_SYNC=y
# CONFIG_PREEMPT is not set
CONFIG_KALLSYMS=y
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
#
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
#
CONFIG_MMU=y
# CONFIG_HOTPLUG is not set
#
# Executable file formats
#
CONFIG_KCORE_ELF=y
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNP is not set
#
# Generic Driver Options
#
# CONFIG_FW_LOADER is not set
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=18432
CONFIG_BLK_DEV_INITRD=y
#
# MIPS initrd options
#
CONFIG_EMBEDDED_RAMDISK=y
CONFIG_EMBEDDED_RAMDISK_IMAGE="ramdisk.gz"
#
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_SCSI is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Fusion MPT device support
#
#
# I2O device support
#
#
# Networking support
#
# CONFIG_NET is not set
#
# Amateur Radio support
#
# CONFIG_HAMRADIO is not set
#
# ISDN subsystem
#
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input I/O drivers
#
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_EXTENDED is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_UNIX98_PTYS is not set
#
# I2C support
#
# CONFIG_I2C is not set
#
# I2C Hardware Sensors Mainboard support
#
#
# I2C Hardware Sensors Chip support
#
# CONFIG_I2C_SENSOR is not set
#
# Mice
#
# CONFIG_BUSMOUSE is not set
# CONFIG_QIC02_TAPE is not set
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_NVRAM is not set
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_HANGCHECK_TIMER is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# File systems
#
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_FAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
# CONFIG_TMPFS is not set
CONFIG_RAMFS=y
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Graphics support
#
#
# Sound
#
# CONFIG_SOUND is not set
#
# USB support
#
# CONFIG_USB_GADGET is not set
#
# Kernel hacking
#
CONFIG_CROSSCOMPILE=y
# CONFIG_DEBUG_KERNEL is not set
#
# Security options
#
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
# CONFIG_CRYPTO is not set
#
# Library routines
#
# CONFIG_CRC32 is not set
arch/mips/mips-boards/atlas/atlas_int.c
View file @ 5d3adbe2
......@@ -24,12 +24,12 @@
*
*/
#include <linux/config.h>
#include <linux/compiler.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/seq_file.h>
#include <asm/irq.h>
#include <asm/mips-boards/atlas.h>
......@@ -41,10 +41,6 @@ struct atlas_ictrl_regs *atlas_hw0_icregs
= (struct atlas_ictrl_regs *)ATLAS_ICTRL_REGS_BASE;
extern asmlinkage void mipsIRQ(void);
extern void do_IRQ(int irq, struct pt_regs *regs);
unsigned long spurious_count = 0;
irq_desc_t irq_desc[NR_IRQS];
#if 0
#define DEBUG_INT(x...) printk(x)
......@@ -52,11 +48,6 @@ irq_desc_t irq_desc[NR_IRQS];
#define DEBUG_INT(x...)
#endif
void inline disable_irq_nosync(unsigned int irq_nr)
{
disable_atlas_irq(irq_nr);
}
void disable_atlas_irq(unsigned int irq_nr)
{
atlas_hw0_icregs->intrsten = (1 << irq_nr);
......@@ -94,80 +85,6 @@ static struct hw_interrupt_type atlas_irq_type = {
NULL
};
int show_interrupts(struct seq_file *p, void *v)
{
int i;
int num = 0;
struct irqaction *action;
unsigned long flags;
for (i = 0; i < ATLASINT_END; i++, num++) {
spin_lock_irqsave(&irq_desc[i].lock, flags);
action = irq_desc[i].action;
if (!action)
goto skip;
seq_printf(p, "%2d: %8d %c %s",
num, kstat_cpu(0).irqs[num],
(action->flags & SA_INTERRUPT) ? '+' : ' ',
action->name);
for (action=action->next; action; action = action->next) {
seq_printf(p, ",%s %s",
(action->flags & SA_INTERRUPT) ? " +" : "",
action->name);
}
seq_printf(p, " [hw0]\n");
skip:
spin_unlock_irqrestore(&irq_desc[i].lock, flags);
}
return 0;
}
int request_irq(unsigned int irq,
void (*handler)(int, void *, struct pt_regs *),
unsigned long irqflags,
const char * devname,
void *dev_id)
{
struct irqaction *action;
DEBUG_INT("request_irq: irq=%d, devname = %s\n", irq, devname);
if (irq >= ATLASINT_END)
return -EINVAL;
if (!handler)
return -EINVAL;
action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
if(!action)
return -ENOMEM;
action->handler = handler;
action->flags = irqflags;
action->mask = 0;
action->name = devname;
action->dev_id = dev_id;
action->next = 0;
irq_desc[irq].action = action;
enable_atlas_irq(irq);
return 0;
}
void free_irq(unsigned int irq, void *dev_id)
{
struct irqaction *action;
if (irq >= ATLASINT_END) {
printk("Trying to free IRQ%d\n",irq);
return;
}
action = irq_desc[irq].action;
irq_desc[irq].action = NULL;
disable_atlas_irq(irq);
kfree(action);
}
static inline int ls1bit32(unsigned int x)
{
int b = 31, s;
......@@ -183,48 +100,23 @@ static inline int ls1bit32(unsigned int x)
void atlas_hw0_irqdispatch(struct pt_regs *regs)
{
struct irqaction *action;
unsigned long int_status;
int irq, cpu = smp_processor_id();
int irq;
int_status = atlas_hw0_icregs->intstatus;
/* if int_status == 0, then the interrupt has already been cleared */
if (int_status == 0)
if (unlikely(int_status == 0))
return;
irq = ls1bit32(int_status);
action = irq_desc[irq].action;
DEBUG_INT("atlas_hw0_irqdispatch: irq=%d\n", irq);
/* if action == NULL, then we don't have a handler for the irq */
if ( action == NULL ) {
printk("No handler for hw0 irq: %i\n", irq);
spurious_count++;
return;
}
irq_enter(cpu, irq);
kstat_cpu(0).irqs[irq]++;
action->handler(irq, action->dev_id, regs);
irq_exit(cpu, irq);
return;
}
unsigned long probe_irq_on (void)
{
return 0;
}
int probe_irq_off (unsigned long irqs)
{
return 0;
do_IRQ(irq, regs);
}
#ifdef CONFIG_REMOTE_DEBUG
#ifdef CONFIG_KGDB
extern void breakpoint(void);
extern int remote_debug;
#endif
......@@ -250,7 +142,7 @@ void __init init_IRQ(void)
spin_lock_init(&irq_desc[i].lock);
}
#ifdef CONFIG_REMOTE_DEBUG
#ifdef CONFIG_KGDB
if (remote_debug) {
set_debug_traps();
breakpoint();
......
arch/mips/mips-boards/atlas/atlas_setup.c
View file @ 5d3adbe2
......@@ -19,6 +19,7 @@
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/mc146818rtc.h>
#include <linux/ioport.h>
......@@ -28,15 +29,17 @@
#include <asm/irq.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/prom.h>
#include <asm/gt64120.h>
#include <asm/mips-boards/atlasint.h>
#include <asm/gt64120.h>
#include <asm/time.h>
#include <asm/traps.h>
#if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_PROM_CONSOLE)
extern void console_setup(char *, int *);
char serial_console[20];
#endif
#ifdef CONFIG_REMOTE_DEBUG
#ifdef CONFIG_KGDB
extern void rs_kgdb_hook(int);
extern void saa9730_kgdb_hook(void);
extern void breakpoint(void);
......@@ -47,9 +50,18 @@ extern struct rtc_ops atlas_rtc_ops;
extern void mips_reboot_setup(void);
const char *get_system_type(void)
{
return "MIPS Atlas";
}
extern void mips_time_init(void);
extern void mips_timer_setup(struct irqaction *irq);
extern unsigned long mips_rtc_get_time(void);
void __init atlas_setup(void)
{
#ifdef CONFIG_REMOTE_DEBUG
#ifdef CONFIG_KGDB
int rs_putDebugChar(char);
char rs_getDebugChar(void);
int saa9730_putDebugChar(char);
......@@ -75,7 +87,7 @@ void __init atlas_setup(void)
}
#endif
#ifdef CONFIG_REMOTE_DEBUG
#ifdef CONFIG_KGDB
argptr = prom_getcmdline();
if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
int line;
......@@ -107,9 +119,12 @@ void __init atlas_setup(void)
argptr = prom_getcmdline();
if ((argptr = strstr(argptr, "nofpu")) != NULL)
mips_cpu.options &= ~MIPS_CPU_FPU;
cpu_data[0].options &= ~MIPS_CPU_FPU;
rtc_ops = &atlas_rtc_ops;
board_time_init = mips_time_init;
board_timer_setup = mips_timer_setup;
rtc_get_time = mips_rtc_get_time;
mips_reboot_setup();
}
arch/mips/mips-boards/generic/Makefile
View file @ 5d3adbe2
......@@ -2,8 +2,6 @@
# Carsten Langgaard, carstenl@mips.com
# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
#
# ########################################################################
#
# This program is free software; you can distribute it and/or modify it
# under the terms of the GNU General Public License (Version 2) as
# published by the Free Software Foundation.
......@@ -17,13 +15,13 @@
# with this program; if not, write to the Free Software Foundation, Inc.,
# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
#
# #######################################################################
#
# Makefile for the MIPS boards generic routines under Linux.
#
EXTRA_AFLAGS := $(CFLAGS)
obj-y := mipsIRQ.o reset.o display.o init.o memory.o \
printf.o cmdline.o
obj-$(CONFIG_MIPS_ATLAS) += time.o
obj-$(CONFIG_MIPS_MALTA) += time.o
obj-$(CONFIG_KGDB) += gdb_hook.o
obj-y := mipsIRQ.o pci.o reset.o display.o init.o \
memory.o printf.o cmdline.o time.o
obj-$(CONFIG_REMOTE_DEBUG) += gdb_hook.o
EXTRA_AFLAGS := $(CFLAGS)
arch/mips/mips-boards/generic/cmdline.c
View file @ 5d3adbe2
......@@ -17,16 +17,21 @@
*
* Kernel command line creation using the prom monitor (YAMON) argc/argv.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/string.h>
#include <asm/bootinfo.h>
extern int prom_argc;
extern char **prom_argv;
extern int *_prom_argv;
char arcs_cmdline[COMMAND_LINE_SIZE];
/*
* YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
* This macro take care of sign extension.
*/
#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
char arcs_cmdline[CL_SIZE];
char * __init prom_getcmdline(void)
{
......@@ -43,8 +48,8 @@ void __init prom_init_cmdline(void)
cp = &(arcs_cmdline[0]);
while(actr < prom_argc) {
strcpy(cp, prom_argv[actr]);
cp += strlen(prom_argv[actr]);
strcpy(cp, prom_argv(actr));
cp += strlen(prom_argv(actr));
*cp++ = ' ';
actr++;
}
......
arch/mips/mips-boards/generic/display.c
View file @ 5d3adbe2
......@@ -39,9 +39,11 @@ void mips_display_message(const char *str)
}
}
#ifndef CONFIG_MIPS_SEAD
void mips_display_word(unsigned int num)
{
volatile unsigned int *display = (void *)ASCII_DISPLAY_WORD_BASE;
*display = num;
}
#endif
arch/mips/mips-boards/generic/gdb_hook.c
View file @ 5d3adbe2
......@@ -2,8 +2,6 @@
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
......@@ -17,12 +15,9 @@
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* This is the interface to the remote debugger stub.
*
*/
#include <linux/config.h>
#include <linux/serialP.h>
#include <linux/serial_reg.h>
......
arch/mips/mips-boards/generic/init.c
View file @ 5d3adbe2
......@@ -27,6 +27,8 @@
#include <asm/mips-boards/generic.h>
#include <asm/gt64120.h>
#include <asm/mips-boards/malta.h>
#include <asm/mips-boards/msc01_pci.h>
#include <asm/mips-boards/bonito64.h>
/* Environment variable */
typedef struct
......@@ -36,27 +38,37 @@ typedef struct
} t_env_var;
int prom_argc;
char **prom_argv, **prom_envp;
int *_prom_argv, *_prom_envp;
/*
* YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
* This macro take care of sign extension, if running in 64-bit mode.
*/
#define prom_envp(index) ((char *)(((int *)(int)_prom_envp)[(index)]))
int init_debug = 0;
unsigned int mips_revision_corid;
char *prom_getenv(char *envname)
{
/*
* Return a pointer to the given environment variable.
* In 64-bit mode: we're using 64-bit pointers, but all pointers
* in the PROM structures are only 32-bit, so we need some
* workarounds, if we are running in 64-bit mode.
*/
t_env_var *env = (t_env_var *)prom_envp;
int i;
int i, index=0;
i = strlen(envname);
while(env->name) {
if(strncmp(envname, env->name, i) == 0) {
return(env->val);
while(prom_envp(index)) {
if(strncmp(envname, prom_envp(index), i) == 0) {
return(prom_envp(index+1));
}
env++;
index += 2;
}
return(NULL);
}
......@@ -109,14 +121,22 @@ int get_ethernet_addr(char *ethernet_addr)
int __init prom_init(int argc, char **argv, char **envp)
{
prom_argc = argc;
prom_argv = argv;
prom_envp = envp;
_prom_argv = (int *)argv;
_prom_envp = (int *)envp;
mips_display_message("LINUX");
#ifdef CONFIG_MIPS_SEAD
set_io_port_base(KSEG1);
#else
mips_revision_corid = MIPS_REVISION_CORID;
switch(mips_revision_corid) {
case MIPS_REVISION_CORID_QED_RM5261:
case MIPS_REVISION_CORID_CORE_LV:
case MIPS_REVISION_CORID_CORE_FPGA:
/*
* Setup the North bridge to do Master byte-lane swapping when
* running in bigendian.
* Setup the North bridge to do Master byte-lane swapping
* when running in bigendian.
*/
#if defined(__MIPSEL__)
GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT |
......@@ -126,11 +146,59 @@ int __init prom_init(int argc, char **argv, char **envp)
#endif
#if defined(CONFIG_MIPS_MALTA)
mips_io_port_base = MALTA_PORT_BASE;
set_io_port_base(MALTA_GT_PORT_BASE);
#else
mips_io_port_base = KSEG1;
set_io_port_base(KSEG1);
#endif
break;
case MIPS_REVISION_CORID_BONITO64:
case MIPS_REVISION_CORID_CORE_20K:
/*
* Disable Bonito IOBC.
*/
BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
/*
* Setup the North bridge to do Master byte-lane swapping
* when running in bigendian.
*/
#if defined(__MIPSEL__)
BONITO_BONGENCFG = BONITO_BONGENCFG &
~(BONITO_BONGENCFG_MSTRBYTESWAP |
BONITO_BONGENCFG_BYTESWAP);
#else
BONITO_BONGENCFG = BONITO_BONGENCFG |
BONITO_BONGENCFG_MSTRBYTESWAP |
BONITO_BONGENCFG_BYTESWAP;
#endif
#if defined(CONFIG_MIPS_MALTA)
set_io_port_base(MALTA_BONITO_PORT_BASE);
#else
set_io_port_base(KSEG1);
#endif
break;
case MIPS_REVISION_CORID_CORE_MSC:
set_io_port_base(MALTA_MSC_PORT_BASE);
#if defined(__MIPSEL__)
MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP);
#else
MSC_WRITE(MSC01_PCI_SWAP,
MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF |
MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF |
MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF);
#endif
break;
default:
/* Unknown Core card */
mips_display_message("CC Error");
while(1); /* We die here... */
}
#endif
setup_prom_printf(0);
prom_printf("\nLINUX started...\n");
prom_init_cmdline();
prom_meminit();
......
arch/mips/mips-boards/generic/memory.c
View file @ 5d3adbe2
......@@ -2,8 +2,6 @@
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
......@@ -17,11 +15,8 @@
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* PROM library functions for acquiring/using memory descriptors given to
* us from the YAMON.
*
*/
#include <linux/config.h>
#include <linux/init.h>
......@@ -168,7 +163,7 @@ prom_free_prom_memory (void)
+ boot_mem_map.map[i].size) {
ClearPageReserved(virt_to_page(__va(addr)));
set_page_count(virt_to_page(__va(addr)), 1);
free_page(__va(addr));
free_page((unsigned long)__va(addr));
addr += PAGE_SIZE;
freed += PAGE_SIZE;
}
......
arch/mips/mips-boards/generic/mipsIRQ.S
View file @ 5d3adbe2
......@@ -56,6 +56,10 @@
* 6 Hardware (ignored)
* 7 R4k timer (what we use)
*
* Note: On the SEAD board thing are a little bit different.
* Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
* wired to UART1.
*
* We handle the IRQ according to _our_ priority which is:
*
* Highest ---- R4k Timer
......@@ -74,7 +78,9 @@
CLI
.set at
mfc0 s0, CP0_CAUSE # get irq mask
mfc0 s0, CP0_CAUSE # get irq bits
mfc0 s1, CP0_STATUS # get irq mask
and s0, s1
/* First we check for r4k counter/timer IRQ. */
andi a0, s0, CAUSEF_IP7
......@@ -90,14 +96,21 @@
nop
1:
#if defined(CONFIG_MIPS_SEAD)
beq a0, zero, 1f
nop
andi a0, s0, CAUSEF_IP3 # delay slot, check hw1 interrupt
#else
beq a0, zero, 1f # delay slot, check hw3 interrupt
andi a0, s0, CAUSEF_IP5
#endif
/* Wheee, combined hardware level zero interrupt. */
#if defined(CONFIG_MIPS_ATLAS)
jal atlas_hw0_irqdispatch
#elif defined(CONFIG_MIPS_MALTA)
jal malta_hw0_irqdispatch
#elif defined(CONFIG_MIPS_SEAD)
jal sead_hw0_irqdispatch
#else
#error "MIPS board not supported\n"
#endif
......@@ -107,6 +120,24 @@
nop # delay slot
1:
#if defined(CONFIG_MIPS_SEAD)
beq a0, zero, 1f
andi a0, s0, CAUSEF_IP5 # delay slot, check hw3 interrupt
jal sead_hw1_irqdispatch
move a0, sp # delay slot
j ret_from_irq
nop # delay slot
1:
#endif
#if defined(CONFIG_MIPS_MALTA)
beq a0, zero, 1f # check hw3 (coreHI) interrupt
nop
jal corehi_irqdispatch
move a0, sp
j ret_from_irq
nop
1:
#endif
/*
* Here by mistake? This is possible, what can happen is that by the
* time we take the exception the IRQ pin goes low, so just leave if
......
arch/mips/mips-boards/generic/pci.c deleted 100644 → 0
View file @ a85be436
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* MIPS boards specific PCI support.
*
*/
#include <linux/config.h>
#ifdef CONFIG_PCI
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/mips-boards/generic.h>
#include <asm/gt64120.h>
#ifdef CONFIG_MIPS_MALTA
#include <asm/mips-boards/malta.h>
#endif
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
static int
mips_pcibios_config_access(unsigned char access_type, struct pci_bus *bus_dev, unsigned int dev_fn, unsigned char where, u32 *data)
{
unsigned char bus = bus_dev->number;
u32 intr;
if ((bus == 0) && (dev_fn >= PCI_DEVFN(31,0)))
return -1; /* Because of a bug in the galileo (for slot 31). */
/* Clear cause register bits */
GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
GT_INTRCAUSE_TARABORT0_BIT));
/* Setup address */
GT_WRITE(GT_PCI0_CFGADDR_OFS,
(bus << GT_PCI0_CFGADDR_BUSNUM_SHF) |
(dev_fn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
GT_PCI0_CFGADDR_CONFIGEN_BIT);
if (access_type == PCI_ACCESS_WRITE) {
if (bus == 0 && dev_fn == 0) {
/*
* Galileo is acting differently than other devices.
*/
GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
} else {
GT_PCI_WRITE(GT_PCI0_CFGDATA_OFS, *data);
}
} else {
if (bus == 0 && dev_fn == 0) {
/*
* Galileo is acting differently than other devices.
*/
GT_READ(GT_PCI0_CFGDATA_OFS, *data);
} else {
GT_PCI_READ(GT_PCI0_CFGDATA_OFS, *data);
}
}
/* Check for master or target abort */
GT_READ(GT_INTRCAUSE_OFS, intr);
if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT))
{
/* Error occurred */
/* Clear bits */
GT_WRITE( GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
GT_INTRCAUSE_TARABORT0_BIT) );
return -1;
}
return 0;
}
/*
* We can't address 8 and 16 bit words directly. Instead we have to
* read/write a 32bit word and mask/modify the data we actually want.
*/
static int
mips_pcibios_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
{
u32 data = 0;
if((size == 2) && (where & 1))
return PCIBIOS_BAD_REGISTER_NUMBER;
else if ((size == 4) && (where & 3))
return PCIBIOS_BAD_REGISTER_NUMBER;
if (mips_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
return -1;
if(size == 1)
*val = (u8)(data >> ((where & 3) << 3)) & 0xff;
else if (size == 2)
*val = (u16)(data >> ((where & 3) << 3)) & 0xffff;
else if (size == 4)
*val = data;
return PCIBIOS_SUCCESSFUL;
}
static int
mips_pcibios_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
{
u32 data = 0;
if((size == 2) && (where & 1))
return PCIBIOS_BAD_REGISTER_NUMBER;
else if (size == 4) {
if(where & 3)
return PCIBIOS_BAD_REGISTER_NUMBER;
if(mips_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, &val))
return -1;
return PCIBIOS_SUCCESSFUL;
}
if (mips_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
return -1;
if(size == 1) {
data = (data & ~(0xff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
} else if (size == 2) {
data = (data & ~(0xffff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
}
return PCIBIOS_SUCCESSFUL;
}
struct pci_ops mips_pci_ops = {
.read = mips_pcibios_read,
.write = mips_pcibios_write,
};
void __init pcibios_init(void)
{
#ifdef CONFIG_MIPS_MALTA
struct pci_dev *pdev = NULL;
unsigned char reg_val;
#endif
printk("PCI: Probing PCI hardware on host bus 0.\n");
pci_scan_bus(0, &mips_pci_ops, NULL);
/*
* Due to a bug in the Galileo system controller, we need to setup
* the PCI BAR for the Galileo internal registers.
* This should be done in the bios/bootprom and will be fixed in
* a later revision of YAMON (the MIPS boards boot prom).
*/
GT_WRITE(GT_PCI0_CFGADDR_OFS,
(0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */
(0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 device */
(0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0 */
((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4 */
GT_PCI0_CFGADDR_CONFIGEN_BIT );
/* Perform the write */
GT_WRITE( GT_PCI0_CFGDATA_OFS, PHYSADDR(MIPS_GT_BASE));
#ifdef CONFIG_MIPS_MALTA
while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev)) != NULL) {
if ((pdev->vendor == PCI_VENDOR_ID_INTEL)
&& (pdev->device == PCI_DEVICE_ID_INTEL_82371AB)
&& (PCI_SLOT(pdev->devfn) == 0x0a)) {
/*
* IDE Decode enable.
*/
pci_read_config_byte(pdev, 0x41, &reg_val);
pci_write_config_byte(pdev, 0x41, reg_val | 0x80);
pci_read_config_byte(pdev, 0x43, &reg_val);
pci_write_config_byte(pdev, 0x43, reg_val | 0x80);
}
if ((pdev->vendor == PCI_VENDOR_ID_INTEL)
&& (pdev->device == PCI_DEVICE_ID_INTEL_82371AB_0)
&& (PCI_SLOT(pdev->devfn) == 0x0a)) {
/*
* Set top of main memory accessible by ISA or DMA
* devices to 16 Mb.
*/
pci_read_config_byte(pdev, 0x69, &reg_val);
pci_write_config_byte(pdev, 0x69, reg_val | 0xf0);
}
}
/*
* Activate Floppy Controller in the SMSC FDC37M817 Super I/O
* Controller.
* This should be done in the bios/bootprom and will be fixed in
* a later revision of YAMON (the MIPS boards boot prom).
*/
/* Entering config state. */
SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
/* Activate floppy controller. */
SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
/* Exit config state. */
SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
#endif
}
int __init
pcibios_enable_device(struct pci_dev *dev)
{
/* Not needed, since we enable all devices at startup. */
return 0;
}
void __init
pcibios_align_resource(void *data, struct resource *res,
unsigned long size, unsigned long align)
{
}
char * __init
pcibios_setup(char *str)
{
/* Nothing to do for now. */
return str;
}
struct pci_fixup pcibios_fixups[] = {
{ 0 }
};
#warning pcibios_update_resource() is now a generic implementation - please check
/*
* Called after each bus is probed, but before its children
* are examined.
*/
void __init pcibios_fixup_bus(struct pci_bus *b)
{
pci_read_bridge_bases(b);
}
unsigned __init int pcibios_assign_all_busses(void)
{
return 1;
}
#endif /* CONFIG_PCI */
arch/mips/mips-boards/generic/printf.c
View file @ 5d3adbe2
......@@ -2,8 +2,6 @@
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
......@@ -17,101 +15,84 @@
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Putting things on the screen/serial line using YAMONs facilities.
*
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/serialP.h>
#include <linux/serial_reg.h>
#include <asm/system.h>
#include <linux/spinlock.h>
#include <asm/io.h>
#include <asm/serial.h>
#ifdef CONFIG_MIPS_ATLAS
#include <asm/mips-boards/atlas.h>
/*
* Atlas registers are memory mapped on 64-bit aligned boundaries and
* only word access are allowed.
* When reading the UART 8 bit registers only the LSB are valid.
*/
unsigned int atlas_serial_in(struct async_struct *info, int offset)
static inline unsigned int serial_in(int offset)
{
return (*(volatile unsigned int *)(info->port + mips_io_port_base + offset*8) & 0xff);
return (*(volatile unsigned int *)(mips_io_port_base + ATLAS_UART_REGS_BASE + offset*8) & 0xff);
}
void atlas_serial_out(struct async_struct *info, int offset, int value)
static inline void serial_out(int offset, int value)
{
*(volatile unsigned int *)(info->port + mips_io_port_base + offset*8) = value;
*(volatile unsigned int *)(mips_io_port_base + ATLAS_UART_REGS_BASE + offset*8) = value;
}
#define serial_in atlas_serial_in
#define serial_out atlas_serial_out
#elif defined(CONFIG_MIPS_SEAD)
#else
#include <asm/mips-boards/sead.h>
static unsigned int serial_in(struct async_struct *info, int offset)
/*
* SEAD registers are just like Atlas registers.
*/
static inline unsigned int serial_in(int offset)
{
return inb(info->port + offset);
return (*(volatile unsigned int *)(mips_io_port_base + SEAD_UART0_REGS_BASE + offset*8) & 0xff);
}
static void serial_out(struct async_struct *info, int offset,
int value)
static inline void serial_out(int offset, int value)
{
outb(value, info->port + offset);
*(volatile unsigned int *)(mips_io_port_base + SEAD_UART0_REGS_BASE + offset*8) = value;
}
#endif
static struct serial_state rs_table[] = {
SERIAL_PORT_DFNS /* Defined in serial.h */
};
/*
* Hooks to fake "prom" console I/O before devices
* are fully initialized.
*/
static struct async_struct prom_port_info = {0};
void __init setup_prom_printf(int tty_no) {
struct serial_state *ser = &rs_table[tty_no];
#else
prom_port_info.state = ser;
prom_port_info.magic = SERIAL_MAGIC;
prom_port_info.port = ser->port;
prom_port_info.flags = ser->flags;
static inline unsigned int serial_in(int offset)
{
return inb(0x3f8 + offset);
}
/* No setup of UART - assume YAMON left in sane state */
static inline void serial_out(int offset, int value)
{
outb(value, 0x3f8 + offset);
}
#endif
int putPromChar(char c)
{
if (!prom_port_info.state) { /* need to init device first */
return 0;
}
while ((serial_in(&prom_port_info, UART_LSR) & UART_LSR_THRE) == 0)
while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0)
;
serial_out(&prom_port_info, UART_TX, c);
serial_out(UART_TX, c);
return 1;
}
char getPromChar(void)
{
if (!prom_port_info.state) { /* need to init device first */
return 0;
}
while (!(serial_in(&prom_port_info, UART_LSR) & 1))
while (!(serial_in(UART_LSR) & 1))
;
return(serial_in(&prom_port_info, UART_RX));
return serial_in(UART_RX);
}
static spinlock_t con_lock = SPIN_LOCK_UNLOCKED;
static char buf[1024];
void __init prom_printf(char *fmt, ...)
......@@ -123,8 +104,7 @@ void __init prom_printf(char *fmt, ...)
int putPromChar(char);
/* Low level, brute force, not SMP safe... */
save_and_cli(flags);
spin_lock_irqsave(con_lock, flags);
va_start(args, fmt);
l = vsprintf(buf, fmt, args); /* hopefully i < sizeof(buf) */
va_end(args);
......@@ -133,8 +113,9 @@ void __init prom_printf(char *fmt, ...)
for (p = buf; p < buf_end; p++) {
/* Crude cr/nl handling is better than none */
if(*p == '\n')putPromChar('\r');
if (*p == '\n')
putPromChar('\r');
putPromChar(*p);
}
restore_flags(flags);
spin_unlock_irqrestore(con_lock, flags);
}
arch/mips/mips-boards/generic/time.c
View file @ 5d3adbe2
......@@ -23,29 +23,29 @@
*
*/
#include <linux/types.h>
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/timex.h>
#include <linux/mc146818rtc.h>
#include <asm/mipsregs.h>
#include <asm/ptrace.h>
#include <asm/hardirq.h>
#include <asm/div64.h>
#include <linux/mc146818rtc.h>
#include <linux/time.h>
#include <linux/timex.h>
#include <asm/cpu.h>
#include <asm/time.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/prom.h>
extern volatile unsigned long wall_jiffies;
static long last_rtc_update = 0;
unsigned long missed_heart_beats = 0;
static unsigned long r4k_offset; /* Amount to increment compare reg each time */
static unsigned long r4k_cur; /* What counter should be at next timer irq */
static unsigned int r4k_offset; /* Amount to increment compare reg each time */
static unsigned int r4k_cur; /* What counter should be at next timer irq */
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
......@@ -58,130 +58,26 @@ static char display_string[] = " LINUX ON MALTA ";
static unsigned int display_count = 0;
#define MAX_DISPLAY_COUNT (sizeof(display_string) - 8)
#define MIPS_CPU_TIMER_IRQ 7
static unsigned int timer_tick_count=0;
static inline void ack_r4ktimer(unsigned long newval)
static inline void ack_r4ktimer(unsigned int newval)
{
write_32bit_cp0_register(CP0_COMPARE, newval);
write_c0_compare(newval);
}
/*
* In order to set the CMOS clock precisely, set_rtc_mmss has to be
* called 500 ms after the second nowtime has started, because when
* nowtime is written into the registers of the CMOS clock, it will
* jump to the next second precisely 500 ms later. Check the Motorola
* MC146818A or Dallas DS12887 data sheet for details.
*
* BUG: This routine does not handle hour overflow properly; it just
* sets the minutes. Usually you won't notice until after reboot!
*/
static int set_rtc_mmss(unsigned long nowtime)
{
int retval = 0;
int real_seconds, real_minutes, cmos_minutes;
unsigned char save_control, save_freq_select;
save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */
CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */
CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
cmos_minutes = CMOS_READ(RTC_MINUTES);
/*
* since we're only adjusting minutes and seconds,
* don't interfere with hour overflow. This avoids
* messing with unknown time zones but requires your
* RTC not to be off by more than 15 minutes
*/
real_seconds = nowtime % 60;
real_minutes = nowtime / 60;
if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
real_minutes += 30; /* correct for half hour time zone */
real_minutes %= 60;
if (abs(real_minutes - cmos_minutes) < 30) {
CMOS_WRITE(real_seconds,RTC_SECONDS);
CMOS_WRITE(real_minutes,RTC_MINUTES);
} else {
printk(KERN_WARNING
"set_rtc_mmss: can't update from %d to %d\n",
cmos_minutes, real_minutes);
retval = -1;
}
/* The following flags have to be released exactly in this order,
* otherwise the DS12887 (popular MC146818A clone with integrated
* battery and quartz) will not reset the oscillator and will not
* update precisely 500 ms later. You won't find this mentioned in
* the Dallas Semiconductor data sheets, but who believes data
* sheets anyway ... -- Markus Kuhn
*/
CMOS_WRITE(save_control, RTC_CONTROL);
CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
return retval;
}
/*
* There are a lot of conceptually broken versions of the MIPS timer interrupt
* handler floating around. This one is rather different, but the algorithm
* is provably more robust.
*/
void mips_timer_interrupt(struct pt_regs *regs)
{
unsigned long flags;
int irq = 7;
unsigned long seq;
if (r4k_offset == 0)
goto null;
do {
kstat_cpu(0).irqs[irq]++;
do_timer(regs);
/* Historical comment/code:
* RTC time of day s updated approx. every 11
* minutes. Because of how the numbers work out
* we need to make absolutely sure we do this update
* within 500ms before the * next second starts,
* thus the following code.
*/
do {
seq = read_seqbegin_irqsave(&xtime_lock, flags);
if ((time_status & STA_UNSYNC) == 0
&& xtime.tv_sec > last_rtc_update + 660
&& xtime.tv_usec >= 500000 - (tick >> 1)
&& xtime.tv_usec <= 500000 + (tick >> 1))
if (set_rtc_mmss(xtime.tv_sec) == 0)
last_rtc_update = xtime.tv_sec;
else
/* do it again in 60 s */
last_rtc_update = xtime.tv_sec - 600;
} while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
if ((timer_tick_count++ % HZ) == 0) {
mips_display_message(&display_string[display_count++]);
if (display_count == MAX_DISPLAY_COUNT)
display_count = 0;
}
r4k_cur += r4k_offset;
ack_r4ktimer(r4k_cur);
} while (((unsigned long)read_32bit_cp0_register(CP0_COUNT)
- r4k_cur) < 0x7fffffff);
return;
}
null:
ack_r4ktimer(0);
ll_timer_interrupt(MIPS_CPU_TIMER_IRQ, regs);
}
/*
......@@ -189,9 +85,8 @@ void mips_timer_interrupt(struct pt_regs *regs)
* register for each time tick.
* Use the RTC to calculate offset.
*/
static unsigned long __init cal_r4koff(void)
static unsigned int __init cal_r4koff(void)
{
unsigned long count;
unsigned int flags;
local_irq_save(flags);
......@@ -201,21 +96,21 @@ static unsigned long __init cal_r4koff(void)
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
/* Start r4k counter. */
write_32bit_cp0_register(CP0_COUNT, 0);
write_c0_count(0);
/* Read counter exactly on falling edge of update flag */
while (CMOS_READ(RTC_REG_A) & RTC_UIP);
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
count = read_32bit_cp0_register(CP0_COUNT);
mips_counter_frequency = read_c0_count();
/* restore interrupts */
local_irq_restore(flags);
return (count / HZ);
return (mips_counter_frequency / HZ);
}
static unsigned long __init get_mips_time(void)
unsigned long __init mips_rtc_get_time(void)
{
unsigned int year, mon, day, hour, min, sec;
unsigned char save_control;
......@@ -250,170 +145,41 @@ static unsigned long __init get_mips_time(void)
return mktime(year, mon, day, hour, min, sec);
}
void __init time_init(void)
void __init mips_time_init(void)
{
unsigned int est_freq, flags;
local_irq_save(flags);
/* Set Data mode - binary. */
CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
printk("calculating r4koff... ");
r4k_offset = cal_r4koff();
printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
printk("%08x(%d)\n", r4k_offset, r4k_offset);
if ((read_c0_prid() & 0xffff00) ==
(PRID_COMP_MIPS | PRID_IMP_20KC))
est_freq = r4k_offset*HZ;
else
est_freq = 2*r4k_offset*HZ;
est_freq += 5000; /* round */
est_freq -= est_freq%10000;
printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
(est_freq%1000000)*100/1000000);
r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset);
write_32bit_cp0_register(CP0_COMPARE, r4k_cur);
change_cp0_status(ST0_IM, ALLINTS);
/* Read time from the RTC chipset. */
write_seqlock_irqsave (&xtime_lock, flags);
xtime.tv_sec = get_mips_time();
xtime.tv_usec = 0;
write_sequnlock_irqrestore(&xtime_lock, flags);
}
/* This is for machines which generate the exact clock. */
#define USECS_PER_JIFFY (1000000/HZ)
#define USECS_PER_JIFFY_FRAC ((1000000 << 32) / HZ & 0xffffffff)
/* Cycle counter value at the previous timer interrupt.. */
static unsigned int timerhi = 0, timerlo = 0;
/*
* FIXME: Does playing with the RP bit in c0_status interfere with this code?
*/
static unsigned long do_fast_gettimeoffset(void)
{
u32 count;
unsigned long res, tmp;
/* Last jiffy when do_fast_gettimeoffset() was called. */
static unsigned long last_jiffies=0;
unsigned long quotient;
/*
* Cached "1/(clocks per usec)*2^32" value.
* It has to be recalculated once each jiffy.
*/
static unsigned long cached_quotient=0;
tmp = jiffies;
quotient = cached_quotient;
if (tmp && last_jiffies != tmp) {
last_jiffies = tmp;
#ifdef CONFIG_CPU_MIPS32
if (last_jiffies != 0) {
unsigned long r0;
do_div64_32(r0, timerhi, timerlo, tmp);
do_div64_32(quotient, USECS_PER_JIFFY,
USECS_PER_JIFFY_FRAC, r0);
cached_quotient = quotient;
}
#else
__asm__(".set\tnoreorder\n\t"
".set\tnoat\n\t"
".set\tmips3\n\t"
"lwu\t%0,%2\n\t"
"dsll32\t$1,%1,0\n\t"
"or\t$1,$1,%0\n\t"
"ddivu\t$0,$1,%3\n\t"
"mflo\t$1\n\t"
"dsll32\t%0,%4,0\n\t"
"nop\n\t"
"ddivu\t$0,%0,$1\n\t"
"mflo\t%0\n\t"
".set\tmips0\n\t"
".set\tat\n\t"
".set\treorder"
:"=&r" (quotient)
:"r" (timerhi),
"m" (timerlo),
"r" (tmp),
"r" (USECS_PER_JIFFY)
:"$1");
cached_quotient = quotient;
#endif
}
/* Get last timer tick in absolute kernel time */
count = read_32bit_cp0_register(CP0_COUNT);
/* .. relative to previous jiffy (32 bits is enough) */
count -= timerlo;
__asm__("multu\t%1,%2\n\t"
"mfhi\t%0"
:"=r" (res)
:"r" (count),
"r" (quotient));
/*
* Due to possible jiffies inconsistencies, we need to check
* the result so that we'll get a timer that is monotonic.
*/
if (res >= USECS_PER_JIFFY)
res = USECS_PER_JIFFY-1;
return res;
}
void do_gettimeofday(struct timeval *tv)
{
unsigned long flags;
unsigned long seq;
do {
seq = read_seqbegin_irqsave(&xtime_lock, flags);
*tv = xtime;
tv->tv_usec += do_fast_gettimeoffset();
/*
* xtime is atomically updated in timer_bh.
* jiffies - wall_jiffies
* is nonzero if the timer bottom half hasnt executed yet.
*/
if (jiffies - wall_jiffies)
tv->tv_usec += USECS_PER_JIFFY;
} while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
if (tv->tv_usec >= 1000000) {
tv->tv_usec -= 1000000;
tv->tv_sec++;
}
local_irq_restore(flags);
}
void do_settimeofday(struct timeval *tv)
void __init mips_timer_setup(struct irqaction *irq)
{
write_seqlock_irq (&xtime_lock);
/* This is revolting. We need to set the xtime.tv_usec correctly.
* However, the value in this location is is value at the last tick.
* Discover what correction gettimeofday would have done, and then
* undo it!
*/
tv->tv_usec -= do_fast_gettimeoffset();
if (tv->tv_usec < 0) {
tv->tv_usec += 1000000;
tv->tv_sec--;
}
xtime = *tv;
time_adjust = 0; /* stop active adjtime() */
time_status |= STA_UNSYNC;
time_maxerror = NTP_PHASE_LIMIT;
time_esterror = NTP_PHASE_LIMIT;
write_sequnlock_irq (&xtime_lock);
/* we are using the cpu counter for timer interrupts */
irq->handler = no_action; /* we use our own handler */
setup_irq(MIPS_CPU_TIMER_IRQ, irq);
/* to generate the first timer interrupt */
r4k_cur = (read_c0_count() + r4k_offset);
write_c0_compare(r4k_cur);
set_c0_status(ALLINTS);
}
arch/mips/mips-boards/malta/malta_int.c
View file @ 5d3adbe2
......@@ -23,58 +23,130 @@
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/random.h>
#include <asm/irq.h>
#include <asm/i8259.h>
#include <asm/io.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/malta.h>
#include <asm/mips-boards/maltaint.h>
#include <asm/mips-boards/piix4.h>
#include <asm/mips-boards/msc01_pci.h>
#include <asm/gt64120.h>
#include <asm/mips-boards/generic.h>
extern asmlinkage void mipsIRQ(void);
extern int mips_pcibios_iack(void);
void malta_hw0_irqdispatch(struct pt_regs *regs)
#ifdef CONFIG_KGDB
extern void breakpoint(void);
extern void set_debug_traps(void);
extern int remote_debug;
#endif
static spinlock_t mips_irq_lock = SPIN_LOCK_UNLOCKED;
static inline int get_int(int *irq)
{
int irq;
unsigned long flags;
/*
* Determine highest priority pending interrupt by performing a PCI
* Interrupt Acknowledge cycle.
*/
GT_READ(GT_PCI0_IACK_OFS, irq);
irq &= 0xFF;
spin_lock_irqsave(&mips_irq_lock, flags);
*irq = mips_pcibios_iack();
/*
* IRQ7 is used to detect spurious interrupts. The interrupt
* acknowledge cycle returns IRQ7, if no interrupts is requested. We
* can differentiate between this situation and a "normal" IRQ7 by
* reading the ISR.
* IRQ7 is used to detect spurious interrupts.
* The interrupt acknowledge cycle returns IRQ7, if no
* interrupts is requested.
* We can differentiate between this situation and a
* "Normal" IRQ7 by reading the ISR.
*/
if (irq == 7) {
outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR, PIIX4_ICTLR1_OCW3);
if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7)))
return; /* Spurious interrupt. */
if (*irq == 7)
{
outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR,
PIIX4_ICTLR1_OCW3);
if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7))) {
spin_unlock_irqrestore(&mips_irq_lock, flags);
printk("We got a spurious interrupt from PIIX4.\n");
atomic_inc(&irq_err_count);
return -1; /* Spurious interrupt. */
}
}
spin_unlock_irqrestore(&mips_irq_lock, flags);
return 0;
}
void malta_hw0_irqdispatch(struct pt_regs *regs)
{
int irq;
if (get_int(&irq))
return; /* interrupt has already been cleared */
do_IRQ(irq, regs);
}
void corehi_irqdispatch(struct pt_regs *regs)
{
unsigned int data,datahi;
/* Mask out corehi interrupt. */
clear_c0_status(IE_IRQ3);
printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
, regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);
switch(mips_revision_corid) {
case MIPS_REVISION_CORID_CORE_MSC:
break;
case MIPS_REVISION_CORID_QED_RM5261:
case MIPS_REVISION_CORID_CORE_LV:
case MIPS_REVISION_CORID_CORE_FPGA:
GT_READ(GT_INTRCAUSE_OFS, data);
printk("GT_INTRCAUSE = %08x\n", data);
GT_READ(0x70, data);
GT_READ(0x78, datahi);
printk("GT_CPU_ERR_ADDR = %0x2%08x\n", datahi,data);
break;
case MIPS_REVISION_CORID_BONITO64:
case MIPS_REVISION_CORID_CORE_20K:
data = BONITO_INTISR;
printk("BONITO_INTISR = %08x\n", data);
data = BONITO_INTEN;
printk("BONITO_INTEN = %08x\n", data);
data = BONITO_INTPOL;
printk("BONITO_INTPOL = %08x\n", data);
data = BONITO_INTEDGE;
printk("BONITO_INTEDGE = %08x\n", data);
data = BONITO_INTSTEER;
printk("BONITO_INTSTEER = %08x\n", data);
data = BONITO_PCICMD;
printk("BONITO_PCICMD = %08x\n", data);
break;
}
/* We die here*/
die("CoreHi interrupt", regs);
}
void __init init_IRQ(void)
{
set_except_vector(0, mipsIRQ);
init_generic_irq();
init_i8259_irqs();
#ifdef CONFIG_REMOTE_DEBUG
#ifdef CONFIG_KGDB
if (remote_debug) {
set_debug_traps();
breakpoint();
}
#endif
}
arch/mips/mips-boards/malta/malta_setup.c
View file @ 5d3adbe2
......@@ -36,17 +36,20 @@
#include <asm/floppy.h>
#endif
#include <asm/dma.h>
#include <asm/time.h>
#include <asm/traps.h>
#ifdef CONFIG_VT
#include <linux/console.h>
#endif
#if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_PROM_CONSOLE)
extern void console_setup(char *, int *);
char serial_console[20];
#endif
#ifdef CONFIG_REMOTE_DEBUG
extern void set_debug_traps(void);
#ifdef CONFIG_KGDB
extern void rs_kgdb_hook(int);
extern void breakpoint(void);
static int remote_debug = 0;
int remote_debug = 0;
#endif
extern struct ide_ops std_ide_ops;
......@@ -56,6 +59,10 @@ extern struct kbd_ops std_kbd_ops;
extern void mips_reboot_setup(void);
extern void mips_time_init(void);
extern void mips_timer_setup(struct irqaction *irq);
extern unsigned long mips_rtc_get_time(void);
struct resource standard_io_resources[] = {
{ "dma1", 0x00, 0x1f, IORESOURCE_BUSY },
{ "timer", 0x40, 0x5f, IORESOURCE_BUSY },
......@@ -65,9 +72,14 @@ struct resource standard_io_resources[] = {
#define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct resource))
const char *get_system_type(void)
{
return "MIPS Malta";
}
void __init malta_setup(void)
{
#ifdef CONFIG_REMOTE_DEBUG
#ifdef CONFIG_KGDB
int rs_putDebugChar(char);
char rs_getDebugChar(void);
extern int (*generic_putDebugChar)(char);
......@@ -93,7 +105,7 @@ void __init malta_setup(void)
}
#endif
#ifdef CONFIG_REMOTE_DEBUG
#ifdef CONFIG_KGDB
argptr = prom_getcmdline();
if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
int line;
......@@ -119,17 +131,38 @@ void __init malta_setup(void)
argptr = prom_getcmdline();
if ((argptr = strstr(argptr, "nofpu")) != NULL)
mips_cpu.options &= ~MIPS_CPU_FPU;
cpu_data[0].options &= ~MIPS_CPU_FPU;
rtc_ops = &malta_rtc_ops;
#ifdef CONFIG_BLK_DEV_IDE
ide_ops = &std_ide_ops;
#endif
#ifdef CONFIG_BLK_DEV_FD
fd_ops = &std_fd_ops;
#endif
#ifdef CONFIG_PC_KEYB
kbd_ops = &std_kbd_ops;
#ifdef CONFIG_VT
#if defined(CONFIG_VGA_CONSOLE)
conswitchp = &vga_con;
screen_info = (struct screen_info) {
0, 25, /* orig-x, orig-y */
0, /* unused */
0, /* orig-video-page */
0, /* orig-video-mode */
80, /* orig-video-cols */
0,0,0, /* ega_ax, ega_bx, ega_cx */
25, /* orig-video-lines */
1, /* orig-video-isVGA */
16 /* orig-video-points */
};
#elif defined(CONFIG_DUMMY_CONSOLE)
conswitchp = &dummy_con;
#endif
#endif
mips_reboot_setup();
board_time_init = mips_time_init;
board_timer_setup = mips_timer_setup;
rtc_get_time = mips_rtc_get_time;
}
arch/mips64/mips-boards/malta/Makefile → arch/mips/mips-boards/sead/Makefile
View file @ 5d3adbe2
#
# Carsten Langgaard, carstenl@mips.com
# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
# Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
#
# ########################################################################
#
......@@ -19,8 +19,8 @@
#
# #######################################################################
#
# Makefile for the MIPS Malta specific kernel interface routines
# Makefile for the MIPS SEAD specific kernel interface routines
# under Linux.
#
obj-y := malta_int.o malta_rtc.o malta_setup.o
obj-y := sead_int.o sead_setup.o sead_time.o
arch/mips64/mips-boards/generic/cmdline.c → arch/mips/mips-boards/sead/sead_int.c
View file @ 5d3adbe2
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
......@@ -19,53 +19,97 @@
*
* ########################################################################
*
* Kernel command line creation using the prom monitor (YAMON) argc/argv.
* Routines for generic manipulation of the interrupts found on the MIPS
* Sead board.
*
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/irq.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <asm/bootinfo.h>
#include <asm/mips-boards/sead.h>
#include <asm/mips-boards/seadint.h>
/*#define DEBUG_CMDLINE*/
extern asmlinkage void mipsIRQ(void);
extern int prom_argc;
extern int *_prom_argv;
void disable_sead_irq(unsigned int irq_nr)
{
if (irq_nr == SEADINT_UART0)
clear_c0_status(0x00000400);
else
if (irq_nr == SEADINT_UART1)
clear_c0_status(0x00000800);
}
/*
* A 32-bit PROM pass arguments and environment as 32-bit pointer.
* This macro take care of sign extension.
*/
#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
void enable_sead_irq(unsigned int irq_nr)
{
if (irq_nr == SEADINT_UART0)
set_c0_status(0x00000400);
else
if (irq_nr == SEADINT_UART1)
set_c0_status(0x00000800);
}
static unsigned int startup_sead_irq(unsigned int irq)
{
enable_sead_irq(irq);
return 0; /* never anything pending */
}
#define shutdown_sead_irq disable_sead_irq
char arcs_cmdline[CL_SIZE];
#define mask_and_ack_sead_irq disable_sead_irq
char * __init prom_getcmdline(void)
static void end_sead_irq(unsigned int irq)
{
return &(arcs_cmdline[0]);
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_sead_irq(irq);
}
static struct hw_interrupt_type sead_irq_type = {
"SEAD",
startup_sead_irq,
shutdown_sead_irq,
enable_sead_irq,
disable_sead_irq,
mask_and_ack_sead_irq,
end_sead_irq,
NULL
};
void __init prom_init_cmdline(void)
void sead_hw0_irqdispatch(struct pt_regs *regs)
{
char *cp;
int actr;
do_IRQ(0, regs);
}
actr = 1; /* Always ignore argv[0] */
void sead_hw1_irqdispatch(struct pt_regs *regs)
{
do_IRQ(1, regs);
}
cp = &(arcs_cmdline[0]);
while(actr < prom_argc) {
strcpy(cp, prom_argv(actr));
cp += strlen(prom_argv(actr));
*cp++ = ' ';
actr++;
}
if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
--cp;
*cp = '\0';
void __init init_IRQ(void)
{
int i;
#ifdef DEBUG_CMDLINE
prom_printf("prom_init_cmdline: %s\n", &(arcs_cmdline[0]));
#endif
/*
* Mask out all interrupt
*/
clear_c0_status(0x0000ff00);
/* Now safe to set the exception vector. */
set_except_vector(0, mipsIRQ);
init_generic_irq();
for (i = 0; i <= SEADINT_END; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
irq_desc[i].lock = SPIN_LOCK_UNLOCKED;
irq_desc[i].handler = &sead_irq_type;
}
}
arch/mips64/mips-boards/atlas/atlas_setup.c → arch/mips/mips-boards/sead/sead_setup.c
View file @ 5d3adbe2
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
......@@ -17,10 +15,7 @@
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Atlas specific setup, including init of the feature struct.
*
* SEAD specific setup.
*/
#include <linux/config.h>
#include <linux/init.h>
......@@ -33,41 +28,26 @@
#include <asm/irq.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/prom.h>
#include <asm/mips-boards/gt64120.h>
#include <asm/mips-boards/atlasint.h>
#include <asm/mmu_context.h>
#include <asm/mips-boards/seadint.h>
#include <asm/time.h>
#if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_PROM_CONSOLE)
extern void console_setup(char *, int *);
char serial_console[20];
#endif
#ifdef CONFIG_REMOTE_DEBUG
extern void rs_kgdb_hook(int);
extern void saa9730_kgdb_hook(void);
extern void breakpoint(void);
int remote_debug = 0;
#endif
extern struct rtc_ops atlas_rtc_ops;
extern void mips_reboot_setup(void);
extern void mips_time_init(void);
extern void mips_timer_setup(struct irqaction *irq);
void __init atlas_setup(void)
const char *get_system_type(void)
{
#ifdef CONFIG_REMOTE_DEBUG
int rs_putDebugChar(char);
char rs_getDebugChar(void);
int saa9730_putDebugChar(char);
char saa9730_getDebugChar(void);
extern int (*putDebugChar)(char);
extern char (*getDebugChar)(void);
#endif
char *argptr;
return "MIPS SEAD";
}
current_cpu_data.asid_cache = ASID_FIRST_VERSION;
TLBMISS_HANDLER_SETUP();
void __init sead_setup(void)
{
char *argptr;
ioport_resource.end = 0x7fffffff;
......@@ -85,39 +65,13 @@ void __init atlas_setup(void)
}
#endif
#ifdef CONFIG_REMOTE_DEBUG
argptr = prom_getcmdline();
if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
int line;
argptr += strlen("kgdb=ttyS");
if (*argptr != '0' && *argptr != '1')
printk("KGDB: Uknown serial line /dev/ttyS%c, "
"falling back to /dev/ttyS1\n", *argptr);
line = *argptr == '0' ? 0 : 1;
printk("KGDB: Using serial line /dev/ttyS%d for session\n",
line ? 1 : 0);
if(line == 0) {
rs_kgdb_hook(line);
putDebugChar = rs_putDebugChar;
getDebugChar = rs_getDebugChar;
} else {
saa9730_kgdb_hook();
putDebugChar = saa9730_putDebugChar;
getDebugChar = saa9730_getDebugChar;
}
prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
"please connect your debugger\n", line ? 1 : 0);
remote_debug = 1;
/* Breakpoints and stuff are in atlas_irq_setup() */
}
#endif
argptr = prom_getcmdline();
if ((argptr = strstr(argptr, "nofpu")) != NULL)
mips_cpu.options &= ~MIPS_CPU_FPU;
cpu_data[0].options &= ~MIPS_CPU_FPU;
board_time_init = mips_time_init;
board_timer_setup = mips_timer_setup;
rtc_ops = &atlas_rtc_ops;
mips_reboot_setup();
}
arch/mips/mips-boards/sead/sead_time.c 0 → 100644
View file @ 5d3adbe2
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* Setting up the clock on the MIPS boards.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <asm/mipsregs.h>
#include <asm/ptrace.h>
#include <asm/hardirq.h>
#include <asm/cpu.h>
#include <linux/interrupt.h>
#include <linux/timex.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/prom.h>
extern volatile unsigned long wall_jiffies;
static unsigned long r4k_offset; /* Amount to increment compare reg each time */
static unsigned long r4k_cur; /* What counter should be at next timer irq */
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ5)
static char display_string[] = " LINUX ON SEAD ";
static unsigned int display_count = 0;
#define MAX_DISPLAY_COUNT (sizeof(display_string) - 8)
#define MIPS_CPU_TIMER_IRQ 7
static unsigned int timer_tick_count=0;
static inline void ack_r4ktimer(unsigned long newval)
{
write_c0_compare(newval);
}
/*
* There are a lot of conceptually broken versions of the MIPS timer interrupt
* handler floating around. This one is rather different, but the algorithm
* is provably more robust.
*/
void mips_timer_interrupt(struct pt_regs *regs)
{
int cpu = smp_processor_id();
int irq = MIPS_CPU_TIMER_IRQ;
irq_enter();
do {
kstat_cpu(cpu).irqs[irq]++;
do_timer(regs);
if ((timer_tick_count++ % HZ) == 0) {
mips_display_message(&display_string[display_count++]);
if (display_count == MAX_DISPLAY_COUNT)
display_count = 0;
}
r4k_cur += r4k_offset;
ack_r4ktimer(r4k_cur);
} while (((unsigned long)read_c0_count()
- r4k_cur) < 0x7fffffff);
irq_exit();
if (softirq_pending(cpu))
do_softirq();
}
/*
* Figure out the r4k offset, the amount to increment the compare
* register for each time tick.
*/
static unsigned long __init cal_r4koff(void)
{
/*
* The SEAD board doesn't have a real time clock, so we can't
* really calculate the timer offset.
* For now we hardwire the SEAD board frequency to 12MHz.
*/
return(6000000/HZ);
}
void __init mips_time_init(void)
{
unsigned int est_freq, flags;
local_irq_save(flags);
/* Start r4k counter. */
write_c0_count(0);
printk("calculating r4koff... ");
r4k_offset = cal_r4koff();
printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
if ((read_c0_prid() & 0xffff00) ==
(PRID_COMP_MIPS | PRID_IMP_20KC))
est_freq = r4k_offset*HZ;
else
est_freq = 2*r4k_offset*HZ;
est_freq += 5000; /* round */
est_freq -= est_freq%10000;
printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
(est_freq%1000000)*100/1000000);
local_irq_restore(flags);
}
void __init mips_timer_setup(struct irqaction *irq)
{
/* we are using the cpu counter for timer interrupts */
irq->handler = no_action; /* we use our own handler */
setup_irq(MIPS_CPU_TIMER_IRQ, irq);
/* to generate the first timer interrupt */
r4k_cur = (read_c0_count() + r4k_offset);
write_c0_compare(r4k_cur);
set_c0_status(ALLINTS);
}
arch/mips64/defconfig-atlas 0 → 100644
View file @ 5d3adbe2
#
# Automatically generated make config: don't edit
#
CONFIG_MIPS=y
# CONFIG_MIPS32 is not set
CONFIG_MIPS64=y
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
#
# General setup
#
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_EMBEDDED is not set
CONFIG_FUTEX=y
CONFIG_EPOLL=y
#
# Loadable module support
#
# CONFIG_MODULES is not set
#
# Machine selection
#
# CONFIG_ACER_PICA_61 is not set
# CONFIG_CASIO_E55 is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_LASAT is not set
# CONFIG_HP_LASERJET is not set
# CONFIG_IBM_WORKPAD is not set
# CONFIG_MIPS_ITE8172 is not set
CONFIG_MIPS_ATLAS=y
# CONFIG_MIPS_MAGNUM_4000 is not set
# CONFIG_MIPS_MALTA is not set
# CONFIG_MIPS_SEAD is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_DDB5074 is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_NEC_OSPREY is not set
# CONFIG_NEC_EAGLE is not set
# CONFIG_OLIVETTI_M700 is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_SB1xxx_SOC is not set
# CONFIG_SNI_RM200_PCI is not set
# CONFIG_TANBAC_TB0226 is not set
# CONFIG_TANBAC_TB0229 is not set
# CONFIG_VICTOR_MPC30X is not set
# CONFIG_ZAO_CAPCELLA is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_NONCOHERENT_IO=y
# CONFIG_CPU_LITTLE_ENDIAN is not set
CONFIG_MIPS_BOARDS_GEN=y
CONFIG_SWAP_IO_SPACE=y
CONFIG_BOOT_ELF32=y
CONFIG_L1_CACHE_SHIFT=5
# CONFIG_FB is not set
#
# CPU selection
#
# CONFIG_CPU_MIPS32 is not set
# CONFIG_CPU_MIPS64 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CPU_R4300 is not set
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_TX49XX is not set
CONFIG_CPU_R5000=y
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_LLDSCD=y
CONFIG_CPU_HAS_SYNC=y
# CONFIG_PREEMPT is not set
CONFIG_KALLSYMS=y
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
#
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
#
# CONFIG_PCI is not set
CONFIG_MMU=y
# CONFIG_HOTPLUG is not set
#
# Executable file formats
#
CONFIG_KCORE_ELF=y
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_MIPS32_COMPAT=y
CONFIG_COMPAT=y
CONFIG_MIPS32_O32=y
# CONFIG_MIPS32_N32 is not set
CONFIG_BINFMT_ELF32=y
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNP is not set
#
# Generic Driver Options
#
# CONFIG_FW_LOADER is not set
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_BLK_DEV_INITRD is not set
#
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_IDE is not set
#
# SCSI device support
#
CONFIG_SCSI=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
# CONFIG_BLK_DEV_SR is not set
# CONFIG_CHR_DEV_SG is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_REPORT_LUNS is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
#
# SCSI low-level drivers
#
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_EATA_PIO is not set
# CONFIG_SCSI_DEBUG is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
#
# I2O device support
#
#
# Networking support
#
CONFIG_NET=y
#
# Networking options
#
# CONFIG_PACKET is not set
CONFIG_NETLINK_DEV=y
# CONFIG_NETFILTER is not set
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
# CONFIG_IP_PNP_DHCP is not set
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_INET_ECN is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_IPV6 is not set
# CONFIG_XFRM_USER is not set
#
# SCTP Configuration (EXPERIMENTAL)
#
CONFIG_IPV6_SCTP__=y
# CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_LLC is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_FASTROUTE is not set
# CONFIG_NET_HW_FLOWCONTROL is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_ETHERTAP is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
# CONFIG_MII is not set
#
# Ethernet (1000 Mbit)
#
#
# Ethernet (10000 Mbit)
#
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
#
# Wireless LAN (non-hamradio)
#
# CONFIG_NET_RADIO is not set
#
# Token Ring devices (depends on LLC=y)
#
# CONFIG_SHAPER is not set
#
# Wan interfaces
#
# CONFIG_WAN is not set
#
# Amateur Radio support
#
# CONFIG_HAMRADIO is not set
#
# IrDA (infrared) support
#
# CONFIG_IRDA is not set
#
# ISDN subsystem
#
# CONFIG_ISDN_BOOL is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input I/O drivers
#
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_EXTENDED is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
#
# I2C support
#
# CONFIG_I2C is not set
#
# I2C Hardware Sensors Mainboard support
#
#
# I2C Hardware Sensors Chip support
#
# CONFIG_I2C_SENSOR is not set
#
# Mice
#
# CONFIG_BUSMOUSE is not set
# CONFIG_QIC02_TAPE is not set
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_NVRAM is not set
CONFIG_RTC=y
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_HANGCHECK_TIMER is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
#
# File systems
#
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_QUOTA is not set
CONFIG_AUTOFS_FS=y
# CONFIG_AUTOFS4_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_FAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
CONFIG_DEVPTS_FS=y
CONFIG_DEVPTS_FS_XATTR=y
CONFIG_DEVPTS_FS_SECURITY=y
# CONFIG_TMPFS is not set
CONFIG_RAMFS=y
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
CONFIG_EFS_FS=y
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFSD is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
# CONFIG_EXPORTFS is not set
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_GSS is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Graphics support
#
#
# Sound
#
# CONFIG_SOUND is not set
#
# USB support
#
# CONFIG_USB_GADGET is not set
#
# Bluetooth support
#
# CONFIG_BT is not set
#
# Kernel hacking
#
CONFIG_CROSSCOMPILE=y
# CONFIG_DEBUG_KERNEL is not set
#
# Security options
#
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
# CONFIG_CRYPTO is not set
#
# Library routines
#
# CONFIG_CRC32 is not set
arch/mips64/defconfig-malta 0 → 100644
View file @ 5d3adbe2
#
# Automatically generated make config: don't edit
#
CONFIG_MIPS=y
# CONFIG_MIPS32 is not set
CONFIG_MIPS64=y
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
#
# General setup
#
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_EMBEDDED is not set
CONFIG_FUTEX=y
CONFIG_EPOLL=y
#
# Loadable module support
#
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_MODULE_FORCE_UNLOAD is not set
CONFIG_OBSOLETE_MODPARM=y
CONFIG_MODVERSIONS=y
CONFIG_KMOD=y
#
# Machine selection
#
# CONFIG_ACER_PICA_61 is not set
# CONFIG_CASIO_E55 is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_LASAT is not set
# CONFIG_HP_LASERJET is not set
# CONFIG_IBM_WORKPAD is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MIPS_ATLAS is not set
# CONFIG_MIPS_MAGNUM_4000 is not set
CONFIG_MIPS_MALTA=y
# CONFIG_MIPS_SEAD is not set
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_DDB5074 is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_NEC_OSPREY is not set
# CONFIG_NEC_EAGLE is not set
# CONFIG_OLIVETTI_M700 is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_SB1xxx_SOC is not set
# CONFIG_SNI_RM200_PCI is not set
# CONFIG_TANBAC_TB0226 is not set
# CONFIG_TANBAC_TB0229 is not set
# CONFIG_VICTOR_MPC30X is not set
# CONFIG_ZAO_CAPCELLA is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_ISA_DMA=y
CONFIG_I8259=y
CONFIG_NONCOHERENT_IO=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_MIPS_BOARDS_GEN=y
CONFIG_SWAP_IO_SPACE=y
CONFIG_BOOT_ELF32=y
CONFIG_L1_CACHE_SHIFT=5
# CONFIG_FB is not set
CONFIG_HAVE_STD_PC_SERIAL_PORT=y
#
# CPU selection
#
# CONFIG_CPU_MIPS32 is not set
# CONFIG_CPU_MIPS64 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CPU_R4300 is not set
CONFIG_CPU_R4X00=y
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_LLDSCD=y
CONFIG_CPU_HAS_SYNC=y
# CONFIG_PREEMPT is not set
CONFIG_KALLSYMS=y
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
#
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
#
# CONFIG_PCI is not set
CONFIG_MMU=y
# CONFIG_HOTPLUG is not set
#
# Executable file formats
#
CONFIG_KCORE_ELF=y
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_MIPS32_COMPAT=y
CONFIG_COMPAT=y
CONFIG_MIPS32_O32=y
# CONFIG_MIPS32_N32 is not set
CONFIG_BINFMT_ELF32=y
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNP is not set
#
# Generic Driver Options
#
# CONFIG_FW_LOADER is not set
#
# Block devices
#
CONFIG_BLK_DEV_FD=y
# CONFIG_BLK_DEV_LOOP is not set
# CONFIG_BLK_DEV_NBD is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=4096
# CONFIG_BLK_DEV_INITRD is not set
#
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_IDE is not set
#
# SCSI device support
#
CONFIG_SCSI=y
#
# SCSI support type (disk, tape, CD-ROM)
#
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
# CONFIG_BLK_DEV_SR is not set
# CONFIG_CHR_DEV_SG is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_REPORT_LUNS is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
#
# SCSI low-level drivers
#
# CONFIG_SCSI_AIC7XXX is not set
# CONFIG_SCSI_AIC7XXX_OLD is not set
# CONFIG_SCSI_DPT_I2O is not set
# CONFIG_SCSI_EATA_PIO is not set
# CONFIG_SCSI_DEBUG is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Fusion MPT device support
#
# CONFIG_FUSION is not set
#
# I2O device support
#
#
# Networking support
#
CONFIG_NET=y
#
# Networking options
#
# CONFIG_PACKET is not set
CONFIG_NETLINK_DEV=y
# CONFIG_NETFILTER is not set
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_INET_ECN is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_IPV6 is not set
# CONFIG_XFRM_USER is not set
#
# SCTP Configuration (EXPERIMENTAL)
#
CONFIG_IPV6_SCTP__=y
# CONFIG_IP_SCTP is not set
# CONFIG_ATM is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_LLC is not set
# CONFIG_DECNET is not set
# CONFIG_BRIDGE is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_NET_DIVERT is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_FASTROUTE is not set
# CONFIG_NET_HW_FLOWCONTROL is not set
#
# QoS and/or fair queueing
#
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_ETHERTAP is not set
#
# Ethernet (10 or 100Mbit)
#
CONFIG_NET_ETHERNET=y
# CONFIG_MII is not set
#
# Ethernet (1000 Mbit)
#
#
# Ethernet (10000 Mbit)
#
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
#
# Wireless LAN (non-hamradio)
#
# CONFIG_NET_RADIO is not set
#
# Token Ring devices (depends on LLC=y)
#
# CONFIG_SHAPER is not set
#
# Wan interfaces
#
# CONFIG_WAN is not set
#
# Amateur Radio support
#
# CONFIG_HAMRADIO is not set
#
# IrDA (infrared) support
#
# CONFIG_IRDA is not set
#
# ISDN subsystem
#
# CONFIG_ISDN_BOOL is not set
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input I/O drivers
#
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_EXTENDED is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_UNIX98_PTY_COUNT=256
#
# I2C support
#
# CONFIG_I2C is not set
#
# I2C Hardware Sensors Mainboard support
#
#
# I2C Hardware Sensors Chip support
#
# CONFIG_I2C_SENSOR is not set
#
# Mice
#
# CONFIG_BUSMOUSE is not set
# CONFIG_QIC02_TAPE is not set
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_NVRAM is not set
CONFIG_RTC=y
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_HANGCHECK_TIMER is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
# CONFIG_DVB is not set
#
# File systems
#
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_QUOTA is not set
CONFIG_AUTOFS_FS=y
# CONFIG_AUTOFS4_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_FAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
CONFIG_DEVPTS_FS=y
CONFIG_DEVPTS_FS_XATTR=y
CONFIG_DEVPTS_FS_SECURITY=y
# CONFIG_TMPFS is not set
CONFIG_RAMFS=y
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
CONFIG_EFS_FS=y
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Network File Systems
#
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
# CONFIG_NFS_V4 is not set
CONFIG_NFSD=y
CONFIG_NFSD_V3=y
# CONFIG_NFSD_V4 is not set
# CONFIG_NFSD_TCP is not set
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_EXPORTFS=y
CONFIG_SUNRPC=y
# CONFIG_SUNRPC_GSS is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_INTERMEZZO_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Graphics support
#
#
# Sound
#
# CONFIG_SOUND is not set
#
# USB support
#
# CONFIG_USB_GADGET is not set
#
# Bluetooth support
#
# CONFIG_BT is not set
#
# Kernel hacking
#
CONFIG_CROSSCOMPILE=y
# CONFIG_DEBUG_KERNEL is not set
#
# Security options
#
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
# CONFIG_CRYPTO is not set
#
# Library routines
#
# CONFIG_CRC32 is not set
arch/mips64/defconfig-sead 0 → 100644
View file @ 5d3adbe2
#
# Automatically generated make config: don't edit
#
CONFIG_MIPS=y
# CONFIG_MIPS32 is not set
CONFIG_MIPS64=y
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
#
# General setup
#
CONFIG_SWAP=y
# CONFIG_SYSVIPC is not set
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_EMBEDDED is not set
CONFIG_FUTEX=y
CONFIG_EPOLL=y
#
# Loadable module support
#
# CONFIG_MODULES is not set
#
# Machine selection
#
# CONFIG_ACER_PICA_61 is not set
# CONFIG_CASIO_E55 is not set
# CONFIG_MIPS_COBALT is not set
# CONFIG_DECSTATION is not set
# CONFIG_MIPS_EV64120 is not set
# CONFIG_MIPS_EV96100 is not set
# CONFIG_MIPS_IVR is not set
# CONFIG_LASAT is not set
# CONFIG_HP_LASERJET is not set
# CONFIG_IBM_WORKPAD is not set
# CONFIG_MIPS_ITE8172 is not set
# CONFIG_MIPS_ATLAS is not set
# CONFIG_MIPS_MAGNUM_4000 is not set
# CONFIG_MIPS_MALTA is not set
CONFIG_MIPS_SEAD=y
# CONFIG_MOMENCO_OCELOT is not set
# CONFIG_MOMENCO_OCELOT_G is not set
# CONFIG_MOMENCO_OCELOT_C is not set
# CONFIG_DDB5074 is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_NEC_OSPREY is not set
# CONFIG_NEC_EAGLE is not set
# CONFIG_OLIVETTI_M700 is not set
# CONFIG_SGI_IP22 is not set
# CONFIG_SGI_IP27 is not set
# CONFIG_SGI_IP32 is not set
# CONFIG_SIBYTE_SB1xxx_SOC is not set
# CONFIG_SNI_RM200_PCI is not set
# CONFIG_TANBAC_TB0226 is not set
# CONFIG_TANBAC_TB0229 is not set
# CONFIG_VICTOR_MPC30X is not set
# CONFIG_ZAO_CAPCELLA is not set
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_NONCOHERENT_IO=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_MIPS_BOARDS_GEN=y
CONFIG_L1_CACHE_SHIFT=5
# CONFIG_FB is not set
#
# CPU selection
#
# CONFIG_CPU_MIPS32 is not set
# CONFIG_CPU_MIPS64 is not set
# CONFIG_CPU_R3000 is not set
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CPU_R4300 is not set
CONFIG_CPU_R4X00=y
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
# CONFIG_CPU_R6000 is not set
# CONFIG_CPU_NEVADA is not set
# CONFIG_CPU_R8000 is not set
# CONFIG_CPU_R10000 is not set
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_LLDSCD=y
CONFIG_CPU_HAS_SYNC=y
# CONFIG_PREEMPT is not set
CONFIG_KALLSYMS=y
# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
#
# Bus options (PCI, PCMCIA, EISA, ISA, TC)
#
CONFIG_MMU=y
# CONFIG_HOTPLUG is not set
#
# Executable file formats
#
CONFIG_KCORE_ELF=y
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_MIPS32_COMPAT=y
CONFIG_COMPAT=y
CONFIG_MIPS32_O32=y
# CONFIG_MIPS32_N32 is not set
CONFIG_BINFMT_ELF32=y
#
# Memory Technology Devices (MTD)
#
# CONFIG_MTD is not set
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Plug and Play support
#
# CONFIG_PNP is not set
#
# Generic Driver Options
#
# CONFIG_FW_LOADER is not set
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=18432
CONFIG_BLK_DEV_INITRD=y
#
# MIPS initrd options
#
# CONFIG_EMBEDDED_RAMDISK is not set
#
# ATA/ATAPI/MFM/RLL support
#
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_SCSI is not set
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Fusion MPT device support
#
#
# I2O device support
#
#
# Networking support
#
# CONFIG_NET is not set
#
# Amateur Radio support
#
# CONFIG_HAMRADIO is not set
#
# ISDN subsystem
#
#
# Telephony Support
#
# CONFIG_PHONE is not set
#
# Input device support
#
CONFIG_INPUT=y
#
# Userland interfaces
#
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input I/O drivers
#
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Character devices
#
# CONFIG_VT is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_EXTENDED is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_UNIX98_PTYS is not set
#
# I2C support
#
# CONFIG_I2C is not set
#
# I2C Hardware Sensors Mainboard support
#
#
# I2C Hardware Sensors Chip support
#
# CONFIG_I2C_SENSOR is not set
#
# Mice
#
# CONFIG_BUSMOUSE is not set
# CONFIG_QIC02_TAPE is not set
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_NVRAM is not set
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_FTAPE is not set
# CONFIG_AGP is not set
# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_HANGCHECK_TIMER is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# File systems
#
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
CONFIG_FS_POSIX_ACL=y
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_FAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_DEVFS_FS is not set
# CONFIG_TMPFS is not set
CONFIG_RAMFS=y
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
#
# Graphics support
#
#
# Sound
#
# CONFIG_SOUND is not set
#
# USB support
#
# CONFIG_USB_GADGET is not set
#
# Kernel hacking
#
CONFIG_CROSSCOMPILE=y
# CONFIG_DEBUG_KERNEL is not set
#
# Security options
#
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
# CONFIG_CRYPTO is not set
#
# Library routines
#
# CONFIG_CRC32 is not set
arch/mips64/mips-boards/atlas/Makefile deleted 100644 → 0
View file @ a85be436
#
# Carsten Langgaard, carstenl@mips.com
# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
#
# ########################################################################
#
# This program is free software; you can distribute it and/or modify it
# under the terms of the GNU General Public License (Version 2) as
# published by the Free Software Foundation.
#
# This program is distributed in the hope it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for more details.
#
# You should have received a copy of the GNU General Public License along
# with this program; if not, write to the Free Software Foundation, Inc.,
# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
#
# #######################################################################
#
# Makefile for the MIPS Atlas specific kernel interface routines
# under Linux.
#
obj-y := atlas_int.o atlas_rtc.o atlas_setup.o
arch/mips64/mips-boards/atlas/atlas_int.c deleted 100644 → 0
View file @ a85be436
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Routines for generic manipulation of the interrupts found on the MIPS
* Atlas board.
*
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/seq_file.h>
#include <asm/irq.h>
#include <asm/mips-boards/atlas.h>
#include <asm/mips-boards/atlasint.h>
#ifdef CONFIG_REMOTE_DEBUG
#include <asm/gdb-stub.h>
#endif
struct atlas_ictrl_regs *atlas_hw0_icregs
= (struct atlas_ictrl_regs *)ATLAS_ICTRL_REGS_BASE;
extern asmlinkage void mipsIRQ(void);
extern void do_IRQ(int irq, struct pt_regs *regs);
unsigned long spurious_count = 0;
irq_desc_t irq_desc[NR_IRQS];
#if 0
#define DEBUG_INT(x...) printk(x)
#else
#define DEBUG_INT(x...)
#endif
void disable_atlas_irq(unsigned int irq_nr)
{
atlas_hw0_icregs->intrsten = (1 << irq_nr);
}
void enable_atlas_irq(unsigned int irq_nr)
{
atlas_hw0_icregs->intseten = (1 << irq_nr);
}
static unsigned int startup_atlas_irq(unsigned int irq)
{
enable_atlas_irq(irq);
return 0; /* never anything pending */
}
#define shutdown_atlas_irq disable_atlas_irq
#define mask_and_ack_atlas_irq disable_atlas_irq
static void end_atlas_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_atlas_irq(irq);
}
static struct hw_interrupt_type atlas_irq_type = {
"Atlas",
startup_atlas_irq,
shutdown_atlas_irq,
enable_atlas_irq,
disable_atlas_irq,
mask_and_ack_atlas_irq,
end_atlas_irq,
NULL
};
int show_interrupts(struct seq_file *p, void *v)
{
int i;
int num = 0;
struct irqaction *action;
unsigned long flags;
for (i = 0; i < ATLASINT_END; i++, num++) {
spin_lock_irqsave(&irq_desc[i].lock, flags);
action = irq_desc[i].action;
if (!action)
goto unlock;
seq_printf(p, "%2d: %8d %c %s",
num, kstat_cpu(0).irqs[num],
(action->flags & SA_INTERRUPT) ? '+' : ' ',
action->name);
for (action=action->next; action; action = action->next) {
seq_printf(p, ",%s %s",
(action->flags & SA_INTERRUPT) ? " +" : "",
action->name);
}
seq_puts(p, " [hw0]\n");
unlock:
spin_unlock_irqrestore(&irq_desc[i].lock, flags);
}
return 0;
}
int request_irq(unsigned int irq,
void (*handler)(int, void *, struct pt_regs *),
unsigned long irqflags,
const char * devname,
void *dev_id)
{
struct irqaction *action;
DEBUG_INT("request_irq: irq=%d, devname = %s\n", irq, devname);
if (irq >= ATLASINT_END)
return -EINVAL;
if (!handler)
return -EINVAL;
action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
if(!action)
return -ENOMEM;
action->handler = handler;
action->flags = irqflags;
action->mask = 0;
action->name = devname;
action->dev_id = dev_id;
action->next = 0;
irq_desc[irq].action = action;
enable_atlas_irq(irq);
return 0;
}
void free_irq(unsigned int irq, void *dev_id)
{
struct irqaction *action;
if (irq >= ATLASINT_END) {
printk("Trying to free IRQ%d\n",irq);
return;
}
action = irq_desc[irq].action;
irq_desc[irq].action = NULL;
disable_atlas_irq(irq);
kfree(action);
}
static inline int ls1bit32(unsigned int x)
{
int b = 31, s;
s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s;
s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s;
s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s;
s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s;
s = 1; if (x << 1 == 0) s = 0; b -= s;
return b;
}
void atlas_hw0_irqdispatch(struct pt_regs *regs)
{
struct irqaction *action;
unsigned long int_status;
int irq, cpu = smp_processor_id();
int_status = atlas_hw0_icregs->intstatus;
/* if int_status == 0, then the interrupt has already been cleared */
if (int_status == 0)
return;
irq = ls1bit32(int_status);
action = irq_desc[irq].action;
DEBUG_INT("atlas_hw0_irqdispatch: irq=%d\n", irq);
/* if action == NULL, then we don't have a handler for the irq */
if ( action == NULL ) {
printk("No handler for hw0 irq: %i\n", irq);
spurious_count++;
return;
}
irq_enter(cpu, irq);
kstat_cpu(0).irqs[irq]++;
action->handler(irq, action->dev_id, regs);
irq_exit(cpu, irq);
return;
}
unsigned long probe_irq_on (void)
{
return 0;
}
int probe_irq_off (unsigned long irqs)
{
return 0;
}
#ifdef CONFIG_REMOTE_DEBUG
extern void breakpoint(void);
extern int remote_debug;
#endif
void __init init_IRQ(void)
{
int i;
/*
* Mask out all interrupt by writing "1" to all bit position in
* the interrupt reset reg.
*/
atlas_hw0_icregs->intrsten = 0xffffffff;
/* Now safe to set the exception vector. */
set_except_vector(0, mipsIRQ);
for (i = 0; i <= ATLASINT_END; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = 0;
irq_desc[i].depth = 1;
irq_desc[i].handler = &atlas_irq_type;
spin_lock_init(&irq_desc[i].lock);
}
#ifdef CONFIG_REMOTE_DEBUG
if (remote_debug) {
set_debug_traps();
breakpoint();
}
#endif
}
arch/mips64/mips-boards/generic/Makefile deleted 100644 → 0
View file @ a85be436
#
# Carsten Langgaard, carstenl@mips.com
# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
#
# ########################################################################
#
# This program is free software; you can distribute it and/or modify it
# under the terms of the GNU General Public License (Version 2) as
# published by the Free Software Foundation.
#
# This program is distributed in the hope it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for more details.
#
# You should have received a copy of the GNU General Public License along
# with this program; if not, write to the Free Software Foundation, Inc.,
# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
#
# #######################################################################
#
# Makefile for the MIPS boards generic routines under Linux.
#
obj-y := mipsIRQ.o pci.o reset.o display.o init.o \
memory.o printf.o cmdline.o time.o
obj-$(CONFIG_REMOTE_DEBUG) += gdb_hook.o
EXTRA_AFLAGS := $(CFLAGS)
arch/mips64/mips-boards/generic/gdb_hook.c deleted 100644 → 0
View file @ a85be436
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* This is the interface to the remote debugger stub.
*
*/
#include <linux/serialP.h>
#include <linux/serial_reg.h>
#include <asm/serial.h>
#include <asm/io.h>
static struct serial_state rs_table[RS_TABLE_SIZE] = {
SERIAL_PORT_DFNS /* Defined in serial.h */
};
static struct async_struct kdb_port_info = {0};
static __inline__ unsigned int serial_in(struct async_struct *info, int offset)
{
return inb(info->port + offset);
}
static __inline__ void serial_out(struct async_struct *info, int offset,
int value)
{
outb(value, info->port+offset);
}
void rs_kgdb_hook(int tty_no) {
int t;
struct serial_state *ser = &rs_table[tty_no];
kdb_port_info.state = ser;
kdb_port_info.magic = SERIAL_MAGIC;
kdb_port_info.port = ser->port;
kdb_port_info.flags = ser->flags;
/*
* Clear all interrupts
*/
serial_in(&kdb_port_info, UART_LSR);
serial_in(&kdb_port_info, UART_RX);
serial_in(&kdb_port_info, UART_IIR);
serial_in(&kdb_port_info, UART_MSR);
/*
* Now, initialize the UART
*/
serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8); /* reset DLAB */
if (kdb_port_info.flags & ASYNC_FOURPORT) {
kdb_port_info.MCR = UART_MCR_DTR | UART_MCR_RTS;
t = UART_MCR_DTR | UART_MCR_OUT1;
} else {
kdb_port_info.MCR
= UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2;
t = UART_MCR_DTR | UART_MCR_RTS;
}
kdb_port_info.MCR = t; /* no interrupts, please */
serial_out(&kdb_port_info, UART_MCR, kdb_port_info.MCR);
/*
* and set the speed of the serial port
* (currently hardwired to 9600 8N1
*/
/* baud rate is fixed to 9600 (is this sufficient?)*/
t = kdb_port_info.state->baud_base / 9600;
/* set DLAB */
serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8 | UART_LCR_DLAB);
serial_out(&kdb_port_info, UART_DLL, t & 0xff);/* LS of divisor */
serial_out(&kdb_port_info, UART_DLM, t >> 8); /* MS of divisor */
/* reset DLAB */
serial_out(&kdb_port_info, UART_LCR, UART_LCR_WLEN8);
}
int rs_putDebugChar(char c)
{
if (!kdb_port_info.state) { /* need to init device first */
return 0;
}
while ((serial_in(&kdb_port_info, UART_LSR) & UART_LSR_THRE) == 0)
;
serial_out(&kdb_port_info, UART_TX, c);
return 1;
}
char rs_getDebugChar(void)
{
if (!kdb_port_info.state) { /* need to init device first */
return 0;
}
while (!(serial_in(&kdb_port_info, UART_LSR) & 1))
;
return(serial_in(&kdb_port_info, UART_RX));
}
#ifdef CONFIG_MIPS_ATLAS
#include <asm/mips-boards/atlas.h>
#include <asm/mips-boards/saa9730_uart.h>
#define INB(a) inb((unsigned long)a)
#define OUTB(x,a) outb(x,(unsigned long)a)
/*
* This is the interface to the remote debugger stub
* if the Philips part is used for the debug port,
* called from the platform setup code.
*
* PCI init will not have been done yet, we make a
* universal assumption about the way the bootloader (YAMON)
* have located and set up the chip.
*/
static t_uart_saa9730_regmap *kgdb_uart = (void *)(ATLAS_SAA9730_REG + SAA9730_UART_REGS_ADDR);
static int saa9730_kgdb_active = 0;
void saa9730_kgdb_hook(void)
{
volatile unsigned char t;
/*
* Clear all interrupts
*/
t = INB(&kgdb_uart->Lsr);
t += INB(&kgdb_uart->Msr);
t += INB(&kgdb_uart->Thr_Rbr);
t += INB(&kgdb_uart->Iir_Fcr);
/*
* Now, initialize the UART
*/
/* 8 data bits, one stop bit, no parity */
OUTB(SAA9730_LCR_DATA8, &kgdb_uart->Lcr);
/* baud rate is fixed to 9600 (is this sufficient?)*/
OUTB(0, &kgdb_uart->BaudDivMsb); /* HACK - Assumes standard crystal */
OUTB(23, &kgdb_uart->BaudDivLsb); /* HACK - known for MIPS Atlas */
/* Set RTS/DTR active */
OUTB(SAA9730_MCR_DTR | SAA9730_MCR_RTS, &kgdb_uart->Mcr);
saa9730_kgdb_active = 1;
}
int saa9730_putDebugChar(char c)
{
if (!saa9730_kgdb_active) { /* need to init device first */
return 0;
}
while (!(INB(&kgdb_uart->Lsr) & SAA9730_LSR_THRE))
;
OUTB(c, &kgdb_uart->Thr_Rbr);
return 1;
}
char saa9730_getDebugChar(void)
{
char c;
if (!saa9730_kgdb_active) { /* need to init device first */
return 0;
}
while (!(INB(&kgdb_uart->Lsr) & SAA9730_LSR_DR))
;
c = INB(&kgdb_uart->Thr_Rbr);
return(c);
}
#endif
arch/mips64/mips-boards/generic/init.c deleted 100644 → 0
View file @ a85be436
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* PROM library initialisation code.
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <asm/io.h>
#include <asm/mips-boards/prom.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/gt64120.h>
#include <asm/mips-boards/malta.h>
/* Environment variable */
typedef struct
{
char *name;
char *val;
}t_env_var;
int prom_argc;
int *_prom_argv, *_prom_envp;
/*
* A 32-bit PROM pass arguments and environment as 32-bit pointer.
* This macro take care of sign extension.
*/
#define prom_envp(index) ((char *)(((int *)(int)_prom_envp)[(index)]))
int init_debug = 0;
char *prom_getenv(char *envname)
{
/*
* Return a pointer to the given environment variable.
* We're using 64-bit pointers, but all pointers in the PROM
* structures are only 32-bit, so we need some workarounds.
*/
int i, index=0;
i = strlen(envname);
while(prom_envp(index)) {
if(strncmp(envname, prom_envp(index), i) == 0) {
return(prom_envp(index+1));
}
index += 2;
}
return(NULL);
}
static inline unsigned char str2hexnum(unsigned char c)
{
if(c >= '0' && c <= '9')
return c - '0';
if(c >= 'a' && c <= 'f')
return c - 'a' + 10;
return 0; /* foo */
}
static inline void str2eaddr(unsigned char *ea, unsigned char *str)
{
int i;
for(i = 0; i < 6; i++) {
unsigned char num;
if((*str == '.') || (*str == ':'))
str++;
num = str2hexnum(*str++) << 4;
num |= (str2hexnum(*str++));
ea[i] = num;
}
}
int get_ethernet_addr(char *ethernet_addr)
{
char *ethaddr_str;
ethaddr_str = prom_getenv("ethaddr");
if (!ethaddr_str) {
printk("ethaddr not set in boot prom\n");
return -1;
}
str2eaddr(ethernet_addr, ethaddr_str);
if (init_debug > 1)
{
int i;
printk("get_ethernet_addr: ");
for (i=0; i<5; i++)
printk("%02x:", (unsigned char)*(ethernet_addr+i));
printk("%02x\n", *(ethernet_addr+i));
}
return 0;
}
int __init prom_init(int argc, char **argv, char **envp)
{
prom_argc = argc;
_prom_argv = (int *)argv;
_prom_envp = (int *)envp;
mips_display_message("LINUX");
/*
* Setup the North bridge to do Master byte-lane swapping when
* running in bigendian.
*/
#if defined(__MIPSEL__)
GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT |
GT_PCI0_CMD_SBYTESWAP_BIT);
#else
GT_WRITE(GT_PCI0_CMD_OFS, 0);
#endif
#if defined(CONFIG_MIPS_MALTA)
mips_io_port_base = MALTA_PORT_BASE;
#else
mips_io_port_base = KSEG1;
#endif
setup_prom_printf(0);
prom_printf("\nLINUX started...\n");
prom_init_cmdline();
prom_meminit();
return 0;
}
arch/mips64/mips-boards/generic/memory.c deleted 100644 → 0
View file @ a85be436
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* PROM library functions for acquiring/using memory descriptors given to
* us from the YAMON.
*
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <asm/bootinfo.h>
#include <asm/page.h>
#include <asm/mips-boards/prom.h>
/*#define DEBUG*/
enum yamon_memtypes {
yamon_dontuse,
yamon_prom,
yamon_free,
};
struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
#define MEMTYPE_DONTUSE 0
#define MEMTYPE_PROM 1
#define MEMTYPE_FREE 2
#ifdef DEBUG
static char *mtypes[3] = {
"Dont use memory",
"YAMON PROM memory",
"Free memmory",
};
#endif
/* References to section boundaries */
extern char _end;
#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
struct prom_pmemblock * __init prom_getmdesc(void)
{
char *memsize_str;
unsigned int memsize;
memsize_str = prom_getenv("memsize");
if (!memsize_str) {
prom_printf("memsize not set in boot prom, set to default (32Mb)\n");
memsize = 0x02000000;
} else {
#ifdef DEBUG
prom_printf("prom_memsize = %s\n", memsize_str);
#endif
memsize = simple_strtol(memsize_str, NULL, 0);
}
memset(mdesc, 0, sizeof(mdesc));
mdesc[0].type = yamon_dontuse;
mdesc[0].base = 0x00000000;
mdesc[0].size = 0x00001000;
mdesc[1].type = yamon_prom;
mdesc[1].base = 0x00001000;
mdesc[1].size = 0x000ef000;
#if (CONFIG_MIPS_MALTA)
/*
* The area 0x000f0000-0x000fffff is allocated for BIOS memory by the
* south bridge and PCI access always forwarded to the ISA Bus and
* BIOSCS# is always generated.
* This mean that this area can't be used as DMA memory for PCI
* devices.
*/
mdesc[2].type = yamon_dontuse;
mdesc[2].base = 0x000f0000;
mdesc[2].size = 0x00010000;
#else
mdesc[2].type = yamon_prom;
mdesc[2].base = 0x000f0000;
mdesc[2].size = 0x00010000;
#endif
mdesc[3].type = yamon_dontuse;
mdesc[3].base = 0x00100000;
mdesc[3].size = CPHYSADDR(PFN_ALIGN(&_end)) - mdesc[3].base;
mdesc[4].type = yamon_free;
mdesc[4].base = CPHYSADDR(PFN_ALIGN(&_end));
mdesc[4].size = memsize - mdesc[4].base;
return &mdesc[0];
}
int __init page_is_ram(unsigned long pagenr)
{
if ((pagenr << PAGE_SHIFT) < mdesc[4].base + mdesc[4].size)
return 1;
return 0;
}
static struct prom_pmemblock pblocks[PROM_MAX_PMEMBLOCKS];
static int __init prom_memtype_classify (unsigned int type)
{
switch (type) {
case yamon_free:
return MEMTYPE_FREE;
case yamon_prom:
return MEMTYPE_PROM;
default:
return MEMTYPE_DONTUSE;
}
}
static inline unsigned long find_max_low_pfn(void)
{
struct prom_pmemblock *p, *highest;
unsigned long pfn;
p = pblocks;
highest = 0;
while (p->size != 0) {
if (!highest || p->base > highest->base)
highest = p;
p++;
}
pfn = (highest->base + highest->size) >> PAGE_SHIFT;
#ifdef DEBUG
prom_printf("find_max_low_pfn: 0x%lx pfns.\n", pfn);
#endif
return pfn;
}
static inline struct prom_pmemblock *find_largest_memblock(void)
{
struct prom_pmemblock *p, *largest;
p = pblocks;
largest = 0;
while (p->size != 0) {
if (!largest || p->size > largest->size)
largest = p;
p++;
}
return largest;
}
void __init prom_meminit(void)
{
struct prom_pmemblock *largest, *p;
unsigned long bootmap_size;
int totram;
int i = 0;
#ifdef DEBUG
prom_printf("YAMON MEMORY DESCRIPTOR dump:\n");
p = prom_getmdesc();
while (p->size) {
prom_printf("[%d,%p]: base<%08lx> size<%08lx> type<%s>\n",
i, p, p->base, p->size, mtypes[p->type]);
p++;
i++;
}
#endif
totram = 0;
i = 0;
p = prom_getmdesc();
while (p->size) {
pblocks[i].type = prom_memtype_classify (p->type);
pblocks[i].base = p->base;
pblocks[i].size = p->size;
switch (pblocks[i].type) {
case MEMTYPE_FREE:
totram += pblocks[i].size;
#ifdef DEBUG
prom_printf("free_chunk[%d]: base=%08lx size=%d\n",
i, pblocks[i].base, pblocks[i].size);
#endif
i++;
break;
case MEMTYPE_PROM:
#ifdef DEBUG
prom_printf("prom_chunk[%d]: base=%08lx size=%d\n",
i, pblocks[i].base, pblocks[i].size);
#endif
i++;
break;
default:
break;
}
p++;
}
pblocks[i].base = 0xdeadbeef;
pblocks[i].size = 0; /* indicates last elem. of array */
max_low_pfn = find_max_low_pfn();
largest = find_largest_memblock();
bootmap_size = init_bootmem(largest->base >> PAGE_SHIFT, max_low_pfn);
for (i = 0; pblocks[i].size; i++)
if (pblocks[i].type == MEMTYPE_FREE)
free_bootmem(pblocks[i].base, pblocks[i].size);
/* This test is simpleminded. It will fail if the bootmem bitmap
falls into multiple adjacent PROM memory areas. */
if (bootmap_size > largest->size) {
prom_printf("CRITIAL: overwriting PROM data.\n");
BUG();
}
/* Reserve the memory bootmap itself */
reserve_bootmem(largest->base, bootmap_size);
printk("PROMLIB: Total free ram %d bytes (%dK,%dMB)\n",
totram, (totram/1024), (totram/1024/1024));
}
void prom_free_prom_memory (void)
{
struct prom_pmemblock *p;
unsigned long freed = 0;
unsigned long addr;
for (p = pblocks; p->size != 0; p++) {
if (p->type != MEMTYPE_PROM)
continue;
addr = p->base;
while (addr < p->base + p->size) {
ClearPageReserved(virt_to_page(__va(addr)));
set_page_count(virt_to_page(__va(addr)), 1);
free_page(__va(addr));
addr += PAGE_SIZE;
freed += PAGE_SIZE;
}
}
printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
}
arch/mips64/mips-boards/generic/mipsIRQ.S deleted 100644 → 0
View file @ a85be436
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Interrupt exception dispatch code.
*
*/
#include <linux/config.h>
#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/regdef.h>
#include <asm/stackframe.h>
/* A lot of complication here is taken away because:
*
* 1) We handle one interrupt and return, sitting in a loop and moving across
* all the pending IRQ bits in the cause register is _NOT_ the answer, the
* common case is one pending IRQ so optimize in that direction.
*
* 2) We need not check against bits in the status register IRQ mask, that
* would make this routine slow as hell.
*
* 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
* between like BSD spl() brain-damage.
*
* Furthermore, the IRQs on the MIPS board look basically (barring software
* IRQs which we don't use at all and all external interrupt sources are
* combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
*
* MIPS IRQ Source
* -------- ------
* 0 Software (ignored)
* 1 Software (ignored)
* 2 Combined hardware interrupt (hw0)
* 3 Hardware (ignored)
* 4 Hardware (ignored)
* 5 Hardware (ignored)
* 6 Hardware (ignored)
* 7 R4k timer (what we use)
*
* We handle the IRQ according to _our_ priority which is:
*
* Highest ---- R4k Timer
* Lowest ---- Combined hardware interrupt
*
* then we just return, if multiple IRQs are pending then we will just take
* another exception, big deal.
*/
.text
.set noreorder
.set noat
.align 5
NESTED(mipsIRQ, PT_SIZE, sp)
SAVE_ALL
CLI
.set at
mfc0 s0, CP0_CAUSE # get irq mask
/* First we check for r4k counter/timer IRQ. */
andi a0, s0, CAUSEF_IP7
beq a0, zero, 1f
andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt
/* Wheee, a timer interrupt. */
move a0, sp
jal mips_timer_interrupt
nop
j ret_from_irq
nop
1:
beq a0, zero, 1f
nop
/* Wheee, combined hardware level zero interrupt. */
#if defined(CONFIG_MIPS_ATLAS)
jal atlas_hw0_irqdispatch
#elif defined(CONFIG_MIPS_MALTA)
jal malta_hw0_irqdispatch
#else
#error "MIPS board not supported\n"
#endif
move a0, sp # delay slot
j ret_from_irq
nop # delay slot
1:
/*
* Here by mistake? This is possible, what can happen is that by the
* time we take the exception the IRQ pin goes low, so just leave if
* this is the case.
*/
move a1,s0
PRINT("Got interrupt: c0_cause = %08x\n")
mfc0 a1, CP0_EPC
PRINT("c0_epc = %08x\n")
j ret_from_irq
nop
END(mipsIRQ)
arch/mips64/mips-boards/generic/pci.c deleted 100644 → 0
View file @ a85be436
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* MIPS boards specific PCI support.
*
*/
#include <linux/config.h>
#ifdef CONFIG_PCI
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/gt64120.h>
#ifdef CONFIG_MIPS_MALTA
#include <asm/mips-boards/malta.h>
#endif
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
static int
mips_pcibios_config_access(unsigned char access_type, struct pci_dev *dev,
unsigned char where, u32 *data)
{
unsigned char bus = dev->bus->number;
unsigned char dev_fn = dev->devfn;
u32 intr;
if ((bus == 0) && (dev_fn >= PCI_DEVFN(31,0)))
return -1; /* Because of a bug in the galileo (for slot 31). */
/* Clear cause register bits */
GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
GT_INTRCAUSE_TARABORT0_BIT));
/* Setup address */
GT_WRITE(GT_PCI0_CFGADDR_OFS,
(bus << GT_PCI0_CFGADDR_BUSNUM_SHF) |
(dev_fn << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
((where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
GT_PCI0_CFGADDR_CONFIGEN_BIT);
if (access_type == PCI_ACCESS_WRITE) {
if (bus == 0 && dev_fn == 0) {
/*
* Galileo is acting differently than other devices.
*/
GT_WRITE(GT_PCI0_CFGDATA_OFS, *data);
} else {
GT_PCI_WRITE(GT_PCI0_CFGDATA_OFS, *data);
}
} else {
if (bus == 0 && dev_fn == 0) {
/*
* Galileo is acting differently than other devices.
*/
GT_READ(GT_PCI0_CFGDATA_OFS, *data);
} else {
GT_PCI_READ(GT_PCI0_CFGDATA_OFS, *data);
}
}
/* Check for master or target abort */
GT_READ(GT_INTRCAUSE_OFS, intr);
if (intr & (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT))
{
/* Error occurred */
/* Clear bits */
GT_WRITE( GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
GT_INTRCAUSE_TARABORT0_BIT) );
return -1;
}
return 0;
}
/*
* We can't address 8 and 16 bit words directly. Instead we have to
* read/write a 32bit word and mask/modify the data we actually want.
*/
static int
mips_pcibios_read_config_byte (struct pci_dev *dev, int where, u8 *val)
{
u32 data = 0;
if (mips_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data))
return -1;
*val = (data >> ((where & 3) << 3)) & 0xff;
return PCIBIOS_SUCCESSFUL;
}
static int
mips_pcibios_read_config_word (struct pci_dev *dev, int where, u16 *val)
{
u32 data = 0;
if (where & 1)
return PCIBIOS_BAD_REGISTER_NUMBER;
if (mips_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data))
return -1;
*val = (data >> ((where & 3) << 3)) & 0xffff;
return PCIBIOS_SUCCESSFUL;
}
static int
mips_pcibios_read_config_dword (struct pci_dev *dev, int where, u32 *val)
{
u32 data = 0;
if (where & 3)
return PCIBIOS_BAD_REGISTER_NUMBER;
if (mips_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data))
return -1;
*val = data;
return PCIBIOS_SUCCESSFUL;
}
static int
mips_pcibios_write_config_byte (struct pci_dev *dev, int where, u8 val)
{
u32 data = 0;
if (mips_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data))
return -1;
data = (data & ~(0xff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
if (mips_pcibios_config_access(PCI_ACCESS_WRITE, dev, where, &data))
return -1;
return PCIBIOS_SUCCESSFUL;
}
static int
mips_pcibios_write_config_word (struct pci_dev *dev, int where, u16 val)
{
u32 data = 0;
if (where & 1)
return PCIBIOS_BAD_REGISTER_NUMBER;
if (mips_pcibios_config_access(PCI_ACCESS_READ, dev, where, &data))
return -1;
data = (data & ~(0xffff << ((where & 3) << 3))) |
(val << ((where & 3) << 3));
if (mips_pcibios_config_access(PCI_ACCESS_WRITE, dev, where, &data))
return -1;
return PCIBIOS_SUCCESSFUL;
}
static int
mips_pcibios_write_config_dword(struct pci_dev *dev, int where, u32 val)
{
if (where & 3)
return PCIBIOS_BAD_REGISTER_NUMBER;
if (mips_pcibios_config_access(PCI_ACCESS_WRITE, dev, where, &val))
return -1;
return PCIBIOS_SUCCESSFUL;
}
struct pci_ops mips_pci_ops = {
mips_pcibios_read_config_byte,
mips_pcibios_read_config_word,
mips_pcibios_read_config_dword,
mips_pcibios_write_config_byte,
mips_pcibios_write_config_word,
mips_pcibios_write_config_dword
};
void __init pcibios_init(void)
{
#ifdef CONFIG_MIPS_MALTA
struct pci_dev *pdev = NULL;
unsigned char reg_val;
#endif
printk("PCI: Probing PCI hardware on host bus 0.\n");
pci_scan_bus(0, &mips_pci_ops, NULL);
/*
* Due to a bug in the Galileo system controller, we need to setup
* the PCI BAR for the Galileo internal registers.
* This should be done in the bios/bootprom and will be fixed in
* a later revision of YAMON (the MIPS boards boot prom).
*/
GT_WRITE(GT_PCI0_CFGADDR_OFS,
(0 << GT_PCI0_CFGADDR_BUSNUM_SHF) | /* Local bus */
(0 << GT_PCI0_CFGADDR_DEVNUM_SHF) | /* GT64120 device */
(0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) | /* Function 0 */
((0x20/4) << GT_PCI0_CFGADDR_REGNUM_SHF) | /* BAR 4 */
GT_PCI0_CFGADDR_CONFIGEN_BIT );
/* Perform the write */
GT_WRITE( GT_PCI0_CFGDATA_OFS, CPHYSADDR(MIPS_GT_BASE));
#ifdef CONFIG_MIPS_MALTA
while ((pdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, pdev)) != NULL) {
if ((pdev->vendor == PCI_VENDOR_ID_INTEL)
&& (pdev->device == PCI_DEVICE_ID_INTEL_82371AB)
&& (PCI_SLOT(pdev->devfn) == 0x0a)) {
/*
* IDE Decode enable.
*/
pci_read_config_byte(pdev, 0x41, &reg_val);
pci_write_config_byte(pdev, 0x41, reg_val | 0x80);
pci_read_config_byte(pdev, 0x43, &reg_val);
pci_write_config_byte(pdev, 0x43, reg_val | 0x80);
}
if ((pdev->vendor == PCI_VENDOR_ID_INTEL)
&& (pdev->device == PCI_DEVICE_ID_INTEL_82371AB_0)
&& (PCI_SLOT(pdev->devfn) == 0x0a)) {
/*
* Set top of main memory accessible by ISA or DMA
* devices to 16 Mb.
*/
pci_read_config_byte(pdev, 0x69, &reg_val);
pci_write_config_byte(pdev, 0x69, reg_val | 0xf0);
}
}
/*
* Activate Floppy Controller in the SMSC FDC37M817 Super I/O
* Controller.
* This should be done in the bios/bootprom and will be fixed in
* a later revision of YAMON (the MIPS boards boot prom).
*/
/* Entering config state. */
SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
/* Activate floppy controller. */
SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
/* Exit config state. */
SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
#endif
}
int __init
pcibios_enable_device(struct pci_dev *dev)
{
/* Not needed, since we enable all devices at startup. */
return 0;
}
void __init
pcibios_align_resource(void *data, struct resource *res,
unsigned long size, unsigned long align)
{
}
char * __init
pcibios_setup(char *str)
{
/* Nothing to do for now. */
return str;
}
struct pci_fixup pcibios_fixups[] = {
{ 0 }
};
#warning pcibios_update_resource() is now a generic implementation - please check
unsigned __init int pcibios_assign_all_busses(void)
{
return 1;
}
/*
* Called after each bus is probed, but before its children
* are examined.
*/
void __init pcibios_fixup_bus(struct pci_bus *b)
{
pci_read_bridge_bases(b);
}
#endif /* CONFIG_PCI */
arch/mips64/mips-boards/generic/printf.c deleted 100644 → 0
View file @ a85be436
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Putting things on the screen/serial line using YAMONs facilities.
*
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/serialP.h>
#include <linux/serial_reg.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/serial.h>
#ifdef CONFIG_MIPS_ATLAS
/*
* Atlas registers are memory mapped on 64-bit aligned boundaries and
* only word access are allowed.
* When reading the UART 8 bit registers only the LSB are valid.
*/
unsigned int atlas_serial_in(struct async_struct *info, int offset)
{
return (*(volatile unsigned int *)(info->port + mips_io_port_base + offset*8) & 0xff);
}
void atlas_serial_out(struct async_struct *info, int offset, int value)
{
*(volatile unsigned int *)(info->port + mips_io_port_base + offset*8) = value;
}
#define serial_in atlas_serial_in
#define serial_out atlas_serial_out
#else
static unsigned int serial_in(struct async_struct *info, int offset)
{
return inb(info->port + offset);
}
static void serial_out(struct async_struct *info, int offset,
int value)
{
outb(value, info->port + offset);
}
#endif
static struct serial_state rs_table[] = {
SERIAL_PORT_DFNS /* Defined in serial.h */
};
/*
* Hooks to fake "prom" console I/O before devices
* are fully initialized.
*/
static struct async_struct prom_port_info = {0};
void __init setup_prom_printf(int tty_no) {
struct serial_state *ser = &rs_table[tty_no];
prom_port_info.state = ser;
prom_port_info.magic = SERIAL_MAGIC;
prom_port_info.port = ser->port;
prom_port_info.flags = ser->flags;
/* No setup of UART - assume YAMON left in sane state */
}
int putPromChar(char c)
{
if (!prom_port_info.state) { /* need to init device first */
return 0;
}
while ((serial_in(&prom_port_info, UART_LSR) & UART_LSR_THRE) == 0)
;
serial_out(&prom_port_info, UART_TX, c);
return 1;
}
char getPromChar(void)
{
if (!prom_port_info.state) { /* need to init device first */
return 0;
}
while (!(serial_in(&prom_port_info, UART_LSR) & 1))
;
return(serial_in(&prom_port_info, UART_RX));
}
static char buf[1024];
void __init prom_printf(char *fmt, ...)
{
va_list args;
int l;
char *p, *buf_end;
long flags;
int putPromChar(char);
/* Low level, brute force, not SMP safe... */
save_and_cli(flags);
va_start(args, fmt);
l = vsprintf(buf, fmt, args); /* hopefully i < sizeof(buf) */
va_end(args);
buf_end = buf + l;
for (p = buf; p < buf_end; p++) {
/* Crude cr/nl handling is better than none */
if(*p == '\n')putPromChar('\r');
putPromChar(*p);
}
restore_flags(flags);
}
arch/mips64/mips-boards/generic/time.c deleted 100644 → 0
View file @ a85be436
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Setting up the clock on the MIPS boards.
*
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/sched.h>
#include <linux/time.h>
#include <linux/spinlock.h>
#include <asm/mipsregs.h>
#include <asm/ptrace.h>
#include <linux/mc146818rtc.h>
#include <linux/timex.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/prom.h>
extern volatile unsigned long wall_jiffies;
static long last_rtc_update = 0;
unsigned long missed_heart_beats = 0;
static unsigned long r4k_offset; /* Amount to increment compare reg each time */
static unsigned long r4k_cur; /* What counter should be at next timer irq */
#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
#if defined(CONFIG_MIPS_ATLAS)
static char display_string[] = " LINUX ON ATLAS ";
#endif
#if defined(CONFIG_MIPS_MALTA)
static char display_string[] = " LINUX ON MALTA ";
#endif
static unsigned int display_count = 0;
#define MAX_DISPLAY_COUNT (sizeof(display_string) - 8)
static unsigned int timer_tick_count=0;
static inline void ack_r4ktimer(unsigned long newval)
{
write_32bit_cp0_register(CP0_COMPARE, newval);
}
/*
* In order to set the CMOS clock precisely, set_rtc_mmss has to be
* called 500 ms after the second nowtime has started, because when
* nowtime is written into the registers of the CMOS clock, it will
* jump to the next second precisely 500 ms later. Check the Motorola
* MC146818A or Dallas DS12887 data sheet for details.
*
* BUG: This routine does not handle hour overflow properly; it just
* sets the minutes. Usually you won't notice until after reboot!
*/
static int set_rtc_mmss(unsigned long nowtime)
{
int retval = 0;
int real_seconds, real_minutes, cmos_minutes;
unsigned char save_control, save_freq_select;
save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */
CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */
CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
cmos_minutes = CMOS_READ(RTC_MINUTES);
/*
* since we're only adjusting minutes and seconds,
* don't interfere with hour overflow. This avoids
* messing with unknown time zones but requires your
* RTC not to be off by more than 15 minutes
*/
real_seconds = nowtime % 60;
real_minutes = nowtime / 60;
if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
real_minutes += 30; /* correct for half hour time zone */
real_minutes %= 60;
if (abs(real_minutes - cmos_minutes) < 30) {
CMOS_WRITE(real_seconds,RTC_SECONDS);
CMOS_WRITE(real_minutes,RTC_MINUTES);
} else {
printk(KERN_WARNING
"set_rtc_mmss: can't update from %d to %d\n",
cmos_minutes, real_minutes);
retval = -1;
}
/* The following flags have to be released exactly in this order,
* otherwise the DS12887 (popular MC146818A clone with integrated
* battery and quartz) will not reset the oscillator and will not
* update precisely 500 ms later. You won't find this mentioned in
* the Dallas Semiconductor data sheets, but who believes data
* sheets anyway ... -- Markus Kuhn
*/
CMOS_WRITE(save_control, RTC_CONTROL);
CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
return retval;
}
/*
* There are a lot of conceptually broken versions of the MIPS timer interrupt
* handler floating around. This one is rather different, but the algorithm
* is provably more robust.
*/
void mips_timer_interrupt(struct pt_regs *regs)
{
unsigned long flags;
unsigned long seq;
int irq = 7;
if (r4k_offset == 0)
goto null;
do {
kstat_cpu(0).irqs[irq]++;
do_timer(regs);
/* Historical comment/code:
* RTC time of day s updated approx. every 11
* minutes. Because of how the numbers work out
* we need to make absolutely sure we do this update
* within 500ms before the * next second starts,
* thus the following code.
*/
do {
seq = read_seqbegin_irqsave(&xtime_lock, flags);
if ((time_status & STA_UNSYNC) == 0
&& xtime.tv_sec > last_rtc_update + 660
&& xtime.tv_usec >= 500000 - (tick >> 1)
&& xtime.tv_usec <= 500000 + (tick >> 1))
if (set_rtc_mmss(xtime.tv_sec) == 0)
last_rtc_update = xtime.tv_sec;
else
/* do it again in 60 s */
last_rtc_update = xtime.tv_sec - 600;
} while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
if ((timer_tick_count++ % HZ) == 0) {
mips_display_message(&display_string[display_count++]);
if (display_count == MAX_DISPLAY_COUNT)
display_count = 0;
}
r4k_cur += r4k_offset;
ack_r4ktimer(r4k_cur);
} while (((unsigned int)read_32bit_cp0_register(CP0_COUNT)
- (unsigned int)r4k_cur) < 0x7fffffff);
return;
null:
ack_r4ktimer(0);
}
/*
* Figure out the r4k offset, the amount to increment the compare
* register for each time tick.
* Use the RTC to calculate offset.
*/
static unsigned long __init cal_r4koff(void)
{
unsigned long count;
unsigned int flags;
local_irq_save(flags);
/* Start counter exactly on falling edge of update flag */
while (CMOS_READ(RTC_REG_A) & RTC_UIP);
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
/* Start r4k counter. */
write_32bit_cp0_register(CP0_COUNT, 0);
/* Read counter exactly on falling edge of update flag */
while (CMOS_READ(RTC_REG_A) & RTC_UIP);
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
count = read_32bit_cp0_register(CP0_COUNT);
/* restore interrupts */
local_irq_restore(flags);
return (count / HZ);
}
static unsigned long __init get_mips_time(void)
{
unsigned int year, mon, day, hour, min, sec;
unsigned char save_control;
save_control = CMOS_READ(RTC_CONTROL);
/* Freeze it. */
CMOS_WRITE(save_control | RTC_SET, RTC_CONTROL);
/* Read regs. */
sec = CMOS_READ(RTC_SECONDS);
min = CMOS_READ(RTC_MINUTES);
hour = CMOS_READ(RTC_HOURS);
if (!(save_control & RTC_24H))
{
if ((hour & 0xf) == 0xc)
hour &= 0x80;
if (hour & 0x80)
hour = (hour & 0xf) + 12;
}
day = CMOS_READ(RTC_DAY_OF_MONTH);
mon = CMOS_READ(RTC_MONTH);
year = CMOS_READ(RTC_YEAR);
/* Unfreeze clock. */
CMOS_WRITE(save_control, RTC_CONTROL);
if ((year += 1900) < 1970)
year += 100;
return mktime(year, mon, day, hour, min, sec);
}
void __init time_init(void)
{
unsigned int est_freq, flags;
/* Set Data mode - binary. */
CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
printk("calculating r4koff... ");
r4k_offset = cal_r4koff();
printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
est_freq = 2*r4k_offset*HZ;
est_freq += 5000; /* round */
est_freq -= est_freq%10000;
printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
(est_freq%1000000)*100/1000000);
r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset);
write_32bit_cp0_register(CP0_COMPARE, r4k_cur);
set_cp0_status(ST0_IM, ALLINTS);
/* Read time from the RTC chipset. */
write_seqlock_irqsave (&xtime_lock, flags);
xtime.tv_sec = get_mips_time();
xtime.tv_usec = 0;
write_sequnlock_irqrestore(&xtime_lock, flags);
}
/* This is for machines which generate the exact clock. */
#define USECS_PER_JIFFY (1000000/HZ)
#define USECS_PER_JIFFY_FRAC (0x100000000*1000000/HZ&0xffffffff)
/* Cycle counter value at the previous timer interrupt.. */
static unsigned int timerhi = 0, timerlo = 0;
/*
* FIXME: Does playing with the RP bit in c0_status interfere with this code?
*/
static unsigned long do_fast_gettimeoffset(void)
{
u32 count;
unsigned long res, tmp;
/* Last jiffy when do_fast_gettimeoffset() was called. */
static unsigned long last_jiffies=0;
unsigned long quotient;
/*
* Cached "1/(clocks per usec)*2^32" value.
* It has to be recalculated once each jiffy.
*/
static unsigned long cached_quotient=0;
tmp = jiffies;
quotient = cached_quotient;
if (tmp && last_jiffies != tmp) {
last_jiffies = tmp;
__asm__(".set\tnoreorder\n\t"
".set\tnoat\n\t"
".set\tmips3\n\t"
"lwu\t%0,%2\n\t"
"dsll32\t$1,%1,0\n\t"
"or\t$1,$1,%0\n\t"
"ddivu\t$0,$1,%3\n\t"
"mflo\t$1\n\t"
"dsll32\t%0,%4,0\n\t"
"nop\n\t"
"ddivu\t$0,%0,$1\n\t"
"mflo\t%0\n\t"
".set\tmips0\n\t"
".set\tat\n\t"
".set\treorder"
:"=&r" (quotient)
:"r" (timerhi),
"m" (timerlo),
"r" (tmp),
"r" (USECS_PER_JIFFY)
:"$1");
cached_quotient = quotient;
}
/* Get last timer tick in absolute kernel time */
count = read_32bit_cp0_register(CP0_COUNT);
/* .. relative to previous jiffy (32 bits is enough) */
count -= timerlo;
__asm__("multu\t%1,%2\n\t"
"mfhi\t%0"
:"=r" (res)
:"r" (count),
"r" (quotient));
/*
* Due to possible jiffies inconsistencies, we need to check
* the result so that we'll get a timer that is monotonic.
*/
if (res >= USECS_PER_JIFFY)
res = USECS_PER_JIFFY-1;
return res;
}
void do_gettimeofday(struct timeval *tv)
{
unsigned long flags;
unsigned long seq;
do {
seq = read_seqbegin_irqsave(&xtime_lock, flags);
*tv = xtime;
tv->tv_usec += do_fast_gettimeoffset();
/*
* xtime is atomically updated in timer_bh.
* jiffies - wall_jiffies
* is nonzero if the timer bottom half hasnt executed yet.
*/
if (jiffies - wall_jiffies)
tv->tv_usec += USECS_PER_JIFFY;
} while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
if (tv->tv_usec >= 1000000) {
tv->tv_usec -= 1000000;
tv->tv_sec++;
}
}
void do_settimeofday(struct timeval *tv)
{
write_seqlock_irq (&xtime_lock);
/* This is revolting. We need to set the xtime.tv_usec correctly.
* However, the value in this location is is value at the last tick.
* Discover what correction gettimeofday would have done, and then
* undo it!
*/
tv->tv_usec -= do_fast_gettimeoffset();
if (tv->tv_usec < 0) {
tv->tv_usec += 1000000;
tv->tv_sec--;
}
xtime = *tv;
time_adjust = 0; /* stop active adjtime() */
time_status |= STA_UNSYNC;
time_maxerror = NTP_PHASE_LIMIT;
time_esterror = NTP_PHASE_LIMIT;
write_sequnlock_irq (&xtime_lock);
}
arch/mips64/mips-boards/malta/malta_int.c deleted 100644 → 0
View file @ a85be436
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Routines for generic manipulation of the interrupts found on the MIPS
* Malta board.
* The interrupt controller is located in the South Bridge a PIIX4 device
* with two internal 82C95 interrupt controllers.
*
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/random.h>
#include <linux/seq_file.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/mips-boards/malta.h>
#include <asm/mips-boards/maltaint.h>
#include <asm/mips-boards/piix4.h>
#include <asm/mips-boards/gt64120.h>
#include <asm/mips-boards/generic.h>
extern asmlinkage void mipsIRQ(void);
unsigned int local_bh_count[NR_CPUS];
unsigned int local_irq_count[NR_CPUS];
unsigned long spurious_count = 0;
static struct irqaction *hw0_irq_action[MALTAINT_END] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL
};
static struct irqaction r4ktimer_action = {
NULL, 0, 0, "R4000 timer/counter", NULL, NULL,
};
static struct irqaction *irq_action[8] = {
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, &r4ktimer_action
};
#if 0
#define DEBUG_INT(x...) printk(x)
#else
#define DEBUG_INT(x...)
#endif
/*
* This contains the interrupt mask for both 82C59 interrupt controllers.
*/
static unsigned int cached_int_mask = 0xffff;
void disable_irq(unsigned int irq_nr)
{
unsigned long flags;
if(irq_nr >= MALTAINT_END) {
printk("whee, invalid irq_nr %d\n", irq_nr);
panic("IRQ, you lose...");
}
save_and_cli(flags);
cached_int_mask |= (1 << irq_nr);
if (irq_nr & 8) {
outb((cached_int_mask >> 8) & 0xff, PIIX4_ICTLR2_OCW1);
} else {
outb(cached_int_mask & 0xff, PIIX4_ICTLR1_OCW1);
}
restore_flags(flags);
}
void enable_irq(unsigned int irq_nr)
{
unsigned long flags;
if(irq_nr >= MALTAINT_END) {
printk("whee, invalid irq_nr %d\n", irq_nr);
panic("IRQ, you lose...");
}
save_and_cli(flags);
cached_int_mask &= ~(1 << irq_nr);
if (irq_nr & 8) {
outb((cached_int_mask >> 8) & 0xff, PIIX4_ICTLR2_OCW1);
/* Enable irq 2 (cascade interrupt). */
cached_int_mask &= ~(1 << 2);
outb(cached_int_mask & 0xff, PIIX4_ICTLR1_OCW1);
} else {
outb(cached_int_mask & 0xff, PIIX4_ICTLR1_OCW1);
}
restore_flags(flags);
}
int show_interrupts(struct seq_file *p, void *v)
{
int i;
int num = 0;
struct irqaction *action;
unsigned long flags;
for (i = 0; i < 8; i++, num++) {
local_irq_save(flags);
action = irq_action[i];
if (!action)
goto skip_1;
seq_printf(p, "%2d: %8d %c %s",
num, kstat_cpu(0).irqs[num],
(action->flags & SA_INTERRUPT) ? '+' : ' ',
action->name);
for (action=action->next; action; action = action->next) {
seq_printf(p, ",%s %s",
(action->flags & SA_INTERRUPT) ? " +" : "",
action->name);
}
seq_puts(p, " [on-chip]\n");
skip_1:
local_irq_restore(flags);
}
for (i = 0; i < MALTAINT_END; i++, num++) {
local_irq_save(flags);
action = hw0_irq_action[i];
if (!action)
goto skip_2;
seq_printf(p, "%2d: %8d %c %s",
num, kstat_cpu(0).irqs[num],
(action->flags & SA_INTERRUPT) ? '+' : ' ',
action->name);
for (action=action->next; action; action = action->next) {
seq_printf(p, ",%s %s",
(action->flags & SA_INTERRUPT) ? " +" : "",
action->name);
}
seq_puts(p, " [hw0]\n");
skip_2:
local_irq_restore(flags);
}
return 0;
}
int request_irq(unsigned int irq,
void (*handler)(int, void *, struct pt_regs *),
unsigned long irqflags,
const char * devname,
void *dev_id)
{
struct irqaction *action;
int retval;
DEBUG_INT("request_irq: irq=%d, devname = %s\n", irq, devname);
if (irq >= MALTAINT_END)
return -EINVAL;
if (!handler)
return -EINVAL;
action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
if(!action)
return -ENOMEM;
action->handler = handler;
action->flags = irqflags;
action->mask = 0;
action->name = devname;
action->dev_id = dev_id;
action->next = 0;
retval = setup_irq(irq, action);
if (retval)
kfree(action);
return retval;
}
void free_irq(unsigned int irq, void *dev_id)
{
struct irqaction *action, **p;
if (irq >= MALTAINT_END) {
printk("Trying to free IRQ%d\n",irq);
return;
}
for (p = &hw0_irq_action[irq]; (action = *p) != NULL;
p = &action->next)
{
if (action->dev_id != dev_id)
continue;
/* Found it - now free it */
*p = action->next;
kfree(action);
if (!hw0_irq_action[irq])
disable_irq(irq);
return;
}
printk("Trying to free IRQ%d\n",irq);
}
void __init init_IRQ(void)
{
irq_setup();
}
static int setup_irq(unsigned int irq, struct irqaction * new)
{
int shared = 0;
struct irqaction *old, **p;
p = &hw0_irq_action[irq];
if ((old = *p) != NULL) {
/* Can't share interrupts unless both agree to */
if (!(old->flags & new->flags & SA_SHIRQ))
return -EBUSY;
/* Can't share interrupts unless both are same type */
if ((old->flags ^ new->flags) & SA_INTERRUPT)
return -EBUSY;
/* add new interrupt at end of irq queue */
do {
p = &old->next;
old = *p;
} while (old);
shared = 1;
}
if (new->flags & SA_SAMPLE_RANDOM)
rand_initialize_irq(irq);
*p = new;
if (!shared)
enable_irq(irq);
return 0;
}
static inline int get_int(int *irq)
{
/*
* Determine highest priority pending interrupt by performing
* a PCI Interrupt Acknowledge cycle.
*/
GT_READ(GT_PCI0_IACK_OFS, *irq);
*irq &= 0xFF;
/*
* IRQ7 is used to detect spurious interrupts.
* The interrupt acknowledge cycle returns IRQ7, if no
* interrupts is requested.
* We can differentiate between this situation and a
* "Normal" IRQ7 by reading the ISR.
*/
if (*irq == 7)
{
outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR, PIIX4_ICTLR1_OCW3);
if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7)))
return -1; /* Spurious interrupt. */
}
return 0;
}
static inline void ack_int(int irq)
{
if (irq & 8) {
/* Specific EOI to cascade */
outb(PIIX4_OCW2_SEL | PIIX4_OCW2_NSEOI | PIIX4_OCW2_ILS_2,
PIIX4_ICTLR1_OCW2);
/* Non specific EOI to cascade */
outb(PIIX4_OCW2_SEL | PIIX4_OCW2_NSEOI, PIIX4_ICTLR2_OCW2);
} else {
/* Non specific EOI to cascade */
outb(PIIX4_OCW2_SEL | PIIX4_OCW2_NSEOI, PIIX4_ICTLR1_OCW2);
}
}
void malta_hw0_irqdispatch(struct pt_regs *regs)
{
struct irqaction *action;
int irq=0, cpu = smp_processor_id();
DEBUG_INT("malta_hw0_irqdispatch\n");
if (get_int(&irq))
return; /* interrupt has already been cleared */
disable_irq(irq);
ack_int(irq);
DEBUG_INT("malta_hw0_irqdispatch: irq=%d\n", irq);
action = hw0_irq_action[irq];
/*
* if action == NULL, then we don't have a handler
* for the irq
*/
if ( action == NULL )
return;
irq_enter(cpu, irq);
kstat_cpu(0).irqs[irq + 8]++;
do {
action->handler(irq, action->dev_id, regs);
action = action->next;
} while (action);
enable_irq(irq);
irq_exit(cpu, irq);
}
unsigned long probe_irq_on (void)
{
unsigned int i, irqs = 0;
unsigned long delay;
/* first, enable any unassigned irqs */
for (i = MALTAINT_END-1; i > 0; i--) {
if (!hw0_irq_action[i]) {
enable_irq(i);
irqs |= (1 << i);
}
}
/* wait for spurious interrupts to mask themselves out again */
for (delay = jiffies + HZ/10; time_before(jiffies, delay); )
/* about 100ms delay */;
/* now filter out any obviously spurious interrupts */
return irqs & ~cached_int_mask;
}
int probe_irq_off (unsigned long irqs)
{
unsigned int i;
irqs &= cached_int_mask;
if (!irqs)
return 0;
i = ffz(~irqs);
if (irqs != (irqs & (1 << i)))
i = -i;
return i;
}
void __init maltaint_init(void)
{
/*
* Mask out all interrupt by writing "1" to all bit position in
* the IMR register.
*/
outb(cached_int_mask & 0xff, PIIX4_ICTLR1_OCW1);
outb((cached_int_mask >> 8) & 0xff, PIIX4_ICTLR2_OCW1);
/* Now safe to set the exception vector. */
set_except_vector(0, mipsIRQ);
}
arch/mips64/mips-boards/malta/malta_setup.c deleted 100644 → 0
View file @ a85be436
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Malta specific setup, including init of the feature struct.
*
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/mc146818rtc.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#ifdef CONFIG_BLK_DEV_IDE
#include <linux/ide.h>
#endif
#include <asm/cpu.h>
#include <asm/bootinfo.h>
#include <asm/irq.h>
#include <asm/mips-boards/generic.h>
#include <asm/mips-boards/prom.h>
#include <asm/mips-boards/gt64120.h>
#include <asm/mips-boards/malta.h>
#include <asm/mips-boards/maltaint.h>
#ifdef CONFIG_BLK_DEV_FD
#include <asm/floppy.h>
#endif
#include <asm/dma.h>
#include <asm/mmu_context.h>
#if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_PROM_CONSOLE)
extern void console_setup(char *, int *);
char serial_console[20];
#endif
#ifdef CONFIG_REMOTE_DEBUG
extern void set_debug_traps(void);
extern void rs_kgdb_hook(int);
extern void breakpoint(void);
static int remote_debug = 0;
#endif
#ifdef CONFIG_BLK_DEV_IDE
extern struct ide_ops std_ide_ops;
#endif
#ifdef CONFIG_BLK_DEV_FD
extern struct fd_ops std_fd_ops;
#endif
extern struct rtc_ops malta_rtc_ops;
extern void mips_reboot_setup(void);
struct resource standard_io_resources[] = {
{ "dma1", 0x00, 0x1f, IORESOURCE_BUSY },
{ "pic1", 0x20, 0x3f, IORESOURCE_BUSY },
{ "timer", 0x40, 0x5f, IORESOURCE_BUSY },
{ "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY },
{ "pic2", 0xa0, 0xbf, IORESOURCE_BUSY },
{ "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
};
#define STANDARD_IO_RESOURCES (sizeof(standard_io_resources)/sizeof(struct resource))
static void __init malta_irq_setup(void)
{
maltaint_init();
#ifdef CONFIG_REMOTE_DEBUG
if (remote_debug) {
set_debug_traps();
breakpoint();
}
#endif
}
void __init malta_setup(void)
{
#ifdef CONFIG_REMOTE_DEBUG
int rs_putDebugChar(char);
char rs_getDebugChar(void);
extern int (*putDebugChar)(char);
extern char (*getDebugChar)(void);
#endif
char *argptr;
int i;
current_cpu_data.asid_cache = ASID_FIRST_VERSION;
TLBMISS_HANDLER_SETUP();
irq_setup = malta_irq_setup;
/* Request I/O space for devices used on the Malta board. */
for (i = 0; i < STANDARD_IO_RESOURCES; i++)
request_resource(&ioport_resource, standard_io_resources+i);
/*
* Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
*/
enable_dma(4);
#ifdef CONFIG_SERIAL_CONSOLE
argptr = prom_getcmdline();
if ((argptr = strstr(argptr, "console=ttyS0")) == NULL)
{
int i=0;
char *s = prom_getenv("modetty0");
while(s[i] >= '0' && s[i] <= '9')
i++;
strcpy(serial_console, "ttyS0,");
strncpy(serial_console + 6, s, i);
prom_printf("Config serial console: %s\n", serial_console);
console_setup(serial_console, NULL);
}
#endif
#ifdef CONFIG_REMOTE_DEBUG
argptr = prom_getcmdline();
if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
int line;
argptr += strlen("kgdb=ttyS");
if (*argptr != '0' && *argptr != '1')
printk("KGDB: Uknown serial line /dev/ttyS%c, "
"falling back to /dev/ttyS1\n", *argptr);
line = *argptr == '0' ? 0 : 1;
printk("KGDB: Using serial line /dev/ttyS%d for session\n",
line ? 1 : 0);
rs_kgdb_hook(line);
putDebugChar = rs_putDebugChar;
getDebugChar = rs_getDebugChar;
prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
"please connect your debugger\n", line ? 1 : 0);
remote_debug = 1;
/* Breakpoints and stuff are in malta_irq_setup() */
}
#endif
argptr = prom_getcmdline();
if ((argptr = strstr(argptr, "nofpu")) != NULL)
mips_cpu.options &= ~MIPS_CPU_FPU;
rtc_ops = &malta_rtc_ops;
#ifdef CONFIG_BLK_DEV_IDE
ide_ops = &std_ide_ops;
#endif
#ifdef CONFIG_BLK_DEV_FD
fd_ops = &std_fd_ops;
#endif
}
include/asm-mips/mips-boards/bonito64.h 0 → 100644
View file @ 5d3adbe2
/*
* bonito.h
*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2001 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This file is the original bonito.h from Algorithmics with minor changes
* to fit into linux.
*/
/*
* Bonito Register Map
* Copyright (c) 1999 Algorithmics Ltd
*
* Algorithmics gives permission for anyone to use and modify this file
* without any obligation or license condition except that you retain
* this copyright message in any source redistribution in whole or part.
*
* Updated copies of this and other files can be found at
* ftp://ftp.algor.co.uk/pub/bonito/
*
* Users of the Bonito controller are warmly recommended to contribute
* any useful changes back to Algorithmics (mail to bonito@algor.co.uk).
*/
/* Revision 1.48 autogenerated on 08/17/99 15:20:01 */
/* This bonito64 version editted from bonito.h Revision 1.48 on 11/09/00 */
#ifndef _ASM_MIPS_BOARDS_BONITO64_H
#define _ASM_MIPS_BOARDS_BONITO64_H
#ifdef __ASSEMBLY__
/* offsets from base register */
#define BONITO(x) (x)
#else /* !__ASSEMBLY__ */
/* offsets from base pointer, this construct allows optimisation */
/* static char * const _bonito = PA_TO_KVA1(BONITO_BASE); */
#define BONITO(x) *(volatile u32 *)(_bonito + (x))
#endif /* __ASSEMBLY__ */
#define BONITO_BOOT_BASE 0x1fc00000
#define BONITO_BOOT_SIZE 0x00100000
#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)
#define BONITO_FLASH_BASE 0x1c000000
#define BONITO_FLASH_SIZE 0x03000000
#define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
#define BONITO_SOCKET_BASE 0x1f800000
#define BONITO_SOCKET_SIZE 0x00400000
#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)
#define BONITO_REG_BASE 0x1fe00000
#define BONITO_REG_SIZE 0x00040000
#define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1)
#define BONITO_DEV_BASE 0x1ff00000
#define BONITO_DEV_SIZE 0x00100000
#define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
#define BONITO_PCILO_BASE 0x10000000
#define BONITO_PCILO_SIZE 0x0c000000
#define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1)
#define BONITO_PCILO0_BASE 0x10000000
#define BONITO_PCILO1_BASE 0x14000000
#define BONITO_PCILO2_BASE 0x18000000
#define BONITO_PCIHI_BASE 0x20000000
#define BONITO_PCIHI_SIZE 0x20000000
#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
#define BONITO_PCIIO_BASE 0x1fd00000
#define BONITO_PCIIO_SIZE 0x00100000
#define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1)
#define BONITO_PCICFG_BASE 0x1fe80000
#define BONITO_PCICFG_SIZE 0x00080000
#define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1)
/* Bonito Register Bases */
#define BONITO_PCICONFIGBASE 0x00
#define BONITO_REGBASE 0x100
/* PCI Configuration Registers */
#define BONITO_PCI_REG(x) BONITO(BONITO_PCICONFIGBASE + (x))
#define BONITO_PCIDID BONITO_PCI_REG(0x00)
#define BONITO_PCICMD BONITO_PCI_REG(0x04)
#define BONITO_PCICLASS BONITO_PCI_REG(0x08)
#define BONITO_PCILTIMER BONITO_PCI_REG(0x0c)
#define BONITO_PCIBASE0 BONITO_PCI_REG(0x10)
#define BONITO_PCIBASE1 BONITO_PCI_REG(0x14)
#define BONITO_PCIBASE2 BONITO_PCI_REG(0x18)
#define BONITO_PCIEXPRBASE BONITO_PCI_REG(0x30)
#define BONITO_PCIINT BONITO_PCI_REG(0x3c)
#define BONITO_PCICMD_PERR_CLR 0x80000000
#define BONITO_PCICMD_SERR_CLR 0x40000000
#define BONITO_PCICMD_MABORT_CLR 0x20000000
#define BONITO_PCICMD_MTABORT_CLR 0x10000000
#define BONITO_PCICMD_TABORT_CLR 0x08000000
#define BONITO_PCICMD_MPERR_CLR 0x01000000
#define BONITO_PCICMD_PERRRESPEN 0x00000040
#define BONITO_PCICMD_ASTEPEN 0x00000080
#define BONITO_PCICMD_SERREN 0x00000100
#define BONITO_PCILTIMER_BUSLATENCY 0x0000ff00
#define BONITO_PCILTIMER_BUSLATENCY_SHIFT 8
/* 1. Bonito h/w Configuration */
/* Power on register */
#define BONITO_BONPONCFG BONITO(BONITO_REGBASE + 0x00)
#define BONITO_BONPONCFG_SYSCONTROLLERRD 0x00040000
#define BONITO_BONPONCFG_ROMCS1SAMP 0x00020000
#define BONITO_BONPONCFG_ROMCS0SAMP 0x00010000
#define BONITO_BONPONCFG_CPUBIGEND 0x00004000
/* Added by RPF 11-9-00 */
#define BONITO_BONPONCFG_BURSTORDER 0x00001000
/* --- */
#define BONITO_BONPONCFG_CPUPARITY 0x00002000
#define BONITO_BONPONCFG_CPUTYPE 0x00000007
#define BONITO_BONPONCFG_CPUTYPE_SHIFT 0
#define BONITO_BONPONCFG_PCIRESET_OUT 0x00000008
#define BONITO_BONPONCFG_IS_ARBITER 0x00000010
#define BONITO_BONPONCFG_ROMBOOT 0x000000c0
#define BONITO_BONPONCFG_ROMBOOT_SHIFT 6
#define BONITO_BONPONCFG_ROMBOOT_FLASH (0x0<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
#define BONITO_BONPONCFG_ROMBOOT_SOCKET (0x1<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
#define BONITO_BONPONCFG_ROMBOOT_SDRAM (0x2<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
#define BONITO_BONPONCFG_ROMBOOT_CPURESET (0x3<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
#define BONITO_BONPONCFG_ROMCS0WIDTH 0x00000100
#define BONITO_BONPONCFG_ROMCS1WIDTH 0x00000200
#define BONITO_BONPONCFG_ROMCS0FAST 0x00000400
#define BONITO_BONPONCFG_ROMCS1FAST 0x00000800
#define BONITO_BONPONCFG_CONFIG_DIS 0x00000020
/* Other Bonito configuration */
#define BONITO_BONGENCFG_OFFSET 0x4
#define BONITO_BONGENCFG BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET)
#define BONITO_BONGENCFG_DEBUGMODE 0x00000001
#define BONITO_BONGENCFG_SNOOPEN 0x00000002
#define BONITO_BONGENCFG_CPUSELFRESET 0x00000004
#define BONITO_BONGENCFG_FORCE_IRQA 0x00000008
#define BONITO_BONGENCFG_IRQA_ISOUT 0x00000010
#define BONITO_BONGENCFG_IRQA_FROM_INT1 0x00000020
#define BONITO_BONGENCFG_BYTESWAP 0x00000040
#define BONITO_BONGENCFG_UNCACHED 0x00000080
#define BONITO_BONGENCFG_PREFETCHEN 0x00000100
#define BONITO_BONGENCFG_WBEHINDEN 0x00000200
#define BONITO_BONGENCFG_CACHEALG 0x00000c00
#define BONITO_BONGENCFG_CACHEALG_SHIFT 10
#define BONITO_BONGENCFG_PCIQUEUE 0x00001000
#define BONITO_BONGENCFG_CACHESTOP 0x00002000
#define BONITO_BONGENCFG_MSTRBYTESWAP 0x00004000
#define BONITO_BONGENCFG_BUSERREN 0x00008000
#define BONITO_BONGENCFG_NORETRYTIMEOUT 0x00010000
#define BONITO_BONGENCFG_SHORTCOPYTIMEOUT 0x00020000
/* 2. IO & IDE configuration */
#define BONITO_IODEVCFG BONITO(BONITO_REGBASE + 0x08)
/* 3. IO & IDE configuration */
#define BONITO_SDCFG BONITO(BONITO_REGBASE + 0x0c)
/* 4. PCI address map control */
#define BONITO_PCIMAP BONITO(BONITO_REGBASE + 0x10)
#define BONITO_PCIMEMBASECFG BONITO(BONITO_REGBASE + 0x14)
#define BONITO_PCIMAP_CFG BONITO(BONITO_REGBASE + 0x18)
/* 5. ICU & GPIO regs */
/* GPIO Regs - r/w */
#define BONITO_GPIODATA_OFFSET 0x1c
#define BONITO_GPIODATA BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET)
#define BONITO_GPIOIE BONITO(BONITO_REGBASE + 0x20)
/* ICU Configuration Regs - r/w */
#define BONITO_INTEDGE BONITO(BONITO_REGBASE + 0x24)
#define BONITO_INTSTEER BONITO(BONITO_REGBASE + 0x28)
#define BONITO_INTPOL BONITO(BONITO_REGBASE + 0x2c)
/* ICU Enable Regs - IntEn & IntISR are r/o. */
#define BONITO_INTENSET BONITO(BONITO_REGBASE + 0x30)
#define BONITO_INTENCLR BONITO(BONITO_REGBASE + 0x34)
#define BONITO_INTEN BONITO(BONITO_REGBASE + 0x38)
#define BONITO_INTISR BONITO(BONITO_REGBASE + 0x3c)
/* PCI mail boxes */
#define BONITO_PCIMAIL0_OFFSET 0x40
#define BONITO_PCIMAIL1_OFFSET 0x44
#define BONITO_PCIMAIL2_OFFSET 0x48
#define BONITO_PCIMAIL3_OFFSET 0x4c
#define BONITO_PCIMAIL0 BONITO(BONITO_REGBASE + 0x40)
#define BONITO_PCIMAIL1 BONITO(BONITO_REGBASE + 0x44)
#define BONITO_PCIMAIL2 BONITO(BONITO_REGBASE + 0x48)
#define BONITO_PCIMAIL3 BONITO(BONITO_REGBASE + 0x4c)
/* 6. PCI cache */
#define BONITO_PCICACHECTRL BONITO(BONITO_REGBASE + 0x50)
#define BONITO_PCICACHETAG BONITO(BONITO_REGBASE + 0x54)
#define BONITO_PCIBADADDR BONITO(BONITO_REGBASE + 0x58)
#define BONITO_PCIMSTAT BONITO(BONITO_REGBASE + 0x5c)
/*
#define BONITO_PCIRDPOST BONITO(BONITO_REGBASE + 0x60)
#define BONITO_PCIDATA BONITO(BONITO_REGBASE + 0x64)
*/
/* 7. IDE DMA & Copier */
#define BONITO_CONFIGBASE 0x000
#define BONITO_BONITOBASE 0x100
#define BONITO_LDMABASE 0x200
#define BONITO_COPBASE 0x300
#define BONITO_REG_BLOCKMASK 0x300
#define BONITO_LDMACTRL BONITO(BONITO_LDMABASE + 0x0)
#define BONITO_LDMASTAT BONITO(BONITO_LDMABASE + 0x0)
#define BONITO_LDMAADDR BONITO(BONITO_LDMABASE + 0x4)
#define BONITO_LDMAGO BONITO(BONITO_LDMABASE + 0x8)
#define BONITO_LDMADATA BONITO(BONITO_LDMABASE + 0xc)
#define BONITO_COPCTRL BONITO(BONITO_COPBASE + 0x0)
#define BONITO_COPSTAT BONITO(BONITO_COPBASE + 0x0)
#define BONITO_COPPADDR BONITO(BONITO_COPBASE + 0x4)
#define BONITO_COPDADDR BONITO(BONITO_COPBASE + 0x8)
#define BONITO_COPGO BONITO(BONITO_COPBASE + 0xc)
/* ###### Bit Definitions for individual Registers #### */
/* Gen DMA. */
#define BONITO_IDECOPDADDR_DMA_DADDR 0x0ffffffc
#define BONITO_IDECOPDADDR_DMA_DADDR_SHIFT 2
#define BONITO_IDECOPPADDR_DMA_PADDR 0xfffffffc
#define BONITO_IDECOPPADDR_DMA_PADDR_SHIFT 2
#define BONITO_IDECOPGO_DMA_SIZE 0x0000fffe
#define BONITO_IDECOPGO_DMA_SIZE_SHIFT 0
#define BONITO_IDECOPGO_DMA_WRITE 0x00010000
#define BONITO_IDECOPGO_DMAWCOUNT 0x000f0000
#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT 16
#define BONITO_IDECOPCTRL_DMA_STARTBIT 0x80000000
#define BONITO_IDECOPCTRL_DMA_RSTBIT 0x40000000
/* DRAM - sdCfg */
#define BONITO_SDCFG_AROWBITS 0x00000003
#define BONITO_SDCFG_AROWBITS_SHIFT 0
#define BONITO_SDCFG_ACOLBITS 0x0000000c
#define BONITO_SDCFG_ACOLBITS_SHIFT 2
#define BONITO_SDCFG_ABANKBIT 0x00000010
#define BONITO_SDCFG_ASIDES 0x00000020
#define BONITO_SDCFG_AABSENT 0x00000040
#define BONITO_SDCFG_AWIDTH64 0x00000080
#define BONITO_SDCFG_BROWBITS 0x00000300
#define BONITO_SDCFG_BROWBITS_SHIFT 8
#define BONITO_SDCFG_BCOLBITS 0x00000c00
#define BONITO_SDCFG_BCOLBITS_SHIFT 10
#define BONITO_SDCFG_BBANKBIT 0x00001000
#define BONITO_SDCFG_BSIDES 0x00002000
#define BONITO_SDCFG_BABSENT 0x00004000
#define BONITO_SDCFG_BWIDTH64 0x00008000
#define BONITO_SDCFG_EXTRDDATA 0x00010000
#define BONITO_SDCFG_EXTRASCAS 0x00020000
#define BONITO_SDCFG_EXTPRECH 0x00040000
#define BONITO_SDCFG_EXTRASWIDTH 0x00180000
#define BONITO_SDCFG_EXTRASWIDTH_SHIFT 19
/* Changed by RPF 11-9-00 */
#define BONITO_SDCFG_DRAMMODESET 0x00200000
/* --- */
#define BONITO_SDCFG_DRAMEXTREGS 0x00400000
#define BONITO_SDCFG_DRAMPARITY 0x00800000
/* Added by RPF 11-9-00 */
#define BONITO_SDCFG_DRAMBURSTLEN 0x03000000
#define BONITO_SDCFG_DRAMBURSTLEN_SHIFT 24
#define BONITO_SDCFG_DRAMMODESET_DONE 0x80000000
/* --- */
/* PCI Cache - pciCacheCtrl */
#define BONITO_PCICACHECTRL_CACHECMD 0x00000007
#define BONITO_PCICACHECTRL_CACHECMD_SHIFT 0
#define BONITO_PCICACHECTRL_CACHECMDLINE 0x00000018
#define BONITO_PCICACHECTRL_CACHECMDLINE_SHIFT 3
#define BONITO_PCICACHECTRL_CMDEXEC 0x00000020
#define BONITO_IODEVCFG_BUFFBIT_CS0 0x00000001
#define BONITO_IODEVCFG_SPEEDBIT_CS0 0x00000002
#define BONITO_IODEVCFG_MOREABITS_CS0 0x00000004
#define BONITO_IODEVCFG_BUFFBIT_CS1 0x00000008
#define BONITO_IODEVCFG_SPEEDBIT_CS1 0x00000010
#define BONITO_IODEVCFG_MOREABITS_CS1 0x00000020
#define BONITO_IODEVCFG_BUFFBIT_CS2 0x00000040
#define BONITO_IODEVCFG_SPEEDBIT_CS2 0x00000080
#define BONITO_IODEVCFG_MOREABITS_CS2 0x00000100
#define BONITO_IODEVCFG_BUFFBIT_CS3 0x00000200
#define BONITO_IODEVCFG_SPEEDBIT_CS3 0x00000400
#define BONITO_IODEVCFG_MOREABITS_CS3 0x00000800
#define BONITO_IODEVCFG_BUFFBIT_IDE 0x00001000
#define BONITO_IODEVCFG_SPEEDBIT_IDE 0x00002000
#define BONITO_IODEVCFG_WORDSWAPBIT_IDE 0x00004000
#define BONITO_IODEVCFG_MODEBIT_IDE 0x00008000
#define BONITO_IODEVCFG_DMAON_IDE 0x001f0000
#define BONITO_IODEVCFG_DMAON_IDE_SHIFT 16
#define BONITO_IODEVCFG_DMAOFF_IDE 0x01e00000
#define BONITO_IODEVCFG_DMAOFF_IDE_SHIFT 21
#define BONITO_IODEVCFG_EPROMSPLIT 0x02000000
/* Added by RPF 11-9-00 */
#define BONITO_IODEVCFG_CPUCLOCKPERIOD 0xfc000000
#define BONITO_IODEVCFG_CPUCLOCKPERIOD_SHIFT 26
/* --- */
/* gpio */
#define BONITO_GPIO_GPIOW 0x000003ff
#define BONITO_GPIO_GPIOW_SHIFT 0
#define BONITO_GPIO_GPIOR 0x01ff0000
#define BONITO_GPIO_GPIOR_SHIFT 16
#define BONITO_GPIO_GPINR 0xfe000000
#define BONITO_GPIO_GPINR_SHIFT 25
#define BONITO_GPIO_IOW(N) (1<<(BONITO_GPIO_GPIOW_SHIFT+(N)))
#define BONITO_GPIO_IOR(N) (1<<(BONITO_GPIO_GPIOR_SHIFT+(N)))
#define BONITO_GPIO_INR(N) (1<<(BONITO_GPIO_GPINR_SHIFT+(N)))
/* ICU */
#define BONITO_ICU_MBOXES 0x0000000f
#define BONITO_ICU_MBOXES_SHIFT 0
#define BONITO_ICU_DMARDY 0x00000010
#define BONITO_ICU_DMAEMPTY 0x00000020
#define BONITO_ICU_COPYRDY 0x00000040
#define BONITO_ICU_COPYEMPTY 0x00000080
#define BONITO_ICU_COPYERR 0x00000100
#define BONITO_ICU_PCIIRQ 0x00000200
#define BONITO_ICU_MASTERERR 0x00000400
#define BONITO_ICU_SYSTEMERR 0x00000800
#define BONITO_ICU_DRAMPERR 0x00001000
#define BONITO_ICU_RETRYERR 0x00002000
#define BONITO_ICU_GPIOS 0x01ff0000
#define BONITO_ICU_GPIOS_SHIFT 16
#define BONITO_ICU_GPINS 0x7e000000
#define BONITO_ICU_GPINS_SHIFT 25
#define BONITO_ICU_MBOX(N) (1<<(BONITO_ICU_MBOXES_SHIFT+(N)))
#define BONITO_ICU_GPIO(N) (1<<(BONITO_ICU_GPIOS_SHIFT+(N)))
#define BONITO_ICU_GPIN(N) (1<<(BONITO_ICU_GPINS_SHIFT+(N)))
/* pcimap */
#define BONITO_PCIMAP_PCIMAP_LO0 0x0000003f
#define BONITO_PCIMAP_PCIMAP_LO0_SHIFT 0
#define BONITO_PCIMAP_PCIMAP_LO1 0x00000fc0
#define BONITO_PCIMAP_PCIMAP_LO1_SHIFT 6
#define BONITO_PCIMAP_PCIMAP_LO2 0x0003f000
#define BONITO_PCIMAP_PCIMAP_LO2_SHIFT 12
#define BONITO_PCIMAP_PCIMAP_2 0x00040000
#define BONITO_PCIMAP_WIN(WIN,ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
#define BONITO_PCIMAP_WINSIZE (1<<26)
#define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1))
#define BONITO_PCIMAP_WINBASE(ADDR) ((ADDR) << 26)
/* pcimembaseCfg */
#define BONITO_PCIMEMBASECFG_MASK 0xf0000000
#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK 0x0000001f
#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT 0
#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS 0x000003e0
#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT 5
#define BONITO_PCIMEMBASECFG_MEMBASE0_CACHED 0x00000400
#define BONITO_PCIMEMBASECFG_MEMBASE0_IO 0x00000800
#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK 0x0001f000
#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT 12
#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS 0x003e0000
#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT 17
#define BONITO_PCIMEMBASECFG_MEMBASE1_CACHED 0x00400000
#define BONITO_PCIMEMBASECFG_MEMBASE1_IO 0x00800000
#define BONITO_PCIMEMBASECFG_ASHIFT 23
#define BONITO_PCIMEMBASECFG_AMASK 0x007fffff
#define BONITO_PCIMEMBASECFGSIZE(WIN,SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)
#define BONITO_PCIMEMBASECFGBASE(WIN,BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS)
#define BONITO_PCIMEMBASECFG_SIZE(WIN,CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK)
#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
#define BONITO_PCITOPHYS(WIN,ADDR,CFG) ( \
(((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)))) | \
(BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG)) \
)
/* PCICmd */
#define BONITO_PCICMD_MEMEN 0x00000002
#define BONITO_PCICMD_MSTREN 0x00000004
#endif /* _ASM_MIPS_BOARDS_BONITO64_H */
include/asm-mips/mips-boards/generic.h
View file @ 5d3adbe2
......@@ -25,14 +25,20 @@
#ifndef _MIPS_GENERIC_H
#define _MIPS_GENERIC_H
#include <linux/config.h>
#include <asm/addrspace.h>
#include <asm/byteorder.h>
#include <asm/mips-boards/bonito64.h>
/*
* Display register base.
*/
#if defined(CONFIG_MIPS_SEAD)
#define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f0005c0))
#else
#define ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1f000410))
#define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f000418))
#endif
/*
......@@ -44,8 +50,28 @@
/*
* Reset register.
*/
#if defined(CONFIG_MIPS_SEAD)
#define SOFTRES_REG (KSEG1ADDR(0x1e800050))
#define GORESET 0x4d
#else
#define SOFTRES_REG (KSEG1ADDR(0x1f000500))
#define GORESET 0x42
#endif
/*
* Revision register.
*/
#define MIPS_REVISION_REG (KSEG1ADDR(0x1fc00010))
#define MIPS_REVISION_CORID_QED_RM5261 0
#define MIPS_REVISION_CORID_CORE_LV 1
#define MIPS_REVISION_CORID_BONITO64 2
#define MIPS_REVISION_CORID_CORE_20K 3
#define MIPS_REVISION_CORID_CORE_FPGA 4
#define MIPS_REVISION_CORID_CORE_MSC 5
#define MIPS_REVISION_CORID (((*(volatile u32 *)(MIPS_REVISION_REG)) >> 10) & 0x3f)
extern unsigned int mips_revision_corid;
/*
......@@ -67,4 +93,19 @@
#define GT_PCI_READ(ofs, data) \
data = *(volatile u32 *)(MIPS_GT_BASE+ofs)
/*
* Algorithmics Bonito64 system controller register base.
*/
static char * const _bonito = (char *)KSEG1ADDR(BONITO_REG_BASE);
/*
* MIPS System controller PCI register base.
*/
#define MSC01_PCI_REG_BASE (KSEG1ADDR(0x1bd00000))
#define MSC_WRITE(reg, data) \
*(volatile u32 *)(reg) = data
#define MSC_READ(reg, data) \
data = *(volatile u32 *)(reg)
#endif /* !(_MIPS_GENERIC_H) */
include/asm-mips/mips-boards/malta.h
View file @ 5d3adbe2
......@@ -2,8 +2,6 @@
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
......@@ -17,21 +15,36 @@
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* ########################################################################
*
* Defines of the Malta board specific address-MAP, registers, etc.
*
*/
#ifndef _MIPS_MALTA_H
#define _MIPS_MALTA_H
#ifndef __ASM_MIPS_MALTA_H
#define __ASM_MIPS_MALTA_H
#include <asm/addrspace.h>
#include <asm/gt64120/gt64120.h>
#include <asm/io.h>
/*
* Malta I/O ports base address.
*/
#define MALTA_PORT_BASE (KSEG1ADDR(0x18000000))
* Malta I/O ports base address for the Galileo GT64120 and Algorithmics
* Bonito system controllers.
*/
#define MALTA_GT_PORT_BASE get_gt_port_base(GT_PCI0IOLD_OFS)
#define MALTA_BONITO_PORT_BASE (KSEG1ADDR(0x1fd00000))
#define MALTA_MSC_PORT_BASE get_msc_port_base(MSC01_PCI_SC2PIOBASL)
static inline unsigned long get_gt_port_base(unsigned long reg)
{
unsigned long addr;
GT_READ(reg, addr);
return KSEG1ADDR((addr & 0xffff) << 21);
}
static inline unsigned long get_msc_port_base(unsigned long reg)
{
unsigned long addr;
MSC_READ(reg, addr);
return KSEG1ADDR(addr);
}
/*
* Malta RTC-device indirect register access.
......@@ -56,4 +69,6 @@
#define SMSC_WRITE(x,a) outb(x,a)
#endif /* !(_MIPS_MALTA_H) */
#define MALTA_JMPRS_REG (KSEG1ADDR(0x1f000210))
#endif /* __ASM_MIPS_MALTA_H */
include/asm-mips/mips-boards/msc01_pci.h 0 → 100644
View file @ 5d3adbe2
/*
* mcs01_pci.h
*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* PCI Register definitions for the MIPS System Controller.
*/
#ifndef MSC01_PCI_H
#define MSC01_PCI_H
/*****************************************************************************
* Register offset addresses
****************************************************************************/
#define MSC01_PCI_ID_OFS 0x0000
#define MSC01_PCI_SC2PMBASL_OFS 0x0208
#define MSC01_PCI_SC2PMMSKL_OFS 0x0218
#define MSC01_PCI_SC2PMMAPL_OFS 0x0228
#define MSC01_PCI_SC2PIOBASL_OFS 0x0248
#define MSC01_PCI_SC2PIOMSKL_OFS 0x0258
#define MSC01_PCI_SC2PIOMAPL_OFS 0x0268
#define MSC01_PCI_P2SCMSKL_OFS 0x0308
#define MSC01_PCI_P2SCMAPL_OFS 0x0318
#define MSC01_PCI_INTCFG_OFS 0x0600
#define MSC01_PCI_INTSTAT_OFS 0x0608
#define MSC01_PCI_CFGADDR_OFS 0x0610
#define MSC01_PCI_CFGDATA_OFS 0x0618
#define MSC01_PCI_IACK_OFS 0x0620
#define MSC01_PCI_HEAD0_OFS 0x2000 /* DevID, VendorID */
#define MSC01_PCI_HEAD1_OFS 0x2008 /* Status, Command */
#define MSC01_PCI_HEAD2_OFS 0x2010 /* Class code, RevID */
#define MSC01_PCI_HEAD3_OFS 0x2018 /* bist, header, latency */
#define MSC01_PCI_HEAD4_OFS 0x2020 /* BAR 0 */
#define MSC01_PCI_HEAD5_OFS 0x2028 /* BAR 1 */
#define MSC01_PCI_HEAD6_OFS 0x2030 /* BAR 2 */
#define MSC01_PCI_HEAD7_OFS 0x2038 /* BAR 3 */
#define MSC01_PCI_HEAD8_OFS 0x2040 /* BAR 4 */
#define MSC01_PCI_HEAD9_OFS 0x2048 /* BAR 5 */
#define MSC01_PCI_HEAD10_OFS 0x2050 /* CardBus CIS Ptr */
#define MSC01_PCI_HEAD11_OFS 0x2058 /* SubSystem ID, -VendorID */
#define MSC01_PCI_HEAD12_OFS 0x2060 /* ROM BAR */
#define MSC01_PCI_HEAD13_OFS 0x2068 /* Capabilities ptr */
#define MSC01_PCI_HEAD14_OFS 0x2070 /* reserved */
#define MSC01_PCI_HEAD15_OFS 0x2078 /* Maxl, ming, intpin, int */
#define MSC01_PCI_BAR0_OFS 0x2220
#define MSC01_PCI_CFG_OFS 0x2380
#define MSC01_PCI_SWAP_OFS 0x2388
/*****************************************************************************
* Register encodings
****************************************************************************/
#define MSC01_PCI_ID_ID_SHF 16
#define MSC01_PCI_ID_ID_MSK 0x00ff0000
#define MSC01_PCI_ID_ID_HOSTBRIDGE 82
#define MSC01_PCI_ID_MAR_SHF 8
#define MSC01_PCI_ID_MAR_MSK 0x0000ff00
#define MSC01_PCI_ID_MIR_SHF 0
#define MSC01_PCI_ID_MIR_MSK 0x000000ff
#define MSC01_PCI_SC2PMBASL_BAS_SHF 24
#define MSC01_PCI_SC2PMBASL_BAS_MSK 0xff000000
#define MSC01_PCI_SC2PMMSKL_MSK_SHF 24
#define MSC01_PCI_SC2PMMSKL_MSK_MSK 0xff000000
#define MSC01_PCI_SC2PMMAPL_MAP_SHF 24
#define MSC01_PCI_SC2PMMAPL_MAP_MSK 0xff000000
#define MSC01_PCI_SC2PIOBASL_BAS_SHF 24
#define MSC01_PCI_SC2PIOBASL_BAS_MSK 0xff000000
#define MSC01_PCI_SC2PIOMSKL_MSK_SHF 24
#define MSC01_PCI_SC2PIOMSKL_MSK_MSK 0xff000000
#define MSC01_PCI_SC2PIOMAPL_MAP_SHF 24
#define MSC01_PCI_SC2PIOMAPL_MAP_MSK 0xff000000
#define MSC01_PCI_P2SCMSKL_MSK_SHF 24
#define MSC01_PCI_P2SCMSKL_MSK_MSK 0xff000000
#define MSC01_PCI_P2SCMAPL_MAP_SHF 24
#define MSC01_PCI_P2SCMAPL_MAP_MSK 0xff000000
#define MSC01_PCI_INTCFG_RST_SHF 10
#define MSC01_PCI_INTCFG_RST_MSK 0x00000400
#define MSC01_PCI_INTCFG_RST_BIT 0x00000400
#define MSC01_PCI_INTCFG_MWE_SHF 9
#define MSC01_PCI_INTCFG_MWE_MSK 0x00000200
#define MSC01_PCI_INTCFG_MWE_BIT 0x00000200
#define MSC01_PCI_INTCFG_DTO_SHF 8
#define MSC01_PCI_INTCFG_DTO_MSK 0x00000100
#define MSC01_PCI_INTCFG_DTO_BIT 0x00000100
#define MSC01_PCI_INTCFG_MA_SHF 7
#define MSC01_PCI_INTCFG_MA_MSK 0x00000080
#define MSC01_PCI_INTCFG_MA_BIT 0x00000080
#define MSC01_PCI_INTCFG_TA_SHF 6
#define MSC01_PCI_INTCFG_TA_MSK 0x00000040
#define MSC01_PCI_INTCFG_TA_BIT 0x00000040
#define MSC01_PCI_INTCFG_RTY_SHF 5
#define MSC01_PCI_INTCFG_RTY_MSK 0x00000020
#define MSC01_PCI_INTCFG_RTY_BIT 0x00000020
#define MSC01_PCI_INTCFG_MWP_SHF 4
#define MSC01_PCI_INTCFG_MWP_MSK 0x00000010
#define MSC01_PCI_INTCFG_MWP_BIT 0x00000010
#define MSC01_PCI_INTCFG_MRP_SHF 3
#define MSC01_PCI_INTCFG_MRP_MSK 0x00000008
#define MSC01_PCI_INTCFG_MRP_BIT 0x00000008
#define MSC01_PCI_INTCFG_SWP_SHF 2
#define MSC01_PCI_INTCFG_SWP_MSK 0x00000004
#define MSC01_PCI_INTCFG_SWP_BIT 0x00000004
#define MSC01_PCI_INTCFG_SRP_SHF 1
#define MSC01_PCI_INTCFG_SRP_MSK 0x00000002
#define MSC01_PCI_INTCFG_SRP_BIT 0x00000002
#define MSC01_PCI_INTCFG_SE_SHF 0
#define MSC01_PCI_INTCFG_SE_MSK 0x00000001
#define MSC01_PCI_INTCFG_SE_BIT 0x00000001
#define MSC01_PCI_INTSTAT_RST_SHF 10
#define MSC01_PCI_INTSTAT_RST_MSK 0x00000400
#define MSC01_PCI_INTSTAT_RST_BIT 0x00000400
#define MSC01_PCI_INTSTAT_MWE_SHF 9
#define MSC01_PCI_INTSTAT_MWE_MSK 0x00000200
#define MSC01_PCI_INTSTAT_MWE_BIT 0x00000200
#define MSC01_PCI_INTSTAT_DTO_SHF 8
#define MSC01_PCI_INTSTAT_DTO_MSK 0x00000100
#define MSC01_PCI_INTSTAT_DTO_BIT 0x00000100
#define MSC01_PCI_INTSTAT_MA_SHF 7
#define MSC01_PCI_INTSTAT_MA_MSK 0x00000080
#define MSC01_PCI_INTSTAT_MA_BIT 0x00000080
#define MSC01_PCI_INTSTAT_TA_SHF 6
#define MSC01_PCI_INTSTAT_TA_MSK 0x00000040
#define MSC01_PCI_INTSTAT_TA_BIT 0x00000040
#define MSC01_PCI_INTSTAT_RTY_SHF 5
#define MSC01_PCI_INTSTAT_RTY_MSK 0x00000020
#define MSC01_PCI_INTSTAT_RTY_BIT 0x00000020
#define MSC01_PCI_INTSTAT_MWP_SHF 4
#define MSC01_PCI_INTSTAT_MWP_MSK 0x00000010
#define MSC01_PCI_INTSTAT_MWP_BIT 0x00000010
#define MSC01_PCI_INTSTAT_MRP_SHF 3
#define MSC01_PCI_INTSTAT_MRP_MSK 0x00000008
#define MSC01_PCI_INTSTAT_MRP_BIT 0x00000008
#define MSC01_PCI_INTSTAT_SWP_SHF 2
#define MSC01_PCI_INTSTAT_SWP_MSK 0x00000004
#define MSC01_PCI_INTSTAT_SWP_BIT 0x00000004
#define MSC01_PCI_INTSTAT_SRP_SHF 1
#define MSC01_PCI_INTSTAT_SRP_MSK 0x00000002
#define MSC01_PCI_INTSTAT_SRP_BIT 0x00000002
#define MSC01_PCI_INTSTAT_SE_SHF 0
#define MSC01_PCI_INTSTAT_SE_MSK 0x00000001
#define MSC01_PCI_INTSTAT_SE_BIT 0x00000001
#define MSC01_PCI_CFGADDR_BNUM_SHF 16
#define MSC01_PCI_CFGADDR_BNUM_MSK 0x00ff0000
#define MSC01_PCI_CFGADDR_DNUM_SHF 11
#define MSC01_PCI_CFGADDR_DNUM_MSK 0x0000f800
#define MSC01_PCI_CFGADDR_FNUM_SHF 8
#define MSC01_PCI_CFGADDR_FNUM_MSK 0x00000700
#define MSC01_PCI_CFGADDR_RNUM_SHF 2
#define MSC01_PCI_CFGADDR_RNUM_MSK 0x000000fc
#define MSC01_PCI_CFGDATA_DATA_SHF 0
#define MSC01_PCI_CFGDATA_DATA_MSK 0xffffffff
/* The defines below are ONLY valid for a MEM bar! */
#define MSC01_PCI_BAR0_SIZE_SHF 4
#define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0
#define MSC01_PCI_BAR0_P_SHF 3
#define MSC01_PCI_BAR0_P_MSK 0x00000008
#define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK
#define MSC01_PCI_BAR0_D_SHF 1
#define MSC01_PCI_BAR0_D_MSK 0x00000006
#define MSC01_PCI_BAR0_T_SHF 0
#define MSC01_PCI_BAR0_T_MSK 0x00000001
#define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK
#define MSC01_PCI_CFG_RA_SHF 17
#define MSC01_PCI_CFG_RA_MSK 0x00020000
#define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK
#define MSC01_PCI_CFG_G_SHF 16
#define MSC01_PCI_CFG_G_MSK 0x00010000
#define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK
#define MSC01_PCI_CFG_EN_SHF 15
#define MSC01_PCI_CFG_EN_MSK 0x00008000
#define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK
#define MSC01_PCI_CFG_MAXRTRY_SHF 0
#define MSC01_PCI_CFG_MAXRTRY_MSK 0x000000ff
#define MSC01_PCI_SWAP_IO_SHF 18
#define MSC01_PCI_SWAP_IO_MSK 0x000c0000
#define MSC01_PCI_SWAP_MEM_SHF 16
#define MSC01_PCI_SWAP_MEM_MSK 0x00030000
#define MSC01_PCI_SWAP_BAR0_SHF 0
#define MSC01_PCI_SWAP_BAR0_MSK 0x00000003
#define MSC01_PCI_SWAP_NOSWAP 0
#define MSC01_PCI_SWAP_BYTESWAP 1
/*****************************************************************************
* Registers absolute addresses
****************************************************************************/
#define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS)
#define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS)
#define MSC01_PCI_SC2PMMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS)
#define MSC01_PCI_SC2PMMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS)
#define MSC01_PCI_SC2PIOBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS)
#define MSC01_PCI_SC2PIOMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS)
#define MSC01_PCI_SC2PIOMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS)
#define MSC01_PCI_P2SCMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS)
#define MSC01_PCI_P2SCMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS)
#define MSC01_PCI_INTCFG (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS)
#define MSC01_PCI_INTSTAT (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS)
#define MSC01_PCI_CFGADDR (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS)
#define MSC01_PCI_CFGDATA (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS)
#define MSC01_PCI_IACK (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS)
#define MSC01_PCI_HEAD0 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS)
#define MSC01_PCI_HEAD1 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS)
#define MSC01_PCI_HEAD2 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD2_OFS)
#define MSC01_PCI_HEAD3 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD3_OFS)
#define MSC01_PCI_HEAD4 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD4_OFS)
#define MSC01_PCI_HEAD5 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD5_OFS)
#define MSC01_PCI_HEAD6 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD6_OFS)
#define MSC01_PCI_HEAD7 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD7_OFS)
#define MSC01_PCI_HEAD8 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD8_OFS)
#define MSC01_PCI_HEAD9 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD9_OFS)
#define MSC01_PCI_HEAD10 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD10_OFS)
#define MSC01_PCI_HEAD11 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
#define MSC01_PCI_HEAD12 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
#define MSC01_PCI_HEAD13 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
#define MSC01_PCI_HEAD14 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
#define MSC01_PCI_HEAD15 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
#define MSC01_PCI_BAR0 (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS)
#define MSC01_PCI_CFG (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS)
#define MSC01_PCI_SWAP (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS)
#endif
/*****************************************************************************
* End of msc01_pci.h
*****************************************************************************/
arch/mips64/mips-boards/generic/display.c → include/asm-mips/mips-boards/sead.h
View file @ 5d3adbe2
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
......@@ -19,29 +19,18 @@
*
* ########################################################################
*
* Display routines for display messages in MIPS boards ascii display.
* Defines of the SEAD board specific address-MAP, registers, etc.
*
*/
#ifndef _MIPS_SEAD_H
#define _MIPS_SEAD_H
#include <asm/mips-boards/generic.h>
#include <asm/addrspace.h>
/*
* SEAD UART register base.
*/
#define SEAD_UART0_REGS_BASE (0x1f000800)
#define SEAD_BASE_BAUD ( 3686400 / 16 )
void mips_display_message(const char *str)
{
volatile unsigned int *display = (void *)ASCII_DISPLAY_POS_BASE;
int i;
for (i = 0; i <= 14; i=i+2) {
if (*str)
display[i] = *str++;
else
display[i] = ' ';
}
}
void mips_display_word(unsigned int num)
{
volatile unsigned int *display = (void *)ASCII_DISPLAY_WORD_BASE;
*display = num;
}
#endif /* !(_MIPS_SEAD_H) */
arch/mips64/mips-boards/malta/malta_rtc.c → include/asm-mips/mips-boards/seadint.h
View file @ 5d3adbe2
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
......@@ -19,32 +19,17 @@
*
* ########################################################################
*
* RTC routines for Malta style attached PIIX4 device, which contains a
* Motorola MC146818A-compatible Real Time Clock.
* Defines for the SEAD interrupt controller.
*
*/
#include <asm/mc146818rtc.h>
#include <asm/mips-boards/malta.h>
#ifndef _MIPS_SEADINT_H
#define _MIPS_SEADINT_H
static unsigned char malta_rtc_read_data(unsigned long addr)
{
outb(addr, MALTA_RTC_ADR_REG);
return inb(MALTA_RTC_DAT_REG);
}
/* Number of IRQ supported */
#define SEADINT_UART0 0
#define SEADINT_UART1 1
#define SEADINT_END 2
static void malta_rtc_write_data(unsigned char data, unsigned long addr)
{
outb(addr, MALTA_RTC_ADR_REG);
outb(data, MALTA_RTC_DAT_REG);
}
extern void seadint_init(void);
static int malta_rtc_bcd_mode(void)
{
return 0;
}
struct rtc_ops malta_rtc_ops = {
&malta_rtc_read_data,
&malta_rtc_write_data,
&malta_rtc_bcd_mode
};
#endif /* !(_MIPS_SEADINT_H) */
include/asm-mips64/mips-boards/bonito64.h 0 → 100644
View file @ 5d3adbe2
/*
* bonito.h
*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2001 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* This file is the original bonito.h from Algorithmics with minor changes
* to fit into linux.
*/
/*
* Bonito Register Map
* Copyright (c) 1999 Algorithmics Ltd
*
* Algorithmics gives permission for anyone to use and modify this file
* without any obligation or license condition except that you retain
* this copyright message in any source redistribution in whole or part.
*
* Updated copies of this and other files can be found at
* ftp://ftp.algor.co.uk/pub/bonito/
*
* Users of the Bonito controller are warmly recommended to contribute
* any useful changes back to Algorithmics (mail to bonito@algor.co.uk).
*/
/* Revision 1.48 autogenerated on 08/17/99 15:20:01 */
/* This bonito64 version editted from bonito.h Revision 1.48 on 11/09/00 */
#ifndef _ASM_MIPS_BOARDS_BONITO64_H
#define _ASM_MIPS_BOARDS_BONITO64_H
#ifdef __ASSEMBLY__
/* offsets from base register */
#define BONITO(x) (x)
#else /* !__ASSEMBLY__ */
/* offsets from base pointer, this construct allows optimisation */
/* static char * const _bonito = PA_TO_KVA1(BONITO_BASE); */
#define BONITO(x) *(volatile u32 *)(_bonito + (x))
#endif /* __ASSEMBLY__ */
#define BONITO_BOOT_BASE 0x1fc00000
#define BONITO_BOOT_SIZE 0x00100000
#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)
#define BONITO_FLASH_BASE 0x1c000000
#define BONITO_FLASH_SIZE 0x03000000
#define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
#define BONITO_SOCKET_BASE 0x1f800000
#define BONITO_SOCKET_SIZE 0x00400000
#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)
#define BONITO_REG_BASE 0x1fe00000
#define BONITO_REG_SIZE 0x00040000
#define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1)
#define BONITO_DEV_BASE 0x1ff00000
#define BONITO_DEV_SIZE 0x00100000
#define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
#define BONITO_PCILO_BASE 0x10000000
#define BONITO_PCILO_SIZE 0x0c000000
#define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1)
#define BONITO_PCILO0_BASE 0x10000000
#define BONITO_PCILO1_BASE 0x14000000
#define BONITO_PCILO2_BASE 0x18000000
#define BONITO_PCIHI_BASE 0x20000000
#define BONITO_PCIHI_SIZE 0x20000000
#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
#define BONITO_PCIIO_BASE 0x1fd00000
#define BONITO_PCIIO_SIZE 0x00100000
#define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1)
#define BONITO_PCICFG_BASE 0x1fe80000
#define BONITO_PCICFG_SIZE 0x00080000
#define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1)
/* Bonito Register Bases */
#define BONITO_PCICONFIGBASE 0x00
#define BONITO_REGBASE 0x100
/* PCI Configuration Registers */
#define BONITO_PCI_REG(x) BONITO(BONITO_PCICONFIGBASE + (x))
#define BONITO_PCIDID BONITO_PCI_REG(0x00)
#define BONITO_PCICMD BONITO_PCI_REG(0x04)
#define BONITO_PCICLASS BONITO_PCI_REG(0x08)
#define BONITO_PCILTIMER BONITO_PCI_REG(0x0c)
#define BONITO_PCIBASE0 BONITO_PCI_REG(0x10)
#define BONITO_PCIBASE1 BONITO_PCI_REG(0x14)
#define BONITO_PCIBASE2 BONITO_PCI_REG(0x18)
#define BONITO_PCIEXPRBASE BONITO_PCI_REG(0x30)
#define BONITO_PCIINT BONITO_PCI_REG(0x3c)
#define BONITO_PCICMD_PERR_CLR 0x80000000
#define BONITO_PCICMD_SERR_CLR 0x40000000
#define BONITO_PCICMD_MABORT_CLR 0x20000000
#define BONITO_PCICMD_MTABORT_CLR 0x10000000
#define BONITO_PCICMD_TABORT_CLR 0x08000000
#define BONITO_PCICMD_MPERR_CLR 0x01000000
#define BONITO_PCICMD_PERRRESPEN 0x00000040
#define BONITO_PCICMD_ASTEPEN 0x00000080
#define BONITO_PCICMD_SERREN 0x00000100
#define BONITO_PCILTIMER_BUSLATENCY 0x0000ff00
#define BONITO_PCILTIMER_BUSLATENCY_SHIFT 8
/* 1. Bonito h/w Configuration */
/* Power on register */
#define BONITO_BONPONCFG BONITO(BONITO_REGBASE + 0x00)
#define BONITO_BONPONCFG_SYSCONTROLLERRD 0x00040000
#define BONITO_BONPONCFG_ROMCS1SAMP 0x00020000
#define BONITO_BONPONCFG_ROMCS0SAMP 0x00010000
#define BONITO_BONPONCFG_CPUBIGEND 0x00004000
/* Added by RPF 11-9-00 */
#define BONITO_BONPONCFG_BURSTORDER 0x00001000
/* --- */
#define BONITO_BONPONCFG_CPUPARITY 0x00002000
#define BONITO_BONPONCFG_CPUTYPE 0x00000007
#define BONITO_BONPONCFG_CPUTYPE_SHIFT 0
#define BONITO_BONPONCFG_PCIRESET_OUT 0x00000008
#define BONITO_BONPONCFG_IS_ARBITER 0x00000010
#define BONITO_BONPONCFG_ROMBOOT 0x000000c0
#define BONITO_BONPONCFG_ROMBOOT_SHIFT 6
#define BONITO_BONPONCFG_ROMBOOT_FLASH (0x0<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
#define BONITO_BONPONCFG_ROMBOOT_SOCKET (0x1<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
#define BONITO_BONPONCFG_ROMBOOT_SDRAM (0x2<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
#define BONITO_BONPONCFG_ROMBOOT_CPURESET (0x3<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
#define BONITO_BONPONCFG_ROMCS0WIDTH 0x00000100
#define BONITO_BONPONCFG_ROMCS1WIDTH 0x00000200
#define BONITO_BONPONCFG_ROMCS0FAST 0x00000400
#define BONITO_BONPONCFG_ROMCS1FAST 0x00000800
#define BONITO_BONPONCFG_CONFIG_DIS 0x00000020
/* Other Bonito configuration */
#define BONITO_BONGENCFG_OFFSET 0x4
#define BONITO_BONGENCFG BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET)
#define BONITO_BONGENCFG_DEBUGMODE 0x00000001
#define BONITO_BONGENCFG_SNOOPEN 0x00000002
#define BONITO_BONGENCFG_CPUSELFRESET 0x00000004
#define BONITO_BONGENCFG_FORCE_IRQA 0x00000008
#define BONITO_BONGENCFG_IRQA_ISOUT 0x00000010
#define BONITO_BONGENCFG_IRQA_FROM_INT1 0x00000020
#define BONITO_BONGENCFG_BYTESWAP 0x00000040
#define BONITO_BONGENCFG_UNCACHED 0x00000080
#define BONITO_BONGENCFG_PREFETCHEN 0x00000100
#define BONITO_BONGENCFG_WBEHINDEN 0x00000200
#define BONITO_BONGENCFG_CACHEALG 0x00000c00
#define BONITO_BONGENCFG_CACHEALG_SHIFT 10
#define BONITO_BONGENCFG_PCIQUEUE 0x00001000
#define BONITO_BONGENCFG_CACHESTOP 0x00002000
#define BONITO_BONGENCFG_MSTRBYTESWAP 0x00004000
#define BONITO_BONGENCFG_BUSERREN 0x00008000
#define BONITO_BONGENCFG_NORETRYTIMEOUT 0x00010000
#define BONITO_BONGENCFG_SHORTCOPYTIMEOUT 0x00020000
/* 2. IO & IDE configuration */
#define BONITO_IODEVCFG BONITO(BONITO_REGBASE + 0x08)
/* 3. IO & IDE configuration */
#define BONITO_SDCFG BONITO(BONITO_REGBASE + 0x0c)
/* 4. PCI address map control */
#define BONITO_PCIMAP BONITO(BONITO_REGBASE + 0x10)
#define BONITO_PCIMEMBASECFG BONITO(BONITO_REGBASE + 0x14)
#define BONITO_PCIMAP_CFG BONITO(BONITO_REGBASE + 0x18)
/* 5. ICU & GPIO regs */
/* GPIO Regs - r/w */
#define BONITO_GPIODATA_OFFSET 0x1c
#define BONITO_GPIODATA BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET)
#define BONITO_GPIOIE BONITO(BONITO_REGBASE + 0x20)
/* ICU Configuration Regs - r/w */
#define BONITO_INTEDGE BONITO(BONITO_REGBASE + 0x24)
#define BONITO_INTSTEER BONITO(BONITO_REGBASE + 0x28)
#define BONITO_INTPOL BONITO(BONITO_REGBASE + 0x2c)
/* ICU Enable Regs - IntEn & IntISR are r/o. */
#define BONITO_INTENSET BONITO(BONITO_REGBASE + 0x30)
#define BONITO_INTENCLR BONITO(BONITO_REGBASE + 0x34)
#define BONITO_INTEN BONITO(BONITO_REGBASE + 0x38)
#define BONITO_INTISR BONITO(BONITO_REGBASE + 0x3c)
/* PCI mail boxes */
#define BONITO_PCIMAIL0_OFFSET 0x40
#define BONITO_PCIMAIL1_OFFSET 0x44
#define BONITO_PCIMAIL2_OFFSET 0x48
#define BONITO_PCIMAIL3_OFFSET 0x4c
#define BONITO_PCIMAIL0 BONITO(BONITO_REGBASE + 0x40)
#define BONITO_PCIMAIL1 BONITO(BONITO_REGBASE + 0x44)
#define BONITO_PCIMAIL2 BONITO(BONITO_REGBASE + 0x48)
#define BONITO_PCIMAIL3 BONITO(BONITO_REGBASE + 0x4c)
/* 6. PCI cache */
#define BONITO_PCICACHECTRL BONITO(BONITO_REGBASE + 0x50)
#define BONITO_PCICACHETAG BONITO(BONITO_REGBASE + 0x54)
#define BONITO_PCIBADADDR BONITO(BONITO_REGBASE + 0x58)
#define BONITO_PCIMSTAT BONITO(BONITO_REGBASE + 0x5c)
/*
#define BONITO_PCIRDPOST BONITO(BONITO_REGBASE + 0x60)
#define BONITO_PCIDATA BONITO(BONITO_REGBASE + 0x64)
*/
/* 7. IDE DMA & Copier */
#define BONITO_CONFIGBASE 0x000
#define BONITO_BONITOBASE 0x100
#define BONITO_LDMABASE 0x200
#define BONITO_COPBASE 0x300
#define BONITO_REG_BLOCKMASK 0x300
#define BONITO_LDMACTRL BONITO(BONITO_LDMABASE + 0x0)
#define BONITO_LDMASTAT BONITO(BONITO_LDMABASE + 0x0)
#define BONITO_LDMAADDR BONITO(BONITO_LDMABASE + 0x4)
#define BONITO_LDMAGO BONITO(BONITO_LDMABASE + 0x8)
#define BONITO_LDMADATA BONITO(BONITO_LDMABASE + 0xc)
#define BONITO_COPCTRL BONITO(BONITO_COPBASE + 0x0)
#define BONITO_COPSTAT BONITO(BONITO_COPBASE + 0x0)
#define BONITO_COPPADDR BONITO(BONITO_COPBASE + 0x4)
#define BONITO_COPDADDR BONITO(BONITO_COPBASE + 0x8)
#define BONITO_COPGO BONITO(BONITO_COPBASE + 0xc)
/* ###### Bit Definitions for individual Registers #### */
/* Gen DMA. */
#define BONITO_IDECOPDADDR_DMA_DADDR 0x0ffffffc
#define BONITO_IDECOPDADDR_DMA_DADDR_SHIFT 2
#define BONITO_IDECOPPADDR_DMA_PADDR 0xfffffffc
#define BONITO_IDECOPPADDR_DMA_PADDR_SHIFT 2
#define BONITO_IDECOPGO_DMA_SIZE 0x0000fffe
#define BONITO_IDECOPGO_DMA_SIZE_SHIFT 0
#define BONITO_IDECOPGO_DMA_WRITE 0x00010000
#define BONITO_IDECOPGO_DMAWCOUNT 0x000f0000
#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT 16
#define BONITO_IDECOPCTRL_DMA_STARTBIT 0x80000000
#define BONITO_IDECOPCTRL_DMA_RSTBIT 0x40000000
/* DRAM - sdCfg */
#define BONITO_SDCFG_AROWBITS 0x00000003
#define BONITO_SDCFG_AROWBITS_SHIFT 0
#define BONITO_SDCFG_ACOLBITS 0x0000000c
#define BONITO_SDCFG_ACOLBITS_SHIFT 2
#define BONITO_SDCFG_ABANKBIT 0x00000010
#define BONITO_SDCFG_ASIDES 0x00000020
#define BONITO_SDCFG_AABSENT 0x00000040
#define BONITO_SDCFG_AWIDTH64 0x00000080
#define BONITO_SDCFG_BROWBITS 0x00000300
#define BONITO_SDCFG_BROWBITS_SHIFT 8
#define BONITO_SDCFG_BCOLBITS 0x00000c00
#define BONITO_SDCFG_BCOLBITS_SHIFT 10
#define BONITO_SDCFG_BBANKBIT 0x00001000
#define BONITO_SDCFG_BSIDES 0x00002000
#define BONITO_SDCFG_BABSENT 0x00004000
#define BONITO_SDCFG_BWIDTH64 0x00008000
#define BONITO_SDCFG_EXTRDDATA 0x00010000
#define BONITO_SDCFG_EXTRASCAS 0x00020000
#define BONITO_SDCFG_EXTPRECH 0x00040000
#define BONITO_SDCFG_EXTRASWIDTH 0x00180000
#define BONITO_SDCFG_EXTRASWIDTH_SHIFT 19
/* Changed by RPF 11-9-00 */
#define BONITO_SDCFG_DRAMMODESET 0x00200000
/* --- */
#define BONITO_SDCFG_DRAMEXTREGS 0x00400000
#define BONITO_SDCFG_DRAMPARITY 0x00800000
/* Added by RPF 11-9-00 */
#define BONITO_SDCFG_DRAMBURSTLEN 0x03000000
#define BONITO_SDCFG_DRAMBURSTLEN_SHIFT 24
#define BONITO_SDCFG_DRAMMODESET_DONE 0x80000000
/* --- */
/* PCI Cache - pciCacheCtrl */
#define BONITO_PCICACHECTRL_CACHECMD 0x00000007
#define BONITO_PCICACHECTRL_CACHECMD_SHIFT 0
#define BONITO_PCICACHECTRL_CACHECMDLINE 0x00000018
#define BONITO_PCICACHECTRL_CACHECMDLINE_SHIFT 3
#define BONITO_PCICACHECTRL_CMDEXEC 0x00000020
#define BONITO_IODEVCFG_BUFFBIT_CS0 0x00000001
#define BONITO_IODEVCFG_SPEEDBIT_CS0 0x00000002
#define BONITO_IODEVCFG_MOREABITS_CS0 0x00000004
#define BONITO_IODEVCFG_BUFFBIT_CS1 0x00000008
#define BONITO_IODEVCFG_SPEEDBIT_CS1 0x00000010
#define BONITO_IODEVCFG_MOREABITS_CS1 0x00000020
#define BONITO_IODEVCFG_BUFFBIT_CS2 0x00000040
#define BONITO_IODEVCFG_SPEEDBIT_CS2 0x00000080
#define BONITO_IODEVCFG_MOREABITS_CS2 0x00000100
#define BONITO_IODEVCFG_BUFFBIT_CS3 0x00000200
#define BONITO_IODEVCFG_SPEEDBIT_CS3 0x00000400
#define BONITO_IODEVCFG_MOREABITS_CS3 0x00000800
#define BONITO_IODEVCFG_BUFFBIT_IDE 0x00001000
#define BONITO_IODEVCFG_SPEEDBIT_IDE 0x00002000
#define BONITO_IODEVCFG_WORDSWAPBIT_IDE 0x00004000
#define BONITO_IODEVCFG_MODEBIT_IDE 0x00008000
#define BONITO_IODEVCFG_DMAON_IDE 0x001f0000
#define BONITO_IODEVCFG_DMAON_IDE_SHIFT 16
#define BONITO_IODEVCFG_DMAOFF_IDE 0x01e00000
#define BONITO_IODEVCFG_DMAOFF_IDE_SHIFT 21
#define BONITO_IODEVCFG_EPROMSPLIT 0x02000000
/* Added by RPF 11-9-00 */
#define BONITO_IODEVCFG_CPUCLOCKPERIOD 0xfc000000
#define BONITO_IODEVCFG_CPUCLOCKPERIOD_SHIFT 26
/* --- */
/* gpio */
#define BONITO_GPIO_GPIOW 0x000003ff
#define BONITO_GPIO_GPIOW_SHIFT 0
#define BONITO_GPIO_GPIOR 0x01ff0000
#define BONITO_GPIO_GPIOR_SHIFT 16
#define BONITO_GPIO_GPINR 0xfe000000
#define BONITO_GPIO_GPINR_SHIFT 25
#define BONITO_GPIO_IOW(N) (1<<(BONITO_GPIO_GPIOW_SHIFT+(N)))
#define BONITO_GPIO_IOR(N) (1<<(BONITO_GPIO_GPIOR_SHIFT+(N)))
#define BONITO_GPIO_INR(N) (1<<(BONITO_GPIO_GPINR_SHIFT+(N)))
/* ICU */
#define BONITO_ICU_MBOXES 0x0000000f
#define BONITO_ICU_MBOXES_SHIFT 0
#define BONITO_ICU_DMARDY 0x00000010
#define BONITO_ICU_DMAEMPTY 0x00000020
#define BONITO_ICU_COPYRDY 0x00000040
#define BONITO_ICU_COPYEMPTY 0x00000080
#define BONITO_ICU_COPYERR 0x00000100
#define BONITO_ICU_PCIIRQ 0x00000200
#define BONITO_ICU_MASTERERR 0x00000400
#define BONITO_ICU_SYSTEMERR 0x00000800
#define BONITO_ICU_DRAMPERR 0x00001000
#define BONITO_ICU_RETRYERR 0x00002000
#define BONITO_ICU_GPIOS 0x01ff0000
#define BONITO_ICU_GPIOS_SHIFT 16
#define BONITO_ICU_GPINS 0x7e000000
#define BONITO_ICU_GPINS_SHIFT 25
#define BONITO_ICU_MBOX(N) (1<<(BONITO_ICU_MBOXES_SHIFT+(N)))
#define BONITO_ICU_GPIO(N) (1<<(BONITO_ICU_GPIOS_SHIFT+(N)))
#define BONITO_ICU_GPIN(N) (1<<(BONITO_ICU_GPINS_SHIFT+(N)))
/* pcimap */
#define BONITO_PCIMAP_PCIMAP_LO0 0x0000003f
#define BONITO_PCIMAP_PCIMAP_LO0_SHIFT 0
#define BONITO_PCIMAP_PCIMAP_LO1 0x00000fc0
#define BONITO_PCIMAP_PCIMAP_LO1_SHIFT 6
#define BONITO_PCIMAP_PCIMAP_LO2 0x0003f000
#define BONITO_PCIMAP_PCIMAP_LO2_SHIFT 12
#define BONITO_PCIMAP_PCIMAP_2 0x00040000
#define BONITO_PCIMAP_WIN(WIN,ADDR) ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
#define BONITO_PCIMAP_WINSIZE (1<<26)
#define BONITO_PCIMAP_WINOFFSET(ADDR) ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1))
#define BONITO_PCIMAP_WINBASE(ADDR) ((ADDR) << 26)
/* pcimembaseCfg */
#define BONITO_PCIMEMBASECFG_MASK 0xf0000000
#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK 0x0000001f
#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT 0
#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS 0x000003e0
#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT 5
#define BONITO_PCIMEMBASECFG_MEMBASE0_CACHED 0x00000400
#define BONITO_PCIMEMBASECFG_MEMBASE0_IO 0x00000800
#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK 0x0001f000
#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT 12
#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS 0x003e0000
#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT 17
#define BONITO_PCIMEMBASECFG_MEMBASE1_CACHED 0x00400000
#define BONITO_PCIMEMBASECFG_MEMBASE1_IO 0x00800000
#define BONITO_PCIMEMBASECFG_ASHIFT 23
#define BONITO_PCIMEMBASECFG_AMASK 0x007fffff
#define BONITO_PCIMEMBASECFGSIZE(WIN,SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)
#define BONITO_PCIMEMBASECFGBASE(WIN,BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS)
#define BONITO_PCIMEMBASECFG_SIZE(WIN,CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK)
#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
#define BONITO_PCITOPHYS(WIN,ADDR,CFG) ( \
(((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN,CFG)))) | \
(BONITO_PCIMEMBASECFG_ADDRTRANS(WIN,CFG)) \
)
/* PCICmd */
#define BONITO_PCICMD_MEMEN 0x00000002
#define BONITO_PCICMD_MSTREN 0x00000004
#endif /* _ASM_MIPS_BOARDS_BONITO64_H */
include/asm-mips64/mips-boards/generic.h
View file @ 5d3adbe2
......@@ -25,14 +25,20 @@
#ifndef _MIPS_GENERIC_H
#define _MIPS_GENERIC_H
#include <linux/config.h>
#include <asm/addrspace.h>
#include <asm/byteorder.h>
#include <asm/mips-boards/bonito64.h>
/*
* Display register base.
*/
#if defined(CONFIG_MIPS_SEAD)
#define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f0005c0))
#else
#define ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1f000410))
#define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f000418))
#endif
/*
......@@ -44,8 +50,28 @@
/*
* Reset register.
*/
#if defined(CONFIG_MIPS_SEAD)
#define SOFTRES_REG (KSEG1ADDR(0x1e800050))
#define GORESET 0x4d
#else
#define SOFTRES_REG (KSEG1ADDR(0x1f000500))
#define GORESET 0x42
#endif
/*
* Revision register.
*/
#define MIPS_REVISION_REG (KSEG1ADDR(0x1fc00010))
#define MIPS_REVISION_CORID_QED_RM5261 0
#define MIPS_REVISION_CORID_CORE_LV 1
#define MIPS_REVISION_CORID_BONITO64 2
#define MIPS_REVISION_CORID_CORE_20K 3
#define MIPS_REVISION_CORID_CORE_FPGA 4
#define MIPS_REVISION_CORID_CORE_MSC 5
#define MIPS_REVISION_CORID (((*(volatile u32 *)(MIPS_REVISION_REG)) >> 10) & 0x3f)
extern unsigned int mips_revision_corid;
/*
......@@ -67,4 +93,19 @@
#define GT_PCI_READ(ofs, data) \
data = *(volatile u32 *)(MIPS_GT_BASE+ofs)
/*
* Algorithmics Bonito64 system controller register base.
*/
static char * const _bonito = (char *)KSEG1ADDR(BONITO_REG_BASE);
/*
* MIPS System controller PCI register base.
*/
#define MSC01_PCI_REG_BASE (KSEG1ADDR(0x1bd00000))
#define MSC_WRITE(reg, data) \
*(volatile u32 *)(reg) = data
#define MSC_READ(reg, data) \
data = *(volatile u32 *)(reg)
#endif /* !(_MIPS_GENERIC_H) */
include/asm-mips64/mips-boards/malta.h
View file @ 5d3adbe2
......@@ -29,9 +29,26 @@
#include <asm/io.h>
/*
* Malta I/O ports base address.
*/
#define MALTA_PORT_BASE (KSEG1ADDR(0x18000000))
* Malta I/O ports base address for the Galileo GT64120 and Algorithmics
* Bonito system controllers.
*/
#define MALTA_GT_PORT_BASE get_gt_port_base(GT_PCI0IOLD_OFS)
#define MALTA_BONITO_PORT_BASE (KSEG1ADDR(0x1fd00000))
#define MALTA_MSC_PORT_BASE get_msc_port_base(MSC01_PCI_SC2PIOBASL)
static inline unsigned long get_gt_port_base(unsigned long reg)
{
unsigned long addr;
GT_READ(reg, addr);
return KSEG1ADDR((addr & 0xffff) << 21);
}
static inline unsigned long get_msc_port_base(unsigned long reg)
{
unsigned long addr;
MSC_READ(reg, addr);
return KSEG1ADDR(addr);
}
/*
* Malta RTC-device indirect register access.
......@@ -56,4 +73,6 @@
#define SMSC_WRITE(x,a) outb(x,a)
#define MALTA_JMPRS_REG (KSEG1ADDR(0x1f000210))
#endif /* !(_MIPS_MALTA_H) */
include/asm-mips64/mips-boards/msc01_pci.h 0 → 100644
View file @ 5d3adbe2
/*
* mcs01_pci.h
*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
* PCI Register definitions for the MIPS System Controller.
*/
#ifndef MSC01_PCI_H
#define MSC01_PCI_H
/*****************************************************************************
* Register offset addresses
****************************************************************************/
#define MSC01_PCI_ID_OFS 0x0000
#define MSC01_PCI_SC2PMBASL_OFS 0x0208
#define MSC01_PCI_SC2PMMSKL_OFS 0x0218
#define MSC01_PCI_SC2PMMAPL_OFS 0x0228
#define MSC01_PCI_SC2PIOBASL_OFS 0x0248
#define MSC01_PCI_SC2PIOMSKL_OFS 0x0258
#define MSC01_PCI_SC2PIOMAPL_OFS 0x0268
#define MSC01_PCI_P2SCMSKL_OFS 0x0308
#define MSC01_PCI_P2SCMAPL_OFS 0x0318
#define MSC01_PCI_INTCFG_OFS 0x0600
#define MSC01_PCI_INTSTAT_OFS 0x0608
#define MSC01_PCI_CFGADDR_OFS 0x0610
#define MSC01_PCI_CFGDATA_OFS 0x0618
#define MSC01_PCI_IACK_OFS 0x0620
#define MSC01_PCI_HEAD0_OFS 0x2000 /* DevID, VendorID */
#define MSC01_PCI_HEAD1_OFS 0x2008 /* Status, Command */
#define MSC01_PCI_HEAD2_OFS 0x2010 /* Class code, RevID */
#define MSC01_PCI_HEAD3_OFS 0x2018 /* bist, header, latency */
#define MSC01_PCI_HEAD4_OFS 0x2020 /* BAR 0 */
#define MSC01_PCI_HEAD5_OFS 0x2028 /* BAR 1 */
#define MSC01_PCI_HEAD6_OFS 0x2030 /* BAR 2 */
#define MSC01_PCI_HEAD7_OFS 0x2038 /* BAR 3 */
#define MSC01_PCI_HEAD8_OFS 0x2040 /* BAR 4 */
#define MSC01_PCI_HEAD9_OFS 0x2048 /* BAR 5 */
#define MSC01_PCI_HEAD10_OFS 0x2050 /* CardBus CIS Ptr */
#define MSC01_PCI_HEAD11_OFS 0x2058 /* SubSystem ID, -VendorID */
#define MSC01_PCI_HEAD12_OFS 0x2060 /* ROM BAR */
#define MSC01_PCI_HEAD13_OFS 0x2068 /* Capabilities ptr */
#define MSC01_PCI_HEAD14_OFS 0x2070 /* reserved */
#define MSC01_PCI_HEAD15_OFS 0x2078 /* Maxl, ming, intpin, int */
#define MSC01_PCI_BAR0_OFS 0x2220
#define MSC01_PCI_CFG_OFS 0x2380
#define MSC01_PCI_SWAP_OFS 0x2388
/*****************************************************************************
* Register encodings
****************************************************************************/
#define MSC01_PCI_ID_ID_SHF 16
#define MSC01_PCI_ID_ID_MSK 0x00ff0000
#define MSC01_PCI_ID_ID_HOSTBRIDGE 82
#define MSC01_PCI_ID_MAR_SHF 8
#define MSC01_PCI_ID_MAR_MSK 0x0000ff00
#define MSC01_PCI_ID_MIR_SHF 0
#define MSC01_PCI_ID_MIR_MSK 0x000000ff
#define MSC01_PCI_SC2PMBASL_BAS_SHF 24
#define MSC01_PCI_SC2PMBASL_BAS_MSK 0xff000000
#define MSC01_PCI_SC2PMMSKL_MSK_SHF 24
#define MSC01_PCI_SC2PMMSKL_MSK_MSK 0xff000000
#define MSC01_PCI_SC2PMMAPL_MAP_SHF 24
#define MSC01_PCI_SC2PMMAPL_MAP_MSK 0xff000000
#define MSC01_PCI_SC2PIOBASL_BAS_SHF 24
#define MSC01_PCI_SC2PIOBASL_BAS_MSK 0xff000000
#define MSC01_PCI_SC2PIOMSKL_MSK_SHF 24
#define MSC01_PCI_SC2PIOMSKL_MSK_MSK 0xff000000
#define MSC01_PCI_SC2PIOMAPL_MAP_SHF 24
#define MSC01_PCI_SC2PIOMAPL_MAP_MSK 0xff000000
#define MSC01_PCI_P2SCMSKL_MSK_SHF 24
#define MSC01_PCI_P2SCMSKL_MSK_MSK 0xff000000
#define MSC01_PCI_P2SCMAPL_MAP_SHF 24
#define MSC01_PCI_P2SCMAPL_MAP_MSK 0xff000000
#define MSC01_PCI_INTCFG_RST_SHF 10
#define MSC01_PCI_INTCFG_RST_MSK 0x00000400
#define MSC01_PCI_INTCFG_RST_BIT 0x00000400
#define MSC01_PCI_INTCFG_MWE_SHF 9
#define MSC01_PCI_INTCFG_MWE_MSK 0x00000200
#define MSC01_PCI_INTCFG_MWE_BIT 0x00000200
#define MSC01_PCI_INTCFG_DTO_SHF 8
#define MSC01_PCI_INTCFG_DTO_MSK 0x00000100
#define MSC01_PCI_INTCFG_DTO_BIT 0x00000100
#define MSC01_PCI_INTCFG_MA_SHF 7
#define MSC01_PCI_INTCFG_MA_MSK 0x00000080
#define MSC01_PCI_INTCFG_MA_BIT 0x00000080
#define MSC01_PCI_INTCFG_TA_SHF 6
#define MSC01_PCI_INTCFG_TA_MSK 0x00000040
#define MSC01_PCI_INTCFG_TA_BIT 0x00000040
#define MSC01_PCI_INTCFG_RTY_SHF 5
#define MSC01_PCI_INTCFG_RTY_MSK 0x00000020
#define MSC01_PCI_INTCFG_RTY_BIT 0x00000020
#define MSC01_PCI_INTCFG_MWP_SHF 4
#define MSC01_PCI_INTCFG_MWP_MSK 0x00000010
#define MSC01_PCI_INTCFG_MWP_BIT 0x00000010
#define MSC01_PCI_INTCFG_MRP_SHF 3
#define MSC01_PCI_INTCFG_MRP_MSK 0x00000008
#define MSC01_PCI_INTCFG_MRP_BIT 0x00000008
#define MSC01_PCI_INTCFG_SWP_SHF 2
#define MSC01_PCI_INTCFG_SWP_MSK 0x00000004
#define MSC01_PCI_INTCFG_SWP_BIT 0x00000004
#define MSC01_PCI_INTCFG_SRP_SHF 1
#define MSC01_PCI_INTCFG_SRP_MSK 0x00000002
#define MSC01_PCI_INTCFG_SRP_BIT 0x00000002
#define MSC01_PCI_INTCFG_SE_SHF 0
#define MSC01_PCI_INTCFG_SE_MSK 0x00000001
#define MSC01_PCI_INTCFG_SE_BIT 0x00000001
#define MSC01_PCI_INTSTAT_RST_SHF 10
#define MSC01_PCI_INTSTAT_RST_MSK 0x00000400
#define MSC01_PCI_INTSTAT_RST_BIT 0x00000400
#define MSC01_PCI_INTSTAT_MWE_SHF 9
#define MSC01_PCI_INTSTAT_MWE_MSK 0x00000200
#define MSC01_PCI_INTSTAT_MWE_BIT 0x00000200
#define MSC01_PCI_INTSTAT_DTO_SHF 8
#define MSC01_PCI_INTSTAT_DTO_MSK 0x00000100
#define MSC01_PCI_INTSTAT_DTO_BIT 0x00000100
#define MSC01_PCI_INTSTAT_MA_SHF 7
#define MSC01_PCI_INTSTAT_MA_MSK 0x00000080
#define MSC01_PCI_INTSTAT_MA_BIT 0x00000080
#define MSC01_PCI_INTSTAT_TA_SHF 6
#define MSC01_PCI_INTSTAT_TA_MSK 0x00000040
#define MSC01_PCI_INTSTAT_TA_BIT 0x00000040
#define MSC01_PCI_INTSTAT_RTY_SHF 5
#define MSC01_PCI_INTSTAT_RTY_MSK 0x00000020
#define MSC01_PCI_INTSTAT_RTY_BIT 0x00000020
#define MSC01_PCI_INTSTAT_MWP_SHF 4
#define MSC01_PCI_INTSTAT_MWP_MSK 0x00000010
#define MSC01_PCI_INTSTAT_MWP_BIT 0x00000010
#define MSC01_PCI_INTSTAT_MRP_SHF 3
#define MSC01_PCI_INTSTAT_MRP_MSK 0x00000008
#define MSC01_PCI_INTSTAT_MRP_BIT 0x00000008
#define MSC01_PCI_INTSTAT_SWP_SHF 2
#define MSC01_PCI_INTSTAT_SWP_MSK 0x00000004
#define MSC01_PCI_INTSTAT_SWP_BIT 0x00000004
#define MSC01_PCI_INTSTAT_SRP_SHF 1
#define MSC01_PCI_INTSTAT_SRP_MSK 0x00000002
#define MSC01_PCI_INTSTAT_SRP_BIT 0x00000002
#define MSC01_PCI_INTSTAT_SE_SHF 0
#define MSC01_PCI_INTSTAT_SE_MSK 0x00000001
#define MSC01_PCI_INTSTAT_SE_BIT 0x00000001
#define MSC01_PCI_CFGADDR_BNUM_SHF 16
#define MSC01_PCI_CFGADDR_BNUM_MSK 0x00ff0000
#define MSC01_PCI_CFGADDR_DNUM_SHF 11
#define MSC01_PCI_CFGADDR_DNUM_MSK 0x0000f800
#define MSC01_PCI_CFGADDR_FNUM_SHF 8
#define MSC01_PCI_CFGADDR_FNUM_MSK 0x00000700
#define MSC01_PCI_CFGADDR_RNUM_SHF 2
#define MSC01_PCI_CFGADDR_RNUM_MSK 0x000000fc
#define MSC01_PCI_CFGDATA_DATA_SHF 0
#define MSC01_PCI_CFGDATA_DATA_MSK 0xffffffff
/* The defines below are ONLY valid for a MEM bar! */
#define MSC01_PCI_BAR0_SIZE_SHF 4
#define MSC01_PCI_BAR0_SIZE_MSK 0xfffffff0
#define MSC01_PCI_BAR0_P_SHF 3
#define MSC01_PCI_BAR0_P_MSK 0x00000008
#define MSC01_PCI_BAR0_P_BIT MSC01_PCI_BAR0_P_MSK
#define MSC01_PCI_BAR0_D_SHF 1
#define MSC01_PCI_BAR0_D_MSK 0x00000006
#define MSC01_PCI_BAR0_T_SHF 0
#define MSC01_PCI_BAR0_T_MSK 0x00000001
#define MSC01_PCI_BAR0_T_BIT MSC01_PCI_BAR0_T_MSK
#define MSC01_PCI_CFG_RA_SHF 17
#define MSC01_PCI_CFG_RA_MSK 0x00020000
#define MSC01_PCI_CFG_RA_BIT MSC01_PCI_CFG_RA_MSK
#define MSC01_PCI_CFG_G_SHF 16
#define MSC01_PCI_CFG_G_MSK 0x00010000
#define MSC01_PCI_CFG_G_BIT MSC01_PCI_CFG_G_MSK
#define MSC01_PCI_CFG_EN_SHF 15
#define MSC01_PCI_CFG_EN_MSK 0x00008000
#define MSC01_PCI_CFG_EN_BIT MSC01_PCI_CFG_EN_MSK
#define MSC01_PCI_CFG_MAXRTRY_SHF 0
#define MSC01_PCI_CFG_MAXRTRY_MSK 0x000000ff
#define MSC01_PCI_SWAP_IO_SHF 18
#define MSC01_PCI_SWAP_IO_MSK 0x000c0000
#define MSC01_PCI_SWAP_MEM_SHF 16
#define MSC01_PCI_SWAP_MEM_MSK 0x00030000
#define MSC01_PCI_SWAP_BAR0_SHF 0
#define MSC01_PCI_SWAP_BAR0_MSK 0x00000003
#define MSC01_PCI_SWAP_NOSWAP 0
#define MSC01_PCI_SWAP_BYTESWAP 1
/*****************************************************************************
* Registers absolute addresses
****************************************************************************/
#define MSC01_PCI_ID (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS)
#define MSC01_PCI_SC2PMBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS)
#define MSC01_PCI_SC2PMMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS)
#define MSC01_PCI_SC2PMMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS)
#define MSC01_PCI_SC2PIOBASL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS)
#define MSC01_PCI_SC2PIOMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS)
#define MSC01_PCI_SC2PIOMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS)
#define MSC01_PCI_P2SCMSKL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS)
#define MSC01_PCI_P2SCMAPL (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS)
#define MSC01_PCI_INTCFG (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS)
#define MSC01_PCI_INTSTAT (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS)
#define MSC01_PCI_CFGADDR (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS)
#define MSC01_PCI_CFGDATA (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS)
#define MSC01_PCI_IACK (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS)
#define MSC01_PCI_HEAD0 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS)
#define MSC01_PCI_HEAD1 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS)
#define MSC01_PCI_HEAD2 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD2_OFS)
#define MSC01_PCI_HEAD3 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD3_OFS)
#define MSC01_PCI_HEAD4 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD4_OFS)
#define MSC01_PCI_HEAD5 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD5_OFS)
#define MSC01_PCI_HEAD6 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD6_OFS)
#define MSC01_PCI_HEAD7 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD7_OFS)
#define MSC01_PCI_HEAD8 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD8_OFS)
#define MSC01_PCI_HEAD9 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD9_OFS)
#define MSC01_PCI_HEAD10 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD10_OFS)
#define MSC01_PCI_HEAD11 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
#define MSC01_PCI_HEAD12 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
#define MSC01_PCI_HEAD13 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
#define MSC01_PCI_HEAD14 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
#define MSC01_PCI_HEAD15 (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
#define MSC01_PCI_BAR0 (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS)
#define MSC01_PCI_CFG (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS)
#define MSC01_PCI_SWAP (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS)
#endif
/*****************************************************************************
* End of msc01_pci.h
*****************************************************************************/
arch/mips64/mips-boards/atlas/atlas_rtc.c → include/asm-mips64/mips-boards/sead.h
View file @ 5d3adbe2
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
......@@ -19,40 +19,18 @@
*
* ########################################################################
*
* RTC routines for Atlas style attached Dallas chip.
* Defines of the SEAD board specific address-MAP, registers, etc.
*
*/
#include <asm/mc146818rtc.h>
#include <asm/mips-boards/atlas.h>
#ifndef _MIPS_SEAD_H
#define _MIPS_SEAD_H
#include <asm/addrspace.h>
static unsigned char atlas_rtc_read_data(unsigned long addr)
{
volatile unsigned int *rtc_adr_reg = (void *)ATLAS_RTC_ADR_REG;
volatile unsigned int *rtc_dat_reg = (void *)ATLAS_RTC_DAT_REG;
*rtc_adr_reg = addr;
return *rtc_dat_reg;
}
static void atlas_rtc_write_data(unsigned char data, unsigned long addr)
{
volatile unsigned int *rtc_adr_reg = (void *)ATLAS_RTC_ADR_REG;
volatile unsigned int *rtc_dat_reg = (void *)ATLAS_RTC_DAT_REG;
*rtc_adr_reg = addr;
*rtc_dat_reg = data;
}
static int atlas_rtc_bcd_mode(void)
{
return 0;
}
struct rtc_ops atlas_rtc_ops = {
&atlas_rtc_read_data,
&atlas_rtc_write_data,
&atlas_rtc_bcd_mode
};
/*
* SEAD UART register base.
*/
#define SEAD_UART0_REGS_BASE (0x1f000800)
#define SEAD_BASE_BAUD ( 3686400 / 16 )
#endif /* !(_MIPS_SEAD_H) */
arch/mips64/mips-boards/generic/reset.c → include/asm-mips64/mips-boards/seadint.h
View file @ 5d3adbe2
/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved.
*
* ########################################################################
*
......@@ -19,43 +19,17 @@
*
* ########################################################################
*
* Reset the MIPS boards.
* Defines for the SEAD interrupt controller.
*
*/
#include <linux/config.h>
#ifndef _MIPS_SEADINT_H
#define _MIPS_SEADINT_H
#include <asm/mips-boards/generic.h>
#if defined(CONFIG_MIPS_ATLAS)
#include <asm/mips-boards/atlas.h>
#endif
/* Number of IRQ supported */
#define SEADINT_UART0 0
#define SEADINT_UART1 1
#define SEADINT_END 2
void machine_restart(char *command) __attribute__((noreturn));
void machine_halt(void) __attribute__((noreturn));
#if defined(CONFIG_MIPS_ATLAS)
void machine_power_off(void) __attribute__((noreturn));
#endif
extern void seadint_init(void);
void machine_restart(char *command)
{
volatile unsigned int *softres_reg = (void *)SOFTRES_REG;
*softres_reg = GORESET;
}
void machine_halt(void)
{
volatile unsigned int *softres_reg = (void *)SOFTRES_REG;
*softres_reg = GORESET;
}
void machine_power_off(void)
{
#if defined(CONFIG_MIPS_ATLAS)
volatile unsigned int *psustby_reg = (void *)ATLAS_PSUSTBY_REG;
*psustby_reg = ATLAS_GOSTBY;
#else
machine_halt();
#endif
}
#endif /* !(_MIPS_SEADINT_H) */
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