Commit 5d4a9fa6 authored by Luciano Coelho's avatar Luciano Coelho

wl18xx: add register table

Add the register table with the appropriate values for wl18xx.
Signed-off-by: default avatarLuciano Coelho <coelho@ti.com>
Signed-off-by: default avatarArik Nemtsov <arik@wizery.com>
parent 82b890cd
...@@ -25,6 +25,8 @@ ...@@ -25,6 +25,8 @@
#include "../wlcore/wlcore.h" #include "../wlcore/wlcore.h"
#include "../wlcore/debug.h" #include "../wlcore/debug.h"
#include "reg.h"
static struct wlcore_ops wl18xx_ops = { static struct wlcore_ops wl18xx_ops = {
}; };
...@@ -62,6 +64,26 @@ static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = { ...@@ -62,6 +64,26 @@ static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
}, },
}; };
static const int wl18xx_rtable[REG_TABLE_LEN] = {
[REG_ECPU_CONTROL] = WL18XX_REG_ECPU_CONTROL,
[REG_INTERRUPT_NO_CLEAR] = WL18XX_REG_INTERRUPT_NO_CLEAR,
[REG_INTERRUPT_ACK] = WL18XX_REG_INTERRUPT_ACK,
[REG_COMMAND_MAILBOX_PTR] = WL18XX_REG_COMMAND_MAILBOX_PTR,
[REG_EVENT_MAILBOX_PTR] = WL18XX_REG_EVENT_MAILBOX_PTR,
[REG_INTERRUPT_TRIG] = WL18XX_REG_INTERRUPT_TRIG_H,
[REG_INTERRUPT_MASK] = WL18XX_REG_INTERRUPT_MASK,
[REG_PC_ON_RECOVERY] = 0, /* TODO: where is the PC? */
[REG_CHIP_ID_B] = WL18XX_REG_CHIP_ID_B,
[REG_CMD_MBOX_ADDRESS] = WL18XX_CMD_MBOX_ADDRESS,
/* data access memory addresses, used with partition translation */
[REG_SLV_MEM_DATA] = WL18XX_SLV_MEM_DATA,
[REG_SLV_REG_DATA] = WL18XX_SLV_REG_DATA,
/* raw data access memory addresses */
[REG_RAW_FW_STATUS_ADDR] = WL18XX_FW_STATUS_ADDR,
};
int __devinit wl18xx_probe(struct platform_device *pdev) int __devinit wl18xx_probe(struct platform_device *pdev)
{ {
struct wl1271 *wl; struct wl1271 *wl;
...@@ -76,6 +98,7 @@ int __devinit wl18xx_probe(struct platform_device *pdev) ...@@ -76,6 +98,7 @@ int __devinit wl18xx_probe(struct platform_device *pdev)
wl = hw->priv; wl = hw->priv;
wl->ops = &wl18xx_ops; wl->ops = &wl18xx_ops;
wl->ptable = wl18xx_ptable; wl->ptable = wl18xx_ptable;
wl->rtable = wl18xx_rtable;
return wlcore_probe(wl, pdev); return wlcore_probe(wl, pdev);
} }
......
/*
* This file is part of wlcore
*
* Copyright (C) 2011 Texas Instruments Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#ifndef __REG_H__
#define __REG_H__
#define WL18XX_REGISTERS_BASE 0x00800000
#define WL18XX_CODE_BASE 0x00000000
#define WL18XX_DATA_BASE 0x00400000
#define WL18XX_DOUBLE_BUFFER_BASE 0x00600000
#define WL18XX_MCU_KEY_SEARCH_BASE 0x00700000
#define WL18XX_PHY_BASE 0x00900000
#define WL18XX_TOP_OCP_BASE 0x00A00000
#define WL18XX_PACKET_RAM_BASE 0x00B00000
#define WL18XX_HOST_BASE 0x00C00000
#define WL18XX_REGISTERS_DOWN_SIZE 0x0000B000
#define WL18XX_REG_BOOT_PART_START 0x00802000
#define WL18XX_REG_BOOT_PART_SIZE 0x00014578
#define WL18XX_PHY_INIT_MEM_ADDR 0x80926000
#define WL18XX_SDIO_WSPI_BASE (WL18XX_REGISTERS_BASE)
#define WL18XX_REG_CONFIG_BASE (WL18XX_REGISTERS_BASE + 0x02000)
#define WL18XX_WGCM_REGS_BASE (WL18XX_REGISTERS_BASE + 0x03000)
#define WL18XX_ENC_BASE (WL18XX_REGISTERS_BASE + 0x04000)
#define WL18XX_INTERRUPT_BASE (WL18XX_REGISTERS_BASE + 0x05000)
#define WL18XX_UART_BASE (WL18XX_REGISTERS_BASE + 0x06000)
#define WL18XX_WELP_BASE (WL18XX_REGISTERS_BASE + 0x07000)
#define WL18XX_TCP_CKSM_BASE (WL18XX_REGISTERS_BASE + 0x08000)
#define WL18XX_FIFO_BASE (WL18XX_REGISTERS_BASE + 0x09000)
#define WL18XX_OCP_BRIDGE_BASE (WL18XX_REGISTERS_BASE + 0x0A000)
#define WL18XX_PMAC_RX_BASE (WL18XX_REGISTERS_BASE + 0x14800)
#define WL18XX_PMAC_ACM_BASE (WL18XX_REGISTERS_BASE + 0x14C00)
#define WL18XX_PMAC_TX_BASE (WL18XX_REGISTERS_BASE + 0x15000)
#define WL18XX_PMAC_CSR_BASE (WL18XX_REGISTERS_BASE + 0x15400)
#define WL18XX_REG_ECPU_CONTROL (WL18XX_REGISTERS_BASE + 0x02004)
#define WL18XX_REG_INTERRUPT_NO_CLEAR (WL18XX_REGISTERS_BASE + 0x050E8)
#define WL18XX_REG_INTERRUPT_ACK (WL18XX_REGISTERS_BASE + 0x050F0)
#define WL18XX_REG_INTERRUPT_TRIG (WL18XX_REGISTERS_BASE + 0x5074)
#define WL18XX_REG_INTERRUPT_TRIG_H (WL18XX_REGISTERS_BASE + 0x5078)
#define WL18XX_REG_INTERRUPT_MASK (WL18XX_REGISTERS_BASE + 0x0050DC)
#define WL18XX_REG_CHIP_ID_B (WL18XX_REGISTERS_BASE + 0x01542C)
#define WL18XX_SLV_MEM_DATA (WL18XX_HOST_BASE + 0x0018)
#define WL18XX_SLV_REG_DATA (WL18XX_HOST_BASE + 0x0008)
/* Scratch Pad registers*/
#define WL18XX_SCR_PAD0 (WL18XX_REGISTERS_BASE + 0x0154EC)
#define WL18XX_SCR_PAD1 (WL18XX_REGISTERS_BASE + 0x0154F0)
#define WL18XX_SCR_PAD2 (WL18XX_REGISTERS_BASE + 0x0154F4)
#define WL18XX_SCR_PAD3 (WL18XX_REGISTERS_BASE + 0x0154F8)
#define WL18XX_SCR_PAD4 (WL18XX_REGISTERS_BASE + 0x0154FC)
#define WL18XX_SCR_PAD4_SET (WL18XX_REGISTERS_BASE + 0x015504)
#define WL18XX_SCR_PAD4_CLR (WL18XX_REGISTERS_BASE + 0x015500)
#define WL18XX_SCR_PAD5 (WL18XX_REGISTERS_BASE + 0x015508)
#define WL18XX_SCR_PAD5_SET (WL18XX_REGISTERS_BASE + 0x015510)
#define WL18XX_SCR_PAD5_CLR (WL18XX_REGISTERS_BASE + 0x01550C)
#define WL18XX_SCR_PAD6 (WL18XX_REGISTERS_BASE + 0x015514)
#define WL18XX_SCR_PAD7 (WL18XX_REGISTERS_BASE + 0x015518)
#define WL18XX_SCR_PAD8 (WL18XX_REGISTERS_BASE + 0x01551C)
#define WL18XX_SCR_PAD9 (WL18XX_REGISTERS_BASE + 0x015520)
/* Spare registers*/
#define WL18XX_SPARE_A1 (WL18XX_REGISTERS_BASE + 0x002194)
#define WL18XX_SPARE_A2 (WL18XX_REGISTERS_BASE + 0x002198)
#define WL18XX_SPARE_A3 (WL18XX_REGISTERS_BASE + 0x00219C)
#define WL18XX_SPARE_A4 (WL18XX_REGISTERS_BASE + 0x0021A0)
#define WL18XX_SPARE_A5 (WL18XX_REGISTERS_BASE + 0x0021A4)
#define WL18XX_SPARE_A6 (WL18XX_REGISTERS_BASE + 0x0021A8)
#define WL18XX_SPARE_A7 (WL18XX_REGISTERS_BASE + 0x0021AC)
#define WL18XX_SPARE_A8 (WL18XX_REGISTERS_BASE + 0x0021B0)
#define WL18XX_SPARE_B1 (WL18XX_REGISTERS_BASE + 0x015524)
#define WL18XX_SPARE_B2 (WL18XX_REGISTERS_BASE + 0x015528)
#define WL18XX_SPARE_B3 (WL18XX_REGISTERS_BASE + 0x01552C)
#define WL18XX_SPARE_B4 (WL18XX_REGISTERS_BASE + 0x015530)
#define WL18XX_SPARE_B5 (WL18XX_REGISTERS_BASE + 0x015534)
#define WL18XX_SPARE_B6 (WL18XX_REGISTERS_BASE + 0x015538)
#define WL18XX_SPARE_B7 (WL18XX_REGISTERS_BASE + 0x01553C)
#define WL18XX_SPARE_B8 (WL18XX_REGISTERS_BASE + 0x015540)
#define WL18XX_REG_COMMAND_MAILBOX_PTR (WL18XX_SCR_PAD0)
#define WL18XX_REG_EVENT_MAILBOX_PTR (WL18XX_SCR_PAD1)
#define WL18XX_CMD_MBOX_ADDRESS 0xB007B4
#define WL18XX_FW_STATUS_ADDR 0x50F8
#define CHIP_ID_185x_PG10 (0x06030101)
#endif /* __REG_H__ */
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment