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Commit 5eb4573e authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'soc-fixes-6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull ARM SoC fixes from Arnd Bergmann:
 "There are a lot of minor DT fixes for Mediatek, Rockchip, Qualcomm and
  Microchip and NXP, addressing both build-time warnings and bugs found
  during runtime testing.

  Most of these changes are machine specific fixups, but there are a few
  notable regressions that affect an entire SoC:

   - The Qualcomm MSI support that was improved for 6.9 ended up being
     wrong on some chips and now gets fixed.

   - The i.MX8MP camera interface broke due to a typo and gets updated
     again.

  The main driver fix is also for Qualcomm platforms, rewriting an
  interface in the QSEECOM firmware support that could lead to crashing
  the kernel from a trusted application.

  The only other code changes are minor fixes for Mediatek SoC drivers"

* tag 'soc-fixes-6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (50 commits)
  ARM: dts: imx6ull-tarragon: fix USB over-current polarity
  soc: mediatek: mtk-socinfo: depends on CONFIG_SOC_BUS
  soc: mediatek: mtk-svs: Append "-thermal" to thermal zone names
  arm64: dts: imx8mp: Fix assigned-clocks for second CSI2
  ARM: dts: microchip: at91-sama7g54_curiosity: Replace regulator-suspend-voltage with the valid property
  ARM: dts: microchip: at91-sama7g5ek: Replace regulator-suspend-voltage with the valid property
  arm64: dts: rockchip: Fix USB interface compatible string on kobol-helios64
  arm64: dts: qcom: sc8180x: Fix ss_phy_irq for secondary USB controller
  arm64: dts: qcom: sm8650: Fix the msi-map entries
  arm64: dts: qcom: sm8550: Fix the msi-map entries
  arm64: dts: qcom: sm8450: Fix the msi-map entries
  arm64: dts: qcom: sc8280xp: add missing PCIe minimum OPP
  arm64: dts: qcom: x1e80100: Fix the compatible for cluster idle states
  arm64: dts: qcom: Fix type of "wdog" IRQs for remoteprocs
  arm64: dts: rockchip: regulator for sd needs to be always on for BPI-R2Pro
  dt-bindings: rockchip: grf: Add missing type to 'pcie-phy' node
  arm64: dts: rockchip: drop redundant disable-gpios in Lubancat 2
  arm64: dts: rockchip: drop redundant disable-gpios in Lubancat 1
  arm64: dts: rockchip: drop redundant pcie-reset-suspend in Scarlet Dumo
  arm64: dts: rockchip: mark system power controller and fix typo on orangepi-5-plus
  ...
parents e6ebf011 9f26bc71
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Showing with 331 additions and 193 deletions
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
View file @ 5eb4573e
...@@ -171,6 +171,7 @@ allOf: ...@@ -171,6 +171,7 @@ allOf:
unevaluatedProperties: false unevaluatedProperties: false
pcie-phy: pcie-phy:
type: object
description: description:
Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
......
arch/arm/boot/dts/microchip/at91-sama7g54_curiosity.dts
View file @ 5eb4573e
...@@ -242,7 +242,7 @@ vddcore: VDD_CORE { ...@@ -242,7 +242,7 @@ vddcore: VDD_CORE {
regulator-state-standby { regulator-state-standby {
regulator-on-in-suspend; regulator-on-in-suspend;
regulator-suspend-voltage = <1150000>; regulator-suspend-microvolt = <1150000>;
regulator-mode = <4>; regulator-mode = <4>;
}; };
...@@ -263,7 +263,7 @@ vddcpu: VDD_OTHER { ...@@ -263,7 +263,7 @@ vddcpu: VDD_OTHER {
regulator-state-standby { regulator-state-standby {
regulator-on-in-suspend; regulator-on-in-suspend;
regulator-suspend-voltage = <1050000>; regulator-suspend-microvolt = <1050000>;
regulator-mode = <4>; regulator-mode = <4>;
}; };
...@@ -280,7 +280,7 @@ vldo1: LDO1 { ...@@ -280,7 +280,7 @@ vldo1: LDO1 {
regulator-always-on; regulator-always-on;
regulator-state-standby { regulator-state-standby {
regulator-suspend-voltage = <1800000>; regulator-suspend-microvolt = <1800000>;
regulator-on-in-suspend; regulator-on-in-suspend;
}; };
...@@ -296,7 +296,7 @@ vldo2: LDO2 { ...@@ -296,7 +296,7 @@ vldo2: LDO2 {
regulator-always-on; regulator-always-on;
regulator-state-standby { regulator-state-standby {
regulator-suspend-voltage = <3300000>; regulator-suspend-microvolt = <3300000>;
regulator-on-in-suspend; regulator-on-in-suspend;
}; };
......
arch/arm/boot/dts/microchip/at91-sama7g5ek.dts
View file @ 5eb4573e
...@@ -293,7 +293,7 @@ vddcore: VDD_CORE { ...@@ -293,7 +293,7 @@ vddcore: VDD_CORE {
regulator-state-standby { regulator-state-standby {
regulator-on-in-suspend; regulator-on-in-suspend;
regulator-suspend-voltage = <1150000>; regulator-suspend-microvolt = <1150000>;
regulator-mode = <4>; regulator-mode = <4>;
}; };
...@@ -314,7 +314,7 @@ vddcpu: VDD_OTHER { ...@@ -314,7 +314,7 @@ vddcpu: VDD_OTHER {
regulator-state-standby { regulator-state-standby {
regulator-on-in-suspend; regulator-on-in-suspend;
regulator-suspend-voltage = <1050000>; regulator-suspend-microvolt = <1050000>;
regulator-mode = <4>; regulator-mode = <4>;
}; };
...@@ -331,7 +331,7 @@ vldo1: LDO1 { ...@@ -331,7 +331,7 @@ vldo1: LDO1 {
regulator-always-on; regulator-always-on;
regulator-state-standby { regulator-state-standby {
regulator-suspend-voltage = <1800000>; regulator-suspend-microvolt = <1800000>;
regulator-on-in-suspend; regulator-on-in-suspend;
}; };
...@@ -346,7 +346,7 @@ vldo2: LDO2 { ...@@ -346,7 +346,7 @@ vldo2: LDO2 {
regulator-max-microvolt = <3700000>; regulator-max-microvolt = <3700000>;
regulator-state-standby { regulator-state-standby {
regulator-suspend-voltage = <1800000>; regulator-suspend-microvolt = <1800000>;
regulator-on-in-suspend; regulator-on-in-suspend;
}; };
......
arch/arm/boot/dts/nxp/imx/imx6ull-tarragon-common.dtsi
View file @ 5eb4573e
...@@ -805,6 +805,7 @@ &usbotg1 { ...@@ -805,6 +805,7 @@ &usbotg1 {
&pinctrl_usb_pwr>; &pinctrl_usb_pwr>;
dr_mode = "host"; dr_mode = "host";
power-active-high; power-active-high;
over-current-active-low;
disable-over-current; disable-over-current;
status = "okay"; status = "okay";
}; };
......
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View file @ 5eb4573e
...@@ -1672,7 +1672,7 @@ mipi_csi_1: csi@32e50000 { ...@@ -1672,7 +1672,7 @@ mipi_csi_1: csi@32e50000 {
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
<&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
clock-names = "pclk", "wrap", "phy", "axi"; clock-names = "pclk", "wrap", "phy", "axi";
assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>,
<&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
<&clk IMX8MP_CLK_24M>; <&clk IMX8MP_CLK_24M>;
......
arch/arm64/boot/dts/mediatek/mt2712-evb.dts
View file @ 5eb4573e
...@@ -129,7 +129,7 @@ ethernet_phy0: ethernet-phy@5 { ...@@ -129,7 +129,7 @@ ethernet_phy0: ethernet-phy@5 {
}; };
&pio { &pio {
eth_default: eth_default { eth_default: eth-default-pins {
tx_pins { tx_pins {
pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3>, pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3>,
<MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2>, <MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2>,
...@@ -156,7 +156,7 @@ mdio_pins { ...@@ -156,7 +156,7 @@ mdio_pins {
}; };
}; };
eth_sleep: eth_sleep { eth_sleep: eth-sleep-pins {
tx_pins { tx_pins {
pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71>, pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71>,
<MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72>, <MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72>,
...@@ -182,14 +182,14 @@ mdio_pins { ...@@ -182,14 +182,14 @@ mdio_pins {
}; };
}; };
usb0_id_pins_float: usb0_iddig { usb0_id_pins_float: usb0-iddig-pins {
pins_iddig { pins_iddig {
pinmux = <MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A>; pinmux = <MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A>;
bias-pull-up; bias-pull-up;
}; };
}; };
usb1_id_pins_float: usb1_iddig { usb1_id_pins_float: usb1-iddig-pins {
pins_iddig { pins_iddig {
pinmux = <MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B>; pinmux = <MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B>;
bias-pull-up; bias-pull-up;
......
arch/arm64/boot/dts/mediatek/mt2712e.dtsi
View file @ 5eb4573e
...@@ -249,10 +249,11 @@ topckgen: syscon@10000000 { ...@@ -249,10 +249,11 @@ topckgen: syscon@10000000 {
#clock-cells = <1>; #clock-cells = <1>;
}; };
infracfg: syscon@10001000 { infracfg: clock-controller@10001000 {
compatible = "mediatek,mt2712-infracfg", "syscon"; compatible = "mediatek,mt2712-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>; reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>;
}; };
pericfg: syscon@10003000 { pericfg: syscon@10003000 {
......
arch/arm64/boot/dts/mediatek/mt7622.dtsi
View file @ 5eb4573e
...@@ -252,7 +252,7 @@ scpsys: power-controller@10006000 { ...@@ -252,7 +252,7 @@ scpsys: power-controller@10006000 {
clock-names = "hif_sel"; clock-names = "hif_sel";
}; };
cir: cir@10009000 { cir: ir-receiver@10009000 {
compatible = "mediatek,mt7622-cir"; compatible = "mediatek,mt7622-cir";
reg = <0 0x10009000 0 0x1000>; reg = <0 0x10009000 0 0x1000>;
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>; interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
...@@ -283,16 +283,14 @@ thermal_calibration: calib@198 { ...@@ -283,16 +283,14 @@ thermal_calibration: calib@198 {
}; };
}; };
apmixedsys: apmixedsys@10209000 { apmixedsys: clock-controller@10209000 {
compatible = "mediatek,mt7622-apmixedsys", compatible = "mediatek,mt7622-apmixedsys";
"syscon";
reg = <0 0x10209000 0 0x1000>; reg = <0 0x10209000 0 0x1000>;
#clock-cells = <1>; #clock-cells = <1>;
}; };
topckgen: topckgen@10210000 { topckgen: clock-controller@10210000 {
compatible = "mediatek,mt7622-topckgen", compatible = "mediatek,mt7622-topckgen";
"syscon";
reg = <0 0x10210000 0 0x1000>; reg = <0 0x10210000 0 0x1000>;
#clock-cells = <1>; #clock-cells = <1>;
}; };
...@@ -515,7 +513,6 @@ thermal: thermal@1100b000 { ...@@ -515,7 +513,6 @@ thermal: thermal@1100b000 {
<&pericfg CLK_PERI_AUXADC_PD>; <&pericfg CLK_PERI_AUXADC_PD>;
clock-names = "therm", "auxadc"; clock-names = "therm", "auxadc";
resets = <&pericfg MT7622_PERI_THERM_SW_RST>; resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
reset-names = "therm";
mediatek,auxadc = <&auxadc>; mediatek,auxadc = <&auxadc>;
mediatek,apmixedsys = <&apmixedsys>; mediatek,apmixedsys = <&apmixedsys>;
nvmem-cells = <&thermal_calibration>; nvmem-cells = <&thermal_calibration>;
...@@ -734,9 +731,8 @@ wmac: wmac@18000000 { ...@@ -734,9 +731,8 @@ wmac: wmac@18000000 {
power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>; power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
}; };
ssusbsys: ssusbsys@1a000000 { ssusbsys: clock-controller@1a000000 {
compatible = "mediatek,mt7622-ssusbsys", compatible = "mediatek,mt7622-ssusbsys";
"syscon";
reg = <0 0x1a000000 0 0x1000>; reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
...@@ -793,9 +789,8 @@ u2port1: usb-phy@1a0c5000 { ...@@ -793,9 +789,8 @@ u2port1: usb-phy@1a0c5000 {
}; };
}; };
pciesys: pciesys@1a100800 { pciesys: clock-controller@1a100800 {
compatible = "mediatek,mt7622-pciesys", compatible = "mediatek,mt7622-pciesys";
"syscon";
reg = <0 0x1a100800 0 0x1000>; reg = <0 0x1a100800 0 0x1000>;
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
...@@ -921,12 +916,13 @@ sata_port: sata-phy@1a243000 { ...@@ -921,12 +916,13 @@ sata_port: sata-phy@1a243000 {
}; };
}; };
hifsys: syscon@1af00000 { hifsys: clock-controller@1af00000 {
compatible = "mediatek,mt7622-hifsys", "syscon"; compatible = "mediatek,mt7622-hifsys";
reg = <0 0x1af00000 0 0x70>; reg = <0 0x1af00000 0 0x70>;
#clock-cells = <1>;
}; };
ethsys: syscon@1b000000 { ethsys: clock-controller@1b000000 {
compatible = "mediatek,mt7622-ethsys", compatible = "mediatek,mt7622-ethsys",
"syscon"; "syscon";
reg = <0 0x1b000000 0 0x1000>; reg = <0 0x1b000000 0 0x1000>;
...@@ -966,9 +962,7 @@ wed1: wed@1020b000 { ...@@ -966,9 +962,7 @@ wed1: wed@1020b000 {
}; };
eth: ethernet@1b100000 { eth: ethernet@1b100000 {
compatible = "mediatek,mt7622-eth", compatible = "mediatek,mt7622-eth";
"mediatek,mt2701-eth",
"syscon";
reg = <0 0x1b100000 0 0x20000>; reg = <0 0x1b100000 0 0x20000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>, interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>, <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
......
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
View file @ 5eb4573e
...@@ -146,19 +146,19 @@ sfp2: sfp-2 { ...@@ -146,19 +146,19 @@ sfp2: sfp-2 {
&cpu_thermal { &cpu_thermal {
cooling-maps { cooling-maps {
cpu-active-high { map-cpu-active-high {
/* active: set fan to cooling level 2 */ /* active: set fan to cooling level 2 */
cooling-device = <&fan 2 2>; cooling-device = <&fan 2 2>;
trip = <&cpu_trip_active_high>; trip = <&cpu_trip_active_high>;
}; };
cpu-active-med { map-cpu-active-med {
/* active: set fan to cooling level 1 */ /* active: set fan to cooling level 1 */
cooling-device = <&fan 1 1>; cooling-device = <&fan 1 1>;
trip = <&cpu_trip_active_med>; trip = <&cpu_trip_active_med>;
}; };
cpu-active-low { map-cpu-active-low {
/* active: set fan to cooling level 0 */ /* active: set fan to cooling level 0 */
cooling-device = <&fan 0 0>; cooling-device = <&fan 0 0>;
trip = <&cpu_trip_active_low>; trip = <&cpu_trip_active_low>;
......
arch/arm64/boot/dts/mediatek/mt7986a.dtsi
View file @ 5eb4573e
...@@ -332,9 +332,8 @@ thermal: thermal@1100c800 { ...@@ -332,9 +332,8 @@ thermal: thermal@1100c800 {
reg = <0 0x1100c800 0 0x800>; reg = <0 0x1100c800 0 0x800>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_INFRA_THERM_CK>, clocks = <&infracfg CLK_INFRA_THERM_CK>,
<&infracfg CLK_INFRA_ADC_26M_CK>, <&infracfg CLK_INFRA_ADC_26M_CK>;
<&infracfg CLK_INFRA_ADC_FRC_CK>; clock-names = "therm", "auxadc";
clock-names = "therm", "auxadc", "adc_32k";
nvmem-cells = <&thermal_calibration>; nvmem-cells = <&thermal_calibration>;
nvmem-cell-names = "calibration-data"; nvmem-cell-names = "calibration-data";
#thermal-sensor-cells = <1>; #thermal-sensor-cells = <1>;
...@@ -492,8 +491,6 @@ ethsys: syscon@15000000 { ...@@ -492,8 +491,6 @@ ethsys: syscon@15000000 {
compatible = "mediatek,mt7986-ethsys", compatible = "mediatek,mt7986-ethsys",
"syscon"; "syscon";
reg = <0 0x15000000 0 0x1000>; reg = <0 0x15000000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
}; };
...@@ -556,7 +553,6 @@ eth: ethernet@15100000 { ...@@ -556,7 +553,6 @@ eth: ethernet@15100000 {
<&topckgen CLK_TOP_SGM_325M_SEL>; <&topckgen CLK_TOP_SGM_325M_SEL>;
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
<&apmixedsys CLK_APMIXED_SGMPLL>; <&apmixedsys CLK_APMIXED_SGMPLL>;
#reset-cells = <1>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
mediatek,ethsys = <&ethsys>; mediatek,ethsys = <&ethsys>;
......
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
View file @ 5eb4573e
...@@ -433,7 +433,6 @@ &mt6358regulator { ...@@ -433,7 +433,6 @@ &mt6358regulator {
}; };
&mt6358_vgpu_reg { &mt6358_vgpu_reg {
regulator-min-microvolt = <625000>;
regulator-max-microvolt = <900000>; regulator-max-microvolt = <900000>;
regulator-coupled-with = <&mt6358_vsram_gpu_reg>; regulator-coupled-with = <&mt6358_vsram_gpu_reg>;
......
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View file @ 5eb4573e
...@@ -1637,6 +1637,7 @@ mfgcfg: syscon@13000000 { ...@@ -1637,6 +1637,7 @@ mfgcfg: syscon@13000000 {
compatible = "mediatek,mt8183-mfgcfg", "syscon"; compatible = "mediatek,mt8183-mfgcfg", "syscon";
reg = <0 0x13000000 0 0x1000>; reg = <0 0x13000000 0 0x1000>;
#clock-cells = <1>; #clock-cells = <1>;
power-domains = <&spm MT8183_POWER_DOMAIN_MFG_ASYNC>;
}; };
gpu: gpu@13040000 { gpu: gpu@13040000 {
......
arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi
View file @ 5eb4573e
...@@ -1296,7 +1296,7 @@ mt6366_vgpu_reg: vgpu { ...@@ -1296,7 +1296,7 @@ mt6366_vgpu_reg: vgpu {
* regulator coupling requirements. * regulator coupling requirements.
*/ */
regulator-name = "ppvar_dvdd_vgpu"; regulator-name = "ppvar_dvdd_vgpu";
regulator-min-microvolt = <600000>; regulator-min-microvolt = <500000>;
regulator-max-microvolt = <950000>; regulator-max-microvolt = <950000>;
regulator-ramp-delay = <6250>; regulator-ramp-delay = <6250>;
regulator-enable-ramp-delay = <200>; regulator-enable-ramp-delay = <200>;
......
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
View file @ 5eb4573e
...@@ -1421,7 +1421,7 @@ regulators { ...@@ -1421,7 +1421,7 @@ regulators {
mt6315_6_vbuck1: vbuck1 { mt6315_6_vbuck1: vbuck1 {
regulator-compatible = "vbuck1"; regulator-compatible = "vbuck1";
regulator-name = "Vbcpu"; regulator-name = "Vbcpu";
regulator-min-microvolt = <300000>; regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>; regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>; regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>; regulator-allowed-modes = <0 1 2>;
...@@ -1431,7 +1431,7 @@ mt6315_6_vbuck1: vbuck1 { ...@@ -1431,7 +1431,7 @@ mt6315_6_vbuck1: vbuck1 {
mt6315_6_vbuck3: vbuck3 { mt6315_6_vbuck3: vbuck3 {
regulator-compatible = "vbuck3"; regulator-compatible = "vbuck3";
regulator-name = "Vlcpu"; regulator-name = "Vlcpu";
regulator-min-microvolt = <300000>; regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>; regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>; regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>; regulator-allowed-modes = <0 1 2>;
...@@ -1448,7 +1448,7 @@ regulators { ...@@ -1448,7 +1448,7 @@ regulators {
mt6315_7_vbuck1: vbuck1 { mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1"; regulator-compatible = "vbuck1";
regulator-name = "Vgpu"; regulator-name = "Vgpu";
regulator-min-microvolt = <606250>; regulator-min-microvolt = <400000>;
regulator-max-microvolt = <800000>; regulator-max-microvolt = <800000>;
regulator-enable-ramp-delay = <256>; regulator-enable-ramp-delay = <256>;
regulator-allowed-modes = <0 1 2>; regulator-allowed-modes = <0 1 2>;
......
arch/arm64/boot/dts/mediatek/mt8192.dtsi
View file @ 5eb4573e
...@@ -1464,6 +1464,7 @@ mutex: mutex@14001000 { ...@@ -1464,6 +1464,7 @@ mutex: mutex@14001000 {
reg = <0 0x14001000 0 0x1000>; reg = <0 0x14001000 0 0x1000>;
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>; interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_DISP_MUTEX0>; clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
<CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>; <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
......
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
View file @ 5eb4573e
...@@ -264,6 +264,38 @@ &auxadc { ...@@ -264,6 +264,38 @@ &auxadc {
status = "okay"; status = "okay";
}; };
&cpu0 {
cpu-supply = <&mt6359_vcore_buck_reg>;
};
&cpu1 {
cpu-supply = <&mt6359_vcore_buck_reg>;
};
&cpu2 {
cpu-supply = <&mt6359_vcore_buck_reg>;
};
&cpu3 {
cpu-supply = <&mt6359_vcore_buck_reg>;
};
&cpu4 {
cpu-supply = <&mt6315_6_vbuck1>;
};
&cpu5 {
cpu-supply = <&mt6315_6_vbuck1>;
};
&cpu6 {
cpu-supply = <&mt6315_6_vbuck1>;
};
&cpu7 {
cpu-supply = <&mt6315_6_vbuck1>;
};
&dp_intf0 { &dp_intf0 {
status = "okay"; status = "okay";
...@@ -1214,7 +1246,7 @@ regulators { ...@@ -1214,7 +1246,7 @@ regulators {
mt6315_6_vbuck1: vbuck1 { mt6315_6_vbuck1: vbuck1 {
regulator-compatible = "vbuck1"; regulator-compatible = "vbuck1";
regulator-name = "Vbcpu"; regulator-name = "Vbcpu";
regulator-min-microvolt = <300000>; regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>; regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>; regulator-enable-ramp-delay = <256>;
regulator-ramp-delay = <6250>; regulator-ramp-delay = <6250>;
...@@ -1232,7 +1264,7 @@ regulators { ...@@ -1232,7 +1264,7 @@ regulators {
mt6315_7_vbuck1: vbuck1 { mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1"; regulator-compatible = "vbuck1";
regulator-name = "Vgpu"; regulator-name = "Vgpu";
regulator-min-microvolt = <625000>; regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>; regulator-max-microvolt = <1193750>;
regulator-enable-ramp-delay = <256>; regulator-enable-ramp-delay = <256>;
regulator-ramp-delay = <6250>; regulator-ramp-delay = <6250>;
......
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View file @ 5eb4573e
...@@ -2028,6 +2028,7 @@ vppsys0: syscon@14000000 { ...@@ -2028,6 +2028,7 @@ vppsys0: syscon@14000000 {
compatible = "mediatek,mt8195-vppsys0", "syscon"; compatible = "mediatek,mt8195-vppsys0", "syscon";
reg = <0 0x14000000 0 0x1000>; reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>; #clock-cells = <1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>;
}; };
dma-controller@14001000 { dma-controller@14001000 {
...@@ -2251,6 +2252,7 @@ vppsys1: syscon@14f00000 { ...@@ -2251,6 +2252,7 @@ vppsys1: syscon@14f00000 {
compatible = "mediatek,mt8195-vppsys1", "syscon"; compatible = "mediatek,mt8195-vppsys1", "syscon";
reg = <0 0x14f00000 0 0x1000>; reg = <0 0x14f00000 0 0x1000>;
#clock-cells = <1>; #clock-cells = <1>;
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>;
}; };
mutex@14f01000 { mutex@14f01000 {
...@@ -3080,6 +3082,7 @@ vdosys0: syscon@1c01a000 { ...@@ -3080,6 +3082,7 @@ vdosys0: syscon@1c01a000 {
reg = <0 0x1c01a000 0 0x1000>; reg = <0 0x1c01a000 0 0x1000>;
mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
#clock-cells = <1>; #clock-cells = <1>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
}; };
...@@ -3261,6 +3264,7 @@ mutex: mutex@1c016000 { ...@@ -3261,6 +3264,7 @@ mutex: mutex@1c016000 {
interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
}; };
...@@ -3331,6 +3335,7 @@ mutex1: mutex@1c101000 { ...@@ -3331,6 +3335,7 @@ mutex1: mutex@1c101000 {
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>;
clock-names = "vdo1_mutex"; clock-names = "vdo1_mutex";
mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>;
mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>; mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
}; };
......
arch/arm64/boot/dts/qcom/sc7280.dtsi
View file @ 5eb4573e
...@@ -3707,7 +3707,7 @@ remoteproc_adsp: remoteproc@3700000 { ...@@ -3707,7 +3707,7 @@ remoteproc_adsp: remoteproc@3700000 {
compatible = "qcom,sc7280-adsp-pas"; compatible = "qcom,sc7280-adsp-pas";
reg = <0 0x03700000 0 0x100>; reg = <0 0x03700000 0 0x100>;
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
...@@ -3944,7 +3944,7 @@ remoteproc_cdsp: remoteproc@a300000 { ...@@ -3944,7 +3944,7 @@ remoteproc_cdsp: remoteproc@a300000 {
compatible = "qcom,sc7280-cdsp-pas"; compatible = "qcom,sc7280-cdsp-pas";
reg = <0 0x0a300000 0 0x10000>; reg = <0 0x0a300000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
......
arch/arm64/boot/dts/qcom/sc8180x.dtsi
View file @ 5eb4573e
...@@ -2701,7 +2701,7 @@ usb_sec: usb@a8f8800 { ...@@ -2701,7 +2701,7 @@ usb_sec: usb@a8f8800 {
resets = <&gcc GCC_USB30_SEC_BCR>; resets = <&gcc GCC_USB30_SEC_BCR>;
power-domains = <&gcc USB30_SEC_GDSC>; power-domains = <&gcc USB30_SEC_GDSC>;
interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 7 IRQ_TYPE_LEVEL_HIGH>, <&pdc 40 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 10 IRQ_TYPE_EDGE_BOTH>, <&pdc 10 IRQ_TYPE_EDGE_BOTH>,
<&pdc 11 IRQ_TYPE_EDGE_BOTH>; <&pdc 11 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq", interrupt-names = "hs_phy_irq", "ss_phy_irq",
......
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View file @ 5eb4573e
...@@ -1774,6 +1774,7 @@ pcie4: pcie@1c00000 { ...@@ -1774,6 +1774,7 @@ pcie4: pcie@1c00000 {
reset-names = "pci"; reset-names = "pci";
power-domains = <&gcc PCIE_4_GDSC>; power-domains = <&gcc PCIE_4_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie4_phy>; phys = <&pcie4_phy>;
phy-names = "pciephy"; phy-names = "pciephy";
...@@ -1872,6 +1873,7 @@ pcie3b: pcie@1c08000 { ...@@ -1872,6 +1873,7 @@ pcie3b: pcie@1c08000 {
reset-names = "pci"; reset-names = "pci";
power-domains = <&gcc PCIE_3B_GDSC>; power-domains = <&gcc PCIE_3B_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie3b_phy>; phys = <&pcie3b_phy>;
phy-names = "pciephy"; phy-names = "pciephy";
...@@ -1970,6 +1972,7 @@ pcie3a: pcie@1c10000 { ...@@ -1970,6 +1972,7 @@ pcie3a: pcie@1c10000 {
reset-names = "pci"; reset-names = "pci";
power-domains = <&gcc PCIE_3A_GDSC>; power-domains = <&gcc PCIE_3A_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie3a_phy>; phys = <&pcie3a_phy>;
phy-names = "pciephy"; phy-names = "pciephy";
...@@ -2071,6 +2074,7 @@ pcie2b: pcie@1c18000 { ...@@ -2071,6 +2074,7 @@ pcie2b: pcie@1c18000 {
reset-names = "pci"; reset-names = "pci";
power-domains = <&gcc PCIE_2B_GDSC>; power-domains = <&gcc PCIE_2B_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie2b_phy>; phys = <&pcie2b_phy>;
phy-names = "pciephy"; phy-names = "pciephy";
...@@ -2169,6 +2173,7 @@ pcie2a: pcie@1c20000 { ...@@ -2169,6 +2173,7 @@ pcie2a: pcie@1c20000 {
reset-names = "pci"; reset-names = "pci";
power-domains = <&gcc PCIE_2A_GDSC>; power-domains = <&gcc PCIE_2A_GDSC>;
required-opps = <&rpmhpd_opp_nom>;
phys = <&pcie2a_phy>; phys = <&pcie2a_phy>;
phy-names = "pciephy"; phy-names = "pciephy";
...@@ -2641,7 +2646,7 @@ remoteproc_adsp: remoteproc@3000000 { ...@@ -2641,7 +2646,7 @@ remoteproc_adsp: remoteproc@3000000 {
compatible = "qcom,sc8280xp-adsp-pas"; compatible = "qcom,sc8280xp-adsp-pas";
reg = <0 0x03000000 0 0x100>; reg = <0 0x03000000 0 0x100>;
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
...@@ -4977,7 +4982,7 @@ remoteproc_nsp0: remoteproc@1b300000 { ...@@ -4977,7 +4982,7 @@ remoteproc_nsp0: remoteproc@1b300000 {
compatible = "qcom,sc8280xp-nsp0-pas"; compatible = "qcom,sc8280xp-nsp0-pas";
reg = <0 0x1b300000 0 0x100>; reg = <0 0x1b300000 0 0x100>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
...@@ -5108,7 +5113,7 @@ remoteproc_nsp1: remoteproc@21300000 { ...@@ -5108,7 +5113,7 @@ remoteproc_nsp1: remoteproc@21300000 {
compatible = "qcom,sc8280xp-nsp1-pas"; compatible = "qcom,sc8280xp-nsp1-pas";
reg = <0 0x21300000 0 0x100>; reg = <0 0x21300000 0 0x100>;
interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>,
<&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,
......
arch/arm64/boot/dts/qcom/sm6350.dtsi
View file @ 5eb4573e
...@@ -1252,7 +1252,7 @@ adsp: remoteproc@3000000 { ...@@ -1252,7 +1252,7 @@ adsp: remoteproc@3000000 {
compatible = "qcom,sm6350-adsp-pas"; compatible = "qcom,sm6350-adsp-pas";
reg = <0 0x03000000 0 0x100>; reg = <0 0x03000000 0 0x100>;
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
...@@ -1511,7 +1511,7 @@ cdsp: remoteproc@8300000 { ...@@ -1511,7 +1511,7 @@ cdsp: remoteproc@8300000 {
compatible = "qcom,sm6350-cdsp-pas"; compatible = "qcom,sm6350-cdsp-pas";
reg = <0 0x08300000 0 0x10000>; reg = <0 0x08300000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
......
arch/arm64/boot/dts/qcom/sm6375.dtsi
View file @ 5eb4573e
...@@ -1561,7 +1561,7 @@ remoteproc_adsp: remoteproc@a400000 { ...@@ -1561,7 +1561,7 @@ remoteproc_adsp: remoteproc@a400000 {
compatible = "qcom,sm6375-adsp-pas"; compatible = "qcom,sm6375-adsp-pas";
reg = <0 0x0a400000 0 0x100>; reg = <0 0x0a400000 0 0x100>;
interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
......
arch/arm64/boot/dts/qcom/sm8250.dtsi
View file @ 5eb4573e
...@@ -3062,7 +3062,7 @@ slpi: remoteproc@5c00000 { ...@@ -3062,7 +3062,7 @@ slpi: remoteproc@5c00000 {
compatible = "qcom,sm8250-slpi-pas"; compatible = "qcom,sm8250-slpi-pas";
reg = <0 0x05c00000 0 0x4000>; reg = <0 0x05c00000 0 0x4000>;
interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
...@@ -3766,7 +3766,7 @@ cdsp: remoteproc@8300000 { ...@@ -3766,7 +3766,7 @@ cdsp: remoteproc@8300000 {
compatible = "qcom,sm8250-cdsp-pas"; compatible = "qcom,sm8250-cdsp-pas";
reg = <0 0x08300000 0 0x10000>; reg = <0 0x08300000 0 0x10000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
...@@ -5928,7 +5928,7 @@ adsp: remoteproc@17300000 { ...@@ -5928,7 +5928,7 @@ adsp: remoteproc@17300000 {
compatible = "qcom,sm8250-adsp-pas"; compatible = "qcom,sm8250-adsp-pas";
reg = <0 0x17300000 0 0x100>; reg = <0 0x17300000 0 0x100>;
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
......
arch/arm64/boot/dts/qcom/sm8450.dtsi
View file @ 5eb4573e
...@@ -1777,12 +1777,8 @@ pcie0: pcie@1c00000 { ...@@ -1777,12 +1777,8 @@ pcie0: pcie@1c00000 {
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
/* msi-map = <0x0 &gic_its 0x5980 0x1>,
* MSIs for BDF (1:0.0) only works with Device ID 0x5980. <0x100 &gic_its 0x5981 0x1>;
* Hence, the IDs are swapped.
*/
msi-map = <0x0 &gic_its 0x5981 0x1>,
<0x100 &gic_its 0x5980 0x1>;
msi-map-mask = <0xff00>; msi-map-mask = <0xff00>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
...@@ -1900,12 +1896,8 @@ pcie1: pcie@1c08000 { ...@@ -1900,12 +1896,8 @@ pcie1: pcie@1c08000 {
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
/* msi-map = <0x0 &gic_its 0x5a00 0x1>,
* MSIs for BDF (1:0.0) only works with Device ID 0x5a00. <0x100 &gic_its 0x5a01 0x1>;
* Hence, the IDs are swapped.
*/
msi-map = <0x0 &gic_its 0x5a01 0x1>,
<0x100 &gic_its 0x5a00 0x1>;
msi-map-mask = <0xff00>; msi-map-mask = <0xff00>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
......
arch/arm64/boot/dts/qcom/sm8550.dtsi
View file @ 5eb4573e
...@@ -1755,9 +1755,8 @@ pcie0: pcie@1c00000 { ...@@ -1755,9 +1755,8 @@ pcie0: pcie@1c00000 {
<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>; <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_0 0>;
interconnect-names = "pcie-mem", "cpu-pcie"; interconnect-names = "pcie-mem", "cpu-pcie";
/* Entries are reversed due to the unusual ITS DeviceID encoding */ msi-map = <0x0 &gic_its 0x1400 0x1>,
msi-map = <0x0 &gic_its 0x1401 0x1>, <0x100 &gic_its 0x1401 0x1>;
<0x100 &gic_its 0x1400 0x1>;
iommu-map = <0x0 &apps_smmu 0x1400 0x1>, iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
<0x100 &apps_smmu 0x1401 0x1>; <0x100 &apps_smmu 0x1401 0x1>;
...@@ -1867,9 +1866,8 @@ pcie1: pcie@1c08000 { ...@@ -1867,9 +1866,8 @@ pcie1: pcie@1c08000 {
<&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>; <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_1 0>;
interconnect-names = "pcie-mem", "cpu-pcie"; interconnect-names = "pcie-mem", "cpu-pcie";
/* Entries are reversed due to the unusual ITS DeviceID encoding */ msi-map = <0x0 &gic_its 0x1480 0x1>,
msi-map = <0x0 &gic_its 0x1481 0x1>, <0x100 &gic_its 0x1481 0x1>;
<0x100 &gic_its 0x1480 0x1>;
iommu-map = <0x0 &apps_smmu 0x1480 0x1>, iommu-map = <0x0 &apps_smmu 0x1480 0x1>,
<0x100 &apps_smmu 0x1481 0x1>; <0x100 &apps_smmu 0x1481 0x1>;
......
arch/arm64/boot/dts/qcom/sm8650.dtsi
View file @ 5eb4573e
...@@ -2274,9 +2274,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, ...@@ -2274,9 +2274,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
interrupt-map-mask = <0 0 0 0x7>; interrupt-map-mask = <0 0 0 0x7>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
/* Entries are reversed due to the unusual ITS DeviceID encoding */ msi-map = <0x0 &gic_its 0x1400 0x1>,
msi-map = <0x0 &gic_its 0x1401 0x1>, <0x100 &gic_its 0x1401 0x1>;
<0x100 &gic_its 0x1400 0x1>;
msi-map-mask = <0xff00>; msi-map-mask = <0xff00>;
linux,pci-domain = <0>; linux,pci-domain = <0>;
...@@ -2402,9 +2401,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, ...@@ -2402,9 +2401,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
interrupt-map-mask = <0 0 0 0x7>; interrupt-map-mask = <0 0 0 0x7>;
#interrupt-cells = <1>; #interrupt-cells = <1>;
/* Entries are reversed due to the unusual ITS DeviceID encoding */ msi-map = <0x0 &gic_its 0x1480 0x1>,
msi-map = <0x0 &gic_its 0x1481 0x1>, <0x100 &gic_its 0x1481 0x1>;
<0x100 &gic_its 0x1480 0x1>;
msi-map-mask = <0xff00>; msi-map-mask = <0xff00>;
linux,pci-domain = <1>; linux,pci-domain = <1>;
......
arch/arm64/boot/dts/qcom/x1e80100.dtsi
View file @ 5eb4573e
...@@ -284,7 +284,7 @@ CLUSTER_C4: cpu-sleep-0 { ...@@ -284,7 +284,7 @@ CLUSTER_C4: cpu-sleep-0 {
domain-idle-states { domain-idle-states {
CLUSTER_CL4: cluster-sleep-0 { CLUSTER_CL4: cluster-sleep-0 {
compatible = "arm,idle-state"; compatible = "domain-idle-state";
idle-state-name = "l2-ret"; idle-state-name = "l2-ret";
arm,psci-suspend-param = <0x01000044>; arm,psci-suspend-param = <0x01000044>;
entry-latency-us = <350>; entry-latency-us = <350>;
...@@ -293,7 +293,7 @@ CLUSTER_CL4: cluster-sleep-0 { ...@@ -293,7 +293,7 @@ CLUSTER_CL4: cluster-sleep-0 {
}; };
CLUSTER_CL5: cluster-sleep-1 { CLUSTER_CL5: cluster-sleep-1 {
compatible = "arm,idle-state"; compatible = "domain-idle-state";
idle-state-name = "ret-pll-off"; idle-state-name = "ret-pll-off";
arm,psci-suspend-param = <0x01000054>; arm,psci-suspend-param = <0x01000054>;
entry-latency-us = <2200>; entry-latency-us = <2200>;
......
arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
View file @ 5eb4573e
...@@ -663,7 +663,7 @@ mipi_in_panel: endpoint { ...@@ -663,7 +663,7 @@ mipi_in_panel: endpoint {
port@1 { port@1 {
reg = <1>; reg = <1>;
mipi1_in_panel: endpoint@1 { mipi1_in_panel: endpoint {
remote-endpoint = <&mipi1_out_panel>; remote-endpoint = <&mipi1_out_panel>;
}; };
}; };
...@@ -689,7 +689,6 @@ &pcie0 { ...@@ -689,7 +689,6 @@ &pcie0 {
ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
/* PERST# asserted in S3 */ /* PERST# asserted in S3 */
pcie-reset-suspend = <1>;
vpcie3v3-supply = <&wlan_3v3>; vpcie3v3-supply = <&wlan_3v3>;
vpcie1v8-supply = <&pp1800_pcie>; vpcie1v8-supply = <&pp1800_pcie>;
......
arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dts
View file @ 5eb4573e
...@@ -611,7 +611,7 @@ device@4 { ...@@ -611,7 +611,7 @@ device@4 {
#size-cells = <0>; #size-cells = <0>;
interface@0 { /* interface 0 of configuration 1 */ interface@0 { /* interface 0 of configuration 1 */
compatible = "usbbda,8156.config1.0"; compatible = "usbifbda,8156.config1.0";
reg = <0 1>; reg = <0 1>;
}; };
}; };
......
arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
View file @ 5eb4573e
...@@ -779,7 +779,6 @@ &pcie_phy { ...@@ -779,7 +779,6 @@ &pcie_phy {
}; };
&pcie0 { &pcie0 {
bus-scan-delay-ms = <1000>;
ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
num-lanes = <4>; num-lanes = <4>;
pinctrl-names = "default"; pinctrl-names = "default";
......
arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts
View file @ 5eb4573e
...@@ -194,6 +194,8 @@ &pcie0 { ...@@ -194,6 +194,8 @@ &pcie0 {
num-lanes = <4>; num-lanes = <4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn_cpm>; pinctrl-0 = <&pcie_clkreqn_cpm>;
vpcie3v3-supply = <&vcc3v3_baseboard>;
vpcie12v-supply = <&dc_12v>;
status = "okay"; status = "okay";
}; };
......
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi
View file @ 5eb4573e
...@@ -79,6 +79,26 @@ vcc5v0_sys: vcc5v0-sys { ...@@ -79,6 +79,26 @@ vcc5v0_sys: vcc5v0-sys {
regulator-max-microvolt = <5000000>; regulator-max-microvolt = <5000000>;
}; };
vcca_0v9: vcca-0v9-regulator {
compatible = "regulator-fixed";
regulator-name = "vcca_0v9";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
vin-supply = <&vcc_1v8>;
};
vcca_1v8: vcca-1v8-regulator {
compatible = "regulator-fixed";
regulator-name = "vcca_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
vin-supply = <&vcc3v3_sys>;
};
vdd_log: vdd-log { vdd_log: vdd-log {
compatible = "pwm-regulator"; compatible = "pwm-regulator";
pwms = <&pwm2 0 25000 1>; pwms = <&pwm2 0 25000 1>;
...@@ -416,16 +436,28 @@ &io_domains { ...@@ -416,16 +436,28 @@ &io_domains {
gpio1830-supply = <&vcc_1v8>; gpio1830-supply = <&vcc_1v8>;
}; };
&pmu_io_domains { &pcie0 {
status = "okay"; /* PCIe PHY supplies */
pmu1830-supply = <&vcc_1v8>; vpcie0v9-supply = <&vcca_0v9>;
vpcie1v8-supply = <&vcca_1v8>;
}; };
&pwm2 { &pcie_clkreqn_cpm {
status = "okay"; rockchip,pins =
<2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
}; };
&pinctrl { &pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&q7_thermal_pin>;
gpios {
q7_thermal_pin: q7-thermal-pin {
rockchip,pins =
<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
i2c8 { i2c8 {
i2c8_xfer_a: i2c8-xfer { i2c8_xfer_a: i2c8-xfer {
rockchip,pins = rockchip,pins =
...@@ -458,11 +490,20 @@ vcc5v0_host_en: vcc5v0-host-en { ...@@ -458,11 +490,20 @@ vcc5v0_host_en: vcc5v0-host-en {
usb3 { usb3 {
usb3_id: usb3-id { usb3_id: usb3-id {
rockchip,pins = rockchip,pins =
<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
}; };
}; };
}; };
&pmu_io_domains {
status = "okay";
pmu1830-supply = <&vcc_1v8>;
};
&pwm2 {
status = "okay";
};
&sdhci { &sdhci {
/* /*
* Signal integrity isn't great at 200MHz but 100MHz has proven stable * Signal integrity isn't great at 200MHz but 100MHz has proven stable
......
arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts
View file @ 5eb4573e
...@@ -447,7 +447,6 @@ rgmii_phy1: phy@0 { ...@@ -447,7 +447,6 @@ rgmii_phy1: phy@0 {
&pcie2x1 { &pcie2x1 {
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
disable-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>; vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay"; status = "okay";
}; };
......
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
View file @ 5eb4573e
...@@ -416,6 +416,8 @@ regulator-state-mem { ...@@ -416,6 +416,8 @@ regulator-state-mem {
vccio_sd: LDO_REG5 { vccio_sd: LDO_REG5 {
regulator-name = "vccio_sd"; regulator-name = "vccio_sd";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
...@@ -525,9 +527,9 @@ &mdio0 { ...@@ -525,9 +527,9 @@ &mdio0 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
switch@0 { switch@1f {
compatible = "mediatek,mt7531"; compatible = "mediatek,mt7531";
reg = <0>; reg = <0x1f>;
ports { ports {
#address-cells = <1>; #address-cells = <1>;
......
arch/arm64/boot/dts/rockchip/rk3568-lubancat-2.dts
View file @ 5eb4573e
...@@ -523,7 +523,6 @@ &pcie3x2 { ...@@ -523,7 +523,6 @@ &pcie3x2 {
&pcie2x1 { &pcie2x1 {
reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
disable-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_mini_pcie>; vpcie3v3-supply = <&vcc3v3_mini_pcie>;
status = "okay"; status = "okay";
}; };
......
arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5.dtsi
View file @ 5eb4573e
...@@ -216,9 +216,9 @@ &i2c7 { ...@@ -216,9 +216,9 @@ &i2c7 {
pinctrl-0 = <&i2c7m0_xfer>; pinctrl-0 = <&i2c7m0_xfer>;
status = "okay"; status = "okay";
es8316: audio-codec@11 { es8316: audio-codec@10 {
compatible = "everest,es8316"; compatible = "everest,es8316";
reg = <0x11>; reg = <0x10>;
assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
assigned-clock-rates = <12288000>; assigned-clock-rates = <12288000>;
clocks = <&cru I2S0_8CH_MCLKOUT>; clocks = <&cru I2S0_8CH_MCLKOUT>;
......
arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-plus.dts
View file @ 5eb4573e
...@@ -485,6 +485,7 @@ pmic@0 { ...@@ -485,6 +485,7 @@ pmic@0 {
pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
<&rk806_dvs2_null>, <&rk806_dvs3_null>; <&rk806_dvs2_null>, <&rk806_dvs3_null>;
spi-max-frequency = <1000000>; spi-max-frequency = <1000000>;
system-power-controller;
vcc1-supply = <&vcc5v0_sys>; vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>; vcc2-supply = <&vcc5v0_sys>;
...@@ -506,7 +507,7 @@ pmic@0 { ...@@ -506,7 +507,7 @@ pmic@0 {
#gpio-cells = <2>; #gpio-cells = <2>;
rk806_dvs1_null: dvs1-null-pins { rk806_dvs1_null: dvs1-null-pins {
pins = "gpio_pwrctrl2"; pins = "gpio_pwrctrl1";
function = "pin_fun0"; function = "pin_fun0";
}; };
......
arch/arm64/boot/dts/rockchip/rk3588-quartzpro64.dts
View file @ 5eb4573e
...@@ -456,6 +456,7 @@ pmic@0 { ...@@ -456,6 +456,7 @@ pmic@0 {
<&rk806_dvs2_null>, <&rk806_dvs3_null>; <&rk806_dvs2_null>, <&rk806_dvs3_null>;
pinctrl-names = "default"; pinctrl-names = "default";
spi-max-frequency = <1000000>; spi-max-frequency = <1000000>;
system-power-controller;
vcc1-supply = <&vcc4v0_sys>; vcc1-supply = <&vcc4v0_sys>;
vcc2-supply = <&vcc4v0_sys>; vcc2-supply = <&vcc4v0_sys>;
......
drivers/firmware/qcom/qcom_qseecom_uefisecapp.c
View file @ 5eb4573e
...@@ -221,6 +221,19 @@ struct qsee_rsp_uefi_query_variable_info { ...@@ -221,6 +221,19 @@ struct qsee_rsp_uefi_query_variable_info {
* alignment of 8 bytes (64 bits) for GUIDs. Our definition of efi_guid_t, * alignment of 8 bytes (64 bits) for GUIDs. Our definition of efi_guid_t,
* however, has an alignment of 4 byte (32 bits). So far, this seems to work * however, has an alignment of 4 byte (32 bits). So far, this seems to work
* fine here. See also the comment on the typedef of efi_guid_t. * fine here. See also the comment on the typedef of efi_guid_t.
*
* Note: It looks like uefisecapp is quite picky about how the memory passed to
* it is structured and aligned. In particular the request/response setup used
* for QSEE_CMD_UEFI_GET_VARIABLE. While qcom_qseecom_app_send(), in theory,
* accepts separate buffers/addresses for the request and response parts, in
* practice, however, it seems to expect them to be both part of a larger
* contiguous block. We initially allocated separate buffers for the request
* and response but this caused the QSEE_CMD_UEFI_GET_VARIABLE command to
* either not write any response to the response buffer or outright crash the
* device. Therefore, we now allocate a single contiguous block of DMA memory
* for both and properly align the data using the macros below. In particular,
* request and response structs are aligned at 8 byte (via __reqdata_offs()),
* following the driver that this has been reverse-engineered from.
*/ */
#define qcuefi_buf_align_fields(fields...) \ #define qcuefi_buf_align_fields(fields...) \
({ \ ({ \
...@@ -244,6 +257,12 @@ struct qsee_rsp_uefi_query_variable_info { ...@@ -244,6 +257,12 @@ struct qsee_rsp_uefi_query_variable_info {
#define __array_offs(type, count, offset) \ #define __array_offs(type, count, offset) \
__field_impl(sizeof(type) * (count), __alignof__(type), offset) __field_impl(sizeof(type) * (count), __alignof__(type), offset)
#define __array_offs_aligned(type, count, align, offset) \
__field_impl(sizeof(type) * (count), align, offset)
#define __reqdata_offs(size, offset) \
__array_offs_aligned(u8, size, 8, offset)
#define __array(type, count) __array_offs(type, count, NULL) #define __array(type, count) __array_offs(type, count, NULL)
#define __field_offs(type, offset) __array_offs(type, 1, offset) #define __field_offs(type, offset) __array_offs(type, 1, offset)
#define __field(type) __array_offs(type, 1, NULL) #define __field(type) __array_offs(type, 1, NULL)
...@@ -277,10 +296,15 @@ static efi_status_t qsee_uefi_get_variable(struct qcuefi_client *qcuefi, const e ...@@ -277,10 +296,15 @@ static efi_status_t qsee_uefi_get_variable(struct qcuefi_client *qcuefi, const e
unsigned long buffer_size = *data_size; unsigned long buffer_size = *data_size;
efi_status_t efi_status = EFI_SUCCESS; efi_status_t efi_status = EFI_SUCCESS;
unsigned long name_length; unsigned long name_length;
dma_addr_t cmd_buf_dma;
size_t cmd_buf_size;
void *cmd_buf;
size_t guid_offs; size_t guid_offs;
size_t name_offs; size_t name_offs;
size_t req_size; size_t req_size;
size_t rsp_size; size_t rsp_size;
size_t req_offs;
size_t rsp_offs;
ssize_t status; ssize_t status;
if (!name || !guid) if (!name || !guid)
...@@ -304,17 +328,19 @@ static efi_status_t qsee_uefi_get_variable(struct qcuefi_client *qcuefi, const e ...@@ -304,17 +328,19 @@ static efi_status_t qsee_uefi_get_variable(struct qcuefi_client *qcuefi, const e
__array(u8, buffer_size) __array(u8, buffer_size)
); );
req_data = kzalloc(req_size, GFP_KERNEL); cmd_buf_size = qcuefi_buf_align_fields(
if (!req_data) { __reqdata_offs(req_size, &req_offs)
__reqdata_offs(rsp_size, &rsp_offs)
);
cmd_buf = qseecom_dma_alloc(qcuefi->client, cmd_buf_size, &cmd_buf_dma, GFP_KERNEL);
if (!cmd_buf) {
efi_status = EFI_OUT_OF_RESOURCES; efi_status = EFI_OUT_OF_RESOURCES;
goto out; goto out;
} }
rsp_data = kzalloc(rsp_size, GFP_KERNEL); req_data = cmd_buf + req_offs;
if (!rsp_data) { rsp_data = cmd_buf + rsp_offs;
efi_status = EFI_OUT_OF_RESOURCES;
goto out_free_req;
}
req_data->command_id = QSEE_CMD_UEFI_GET_VARIABLE; req_data->command_id = QSEE_CMD_UEFI_GET_VARIABLE;
req_data->data_size = buffer_size; req_data->data_size = buffer_size;
...@@ -332,7 +358,9 @@ static efi_status_t qsee_uefi_get_variable(struct qcuefi_client *qcuefi, const e ...@@ -332,7 +358,9 @@ static efi_status_t qsee_uefi_get_variable(struct qcuefi_client *qcuefi, const e
memcpy(((void *)req_data) + req_data->guid_offset, guid, req_data->guid_size); memcpy(((void *)req_data) + req_data->guid_offset, guid, req_data->guid_size);
status = qcom_qseecom_app_send(qcuefi->client, req_data, req_size, rsp_data, rsp_size); status = qcom_qseecom_app_send(qcuefi->client,
cmd_buf_dma + req_offs, req_size,
cmd_buf_dma + rsp_offs, rsp_size);
if (status) { if (status) {
efi_status = EFI_DEVICE_ERROR; efi_status = EFI_DEVICE_ERROR;
goto out_free; goto out_free;
...@@ -407,9 +435,7 @@ static efi_status_t qsee_uefi_get_variable(struct qcuefi_client *qcuefi, const e ...@@ -407,9 +435,7 @@ static efi_status_t qsee_uefi_get_variable(struct qcuefi_client *qcuefi, const e
memcpy(data, ((void *)rsp_data) + rsp_data->data_offset, rsp_data->data_size); memcpy(data, ((void *)rsp_data) + rsp_data->data_offset, rsp_data->data_size);
out_free: out_free:
kfree(rsp_data); qseecom_dma_free(qcuefi->client, cmd_buf_size, cmd_buf, cmd_buf_dma);
out_free_req:
kfree(req_data);
out: out:
return efi_status; return efi_status;
} }
...@@ -422,10 +448,15 @@ static efi_status_t qsee_uefi_set_variable(struct qcuefi_client *qcuefi, const e ...@@ -422,10 +448,15 @@ static efi_status_t qsee_uefi_set_variable(struct qcuefi_client *qcuefi, const e
struct qsee_rsp_uefi_set_variable *rsp_data; struct qsee_rsp_uefi_set_variable *rsp_data;
efi_status_t efi_status = EFI_SUCCESS; efi_status_t efi_status = EFI_SUCCESS;
unsigned long name_length; unsigned long name_length;
dma_addr_t cmd_buf_dma;
size_t cmd_buf_size;
void *cmd_buf;
size_t name_offs; size_t name_offs;
size_t guid_offs; size_t guid_offs;
size_t data_offs; size_t data_offs;
size_t req_size; size_t req_size;
size_t req_offs;
size_t rsp_offs;
ssize_t status; ssize_t status;
if (!name || !guid) if (!name || !guid)
...@@ -450,17 +481,19 @@ static efi_status_t qsee_uefi_set_variable(struct qcuefi_client *qcuefi, const e ...@@ -450,17 +481,19 @@ static efi_status_t qsee_uefi_set_variable(struct qcuefi_client *qcuefi, const e
__array_offs(u8, data_size, &data_offs) __array_offs(u8, data_size, &data_offs)
); );
req_data = kzalloc(req_size, GFP_KERNEL); cmd_buf_size = qcuefi_buf_align_fields(
if (!req_data) { __reqdata_offs(req_size, &req_offs)
__reqdata_offs(sizeof(*rsp_data), &rsp_offs)
);
cmd_buf = qseecom_dma_alloc(qcuefi->client, cmd_buf_size, &cmd_buf_dma, GFP_KERNEL);
if (!cmd_buf) {
efi_status = EFI_OUT_OF_RESOURCES; efi_status = EFI_OUT_OF_RESOURCES;
goto out; goto out;
} }
rsp_data = kzalloc(sizeof(*rsp_data), GFP_KERNEL); req_data = cmd_buf + req_offs;
if (!rsp_data) { rsp_data = cmd_buf + rsp_offs;
efi_status = EFI_OUT_OF_RESOURCES;
goto out_free_req;
}
req_data->command_id = QSEE_CMD_UEFI_SET_VARIABLE; req_data->command_id = QSEE_CMD_UEFI_SET_VARIABLE;
req_data->attributes = attributes; req_data->attributes = attributes;
...@@ -483,8 +516,9 @@ static efi_status_t qsee_uefi_set_variable(struct qcuefi_client *qcuefi, const e ...@@ -483,8 +516,9 @@ static efi_status_t qsee_uefi_set_variable(struct qcuefi_client *qcuefi, const e
if (data_size) if (data_size)
memcpy(((void *)req_data) + req_data->data_offset, data, req_data->data_size); memcpy(((void *)req_data) + req_data->data_offset, data, req_data->data_size);
status = qcom_qseecom_app_send(qcuefi->client, req_data, req_size, rsp_data, status = qcom_qseecom_app_send(qcuefi->client,
sizeof(*rsp_data)); cmd_buf_dma + req_offs, req_size,
cmd_buf_dma + rsp_offs, sizeof(*rsp_data));
if (status) { if (status) {
efi_status = EFI_DEVICE_ERROR; efi_status = EFI_DEVICE_ERROR;
goto out_free; goto out_free;
...@@ -507,9 +541,7 @@ static efi_status_t qsee_uefi_set_variable(struct qcuefi_client *qcuefi, const e ...@@ -507,9 +541,7 @@ static efi_status_t qsee_uefi_set_variable(struct qcuefi_client *qcuefi, const e
} }
out_free: out_free:
kfree(rsp_data); qseecom_dma_free(qcuefi->client, cmd_buf_size, cmd_buf, cmd_buf_dma);
out_free_req:
kfree(req_data);
out: out:
return efi_status; return efi_status;
} }
...@@ -521,10 +553,15 @@ static efi_status_t qsee_uefi_get_next_variable(struct qcuefi_client *qcuefi, ...@@ -521,10 +553,15 @@ static efi_status_t qsee_uefi_get_next_variable(struct qcuefi_client *qcuefi,
struct qsee_req_uefi_get_next_variable *req_data; struct qsee_req_uefi_get_next_variable *req_data;
struct qsee_rsp_uefi_get_next_variable *rsp_data; struct qsee_rsp_uefi_get_next_variable *rsp_data;
efi_status_t efi_status = EFI_SUCCESS; efi_status_t efi_status = EFI_SUCCESS;
dma_addr_t cmd_buf_dma;
size_t cmd_buf_size;
void *cmd_buf;
size_t guid_offs; size_t guid_offs;
size_t name_offs; size_t name_offs;
size_t req_size; size_t req_size;
size_t rsp_size; size_t rsp_size;
size_t req_offs;
size_t rsp_offs;
ssize_t status; ssize_t status;
if (!name_size || !name || !guid) if (!name_size || !name || !guid)
...@@ -545,17 +582,19 @@ static efi_status_t qsee_uefi_get_next_variable(struct qcuefi_client *qcuefi, ...@@ -545,17 +582,19 @@ static efi_status_t qsee_uefi_get_next_variable(struct qcuefi_client *qcuefi,
__array(*name, *name_size / sizeof(*name)) __array(*name, *name_size / sizeof(*name))
); );
req_data = kzalloc(req_size, GFP_KERNEL); cmd_buf_size = qcuefi_buf_align_fields(
if (!req_data) { __reqdata_offs(req_size, &req_offs)
__reqdata_offs(rsp_size, &rsp_offs)
);
cmd_buf = qseecom_dma_alloc(qcuefi->client, cmd_buf_size, &cmd_buf_dma, GFP_KERNEL);
if (!cmd_buf) {
efi_status = EFI_OUT_OF_RESOURCES; efi_status = EFI_OUT_OF_RESOURCES;
goto out; goto out;
} }
rsp_data = kzalloc(rsp_size, GFP_KERNEL); req_data = cmd_buf + req_offs;
if (!rsp_data) { rsp_data = cmd_buf + rsp_offs;
efi_status = EFI_OUT_OF_RESOURCES;
goto out_free_req;
}
req_data->command_id = QSEE_CMD_UEFI_GET_NEXT_VARIABLE; req_data->command_id = QSEE_CMD_UEFI_GET_NEXT_VARIABLE;
req_data->guid_offset = guid_offs; req_data->guid_offset = guid_offs;
...@@ -572,7 +611,9 @@ static efi_status_t qsee_uefi_get_next_variable(struct qcuefi_client *qcuefi, ...@@ -572,7 +611,9 @@ static efi_status_t qsee_uefi_get_next_variable(struct qcuefi_client *qcuefi,
goto out_free; goto out_free;
} }
status = qcom_qseecom_app_send(qcuefi->client, req_data, req_size, rsp_data, rsp_size); status = qcom_qseecom_app_send(qcuefi->client,
cmd_buf_dma + req_offs, req_size,
cmd_buf_dma + rsp_offs, rsp_size);
if (status) { if (status) {
efi_status = EFI_DEVICE_ERROR; efi_status = EFI_DEVICE_ERROR;
goto out_free; goto out_free;
...@@ -645,9 +686,7 @@ static efi_status_t qsee_uefi_get_next_variable(struct qcuefi_client *qcuefi, ...@@ -645,9 +686,7 @@ static efi_status_t qsee_uefi_get_next_variable(struct qcuefi_client *qcuefi,
} }
out_free: out_free:
kfree(rsp_data); qseecom_dma_free(qcuefi->client, cmd_buf_size, cmd_buf, cmd_buf_dma);
out_free_req:
kfree(req_data);
out: out:
return efi_status; return efi_status;
} }
...@@ -659,26 +698,34 @@ static efi_status_t qsee_uefi_query_variable_info(struct qcuefi_client *qcuefi, ...@@ -659,26 +698,34 @@ static efi_status_t qsee_uefi_query_variable_info(struct qcuefi_client *qcuefi,
struct qsee_req_uefi_query_variable_info *req_data; struct qsee_req_uefi_query_variable_info *req_data;
struct qsee_rsp_uefi_query_variable_info *rsp_data; struct qsee_rsp_uefi_query_variable_info *rsp_data;
efi_status_t efi_status = EFI_SUCCESS; efi_status_t efi_status = EFI_SUCCESS;
dma_addr_t cmd_buf_dma;
size_t cmd_buf_size;
void *cmd_buf;
size_t req_offs;
size_t rsp_offs;
int status; int status;
req_data = kzalloc(sizeof(*req_data), GFP_KERNEL); cmd_buf_size = qcuefi_buf_align_fields(
if (!req_data) { __reqdata_offs(sizeof(*req_data), &req_offs)
__reqdata_offs(sizeof(*rsp_data), &rsp_offs)
);
cmd_buf = qseecom_dma_alloc(qcuefi->client, cmd_buf_size, &cmd_buf_dma, GFP_KERNEL);
if (!cmd_buf) {
efi_status = EFI_OUT_OF_RESOURCES; efi_status = EFI_OUT_OF_RESOURCES;
goto out; goto out;
} }
rsp_data = kzalloc(sizeof(*rsp_data), GFP_KERNEL); req_data = cmd_buf + req_offs;
if (!rsp_data) { rsp_data = cmd_buf + rsp_offs;
efi_status = EFI_OUT_OF_RESOURCES;
goto out_free_req;
}
req_data->command_id = QSEE_CMD_UEFI_QUERY_VARIABLE_INFO; req_data->command_id = QSEE_CMD_UEFI_QUERY_VARIABLE_INFO;
req_data->attributes = attr; req_data->attributes = attr;
req_data->length = sizeof(*req_data); req_data->length = sizeof(*req_data);
status = qcom_qseecom_app_send(qcuefi->client, req_data, sizeof(*req_data), rsp_data, status = qcom_qseecom_app_send(qcuefi->client,
sizeof(*rsp_data)); cmd_buf_dma + req_offs, sizeof(*req_data),
cmd_buf_dma + rsp_offs, sizeof(*rsp_data));
if (status) { if (status) {
efi_status = EFI_DEVICE_ERROR; efi_status = EFI_DEVICE_ERROR;
goto out_free; goto out_free;
...@@ -711,9 +758,7 @@ static efi_status_t qsee_uefi_query_variable_info(struct qcuefi_client *qcuefi, ...@@ -711,9 +758,7 @@ static efi_status_t qsee_uefi_query_variable_info(struct qcuefi_client *qcuefi,
*max_variable_size = rsp_data->max_variable_size; *max_variable_size = rsp_data->max_variable_size;
out_free: out_free:
kfree(rsp_data); qseecom_dma_free(qcuefi->client, cmd_buf_size, cmd_buf, cmd_buf_dma);
out_free_req:
kfree(req_data);
out: out:
return efi_status; return efi_status;
} }
......
drivers/firmware/qcom/qcom_scm.c
View file @ 5eb4573e
...@@ -1576,9 +1576,9 @@ EXPORT_SYMBOL_GPL(qcom_scm_qseecom_app_get_id); ...@@ -1576,9 +1576,9 @@ EXPORT_SYMBOL_GPL(qcom_scm_qseecom_app_get_id);
/** /**
* qcom_scm_qseecom_app_send() - Send to and receive data from a given QSEE app. * qcom_scm_qseecom_app_send() - Send to and receive data from a given QSEE app.
* @app_id: The ID of the target app. * @app_id: The ID of the target app.
* @req: Request buffer sent to the app (must be DMA-mappable). * @req: DMA address of the request buffer sent to the app.
* @req_size: Size of the request buffer. * @req_size: Size of the request buffer.
* @rsp: Response buffer, written to by the app (must be DMA-mappable). * @rsp: DMA address of the response buffer, written to by the app.
* @rsp_size: Size of the response buffer. * @rsp_size: Size of the response buffer.
* *
* Sends a request to the QSEE app associated with the given ID and read back * Sends a request to the QSEE app associated with the given ID and read back
...@@ -1589,33 +1589,13 @@ EXPORT_SYMBOL_GPL(qcom_scm_qseecom_app_get_id); ...@@ -1589,33 +1589,13 @@ EXPORT_SYMBOL_GPL(qcom_scm_qseecom_app_get_id);
* *
* Return: Zero on success, nonzero on failure. * Return: Zero on success, nonzero on failure.
*/ */
int qcom_scm_qseecom_app_send(u32 app_id, void *req, size_t req_size, void *rsp, int qcom_scm_qseecom_app_send(u32 app_id, dma_addr_t req, size_t req_size,
size_t rsp_size) dma_addr_t rsp, size_t rsp_size)
{ {
struct qcom_scm_qseecom_resp res = {}; struct qcom_scm_qseecom_resp res = {};
struct qcom_scm_desc desc = {}; struct qcom_scm_desc desc = {};
dma_addr_t req_phys;
dma_addr_t rsp_phys;
int status; int status;
/* Map request buffer */
req_phys = dma_map_single(__scm->dev, req, req_size, DMA_TO_DEVICE);
status = dma_mapping_error(__scm->dev, req_phys);
if (status) {
dev_err(__scm->dev, "qseecom: failed to map request buffer\n");
return status;
}
/* Map response buffer */
rsp_phys = dma_map_single(__scm->dev, rsp, rsp_size, DMA_FROM_DEVICE);
status = dma_mapping_error(__scm->dev, rsp_phys);
if (status) {
dma_unmap_single(__scm->dev, req_phys, req_size, DMA_TO_DEVICE);
dev_err(__scm->dev, "qseecom: failed to map response buffer\n");
return status;
}
/* Set up SCM call data */
desc.owner = QSEECOM_TZ_OWNER_TZ_APPS; desc.owner = QSEECOM_TZ_OWNER_TZ_APPS;
desc.svc = QSEECOM_TZ_SVC_APP_ID_PLACEHOLDER; desc.svc = QSEECOM_TZ_SVC_APP_ID_PLACEHOLDER;
desc.cmd = QSEECOM_TZ_CMD_APP_SEND; desc.cmd = QSEECOM_TZ_CMD_APP_SEND;
...@@ -1623,18 +1603,13 @@ int qcom_scm_qseecom_app_send(u32 app_id, void *req, size_t req_size, void *rsp, ...@@ -1623,18 +1603,13 @@ int qcom_scm_qseecom_app_send(u32 app_id, void *req, size_t req_size, void *rsp,
QCOM_SCM_RW, QCOM_SCM_VAL, QCOM_SCM_RW, QCOM_SCM_VAL,
QCOM_SCM_RW, QCOM_SCM_VAL); QCOM_SCM_RW, QCOM_SCM_VAL);
desc.args[0] = app_id; desc.args[0] = app_id;
desc.args[1] = req_phys; desc.args[1] = req;
desc.args[2] = req_size; desc.args[2] = req_size;
desc.args[3] = rsp_phys; desc.args[3] = rsp;
desc.args[4] = rsp_size; desc.args[4] = rsp_size;
/* Perform call */
status = qcom_scm_qseecom_call(&desc, &res); status = qcom_scm_qseecom_call(&desc, &res);
/* Unmap buffers */
dma_unmap_single(__scm->dev, rsp_phys, rsp_size, DMA_FROM_DEVICE);
dma_unmap_single(__scm->dev, req_phys, req_size, DMA_TO_DEVICE);
if (status) if (status)
return status; return status;
......
drivers/soc/mediatek/Kconfig
View file @ 5eb4573e
...@@ -72,6 +72,7 @@ config MTK_SOCINFO ...@@ -72,6 +72,7 @@ config MTK_SOCINFO
tristate "MediaTek SoC Information" tristate "MediaTek SoC Information"
default y default y
depends on NVMEM_MTK_EFUSE depends on NVMEM_MTK_EFUSE
select SOC_BUS
help help
The MediaTek SoC Information (mtk-socinfo) driver provides The MediaTek SoC Information (mtk-socinfo) driver provides
information about the SoC to the userspace including the information about the SoC to the userspace including the
......
drivers/soc/mediatek/mtk-svs.c
View file @ 5eb4573e
...@@ -1768,6 +1768,7 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) ...@@ -1768,6 +1768,7 @@ static int svs_bank_resource_setup(struct svs_platform *svsp)
const struct svs_bank_pdata *bdata; const struct svs_bank_pdata *bdata;
struct svs_bank *svsb; struct svs_bank *svsb;
struct dev_pm_opp *opp; struct dev_pm_opp *opp;
char tz_name_buf[20];
unsigned long freq; unsigned long freq;
int count, ret; int count, ret;
u32 idx, i; u32 idx, i;
...@@ -1819,10 +1820,12 @@ static int svs_bank_resource_setup(struct svs_platform *svsp) ...@@ -1819,10 +1820,12 @@ static int svs_bank_resource_setup(struct svs_platform *svsp)
} }
if (!IS_ERR_OR_NULL(bdata->tzone_name)) { if (!IS_ERR_OR_NULL(bdata->tzone_name)) {
svsb->tzd = thermal_zone_get_zone_by_name(bdata->tzone_name); snprintf(tz_name_buf, ARRAY_SIZE(tz_name_buf),
"%s-thermal", bdata->tzone_name);
svsb->tzd = thermal_zone_get_zone_by_name(tz_name_buf);
if (IS_ERR(svsb->tzd)) { if (IS_ERR(svsb->tzd)) {
dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n", dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n",
bdata->tzone_name); tz_name_buf);
return PTR_ERR(svsb->tzd); return PTR_ERR(svsb->tzd);
} }
} }
......
include/linux/firmware/qcom/qcom_qseecom.h
View file @ 5eb4573e
...@@ -10,6 +10,7 @@ ...@@ -10,6 +10,7 @@
#define __QCOM_QSEECOM_H #define __QCOM_QSEECOM_H
#include <linux/auxiliary_bus.h> #include <linux/auxiliary_bus.h>
#include <linux/dma-mapping.h>
#include <linux/types.h> #include <linux/types.h>
#include <linux/firmware/qcom/qcom_scm.h> #include <linux/firmware/qcom/qcom_scm.h>
...@@ -24,12 +25,57 @@ struct qseecom_client { ...@@ -24,12 +25,57 @@ struct qseecom_client {
u32 app_id; u32 app_id;
}; };
/**
* qseecom_scm_dev() - Get the SCM device associated with the QSEECOM client.
* @client: The QSEECOM client device.
*
* Returns the SCM device under which the provided QSEECOM client device
* operates. This function is intended to be used for DMA allocations.
*/
static inline struct device *qseecom_scm_dev(struct qseecom_client *client)
{
return client->aux_dev.dev.parent->parent;
}
/**
* qseecom_dma_alloc() - Allocate DMA memory for a QSEECOM client.
* @client: The QSEECOM client to allocate the memory for.
* @size: The number of bytes to allocate.
* @dma_handle: Pointer to where the DMA address should be stored.
* @gfp: Allocation flags.
*
* Wrapper function for dma_alloc_coherent(), allocating DMA memory usable for
* TZ/QSEECOM communication. Refer to dma_alloc_coherent() for details.
*/
static inline void *qseecom_dma_alloc(struct qseecom_client *client, size_t size,
dma_addr_t *dma_handle, gfp_t gfp)
{
return dma_alloc_coherent(qseecom_scm_dev(client), size, dma_handle, gfp);
}
/**
* dma_free_coherent() - Free QSEECOM DMA memory.
* @client: The QSEECOM client for which the memory has been allocated.
* @size: The number of bytes allocated.
* @cpu_addr: Virtual memory address to free.
* @dma_handle: DMA memory address to free.
*
* Wrapper function for dma_free_coherent(), freeing memory previously
* allocated with qseecom_dma_alloc(). Refer to dma_free_coherent() for
* details.
*/
static inline void qseecom_dma_free(struct qseecom_client *client, size_t size,
void *cpu_addr, dma_addr_t dma_handle)
{
return dma_free_coherent(qseecom_scm_dev(client), size, cpu_addr, dma_handle);
}
/** /**
* qcom_qseecom_app_send() - Send to and receive data from a given QSEE app. * qcom_qseecom_app_send() - Send to and receive data from a given QSEE app.
* @client: The QSEECOM client associated with the target app. * @client: The QSEECOM client associated with the target app.
* @req: Request buffer sent to the app (must be DMA-mappable). * @req: DMA address of the request buffer sent to the app.
* @req_size: Size of the request buffer. * @req_size: Size of the request buffer.
* @rsp: Response buffer, written to by the app (must be DMA-mappable). * @rsp: DMA address of the response buffer, written to by the app.
* @rsp_size: Size of the response buffer. * @rsp_size: Size of the response buffer.
* *
* Sends a request to the QSEE app associated with the given client and read * Sends a request to the QSEE app associated with the given client and read
...@@ -43,8 +89,9 @@ struct qseecom_client { ...@@ -43,8 +89,9 @@ struct qseecom_client {
* *
* Return: Zero on success, nonzero on failure. * Return: Zero on success, nonzero on failure.
*/ */
static inline int qcom_qseecom_app_send(struct qseecom_client *client, void *req, size_t req_size, static inline int qcom_qseecom_app_send(struct qseecom_client *client,
void *rsp, size_t rsp_size) dma_addr_t req, size_t req_size,
dma_addr_t rsp, size_t rsp_size)
{ {
return qcom_scm_qseecom_app_send(client->app_id, req, req_size, rsp, rsp_size); return qcom_scm_qseecom_app_send(client->app_id, req, req_size, rsp, rsp_size);
} }
......
include/linux/firmware/qcom/qcom_scm.h
View file @ 5eb4573e
...@@ -118,8 +118,8 @@ bool qcom_scm_lmh_dcvsh_available(void); ...@@ -118,8 +118,8 @@ bool qcom_scm_lmh_dcvsh_available(void);
#ifdef CONFIG_QCOM_QSEECOM #ifdef CONFIG_QCOM_QSEECOM
int qcom_scm_qseecom_app_get_id(const char *app_name, u32 *app_id); int qcom_scm_qseecom_app_get_id(const char *app_name, u32 *app_id);
int qcom_scm_qseecom_app_send(u32 app_id, void *req, size_t req_size, void *rsp, int qcom_scm_qseecom_app_send(u32 app_id, dma_addr_t req, size_t req_size,
size_t rsp_size); dma_addr_t rsp, size_t rsp_size);
#else /* CONFIG_QCOM_QSEECOM */ #else /* CONFIG_QCOM_QSEECOM */
...@@ -128,9 +128,9 @@ static inline int qcom_scm_qseecom_app_get_id(const char *app_name, u32 *app_id) ...@@ -128,9 +128,9 @@ static inline int qcom_scm_qseecom_app_get_id(const char *app_name, u32 *app_id)
return -EINVAL; return -EINVAL;
} }
static inline int qcom_scm_qseecom_app_send(u32 app_id, void *req, static inline int qcom_scm_qseecom_app_send(u32 app_id,
size_t req_size, void *rsp, dma_addr_t req, size_t req_size,
size_t rsp_size) dma_addr_t rsp, size_t rsp_size)
{ {
return -EINVAL; return -EINVAL;
} }
......
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