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Commit 5ecab603 authored by Rafał Miłecki's avatar Rafał Miłecki Committed by John W. Linville
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b43: N-PHY: reorder functions: move RSSI calibration 

Signed-off-by: default avatarRafał Miłecki <zajec5@gmail.com>
Acked-by: default avatarLarry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 64712095
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Showing with 399 additions and 399 deletions
drivers/net/wireless/b43/phy_n.c
View file @ 5ecab603
...@@ -1193,1650 +1193,1650 @@ static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type) ...@@ -1193,1650 +1193,1650 @@ static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
b43_nphy_rev2_rssi_select(dev, code, type); b43_nphy_rev2_rssi_select(dev, code, type);
} }
/************************************************** /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
* Workarounds static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
**************************************************/ {
int i;
for (i = 0; i < 2; i++) {
if (type == 2) {
if (i == 0) {
b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
0xFC, buf[0]);
b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
0xFC, buf[1]);
} else {
b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
0xFC, buf[2 * i]);
b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
0xFC, buf[2 * i + 1]);
}
} else {
if (i == 0)
b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
0xF3, buf[0] << 2);
else
b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
0xF3, buf[2 * i + 1] << 2);
}
}
}
static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev) /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
u8 nsamp)
{ {
struct ssb_sprom *sprom = dev->dev->bus_sprom; int i;
int out;
u16 save_regs_phy[9];
u16 s[2];
bool ghz5; if (dev->phy.rev >= 3) {
bool ext_lna; save_regs_phy[0] = b43_phy_read(dev,
u16 rssi_gain; B43_NPHY_RFCTL_LUT_TRSW_UP1);
struct nphy_gain_ctl_workaround_entry *e; save_regs_phy[1] = b43_phy_read(dev,
u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 }; B43_NPHY_RFCTL_LUT_TRSW_UP2);
u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 }; save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
save_regs_phy[8] = 0;
} else {
save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
save_regs_phy[7] = 0;
save_regs_phy[8] = 0;
}
/* Prepare values */ b43_nphy_rssi_select(dev, 5, type);
ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
& B43_NPHY_BANDCTL_5GHZ;
ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
if (ghz5 && dev->phy.rev >= 5)
rssi_gain = 0x90;
else
rssi_gain = 0x50;
b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040); if (dev->phy.rev < 2) {
save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
}
/* Set Clip 2 detect */ for (i = 0; i < 4; i++)
b43_phy_set(dev, B43_NPHY_C1_CGAINI, buf[i] = 0;
B43_NPHY_C1_CGAINI_CL2DETECT);
b43_phy_set(dev, B43_NPHY_C2_CGAINI,
B43_NPHY_C2_CGAINI_CL2DETECT);
b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC, for (i = 0; i < nsamp; i++) {
0x17); if (dev->phy.rev < 2) {
b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC, s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
0x17); s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0); } else {
b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0); s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00); s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00); }
b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
rssi_gain);
b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
rssi_gain);
b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
0x17);
b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
0x17);
b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain); buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain); buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain); buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain); buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db); }
b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db); out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits); (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain); if (dev->phy.rev < 2)
b43_phy_write(dev, 0x2A7, e->init_gain); b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
e->rfseq_init);
b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
/* TODO: check defines. Do not match variables names */ if (dev->phy.rev >= 3) {
b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain); b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
b43_phy_write(dev, 0x2A9, e->cliphi_gain); save_regs_phy[0]);
b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain); b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
b43_phy_write(dev, 0x2AB, e->clipmd_gain); save_regs_phy[1]);
b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain); b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
b43_phy_write(dev, 0x2AD, e->cliplo_gain); b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
} else {
b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
}
b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin); return out;
b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
} }
static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev) /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
{ {
struct b43_phy_n *nphy = dev->phy.n; int i, j;
u8 state[4];
u8 i, j; u8 code, val;
u8 code; u16 class, override;
u16 tmp; u8 regs_save_radio[2];
u8 rfseq_events[3] = { 6, 8, 7 }; u16 regs_save_phy[2];
u8 rfseq_delays[3] = { 10, 30, 1 };
/* Set Clip 2 detect */
b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
/* Set narrowband clip threshold */
b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
if (!dev->phy.is_40mhz) { s8 offset[4];
/* Set dwell lengths */ u8 core;
b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B); u8 rail;
b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
}
/* Set wideband clip 2 threshold */ u16 clip_state[2];
b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, u16 clip_off[2] = { 0xFFFF, 0xFFFF };
~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21); s32 results_min[4] = { };
b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, u8 vcm_final[4] = { };
~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21); s32 results[4][4] = { };
s32 miniq[4][2] = { };
if (!dev->phy.is_40mhz) { if (type == 2) {
b43_phy_maskset(dev, B43_NPHY_C1_CGAINI, code = 0;
~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1); val = 6;
b43_phy_maskset(dev, B43_NPHY_C2_CGAINI, } else if (type < 2) {
~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1); code = 25;
b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI, val = 4;
~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1); } else {
b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI, B43_WARN_ON(1);
~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1); return;
} }
b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C); class = b43_nphy_classifier(dev, 0, 0);
b43_nphy_classifier(dev, 7, 4);
b43_nphy_read_clip_detection(dev, clip_state);
b43_nphy_write_clip_detection(dev, clip_off);
if (nphy->gain_boost) { if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ && override = 0x140;
dev->phy.is_40mhz)
code = 4;
else else
code = 5; override = 0x110;
} else {
code = dev->phy.is_40mhz ? 6 : 7;
}
/* Set HPVGA2 index */
b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
/* specs say about 2 loops, but wl does 4 */ regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
for (i = 0; i < 4; i++) b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C)); b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
b43_nphy_adjust_lna_gain_table(dev); regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
if (nphy->elna_gain_config) { state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808); state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08); b43_nphy_rssi_select(dev, 5, type);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0); b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1); b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06); for (i = 0; i < 4; i++) {
/* specs say about 2 loops, but wl does 4 */ u8 tmp[4];
for (i = 0; i < 4; i++) for (j = 0; j < 4; j++)
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, tmp[j] = i;
(code << 8 | 0x74)); if (type != 1)
b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
b43_nphy_poll_rssi(dev, type, results[i], 8);
if (type < 2)
for (j = 0; j < 2; j++)
miniq[i][j] = min(results[i][2 * j],
results[i][2 * j + 1]);
} }
if (dev->phy.rev == 2) {
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, s32 mind = 40;
(0x0400 * i) + 0x0020); u8 minvcm = 0;
for (j = 0; j < 21; j++) { s32 minpoll = 249;
tmp = j * (i < 2 ? 3 : 1); s32 curr;
b43_phy_write(dev, for (j = 0; j < 4; j++) {
B43_NPHY_TABLE_DATALO, tmp); if (type == 2)
curr = abs(results[j][i]);
else
curr = abs(miniq[j][i / 2] - code * 8);
if (curr < mind) {
mind = curr;
minvcm = j;
} }
if (results[j][i] < minpoll)
minpoll = results[j][i];
} }
results_min[i] = minpoll;
vcm_final[i] = minvcm;
} }
b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3); if (type != 1)
b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1, b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) for (i = 0; i < 4; i++) {
b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4); offset[i] = (code * 8) - results[vcm_final[i]][i];
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */ if (offset[i] < 0)
static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev) offset[i] = -((abs(offset[i]) + 4) / 8);
{
if (dev->phy.rev >= 3)
b43_nphy_gain_ctl_workarounds_rev3plus(dev);
else else
b43_nphy_gain_ctl_workarounds_rev1_2(dev); offset[i] = (offset[i] + 4) / 8;
}
if (results_min[i] == 248)
offset[i] = code - 32;
core = (i / 2) ? 2 : 1;
rail = (i % 2) ? 1 : 0;
b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
type);
}
b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
switch (state[2]) {
case 1:
b43_nphy_rssi_select(dev, 1, 2);
break;
case 4:
b43_nphy_rssi_select(dev, 1, 0);
break;
case 2:
b43_nphy_rssi_select(dev, 1, 1);
break;
default:
b43_nphy_rssi_select(dev, 1, 1);
break;
}
/************************************************** switch (state[3]) {
* Others case 1:
**************************************************/ b43_nphy_rssi_select(dev, 2, 2);
break;
case 4:
b43_nphy_rssi_select(dev, 2, 0);
break;
default:
b43_nphy_rssi_select(dev, 2, 1);
break;
}
void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna) b43_nphy_rssi_select(dev, 0, type);
{//TODO
}
static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev) b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
{//TODO b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
} b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev, b43_nphy_classifier(dev, 7, class);
bool ignore_tssi) b43_nphy_write_clip_detection(dev, clip_state);
{//TODO /* Specs don't say about reset here, but it makes wl and b43 dumps
return B43_TXPWR_RES_DONE; identical, it really seems wl performs this */
b43_nphy_reset_cca(dev);
} }
static void b43_chantab_phy_upload(struct b43_wldev *dev, /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
const struct b43_phy_n_sfo_cfg *e) static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
{ {
b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a); /* TODO */
b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
} }
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */ /*
static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable) * RSSI Calibration
* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
*/
static void b43_nphy_rssi_cal(struct b43_wldev *dev)
{ {
struct b43_phy_n *nphy = dev->phy.n;
u8 i;
u16 bmask, val, tmp;
enum ieee80211_band band = b43_current_band(dev->wl);
if (nphy->hang_avoid)
b43_nphy_stay_in_carrier_search(dev, 1);
nphy->txpwrctrl = enable;
if (!enable) {
if (dev->phy.rev >= 3 &&
(b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
(B43_NPHY_TXPCTL_CMD_COEFF |
B43_NPHY_TXPCTL_CMD_HWPCTLEN |
B43_NPHY_TXPCTL_CMD_PCTLEN))) {
/* We disable enabled TX pwr ctl, save it's state */
nphy->tx_pwr_idx[0] = b43_phy_read(dev,
B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
nphy->tx_pwr_idx[1] = b43_phy_read(dev,
B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
}
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
for (i = 0; i < 84; i++)
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
for (i = 0; i < 84; i++)
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
if (dev->phy.rev >= 3)
tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
if (dev->phy.rev >= 3) { if (dev->phy.rev >= 3) {
b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100); b43_nphy_rev3_rssi_cal(dev);
b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
} else { } else {
b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000); b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
} }
}
if (dev->phy.rev == 2) /**************************************************
b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, * Workarounds
~B43_NPHY_BPHY_CTL3_SCALE, 0x53); **************************************************/
else if (dev->phy.rev < 2)
b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
if (dev->phy.rev < 2 && dev->phy.is_40mhz) static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW); {
} else { struct ssb_sprom *sprom = dev->dev->bus_sprom;
b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
nphy->adj_pwr_tbl);
b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
nphy->adj_pwr_tbl);
bmask = B43_NPHY_TXPCTL_CMD_COEFF | bool ghz5;
B43_NPHY_TXPCTL_CMD_HWPCTLEN; bool ext_lna;
/* wl does useless check for "enable" param here */ u16 rssi_gain;
val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN; struct nphy_gain_ctl_workaround_entry *e;
if (dev->phy.rev >= 3) { u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN; u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
if (val)
val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
}
b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
if (band == IEEE80211_BAND_5GHZ) { /* Prepare values */
b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
~B43_NPHY_TXPCTL_CMD_INIT, 0x64); & B43_NPHY_BANDCTL_5GHZ;
if (dev->phy.rev > 1) ext_lna = sprom->boardflags_lo & B43_BFL_EXTLNA;
b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT, e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
~B43_NPHY_TXPCTL_INIT_PIDXI1, if (ghz5 && dev->phy.rev >= 5)
0x64); rssi_gain = 0x90;
} else
rssi_gain = 0x50;
if (dev->phy.rev >= 3) { b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
if (nphy->tx_pwr_idx[0] != 128 &&
nphy->tx_pwr_idx[1] != 128) {
/* Recover TX pwr ctl state */
b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
~B43_NPHY_TXPCTL_CMD_INIT,
nphy->tx_pwr_idx[0]);
if (dev->phy.rev > 1)
b43_phy_maskset(dev,
B43_NPHY_TXPCTL_INIT,
~0xff, nphy->tx_pwr_idx[1]);
}
}
if (dev->phy.rev >= 3) { /* Set Clip 2 detect */
b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100); b43_phy_set(dev, B43_NPHY_C1_CGAINI,
b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100); B43_NPHY_C1_CGAINI_CL2DETECT);
} else { b43_phy_set(dev, B43_NPHY_C2_CGAINI,
b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000); B43_NPHY_C2_CGAINI_CL2DETECT);
}
if (dev->phy.rev == 2) b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b); 0x17);
else if (dev->phy.rev < 2) b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40); 0x17);
b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
rssi_gain);
b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
rssi_gain);
b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
0x17);
b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
0x17);
b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
if (dev->phy.rev < 2 && dev->phy.is_40mhz) b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW); b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
if (b43_nphy_ipa(dev)) { b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4); b43_phy_write(dev, 0x2A7, e->init_gain);
b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4); b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
} e->rfseq_init);
} b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
if (nphy->hang_avoid) /* TODO: check defines. Do not match variables names */
b43_nphy_stay_in_carrier_search(dev, 0); b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
b43_phy_write(dev, 0x2A9, e->cliphi_gain);
b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
b43_phy_write(dev, 0x2AB, e->clipmd_gain);
b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
b43_phy_write(dev, 0x2AD, e->cliplo_gain);
b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
} }
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */ static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
{ {
struct b43_phy_n *nphy = dev->phy.n; struct b43_phy_n *nphy = dev->phy.n;
struct ssb_sprom *sprom = dev->dev->bus_sprom;
u8 txpi[2], bbmult, i; u8 i, j;
u16 tmp, radio_gain, dac_gain; u8 code;
u16 freq = dev->phy.channel_freq; u16 tmp;
u32 txgain; u8 rfseq_events[3] = { 6, 8, 7 };
/* u32 gaintbl; rev3+ */ u8 rfseq_delays[3] = { 10, 30, 1 };
/* Set Clip 2 detect */
b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
if (nphy->hang_avoid) /* Set narrowband clip threshold */
b43_nphy_stay_in_carrier_search(dev, 1); b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
if (dev->phy.rev >= 7) { if (!dev->phy.is_40mhz) {
txpi[0] = txpi[1] = 30; /* Set dwell lengths */
} else if (dev->phy.rev >= 3) { b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
txpi[0] = 40; b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
txpi[1] = 40; b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
} else if (sprom->revision < 4) { b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
txpi[0] = 72;
txpi[1] = 72;
} else {
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
txpi[0] = sprom->txpid2g[0];
txpi[1] = sprom->txpid2g[1];
} else if (freq >= 4900 && freq < 5100) {
txpi[0] = sprom->txpid5gl[0];
txpi[1] = sprom->txpid5gl[1];
} else if (freq >= 5100 && freq < 5500) {
txpi[0] = sprom->txpid5g[0];
txpi[1] = sprom->txpid5g[1];
} else if (freq >= 5500) {
txpi[0] = sprom->txpid5gh[0];
txpi[1] = sprom->txpid5gh[1];
} else {
txpi[0] = 91;
txpi[1] = 91;
}
} }
if (dev->phy.rev < 7 &&
(txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 10))
txpi[0] = txpi[1] = 91;
/* /* Set wideband clip 2 threshold */
for (i = 0; i < 2; i++) { b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
nphy->txpwrindex[i].index_internal = txpi[i]; ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
nphy->txpwrindex[i].index_internal_save = txpi[i]; b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
} ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
*/
for (i = 0; i < 2; i++) { if (!dev->phy.is_40mhz) {
if (dev->phy.rev >= 3) { b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
if (b43_nphy_ipa(dev)) { ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
txgain = *(b43_nphy_get_ipa_gain_table(dev) + b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
txpi[i]); ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
} else if (b43_current_band(dev->wl) == b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
IEEE80211_BAND_5GHZ) { ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
/* FIXME: use 5GHz tables */ b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
txgain = ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
} else {
if (dev->phy.rev >= 5 &&
sprom->fem.ghz5.extpa_gain == 3)
; /* FIXME: 5GHz_txgain_HiPwrEPA */
txgain =
b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
}
radio_gain = (txgain >> 16) & 0x1FFFF;
} else {
txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
radio_gain = (txgain >> 16) & 0x1FFF;
} }
if (dev->phy.rev >= 7) b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
dac_gain = (txgain >> 8) & 0x7;
else
dac_gain = (txgain >> 8) & 0x3F;
bbmult = txgain & 0xFF;
if (dev->phy.rev >= 3) { if (nphy->gain_boost) {
if (i == 0) if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100); dev->phy.is_40mhz)
code = 4;
else else
b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100); code = 5;
} else { } else {
b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000); code = dev->phy.is_40mhz ? 6 : 7;
} }
if (i == 0) /* Set HPVGA2 index */
b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain); b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
else code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain); b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain); b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
/* specs say about 2 loops, but wl does 4 */
for (i = 0; i < 4; i++)
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57)); b43_nphy_adjust_lna_gain_table(dev);
if (i == 0)
tmp = (tmp & 0x00FF) | (bbmult << 8);
else
tmp = (tmp & 0xFF00) | bbmult;
b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
if (b43_nphy_ipa(dev)) { if (nphy->elna_gain_config) {
u32 tmp32; b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
u16 reg = (i == 0) ? b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1; b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i, b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
576 + txpi[i])); b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
b43_phy_set(dev, reg, 0x4); b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
/* specs say about 2 loops, but wl does 4 */
for (i = 0; i < 4; i++)
b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
(code << 8 | 0x74));
}
if (dev->phy.rev == 2) {
for (i = 0; i < 4; i++) {
b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
(0x0400 * i) + 0x0020);
for (j = 0; j < 21; j++) {
tmp = j * (i < 2 ? 3 : 1);
b43_phy_write(dev,
B43_NPHY_TABLE_DATALO, tmp);
}
} }
} }
b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT); b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
if (nphy->hang_avoid) if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
b43_nphy_stay_in_carrier_search(dev, 0); b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
} }
static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev) /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
{ {
struct b43_phy *phy = &dev->phy; if (dev->phy.rev >= 3)
b43_nphy_gain_ctl_workarounds_rev3plus(dev);
else
b43_nphy_gain_ctl_workarounds_rev1_2(dev);
}
const u32 *table = NULL; /**************************************************
#if 0 * Others
TODO: b43_ntab_papd_pga_gain_delta_ipa_2* **************************************************/
u32 rfpwr_offset;
u8 pga_gain;
int i;
#endif
if (phy->rev >= 3) { void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
if (b43_nphy_ipa(dev)) { {//TODO
table = b43_nphy_get_ipa_gain_table(dev); }
} else {
if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
if (phy->rev == 3)
table = b43_ntab_tx_gain_rev3_5ghz;
if (phy->rev == 4)
table = b43_ntab_tx_gain_rev4_5ghz;
else
table = b43_ntab_tx_gain_rev5plus_5ghz;
} else {
table = b43_ntab_tx_gain_rev3plus_2ghz;
}
}
} else {
table = b43_ntab_tx_gain_rev0_1_2;
}
b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
if (phy->rev >= 3) { static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
#if 0 {//TODO
nphy->gmval = (table[0] >> 16) & 0x7000; }
for (i = 0; i < 128; i++) { static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
pga_gain = (table[i] >> 24) & 0xF; bool ignore_tssi)
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {//TODO
rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain]; return B43_TXPWR_RES_DONE;
else
rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_5g[pga_gain];
b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
rfpwr_offset);
b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
rfpwr_offset);
}
#endif
}
} }
/* static void b43_chantab_phy_upload(struct b43_wldev *dev,
* Upload the N-PHY tables. const struct b43_phy_n_sfo_cfg *e)
* http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
*/
static void b43_nphy_tables_init(struct b43_wldev *dev)
{ {
if (dev->phy.rev < 3) b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
b43_nphy_rev0_1_2_tables_init(dev); b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
else b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
b43_nphy_rev3plus_tables_init(dev); b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
} }
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable) static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
{ {
struct b43_phy_n *nphy = dev->phy.n; struct b43_phy_n *nphy = dev->phy.n;
enum ieee80211_band band; u8 i;
u16 tmp; u16 bmask, val, tmp;
enum ieee80211_band band = b43_current_band(dev->wl);
if (nphy->hang_avoid)
b43_nphy_stay_in_carrier_search(dev, 1);
nphy->txpwrctrl = enable;
if (!enable) { if (!enable) {
nphy->rfctrl_intc1_save = b43_phy_read(dev, if (dev->phy.rev >= 3 &&
B43_NPHY_RFCTL_INTC1); (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
nphy->rfctrl_intc2_save = b43_phy_read(dev, (B43_NPHY_TXPCTL_CMD_COEFF |
B43_NPHY_RFCTL_INTC2); B43_NPHY_TXPCTL_CMD_HWPCTLEN |
band = b43_current_band(dev->wl); B43_NPHY_TXPCTL_CMD_PCTLEN))) {
if (dev->phy.rev >= 3) { /* We disable enabled TX pwr ctl, save it's state */
if (band == IEEE80211_BAND_5GHZ) nphy->tx_pwr_idx[0] = b43_phy_read(dev,
tmp = 0x600; B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
else nphy->tx_pwr_idx[1] = b43_phy_read(dev,
tmp = 0x480; B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
} else {
if (band == IEEE80211_BAND_5GHZ)
tmp = 0x180;
else
tmp = 0x120;
} }
b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp); b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
for (i = 0; i < 84; i++)
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
for (i = 0; i < 84; i++)
b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
if (dev->phy.rev >= 3)
tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
if (dev->phy.rev >= 3) {
b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
} else { } else {
b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
nphy->rfctrl_intc1_save);
b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
nphy->rfctrl_intc2_save);
} }
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */ if (dev->phy.rev == 2)
static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev) b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
{ ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
u16 tmp; else if (dev->phy.rev < 2)
b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
if (dev->phy.rev < 2 && dev->phy.is_40mhz)
b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
} else {
b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
nphy->adj_pwr_tbl);
b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
nphy->adj_pwr_tbl);
bmask = B43_NPHY_TXPCTL_CMD_COEFF |
B43_NPHY_TXPCTL_CMD_HWPCTLEN;
/* wl does useless check for "enable" param here */
val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
if (dev->phy.rev >= 3) { if (dev->phy.rev >= 3) {
if (b43_nphy_ipa(dev)) { bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
tmp = 4; if (val)
b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2, val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
(((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
} }
b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
tmp = 1; if (band == IEEE80211_BAND_5GHZ) {
b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2, b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
(((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp); ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
if (dev->phy.rev > 1)
b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
~B43_NPHY_TXPCTL_INIT_PIDXI1,
0x64);
} }
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */ if (dev->phy.rev >= 3) {
static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble) if (nphy->tx_pwr_idx[0] != 128 &&
{ nphy->tx_pwr_idx[1] != 128) {
u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG); /* Recover TX pwr ctl state */
b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
mimocfg |= B43_NPHY_MIMOCFG_AUTO; ~B43_NPHY_TXPCTL_CMD_INIT,
if (preamble == 1) nphy->tx_pwr_idx[0]);
mimocfg |= B43_NPHY_MIMOCFG_GFMIX; if (dev->phy.rev > 1)
else b43_phy_maskset(dev,
mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX; B43_NPHY_TXPCTL_INIT,
~0xff, nphy->tx_pwr_idx[1]);
}
}
b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg); if (dev->phy.rev >= 3) {
} b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
} else {
b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */ if (dev->phy.rev == 2)
static void b43_nphy_update_txrx_chain(struct b43_wldev *dev) b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
{ else if (dev->phy.rev < 2)
struct b43_phy_n *nphy = dev->phy.n; b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
bool override = false; if (dev->phy.rev < 2 && dev->phy.is_40mhz)
u16 chain = 0x33; b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
if (nphy->txrx_chain == 0) { if (b43_nphy_ipa(dev)) {
chain = 0x11; b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
override = true; b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
} else if (nphy->txrx_chain == 1) { }
chain = 0x22;
override = true;
} }
b43_phy_maskset(dev, B43_NPHY_RFSEQCA, if (nphy->hang_avoid)
~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN), b43_nphy_stay_in_carrier_search(dev, 0);
chain);
if (override)
b43_phy_set(dev, B43_NPHY_RFSEQMODE,
B43_NPHY_RFSEQMODE_CAOVER);
else
b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
~B43_NPHY_RFSEQMODE_CAOVER);
} }
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est, static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
u16 samps, u8 time, bool wait)
{ {
int i; struct b43_phy_n *nphy = dev->phy.n;
u16 tmp; struct ssb_sprom *sprom = dev->dev->bus_sprom;
b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
if (wait)
b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
else
b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START); u8 txpi[2], bbmult, i;
u16 tmp, radio_gain, dac_gain;
u16 freq = dev->phy.channel_freq;
u32 txgain;
/* u32 gaintbl; rev3+ */
for (i = 1000; i; i--) { if (nphy->hang_avoid)
tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD); b43_nphy_stay_in_carrier_search(dev, 1);
if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) | if (dev->phy.rev >= 7) {
b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1); txpi[0] = txpi[1] = 30;
est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) | } else if (dev->phy.rev >= 3) {
b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1); txpi[0] = 40;
est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) | txpi[1] = 40;
b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1); } else if (sprom->revision < 4) {
return; txpi[0] = 72;
txpi[1] = 72;
} else {
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
txpi[0] = sprom->txpid2g[0];
txpi[1] = sprom->txpid2g[1];
} else if (freq >= 4900 && freq < 5100) {
txpi[0] = sprom->txpid5gl[0];
txpi[1] = sprom->txpid5gl[1];
} else if (freq >= 5100 && freq < 5500) {
txpi[0] = sprom->txpid5g[0];
txpi[1] = sprom->txpid5g[1];
} else if (freq >= 5500) {
txpi[0] = sprom->txpid5gh[0];
txpi[1] = sprom->txpid5gh[1];
} else {
txpi[0] = 91;
txpi[1] = 91;
} }
udelay(10);
} }
memset(est, 0, sizeof(*est)); if (dev->phy.rev < 7 &&
} (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 10))
txpi[0] = txpi[1] = 91;
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */ /*
static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write, for (i = 0; i < 2; i++) {
struct b43_phy_n_iq_comp *pcomp) nphy->txpwrindex[i].index_internal = txpi[i];
{ nphy->txpwrindex[i].index_internal_save = txpi[i];
if (write) {
b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
} else {
pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
} }
} */
#if 0
/* Ready but not used anywhere */
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
{
u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]); for (i = 0; i < 2; i++) {
if (core == 0) { if (dev->phy.rev >= 3) {
b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]); if (b43_nphy_ipa(dev)) {
b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]); txgain = *(b43_nphy_get_ipa_gain_table(dev) +
txpi[i]);
} else if (b43_current_band(dev->wl) ==
IEEE80211_BAND_5GHZ) {
/* FIXME: use 5GHz tables */
txgain =
b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
} else { } else {
b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]); if (dev->phy.rev >= 5 &&
b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]); sprom->fem.ghz5.extpa_gain == 3)
; /* FIXME: 5GHz_txgain_HiPwrEPA */
txgain =
b43_ntab_tx_gain_rev3plus_2ghz[txpi[i]];
}
radio_gain = (txgain >> 16) & 0x1FFFF;
} else {
txgain = b43_ntab_tx_gain_rev0_1_2[txpi[i]];
radio_gain = (txgain >> 16) & 0x1FFF;
} }
b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */ if (dev->phy.rev >= 7)
static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core) dac_gain = (txgain >> 8) & 0x7;
{ else
u8 rxval, txval; dac_gain = (txgain >> 8) & 0x3F;
u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs; bbmult = txgain & 0xFF;
regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA); if (dev->phy.rev >= 3) {
if (core == 0) { if (i == 0)
regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); else
b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
} else { } else {
regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
} }
regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001); if (i == 0)
b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001); b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
else
b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
b43_phy_maskset(dev, B43_NPHY_RFSEQCA, b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
(core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
(core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
if (core == 0) { tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007); if (i == 0)
b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007); tmp = (tmp & 0x00FF) | (bbmult << 8);
} else { else
b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007); tmp = (tmp & 0xFF00) | bbmult;
b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007); b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
if (b43_nphy_ipa(dev)) {
u32 tmp32;
u16 reg = (i == 0) ?
B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
576 + txpi[i]));
b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
b43_phy_set(dev, reg, 0x4);
}
} }
b43_nphy_rf_control_intc_override(dev, 2, 0, 3); b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
b43_nphy_rf_control_override(dev, 8, 0, 3, false);
b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
if (core == 0) { if (nphy->hang_avoid)
rxval = 1; b43_nphy_stay_in_carrier_search(dev, 0);
txval = 8;
} else {
rxval = 4;
txval = 2;
}
b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
} }
#endif
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */ static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
{ {
int i; struct b43_phy *phy = &dev->phy;
s32 iq;
u32 ii;
u32 qq;
int iq_nbits, qq_nbits;
int arsh, brsh;
u16 tmp, a, b;
struct nphy_iq_est est;
struct b43_phy_n_iq_comp old;
struct b43_phy_n_iq_comp new = { };
bool error = false;
if (mask == 0)
return;
b43_nphy_rx_iq_coeffs(dev, false, &old); const u32 *table = NULL;
b43_nphy_rx_iq_coeffs(dev, true, &new); #if 0
b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false); TODO: b43_ntab_papd_pga_gain_delta_ipa_2*
new = old; u32 rfpwr_offset;
u8 pga_gain;
int i;
#endif
for (i = 0; i < 2; i++) { if (phy->rev >= 3) {
if (i == 0 && (mask & 1)) { if (b43_nphy_ipa(dev)) {
iq = est.iq0_prod; table = b43_nphy_get_ipa_gain_table(dev);
ii = est.i0_pwr;
qq = est.q0_pwr;
} else if (i == 1 && (mask & 2)) {
iq = est.iq1_prod;
ii = est.i1_pwr;
qq = est.q1_pwr;
} else { } else {
continue; if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
if (phy->rev == 3)
table = b43_ntab_tx_gain_rev3_5ghz;
if (phy->rev == 4)
table = b43_ntab_tx_gain_rev4_5ghz;
else
table = b43_ntab_tx_gain_rev5plus_5ghz;
} else {
table = b43_ntab_tx_gain_rev3plus_2ghz;
} }
if (ii + qq < 2) {
error = true;
break;
} }
iq_nbits = fls(abs(iq));
qq_nbits = fls(qq);
arsh = iq_nbits - 20;
if (arsh >= 0) {
a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
tmp = ii >> arsh;
} else { } else {
a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh))); table = b43_ntab_tx_gain_rev0_1_2;
tmp = ii << -arsh;
}
if (tmp == 0) {
error = true;
break;
} }
a /= tmp; b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
brsh = qq_nbits - 11; if (phy->rev >= 3) {
if (brsh >= 0) { #if 0
b = (qq << (31 - qq_nbits)); nphy->gmval = (table[0] >> 16) & 0x7000;
tmp = ii >> brsh;
} else { for (i = 0; i < 128; i++) {
b = (qq << (31 - qq_nbits)); pga_gain = (table[i] >> 24) & 0xF;
tmp = ii << -brsh; if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
else
rfpwr_offset = b43_ntab_papd_pga_gain_delta_ipa_5g[pga_gain];
b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
rfpwr_offset);
b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
rfpwr_offset);
} }
if (tmp == 0) { #endif
error = true;
break;
} }
b = int_sqrt(b / tmp - a * a) - (1 << 10); }
if (i == 0 && (mask & 0x1)) { /*
* Upload the N-PHY tables.
* http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
*/
static void b43_nphy_tables_init(struct b43_wldev *dev)
{
if (dev->phy.rev < 3)
b43_nphy_rev0_1_2_tables_init(dev);
else
b43_nphy_rev3plus_tables_init(dev);
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
{
struct b43_phy_n *nphy = dev->phy.n;
enum ieee80211_band band;
u16 tmp;
if (!enable) {
nphy->rfctrl_intc1_save = b43_phy_read(dev,
B43_NPHY_RFCTL_INTC1);
nphy->rfctrl_intc2_save = b43_phy_read(dev,
B43_NPHY_RFCTL_INTC2);
band = b43_current_band(dev->wl);
if (dev->phy.rev >= 3) { if (dev->phy.rev >= 3) {
new.a0 = a & 0x3FF; if (band == IEEE80211_BAND_5GHZ)
new.b0 = b & 0x3FF; tmp = 0x600;
else
tmp = 0x480;
} else { } else {
new.a0 = b & 0x3FF; if (band == IEEE80211_BAND_5GHZ)
new.b0 = a & 0x3FF; tmp = 0x180;
else
tmp = 0x120;
} }
} else if (i == 1 && (mask & 0x2)) { b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
if (dev->phy.rev >= 3) { b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
new.a1 = a & 0x3FF;
new.b1 = b & 0x3FF;
} else { } else {
new.a1 = b & 0x3FF; b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
new.b1 = a & 0x3FF; nphy->rfctrl_intc1_save);
} b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
} nphy->rfctrl_intc2_save);
} }
if (error)
new = old;
b43_nphy_rx_iq_coeffs(dev, true, &new);
} }
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev) static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
{ {
u16 array[4]; u16 tmp;
b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
{
if (dev->phy.rev >= 3) { if (dev->phy.rev >= 3) {
if (!init) if (b43_nphy_ipa(dev)) {
return; tmp = 4;
if (0 /* FIXME */) { b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211); (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
} }
} else {
b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
switch (dev->dev->bus_type) { tmp = 1;
#ifdef CONFIG_B43_BCMA b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
case B43_BUS_BCMA: (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
0xFC00, 0xFC00);
break;
#endif
#ifdef CONFIG_B43_SSB
case B43_BUS_SSB:
ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
0xFC00, 0xFC00);
break;
#endif
} }
}
b43_write32(dev, B43_MMIO_MACCTL, /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
b43_read32(dev, B43_MMIO_MACCTL) & static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
~B43_MACCTL_GPOUTSMSK); {
b43_write16(dev, B43_MMIO_GPIO_MASK, u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
b43_write16(dev, B43_MMIO_GPIO_CONTROL,
b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
if (init) { mimocfg |= B43_NPHY_MIMOCFG_AUTO;
b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); if (preamble == 1)
b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); else
b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
}
} b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
} }
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
static void b43_nphy_stop_playback(struct b43_wldev *dev) static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
{ {
struct b43_phy_n *nphy = dev->phy.n; struct b43_phy_n *nphy = dev->phy.n;
u16 tmp;
if (nphy->hang_avoid)
b43_nphy_stay_in_carrier_search(dev, 1);
tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
if (tmp & 0x1)
b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
else if (tmp & 0x2)
b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004); bool override = false;
u16 chain = 0x33;
if (nphy->bb_mult_save & 0x80000000) { if (nphy->txrx_chain == 0) {
tmp = nphy->bb_mult_save & 0xFFFF; chain = 0x11;
b43_ntab_write(dev, B43_NTAB16(15, 87), tmp); override = true;
nphy->bb_mult_save = 0; } else if (nphy->txrx_chain == 1) {
chain = 0x22;
override = true;
} }
if (nphy->hang_avoid) b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
b43_nphy_stay_in_carrier_search(dev, 0); ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
chain);
if (override)
b43_phy_set(dev, B43_NPHY_RFSEQMODE,
B43_NPHY_RFSEQMODE_CAOVER);
else
b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
~B43_NPHY_RFSEQMODE_CAOVER);
} }
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
static void b43_nphy_spur_workaround(struct b43_wldev *dev) static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
u16 samps, u8 time, bool wait)
{ {
struct b43_phy_n *nphy = dev->phy.n; int i;
u16 tmp;
u8 channel = dev->phy.channel; b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
int tone[2] = { 57, 58 }; b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
u32 noise[2] = { 0x3FF, 0x3FF }; if (wait)
b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
else
b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
B43_WARN_ON(dev->phy.rev < 3); b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
if (nphy->hang_avoid) for (i = 1000; i; i--) {
b43_nphy_stay_in_carrier_search(dev, 1); tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
if (nphy->gband_spurwar_en) { est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
/* TODO: N PHY Adjust Analog Pfbw (7) */ b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
if (channel == 11 && dev->phy.is_40mhz) est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/ b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
else est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
/* TODO: N PHY Adjust CRS Min Power (0x1E) */ return;
} }
udelay(10);
if (nphy->aband_spurwar_en) {
if (channel == 54) {
tone[0] = 0x20;
noise[0] = 0x25F;
} else if (channel == 38 || channel == 102 || channel == 118) {
if (0 /* FIXME */) {
tone[0] = 0x20;
noise[0] = 0x21F;
} else {
tone[0] = 0;
noise[0] = 0;
} }
} else if (channel == 134) { memset(est, 0, sizeof(*est));
tone[0] = 0x20; }
noise[0] = 0x21F;
} else if (channel == 151) { /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
tone[0] = 0x10; static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
noise[0] = 0x23F; struct b43_phy_n_iq_comp *pcomp)
} else if (channel == 153 || channel == 161) { {
tone[0] = 0x30; if (write) {
noise[0] = 0x23F; b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
} else { } else {
tone[0] = 0; pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
noise[0] = 0; pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
} }
}
if (!tone[0] && !noise[0]) #if 0
; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/ /* Ready but not used anywhere */
else /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
} {
u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
if (nphy->hang_avoid) b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
b43_nphy_stay_in_carrier_search(dev, 0); if (core == 0) {
b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
} else {
b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
}
b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
} }
static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev) /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
{ {
struct b43_phy_n *nphy = dev->phy.n; u8 rxval, txval;
struct ssb_sprom *sprom = dev->dev->bus_sprom; u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
/* TX to RX */
u8 tx2rx_events[8] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
u8 tx2rx_delays[8] = { 8, 4, 2, 2, 4, 4, 6, 1 };
/* RX to TX */
u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
0x1F };
u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
u16 tmp16;
u32 tmp32;
b43_phy_write(dev, 0x23f, 0x1f8); regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
b43_phy_write(dev, 0x240, 0x1f8); if (core == 0) {
regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
} else {
regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
}
regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
tmp32 &= 0xffffff; b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125); b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3); ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105); ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E); b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD); ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
(core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
(core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C); if (core == 0) {
b43_phy_write(dev, 0x2AE, 0x000C); b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
} else {
b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
}
/* TX to RX */ b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, b43_nphy_rf_control_override(dev, 8, 0, 3, false);
ARRAY_SIZE(tx2rx_events)); b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
/* RX to TX */ if (core == 0) {
if (b43_nphy_ipa(dev)) rxval = 1;
b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa, txval = 8;
rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa)); } else {
if (nphy->hw_phyrxchain != 3 && rxval = 4;
nphy->hw_phyrxchain != nphy->hw_phytxchain) { txval = 2;
if (b43_nphy_ipa(dev)) {
rx2tx_delays[5] = 59;
rx2tx_delays[6] = 1;
rx2tx_events[7] = 0x1F;
}
b43_nphy_set_rf_sequence(dev, 1, rx2tx_events, rx2tx_delays,
ARRAY_SIZE(rx2tx_events));
} }
b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
}
#endif
tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
0x2 : 0x9C40; static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16); {
int i;
s32 iq;
u32 ii;
u32 qq;
int iq_nbits, qq_nbits;
int arsh, brsh;
u16 tmp, a, b;
b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700); struct nphy_iq_est est;
struct b43_phy_n_iq_comp old;
struct b43_phy_n_iq_comp new = { };
bool error = false;
b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D); if (mask == 0)
b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D); return;
b43_nphy_gain_ctl_workarounds(dev); b43_nphy_rx_iq_coeffs(dev, false, &old);
b43_nphy_rx_iq_coeffs(dev, true, &new);
b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
new = old;
b43_ntab_write(dev, B43_NTAB16(8, 0), 2); for (i = 0; i < 2; i++) {
b43_ntab_write(dev, B43_NTAB16(8, 16), 2); if (i == 0 && (mask & 1)) {
iq = est.iq0_prod;
ii = est.i0_pwr;
qq = est.q0_pwr;
} else if (i == 1 && (mask & 2)) {
iq = est.iq1_prod;
ii = est.i1_pwr;
qq = est.q1_pwr;
} else {
continue;
}
/* TODO */ if (ii + qq < 2) {
error = true;
break;
}
b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00); iq_nbits = fls(abs(iq));
b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00); qq_nbits = fls(qq);
b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
/* N PHY WAR TX Chain Update with hw_phytxchain as argument */ arsh = iq_nbits - 20;
if (arsh >= 0) {
a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
tmp = ii >> arsh;
} else {
a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
tmp = ii << -arsh;
}
if (tmp == 0) {
error = true;
break;
}
a /= tmp;
if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR && brsh = qq_nbits - 11;
b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) || if (brsh >= 0) {
(sprom->boardflags2_lo & B43_BFL2_GPLL_WAR && b = (qq << (31 - qq_nbits));
b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) tmp = ii >> brsh;
tmp32 = 0x00088888; } else {
else b = (qq << (31 - qq_nbits));
tmp32 = 0x88888888; tmp = ii << -brsh;
b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32); }
b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32); if (tmp == 0) {
b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32); error = true;
break;
}
b = int_sqrt(b / tmp - a * a) - (1 << 10);
if (dev->phy.rev == 4 && if (i == 0 && (mask & 0x1)) {
b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { if (dev->phy.rev >= 3) {
b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC, new.a0 = a & 0x3FF;
0x70); new.b0 = b & 0x3FF;
b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC, } else {
0x70); new.a0 = b & 0x3FF;
new.b0 = a & 0x3FF;
}
} else if (i == 1 && (mask & 0x2)) {
if (dev->phy.rev >= 3) {
new.a1 = a & 0x3FF;
new.b1 = b & 0x3FF;
} else {
new.a1 = b & 0x3FF;
new.b1 = a & 0x3FF;
}
}
} }
b43_phy_write(dev, 0x224, 0x03eb); if (error)
b43_phy_write(dev, 0x225, 0x03eb); new = old;
b43_phy_write(dev, 0x226, 0x0341);
b43_phy_write(dev, 0x227, 0x0341); b43_nphy_rx_iq_coeffs(dev, true, &new);
b43_phy_write(dev, 0x228, 0x042b);
b43_phy_write(dev, 0x229, 0x042b);
b43_phy_write(dev, 0x22a, 0x0381);
b43_phy_write(dev, 0x22b, 0x0381);
b43_phy_write(dev, 0x22c, 0x042b);
b43_phy_write(dev, 0x22d, 0x042b);
b43_phy_write(dev, 0x22e, 0x0381);
b43_phy_write(dev, 0x22f, 0x0381);
} }
static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev) /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
{ {
struct ssb_sprom *sprom = dev->dev->bus_sprom; u16 array[4];
struct b43_phy *phy = &dev->phy; b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
struct b43_phy_n *nphy = phy->n;
u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ && b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
nphy->band5g_pwrgain) { b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8); b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8); b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
} else { }
b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
}
b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A); /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A); static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA); {
b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA); if (dev->phy.rev >= 3) {
if (!init)
return;
if (0 /* FIXME */) {
b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
}
} else {
b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
if (dev->phy.rev < 2) { switch (dev->dev->bus_type) {
b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000); #ifdef CONFIG_B43_BCMA
b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000); case B43_BUS_BCMA:
b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB); bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB); 0xFC00, 0xFC00);
b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800); break;
b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800); #endif
#ifdef CONFIG_B43_SSB
case B43_BUS_SSB:
ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
0xFC00, 0xFC00);
break;
#endif
} }
b43_write32(dev, B43_MMIO_MACCTL,
b43_read32(dev, B43_MMIO_MACCTL) &
~B43_MACCTL_GPOUTSMSK);
b43_write16(dev, B43_MMIO_GPIO_MASK,
b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
b43_write16(dev, B43_MMIO_GPIO_CONTROL,
b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
if (init) {
b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD &&
dev->dev->board_type == 0x8B) {
delays1[0] = 0x1;
delays1[5] = 0x14;
} }
b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
b43_nphy_gain_ctl_workarounds(dev);
if (dev->phy.rev < 2) {
if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
b43_hf_write(dev, b43_hf_read(dev) |
B43_HF_MLADVW);
} else if (dev->phy.rev == 2) {
b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
} }
if (dev->phy.rev < 2)
b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
~B43_NPHY_SCRAM_SIGCTL_SCM);
/* Set phase track alpha and beta */
b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
b43_phy_mask(dev, B43_NPHY_PIL_DW1,
~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
if (dev->phy.rev == 2)
b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
B43_NPHY_FINERX2_CGC_DECGC);
} }
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
static void b43_nphy_workarounds(struct b43_wldev *dev) static void b43_nphy_stop_playback(struct b43_wldev *dev)
{ {
struct b43_phy *phy = &dev->phy; struct b43_phy_n *nphy = dev->phy.n;
struct b43_phy_n *nphy = phy->n; u16 tmp;
if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
b43_nphy_classifier(dev, 1, 0);
else
b43_nphy_classifier(dev, 1, 1);
if (nphy->hang_avoid) if (nphy->hang_avoid)
b43_nphy_stay_in_carrier_search(dev, 1); b43_nphy_stay_in_carrier_search(dev, 1);
b43_phy_set(dev, B43_NPHY_IQFLIP, tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2); if (tmp & 0x1)
b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
else if (tmp & 0x2)
b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
if (dev->phy.rev >= 3) b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
b43_nphy_workarounds_rev3plus(dev);
else if (nphy->bb_mult_save & 0x80000000) {
b43_nphy_workarounds_rev1_2(dev); tmp = nphy->bb_mult_save & 0xFFFF;
b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
nphy->bb_mult_save = 0;
}
if (nphy->hang_avoid) if (nphy->hang_avoid)
b43_nphy_stay_in_carrier_search(dev, 0); b43_nphy_stay_in_carrier_search(dev, 0);
} }
/* /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
* Transmits a known value for LO calibration static void b43_nphy_spur_workaround(struct b43_wldev *dev)
* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
*/
static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
bool iqmode, bool dac_test)
{
u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
if (samp == 0)
return -1;
b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
return 0;
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
{ {
struct b43_phy_n *nphy = dev->phy.n; struct b43_phy_n *nphy = dev->phy.n;
int i, j;
u32 tmp;
u32 cur_real, cur_imag, real_part, imag_part;
u16 buffer[7];
if (nphy->hang_avoid)
b43_nphy_stay_in_carrier_search(dev, true);
b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
for (i = 0; i < 2; i++) {
tmp = ((buffer[i * 2] & 0x3FF) << 10) |
(buffer[i * 2 + 1] & 0x3FF);
b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
(((i + 26) << 10) | 320));
for (j = 0; j < 128; j++) {
b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
((tmp >> 16) & 0xFFFF));
b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
(tmp & 0xFFFF));
}
}
for (i = 0; i < 2; i++) {
tmp = buffer[5 + i];
real_part = (tmp >> 8) & 0xFF;
imag_part = (tmp & 0xFF);
b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
(((i + 26) << 10) | 448));
if (dev->phy.rev >= 3) {
cur_real = real_part;
cur_imag = imag_part;
tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
}
for (j = 0; j < 128; j++) { u8 channel = dev->phy.channel;
if (dev->phy.rev < 3) { int tone[2] = { 57, 58 };
cur_real = (real_part * loscale[j] + 128) >> 8; u32 noise[2] = { 0x3FF, 0x3FF };
cur_imag = (imag_part * loscale[j] + 128) >> 8;
tmp = ((cur_real & 0xFF) << 8) |
(cur_imag & 0xFF);
}
b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
((tmp >> 16) & 0xFFFF));
b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
(tmp & 0xFFFF));
}
}
if (dev->phy.rev >= 3) { B43_WARN_ON(dev->phy.rev < 3);
b43_shm_write16(dev, B43_SHM_SHARED,
B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
b43_shm_write16(dev, B43_SHM_SHARED,
B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
}
if (nphy->hang_avoid) if (nphy->hang_avoid)
b43_nphy_stay_in_carrier_search(dev, false); b43_nphy_stay_in_carrier_search(dev, 1);
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
static void b43_nphy_bphy_init(struct b43_wldev *dev)
{
unsigned int i;
u16 val;
val = 0x1E1F; if (nphy->gband_spurwar_en) {
for (i = 0; i < 16; i++) { /* TODO: N PHY Adjust Analog Pfbw (7) */
b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val); if (channel == 11 && dev->phy.is_40mhz)
val -= 0x202; ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
} else
val = 0x3E3F; ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
for (i = 0; i < 16; i++) { /* TODO: N PHY Adjust CRS Min Power (0x1E) */
b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
val -= 0x202;
} }
b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */ if (nphy->aband_spurwar_en) {
static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf) if (channel == 54) {
{ tone[0] = 0x20;
int i; noise[0] = 0x25F;
for (i = 0; i < 2; i++) { } else if (channel == 38 || channel == 102 || channel == 118) {
if (type == 2) { if (0 /* FIXME */) {
if (i == 0) { tone[0] = 0x20;
b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM, noise[0] = 0x21F;
0xFC, buf[0]);
b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
0xFC, buf[1]);
} else { } else {
b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM, tone[0] = 0;
0xFC, buf[2 * i]); noise[0] = 0;
b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
0xFC, buf[2 * i + 1]);
} }
} else if (channel == 134) {
tone[0] = 0x20;
noise[0] = 0x21F;
} else if (channel == 151) {
tone[0] = 0x10;
noise[0] = 0x23F;
} else if (channel == 153 || channel == 161) {
tone[0] = 0x30;
noise[0] = 0x23F;
} else { } else {
if (i == 0) tone[0] = 0;
b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5, noise[0] = 0;
0xF3, buf[0] << 2);
else
b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
0xF3, buf[2 * i + 1] << 2);
} }
if (!tone[0] && !noise[0])
; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
else
; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
} }
if (nphy->hang_avoid)
b43_nphy_stay_in_carrier_search(dev, 0);
} }
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
u8 nsamp)
{ {
int i; struct b43_phy_n *nphy = dev->phy.n;
int out; struct ssb_sprom *sprom = dev->dev->bus_sprom;
u16 save_regs_phy[9];
u16 s[2];
if (dev->phy.rev >= 3) { /* TX to RX */
save_regs_phy[0] = b43_phy_read(dev, u8 tx2rx_events[8] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
B43_NPHY_RFCTL_LUT_TRSW_UP1); u8 tx2rx_delays[8] = { 8, 4, 2, 2, 4, 4, 6, 1 };
save_regs_phy[1] = b43_phy_read(dev, /* RX to TX */
B43_NPHY_RFCTL_LUT_TRSW_UP2); u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1); 0x1F };
save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2); u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1); u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER); u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
save_regs_phy[8] = 0;
} else {
save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
save_regs_phy[7] = 0;
save_regs_phy[8] = 0;
}
b43_nphy_rssi_select(dev, 5, type); u16 tmp16;
u32 tmp32;
if (dev->phy.rev < 2) { b43_phy_write(dev, 0x23f, 0x1f8);
save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL); b43_phy_write(dev, 0x240, 0x1f8);
b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
}
for (i = 0; i < 4; i++) tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
buf[i] = 0; tmp32 &= 0xffffff;
b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
for (i = 0; i < nsamp; i++) { b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
if (dev->phy.rev < 2) { b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT); b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT); b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
} else { b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
s[0] = b43_phy_read(dev, B43_NPHY_RSSI1); b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
}
buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2; b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2; b43_phy_write(dev, 0x2AE, 0x000C);
buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2; /* TX to RX */
b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
ARRAY_SIZE(tx2rx_events));
/* RX to TX */
if (b43_nphy_ipa(dev))
b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
if (nphy->hw_phyrxchain != 3 &&
nphy->hw_phyrxchain != nphy->hw_phytxchain) {
if (b43_nphy_ipa(dev)) {
rx2tx_delays[5] = 59;
rx2tx_delays[6] = 1;
rx2tx_events[7] = 0x1F;
}
b43_nphy_set_rf_sequence(dev, 1, rx2tx_events, rx2tx_delays,
ARRAY_SIZE(rx2tx_events));
} }
out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
(buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
if (dev->phy.rev < 2) tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]); 0x2 : 0x9C40;
b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
if (dev->phy.rev >= 3) { b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
save_regs_phy[0]); b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
save_regs_phy[1]);
b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]); b43_nphy_gain_ctl_workarounds(dev);
b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]); b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]); b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]); /* TODO */
} else {
b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]); b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]); b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]); b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]); b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]); b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]); b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]); b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
/* N PHY WAR TX Chain Update with hw_phytxchain as argument */
if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
(sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
tmp32 = 0x00088888;
else
tmp32 = 0x88888888;
b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
if (dev->phy.rev == 4 &&
b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
0x70);
b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
0x70);
} }
return out; b43_phy_write(dev, 0x224, 0x03eb);
b43_phy_write(dev, 0x225, 0x03eb);
b43_phy_write(dev, 0x226, 0x0341);
b43_phy_write(dev, 0x227, 0x0341);
b43_phy_write(dev, 0x228, 0x042b);
b43_phy_write(dev, 0x229, 0x042b);
b43_phy_write(dev, 0x22a, 0x0381);
b43_phy_write(dev, 0x22b, 0x0381);
b43_phy_write(dev, 0x22c, 0x042b);
b43_phy_write(dev, 0x22d, 0x042b);
b43_phy_write(dev, 0x22e, 0x0381);
b43_phy_write(dev, 0x22f, 0x0381);
} }
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */ static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
{ {
int i, j; struct ssb_sprom *sprom = dev->dev->bus_sprom;
u8 state[4]; struct b43_phy *phy = &dev->phy;
u8 code, val; struct b43_phy_n *nphy = phy->n;
u16 class, override;
u8 regs_save_radio[2];
u16 regs_save_phy[2];
s8 offset[4]; u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
u8 core; u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
u8 rail;
u16 clip_state[2]; u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
u16 clip_off[2] = { 0xFFFF, 0xFFFF }; u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
s32 results_min[4] = { };
u8 vcm_final[4] = { };
s32 results[4][4] = { };
s32 miniq[4][2] = { };
if (type == 2) { if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
code = 0; nphy->band5g_pwrgain) {
val = 6; b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
} else if (type < 2) { b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
code = 25;
val = 4;
} else { } else {
B43_WARN_ON(1); b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
return; b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
}
b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
if (dev->phy.rev < 2) {
b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
}
b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD &&
dev->dev->board_type == 0x8B) {
delays1[0] = 0x1;
delays1[5] = 0x14;
} }
b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
class = b43_nphy_classifier(dev, 0, 0); b43_nphy_gain_ctl_workarounds(dev);
b43_nphy_classifier(dev, 7, 4);
b43_nphy_read_clip_detection(dev, clip_state);
b43_nphy_write_clip_detection(dev, clip_off);
if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) if (dev->phy.rev < 2) {
override = 0x140; if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
else b43_hf_write(dev, b43_hf_read(dev) |
override = 0x110; B43_HF_MLADVW);
} else if (dev->phy.rev == 2) {
b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
}
regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); if (dev->phy.rev < 2)
regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX); b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override); ~B43_NPHY_SCRAM_SIGCTL_SCM);
b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); /* Set phase track alpha and beta */
regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX); b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override); b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
b43_radio_write16(dev, B2055_C2_PD_RXTX, val); b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07; b43_phy_mask(dev, B43_NPHY_PIL_DW1,
state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07; ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8); b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8); b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07; b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
b43_nphy_rssi_select(dev, 5, type); if (dev->phy.rev == 2)
b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type); b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type); B43_NPHY_FINERX2_CGC_DECGC);
}
for (i = 0; i < 4; i++) { /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
u8 tmp[4]; static void b43_nphy_workarounds(struct b43_wldev *dev)
for (j = 0; j < 4; j++) {
tmp[j] = i; struct b43_phy *phy = &dev->phy;
if (type != 1) struct b43_phy_n *nphy = phy->n;
b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
b43_nphy_poll_rssi(dev, type, results[i], 8);
if (type < 2)
for (j = 0; j < 2; j++)
miniq[i][j] = min(results[i][2 * j],
results[i][2 * j + 1]);
}
for (i = 0; i < 4; i++) { if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
s32 mind = 40; b43_nphy_classifier(dev, 1, 0);
u8 minvcm = 0;
s32 minpoll = 249;
s32 curr;
for (j = 0; j < 4; j++) {
if (type == 2)
curr = abs(results[j][i]);
else else
curr = abs(miniq[j][i / 2] - code * 8); b43_nphy_classifier(dev, 1, 1);
if (curr < mind) { if (nphy->hang_avoid)
mind = curr; b43_nphy_stay_in_carrier_search(dev, 1);
minvcm = j;
}
if (results[j][i] < minpoll) b43_phy_set(dev, B43_NPHY_IQFLIP,
minpoll = results[j][i]; B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
}
results_min[i] = minpoll;
vcm_final[i] = minvcm;
}
if (type != 1) if (dev->phy.rev >= 3)
b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final); b43_nphy_workarounds_rev3plus(dev);
else
b43_nphy_workarounds_rev1_2(dev);
for (i = 0; i < 4; i++) { if (nphy->hang_avoid)
offset[i] = (code * 8) - results[vcm_final[i]][i]; b43_nphy_stay_in_carrier_search(dev, 0);
}
if (offset[i] < 0) /*
offset[i] = -((abs(offset[i]) + 4) / 8); * Transmits a known value for LO calibration
else * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
offset[i] = (offset[i] + 4) / 8; */
static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
bool iqmode, bool dac_test)
{
u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
if (samp == 0)
return -1;
b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
return 0;
}
if (results_min[i] == 248) /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
offset[i] = code - 32; static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
{
struct b43_phy_n *nphy = dev->phy.n;
int i, j;
u32 tmp;
u32 cur_real, cur_imag, real_part, imag_part;
core = (i / 2) ? 2 : 1; u16 buffer[7];
rail = (i % 2) ? 1 : 0;
b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail, if (nphy->hang_avoid)
type); b43_nphy_stay_in_carrier_search(dev, true);
}
b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]); b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
switch (state[2]) { for (i = 0; i < 2; i++) {
case 1: tmp = ((buffer[i * 2] & 0x3FF) << 10) |
b43_nphy_rssi_select(dev, 1, 2); (buffer[i * 2 + 1] & 0x3FF);
break; b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
case 4: (((i + 26) << 10) | 320));
b43_nphy_rssi_select(dev, 1, 0); for (j = 0; j < 128; j++) {
break; b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
case 2: ((tmp >> 16) & 0xFFFF));
b43_nphy_rssi_select(dev, 1, 1); b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
break; (tmp & 0xFFFF));
default: }
b43_nphy_rssi_select(dev, 1, 1);
break;
} }
switch (state[3]) { for (i = 0; i < 2; i++) {
case 1: tmp = buffer[5 + i];
b43_nphy_rssi_select(dev, 2, 2); real_part = (tmp >> 8) & 0xFF;
break; imag_part = (tmp & 0xFF);
case 4: b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
b43_nphy_rssi_select(dev, 2, 0); (((i + 26) << 10) | 448));
break;
default: if (dev->phy.rev >= 3) {
b43_nphy_rssi_select(dev, 2, 1); cur_real = real_part;
break; cur_imag = imag_part;
tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
} }
b43_nphy_rssi_select(dev, 0, type); for (j = 0; j < 128; j++) {
if (dev->phy.rev < 3) {
cur_real = (real_part * loscale[j] + 128) >> 8;
cur_imag = (imag_part * loscale[j] + 128) >> 8;
tmp = ((cur_real & 0xFF) << 8) |
(cur_imag & 0xFF);
}
b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
((tmp >> 16) & 0xFFFF));
b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
(tmp & 0xFFFF));
}
}
b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]); if (dev->phy.rev >= 3) {
b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]); b43_shm_write16(dev, B43_SHM_SHARED,
b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]); B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]); b43_shm_write16(dev, B43_SHM_SHARED,
B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
}
b43_nphy_classifier(dev, 7, class); if (nphy->hang_avoid)
b43_nphy_write_clip_detection(dev, clip_state); b43_nphy_stay_in_carrier_search(dev, false);
/* Specs don't say about reset here, but it makes wl and b43 dumps
identical, it really seems wl performs this */
b43_nphy_reset_cca(dev);
} }
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev) static void b43_nphy_bphy_init(struct b43_wldev *dev)
{ {
/* TODO */ unsigned int i;
} u16 val;
/* val = 0x1E1F;
* RSSI Calibration for (i = 0; i < 16; i++) {
* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
*/ val -= 0x202;
static void b43_nphy_rssi_cal(struct b43_wldev *dev) }
{ val = 0x3E3F;
if (dev->phy.rev >= 3) { for (i = 0; i < 16; i++) {
b43_nphy_rev3_rssi_cal(dev); b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
} else { val -= 0x202;
b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
} }
b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
} }
/* /*
......
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