Commit 5f7f726d authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter

drm/i915: set interlaced bits for TRANSCONF

I'm not sure why they are needed (I didn't notice any difference in my
tests), but these bits are in our documentation and they are also set by
the Windows driver.
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 75c13993
...@@ -3362,7 +3362,9 @@ ...@@ -3362,7 +3362,9 @@
#define TRANS_FSYNC_DELAY_HB4 (3<<27) #define TRANS_FSYNC_DELAY_HB4 (3<<27)
#define TRANS_DP_AUDIO_ONLY (1<<26) #define TRANS_DP_AUDIO_ONLY (1<<26)
#define TRANS_DP_VIDEO_AUDIO (0<<26) #define TRANS_DP_VIDEO_AUDIO (0<<26)
#define TRANS_INTERLACE_MASK (7<<21)
#define TRANS_PROGRESSIVE (0<<21) #define TRANS_PROGRESSIVE (0<<21)
#define TRANS_INTERLACED (3<<21)
#define TRANS_8BPC (0<<5) #define TRANS_8BPC (0<<5)
#define TRANS_10BPC (1<<5) #define TRANS_10BPC (1<<5)
#define TRANS_6BPC (2<<5) #define TRANS_6BPC (2<<5)
......
...@@ -1266,7 +1266,7 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv, ...@@ -1266,7 +1266,7 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
enum pipe pipe) enum pipe pipe)
{ {
int reg; int reg;
u32 val; u32 val, pipeconf_val;
/* PCH only available on ILK+ */ /* PCH only available on ILK+ */
BUG_ON(dev_priv->info->gen < 5); BUG_ON(dev_priv->info->gen < 5);
...@@ -1280,6 +1280,7 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv, ...@@ -1280,6 +1280,7 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
reg = TRANSCONF(pipe); reg = TRANSCONF(pipe);
val = I915_READ(reg); val = I915_READ(reg);
pipeconf_val = I915_READ(PIPECONF(pipe));
if (HAS_PCH_IBX(dev_priv->dev)) { if (HAS_PCH_IBX(dev_priv->dev)) {
/* /*
...@@ -1287,8 +1288,15 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv, ...@@ -1287,8 +1288,15 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
* that in pipeconf reg. * that in pipeconf reg.
*/ */
val &= ~PIPE_BPC_MASK; val &= ~PIPE_BPC_MASK;
val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK; val |= pipeconf_val & PIPE_BPC_MASK;
} }
val &= ~TRANS_INTERLACE_MASK;
if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
val |= TRANS_INTERLACED;
else
val |= TRANS_PROGRESSIVE;
I915_WRITE(reg, val | TRANS_ENABLE); I915_WRITE(reg, val | TRANS_ENABLE);
if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
DRM_ERROR("failed to enable transcoder %d\n", pipe); DRM_ERROR("failed to enable transcoder %d\n", pipe);
......
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