Commit 6246059a authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu: simplify amdgpu_ras_eeprom.c

All chips that support RAS also support IP discovery, so
use the IP versions rather than a mix of IP versions and
asic types.  Checking the validity of the atom_ctx pointer
is not required as the vbios is already fetched at this
point.

v2: add comments to id asic types based on feedback from Luben
Reviewed-by: default avatarLuben Tuikov <luben.tuikov@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: Luben Tuikov <luben.tuikov@amd.com>
parent 27488686
...@@ -107,51 +107,16 @@ ...@@ -107,51 +107,16 @@
static bool __is_ras_eeprom_supported(struct amdgpu_device *adev) static bool __is_ras_eeprom_supported(struct amdgpu_device *adev)
{ {
if (adev->asic_type == CHIP_IP_DISCOVERY) {
switch (adev->ip_versions[MP1_HWIP][0]) { switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(11, 0, 2): /* VEGA20 and ARCTURUS */
case IP_VERSION(11, 0, 7): /* Sienna cichlid */
case IP_VERSION(13, 0, 0): case IP_VERSION(13, 0, 0):
case IP_VERSION(13, 0, 2): /* Aldebaran */
case IP_VERSION(13, 0, 10): case IP_VERSION(13, 0, 10):
return true; return true;
default: default:
return false; return false;
} }
}
return adev->asic_type == CHIP_VEGA20 ||
adev->asic_type == CHIP_ARCTURUS ||
adev->asic_type == CHIP_SIENNA_CICHLID ||
adev->asic_type == CHIP_ALDEBARAN;
}
static bool __get_eeprom_i2c_addr_arct(struct amdgpu_device *adev,
struct amdgpu_ras_eeprom_control *control)
{
struct atom_context *atom_ctx = adev->mode_info.atom_context;
if (!control || !atom_ctx)
return false;
if (strnstr(atom_ctx->vbios_version,
"D342",
sizeof(atom_ctx->vbios_version)))
control->i2c_address = EEPROM_I2C_MADDR_0;
else
control->i2c_address = EEPROM_I2C_MADDR_4;
return true;
}
static bool __get_eeprom_i2c_addr_ip_discovery(struct amdgpu_device *adev,
struct amdgpu_ras_eeprom_control *control)
{
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 0):
case IP_VERSION(13, 0, 10):
control->i2c_address = EEPROM_I2C_MADDR_4;
return true;
default:
return false;
}
} }
static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
...@@ -178,29 +143,32 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev, ...@@ -178,29 +143,32 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
return true; return true;
} }
switch (adev->asic_type) { switch (adev->ip_versions[MP1_HWIP][0]) {
case CHIP_VEGA20: case IP_VERSION(11, 0, 2):
/* VEGA20 and ARCTURUS */
if (adev->asic_type == CHIP_VEGA20)
control->i2c_address = EEPROM_I2C_MADDR_0;
else if (strnstr(atom_ctx->vbios_version,
"D342",
sizeof(atom_ctx->vbios_version)))
control->i2c_address = EEPROM_I2C_MADDR_0; control->i2c_address = EEPROM_I2C_MADDR_0;
else
control->i2c_address = EEPROM_I2C_MADDR_4;
return true; return true;
case IP_VERSION(11, 0, 7):
case CHIP_ARCTURUS:
return __get_eeprom_i2c_addr_arct(adev, control);
case CHIP_SIENNA_CICHLID:
control->i2c_address = EEPROM_I2C_MADDR_0; control->i2c_address = EEPROM_I2C_MADDR_0;
return true; return true;
case IP_VERSION(13, 0, 2):
case CHIP_ALDEBARAN:
if (strnstr(atom_ctx->vbios_version, "D673", if (strnstr(atom_ctx->vbios_version, "D673",
sizeof(atom_ctx->vbios_version))) sizeof(atom_ctx->vbios_version)))
control->i2c_address = EEPROM_I2C_MADDR_4; control->i2c_address = EEPROM_I2C_MADDR_4;
else else
control->i2c_address = EEPROM_I2C_MADDR_0; control->i2c_address = EEPROM_I2C_MADDR_0;
return true; return true;
case IP_VERSION(13, 0, 0):
case CHIP_IP_DISCOVERY: case IP_VERSION(13, 0, 10):
return __get_eeprom_i2c_addr_ip_discovery(adev, control); control->i2c_address = EEPROM_I2C_MADDR_4;
return true;
default: default:
return false; return false;
} }
......
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