Commit 675e979d authored by Fabio M. De Francesco's avatar Fabio M. De Francesco Committed by Dave Jiang

cxl/events: Use a common struct for DRAM and General Media events

cxl_event_common was an unfortunate naming choice and caused confusion with
the existing Common Event Record. Furthermore, its fields didn't map all
the common information between DRAM and General Media Events.

Remove cxl_event_common and introduce cxl_event_media_hdr to record common
information between DRAM and General Media events.

cxl_event_media_hdr, which is embedded in both cxl_event_gen_media and
cxl_event_dram, leverages the commonalities between the two events to
simplify their respective handling.
Suggested-by: default avatarDan Williams <dan.j.williams@intel.com>
Reviewed-by: default avatarAlison Schofield <alison.schofield@intel.com>
Reviewed-by: default avatarDan Williams <dan.j.williams@intel.com>
Reviewed-by: default avatarIra Weiny <ira.weiny@intel.com>
Signed-off-by: default avatarFabio M. De Francesco <fabio.m.de.francesco@linux.intel.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20240607144423.48681-1-fabio.m.de.francesco@linux.intel.comSigned-off-by: default avatarDave Jiang <dave.jiang@intel.com>
parent 22a40d14
...@@ -875,7 +875,7 @@ void cxl_event_trace_record(const struct cxl_memdev *cxlmd, ...@@ -875,7 +875,7 @@ void cxl_event_trace_record(const struct cxl_memdev *cxlmd,
guard(rwsem_read)(&cxl_region_rwsem); guard(rwsem_read)(&cxl_region_rwsem);
guard(rwsem_read)(&cxl_dpa_rwsem); guard(rwsem_read)(&cxl_dpa_rwsem);
dpa = le64_to_cpu(evt->common.phys_addr) & CXL_DPA_MASK; dpa = le64_to_cpu(evt->media_hdr.phys_addr) & CXL_DPA_MASK;
cxlr = cxl_dpa_to_region(cxlmd, dpa); cxlr = cxl_dpa_to_region(cxlmd, dpa);
if (cxlr) if (cxlr)
hpa = cxl_trace_hpa(cxlr, cxlmd, dpa); hpa = cxl_trace_hpa(cxlr, cxlmd, dpa);
......
...@@ -340,23 +340,23 @@ TRACE_EVENT(cxl_general_media, ...@@ -340,23 +340,23 @@ TRACE_EVENT(cxl_general_media,
), ),
TP_fast_assign( TP_fast_assign(
CXL_EVT_TP_fast_assign(cxlmd, log, rec->hdr); CXL_EVT_TP_fast_assign(cxlmd, log, rec->media_hdr.hdr);
__entry->hdr_uuid = CXL_EVENT_GEN_MEDIA_UUID; __entry->hdr_uuid = CXL_EVENT_GEN_MEDIA_UUID;
/* General Media */ /* General Media */
__entry->dpa = le64_to_cpu(rec->phys_addr); __entry->dpa = le64_to_cpu(rec->media_hdr.phys_addr);
__entry->dpa_flags = __entry->dpa & CXL_DPA_FLAGS_MASK; __entry->dpa_flags = __entry->dpa & CXL_DPA_FLAGS_MASK;
/* Mask after flags have been parsed */ /* Mask after flags have been parsed */
__entry->dpa &= CXL_DPA_MASK; __entry->dpa &= CXL_DPA_MASK;
__entry->descriptor = rec->descriptor; __entry->descriptor = rec->media_hdr.descriptor;
__entry->type = rec->type; __entry->type = rec->media_hdr.type;
__entry->transaction_type = rec->transaction_type; __entry->transaction_type = rec->media_hdr.transaction_type;
__entry->channel = rec->channel; __entry->channel = rec->media_hdr.channel;
__entry->rank = rec->rank; __entry->rank = rec->media_hdr.rank;
__entry->device = get_unaligned_le24(rec->device); __entry->device = get_unaligned_le24(rec->device);
memcpy(__entry->comp_id, &rec->component_id, memcpy(__entry->comp_id, &rec->component_id,
CXL_EVENT_GEN_MED_COMP_ID_SIZE); CXL_EVENT_GEN_MED_COMP_ID_SIZE);
__entry->validity_flags = get_unaligned_le16(&rec->validity_flags); __entry->validity_flags = get_unaligned_le16(&rec->media_hdr.validity_flags);
__entry->hpa = hpa; __entry->hpa = hpa;
if (cxlr) { if (cxlr) {
__assign_str(region_name); __assign_str(region_name);
...@@ -440,19 +440,19 @@ TRACE_EVENT(cxl_dram, ...@@ -440,19 +440,19 @@ TRACE_EVENT(cxl_dram,
), ),
TP_fast_assign( TP_fast_assign(
CXL_EVT_TP_fast_assign(cxlmd, log, rec->hdr); CXL_EVT_TP_fast_assign(cxlmd, log, rec->media_hdr.hdr);
__entry->hdr_uuid = CXL_EVENT_DRAM_UUID; __entry->hdr_uuid = CXL_EVENT_DRAM_UUID;
/* DRAM */ /* DRAM */
__entry->dpa = le64_to_cpu(rec->phys_addr); __entry->dpa = le64_to_cpu(rec->media_hdr.phys_addr);
__entry->dpa_flags = __entry->dpa & CXL_DPA_FLAGS_MASK; __entry->dpa_flags = __entry->dpa & CXL_DPA_FLAGS_MASK;
__entry->dpa &= CXL_DPA_MASK; __entry->dpa &= CXL_DPA_MASK;
__entry->descriptor = rec->descriptor; __entry->descriptor = rec->media_hdr.descriptor;
__entry->type = rec->type; __entry->type = rec->media_hdr.type;
__entry->transaction_type = rec->transaction_type; __entry->transaction_type = rec->media_hdr.transaction_type;
__entry->validity_flags = get_unaligned_le16(rec->validity_flags); __entry->validity_flags = get_unaligned_le16(rec->media_hdr.validity_flags);
__entry->channel = rec->channel; __entry->channel = rec->media_hdr.channel;
__entry->rank = rec->rank; __entry->rank = rec->media_hdr.rank;
__entry->nibble_mask = get_unaligned_le24(rec->nibble_mask); __entry->nibble_mask = get_unaligned_le24(rec->nibble_mask);
__entry->bank_group = rec->bank_group; __entry->bank_group = rec->bank_group;
__entry->bank = rec->bank; __entry->bank = rec->bank;
......
...@@ -21,6 +21,21 @@ struct cxl_event_record_hdr { ...@@ -21,6 +21,21 @@ struct cxl_event_record_hdr {
u8 reserved[15]; u8 reserved[15];
} __packed; } __packed;
struct cxl_event_media_hdr {
struct cxl_event_record_hdr hdr;
__le64 phys_addr;
u8 descriptor;
u8 type;
u8 transaction_type;
/*
* The meaning of Validity Flags from bit 2 is
* different across DRAM and General Media records
*/
u8 validity_flags[2];
u8 channel;
u8 rank;
} __packed;
#define CXL_EVENT_RECORD_DATA_LENGTH 0x50 #define CXL_EVENT_RECORD_DATA_LENGTH 0x50
struct cxl_event_generic { struct cxl_event_generic {
struct cxl_event_record_hdr hdr; struct cxl_event_record_hdr hdr;
...@@ -33,14 +48,7 @@ struct cxl_event_generic { ...@@ -33,14 +48,7 @@ struct cxl_event_generic {
*/ */
#define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10 #define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10
struct cxl_event_gen_media { struct cxl_event_gen_media {
struct cxl_event_record_hdr hdr; struct cxl_event_media_hdr media_hdr;
__le64 phys_addr;
u8 descriptor;
u8 type;
u8 transaction_type;
u8 validity_flags[2];
u8 channel;
u8 rank;
u8 device[3]; u8 device[3];
u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE]; u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
u8 reserved[46]; u8 reserved[46];
...@@ -52,14 +60,7 @@ struct cxl_event_gen_media { ...@@ -52,14 +60,7 @@ struct cxl_event_gen_media {
*/ */
#define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20 #define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20
struct cxl_event_dram { struct cxl_event_dram {
struct cxl_event_record_hdr hdr; struct cxl_event_media_hdr media_hdr;
__le64 phys_addr;
u8 descriptor;
u8 type;
u8 transaction_type;
u8 validity_flags[2];
u8 channel;
u8 rank;
u8 nibble_mask[3]; u8 nibble_mask[3];
u8 bank_group; u8 bank_group;
u8 bank; u8 bank;
...@@ -95,21 +96,13 @@ struct cxl_event_mem_module { ...@@ -95,21 +96,13 @@ struct cxl_event_mem_module {
u8 reserved[0x3d]; u8 reserved[0x3d];
} __packed; } __packed;
/*
* General Media or DRAM Event Common Fields
* - provides common access to phys_addr
*/
struct cxl_event_common {
struct cxl_event_record_hdr hdr;
__le64 phys_addr;
} __packed;
union cxl_event { union cxl_event {
struct cxl_event_generic generic; struct cxl_event_generic generic;
struct cxl_event_gen_media gen_media; struct cxl_event_gen_media gen_media;
struct cxl_event_dram dram; struct cxl_event_dram dram;
struct cxl_event_mem_module mem_module; struct cxl_event_mem_module mem_module;
struct cxl_event_common common; /* dram & gen_media event header */
struct cxl_event_media_hdr media_hdr;
} __packed; } __packed;
/* /*
......
...@@ -385,6 +385,7 @@ struct cxl_test_gen_media { ...@@ -385,6 +385,7 @@ struct cxl_test_gen_media {
struct cxl_test_gen_media gen_media = { struct cxl_test_gen_media gen_media = {
.id = CXL_EVENT_GEN_MEDIA_UUID, .id = CXL_EVENT_GEN_MEDIA_UUID,
.rec = { .rec = {
.media_hdr = {
.hdr = { .hdr = {
.length = sizeof(struct cxl_test_gen_media), .length = sizeof(struct cxl_test_gen_media),
.flags[0] = CXL_EVENT_RECORD_FLAG_PERMANENT, .flags[0] = CXL_EVENT_RECORD_FLAG_PERMANENT,
...@@ -397,7 +398,8 @@ struct cxl_test_gen_media gen_media = { ...@@ -397,7 +398,8 @@ struct cxl_test_gen_media gen_media = {
.transaction_type = CXL_GMER_TRANS_HOST_WRITE, .transaction_type = CXL_GMER_TRANS_HOST_WRITE,
/* .validity_flags = <set below> */ /* .validity_flags = <set below> */
.channel = 1, .channel = 1,
.rank = 30 .rank = 30,
},
}, },
}; };
...@@ -409,6 +411,7 @@ struct cxl_test_dram { ...@@ -409,6 +411,7 @@ struct cxl_test_dram {
struct cxl_test_dram dram = { struct cxl_test_dram dram = {
.id = CXL_EVENT_DRAM_UUID, .id = CXL_EVENT_DRAM_UUID,
.rec = { .rec = {
.media_hdr = {
.hdr = { .hdr = {
.length = sizeof(struct cxl_test_dram), .length = sizeof(struct cxl_test_dram),
.flags[0] = CXL_EVENT_RECORD_FLAG_PERF_DEGRADED, .flags[0] = CXL_EVENT_RECORD_FLAG_PERF_DEGRADED,
...@@ -421,6 +424,7 @@ struct cxl_test_dram dram = { ...@@ -421,6 +424,7 @@ struct cxl_test_dram dram = {
.transaction_type = CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB, .transaction_type = CXL_GMER_TRANS_INTERNAL_MEDIA_SCRUB,
/* .validity_flags = <set below> */ /* .validity_flags = <set below> */
.channel = 1, .channel = 1,
},
.bank_group = 5, .bank_group = 5,
.bank = 2, .bank = 2,
.column = {0xDE, 0xAD}, .column = {0xDE, 0xAD},
...@@ -474,11 +478,11 @@ static int mock_set_timestamp(struct cxl_dev_state *cxlds, ...@@ -474,11 +478,11 @@ static int mock_set_timestamp(struct cxl_dev_state *cxlds,
static void cxl_mock_add_event_logs(struct mock_event_store *mes) static void cxl_mock_add_event_logs(struct mock_event_store *mes)
{ {
put_unaligned_le16(CXL_GMER_VALID_CHANNEL | CXL_GMER_VALID_RANK, put_unaligned_le16(CXL_GMER_VALID_CHANNEL | CXL_GMER_VALID_RANK,
&gen_media.rec.validity_flags); &gen_media.rec.media_hdr.validity_flags);
put_unaligned_le16(CXL_DER_VALID_CHANNEL | CXL_DER_VALID_BANK_GROUP | put_unaligned_le16(CXL_DER_VALID_CHANNEL | CXL_DER_VALID_BANK_GROUP |
CXL_DER_VALID_BANK | CXL_DER_VALID_COLUMN, CXL_DER_VALID_BANK | CXL_DER_VALID_COLUMN,
&dram.rec.validity_flags); &dram.rec.media_hdr.validity_flags);
mes_add_event(mes, CXL_EVENT_TYPE_INFO, &maint_needed); mes_add_event(mes, CXL_EVENT_TYPE_INFO, &maint_needed);
mes_add_event(mes, CXL_EVENT_TYPE_INFO, mes_add_event(mes, CXL_EVENT_TYPE_INFO,
......
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