Merge tiger.hpl.hp.com:/data1/bk/vanilla/linux-2.5

into tiger.hpl.hp.com:/data1/bk/lia64/to-linus-2.5

arch/ia64/hp/sim/boot/boot_head.S

@@ -105,37 +105,37 @@ static:	cmp.eq p6,p7=6,r28		/* PAL_PTCE_INFO */
 1:	cmp.eq p6,p7=15,r28		/* PAL_PERF_MON_INFO */
 (p7)	br.cond.sptk.few 1f
 	mov r8=0			/* status = 0 */
-	movl r9 =0x12082004		/* generic=4 width=32 retired=8 cycles=18 */
+	movl r9 =0x08122f04		/* generic=4 width=47 retired=8 cycles=18 */
 	mov r10=0			/* reserved */
 	mov r11=0			/* reserved */
 	mov r16=0xffff			/* implemented PMC */
-	mov r17=0xffff			/* implemented PMD */
+	mov r17=0x3ffff			/* implemented PMD */
 	add r18=8,r29			/* second index */
 	;;
 	st8 [r29]=r16,16		/* store implemented PMC */
 	st8 [r18]=r0,16			/* clear remaining bits  */
 	;;
-	st8 [r29]=r0,16			/* store implemented PMC */
+	st8 [r29]=r0,16			/* clear remaining bits  */
 	st8 [r18]=r0,16			/* clear remaining bits  */
 	;;
 	st8 [r29]=r17,16		/* store implemented PMD */
 	st8 [r18]=r0,16			/* clear remaining bits  */
 	mov r16=0xf0			/* cycles count capable PMC */
 	;;
-	st8 [r29]=r0,16			/* store implemented PMC */
+	st8 [r29]=r0,16			/* clear remaining bits  */
 	st8 [r18]=r0,16			/* clear remaining bits  */
-	mov r17=0x10			/* retired bundles capable PMC */
+	mov r17=0xf0			/* retired bundles capable PMC */
 	;;
 	st8 [r29]=r16,16		/* store cycles capable */
 	st8 [r18]=r0,16			/* clear remaining bits  */
 	;;
-	st8 [r29]=r0,16			/* store implemented PMC */
+	st8 [r29]=r0,16			/* clear remaining bits  */
 	st8 [r18]=r0,16			/* clear remaining bits  */
 	;;
 	st8 [r29]=r17,16		/* store retired bundle capable */
 	st8 [r18]=r0,16			/* clear remaining bits  */
 	;;
-	st8 [r29]=r0,16			/* store implemented PMC */
+	st8 [r29]=r0,16			/* clear remaining bits  */
 	st8 [r18]=r0,16			/* clear remaining bits  */
 	;;
 1:	br.cond.sptk.few rp

arch/ia64/kernel/efi.c

@@ -39,7 +39,7 @@ extern efi_status_t efi_call_phys (void *, ...);
 struct efi efi;
 EXPORT_SYMBOL(efi);
 static efi_runtime_services_t *runtime;
-static unsigned long mem_limit = ~0UL;
+static unsigned long mem_limit = ~0UL, max_addr = ~0UL;
 
 #define efi_call_virt(f, args...)	(*(f))(args)
 
@@ -290,6 +290,7 @@ efi_memmap_walk (efi_freemem_callback_t callback, void *arg)
 	void *efi_map_start, *efi_map_end, *p, *q;
 	efi_memory_desc_t *md, *check_md;
 	u64 efi_desc_size, start, end, granule_addr, last_granule_addr, first_non_wb_addr = 0;
+	unsigned long total_mem = 0;
 
 	efi_map_start = __va(ia64_boot_param->efi_memmap);
 	efi_map_end   = efi_map_start + ia64_boot_param->efi_memmap_size;
@@ -331,12 +332,18 @@ efi_memmap_walk (efi_freemem_callback_t callback, void *arg)
 			trim_top(md, last_granule_addr);
 
 		if (is_available_memory(md)) {
-			if (md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT) > mem_limit) {
-				if (md->phys_addr > mem_limit)
+			if (md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT) > max_addr) {
+				if (md->phys_addr > max_addr)
 					continue;
-				md->num_pages = (mem_limit - md->phys_addr) >> EFI_PAGE_SHIFT;
+				md->num_pages = (max_addr - md->phys_addr) >> EFI_PAGE_SHIFT;
 			}
 
+			if (total_mem >= mem_limit)
+				continue;
+			total_mem += (md->num_pages << EFI_PAGE_SHIFT);
+			if (total_mem > mem_limit)
+				md->num_pages -= ((total_mem - mem_limit) >> EFI_PAGE_SHIFT);
+
 			if (md->num_pages == 0)
 				continue;
 
@@ -470,7 +477,13 @@ efi_init (void)
 	for (cp = saved_command_line; *cp; ) {
 		if (memcmp(cp, "mem=", 4) == 0) {
 			cp += 4;
-			mem_limit = memparse(cp, &end) - 1;
+			mem_limit = memparse(cp, &end) - 2;
+			if (end != cp)
+				break;
+			cp = end;
+		} else if (memcmp(cp, "max_addr=", 9) == 0) {
+			cp += 9;
+			max_addr = memparse(cp, &end) - 1;
 			if (end != cp)
 				break;
 			cp = end;
@@ -481,8 +494,8 @@ efi_init (void)
 				++cp;
 		}
 	}
-	if (mem_limit != ~0UL)
-		printk(KERN_INFO "Ignoring memory above %luMB\n", mem_limit >> 20);
+	if (max_addr != ~0UL)
+		printk(KERN_INFO "Ignoring memory above %luMB\n", max_addr >> 20);
 
 	efi.systab = __va(ia64_boot_param->efi_systab);
 

arch/ia64/kernel/fsys.S

@@ -574,6 +574,10 @@ GLOBAL_ENTRY(fsys_bubble_down)
 	or r29=r8,r29			// construct cr.ipsr value to save
 	addl r22=IA64_RBS_OFFSET,r2	// compute base of RBS
 	;;
+	// GAS reports a spurious RAW hazard on the read of ar.rnat because it thinks
+	// we may be reading ar.itc after writing to psr.l.  Avoid that message with
+	// this directive:
+	dv_serialize_data
 	mov.m r24=ar.rnat		// read ar.rnat (5 cyc lat)
 	lfetch.fault.excl.nt1 [r22]
 	adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r2

arch/ia64/kernel/head.S

@@ -818,7 +818,8 @@ END(ia64_delay_loop)
 
 GLOBAL_ENTRY(start_kernel_thread)
 	.prologue
-	.save rp, r0				// this is the end of the call-chain
+	.save rp, r4				// this is the end of the call-chain
+	mov r4=r0
 	.body
 	alloc r2 = ar.pfs, 0, 0, 2, 0
 	mov out0 = r9

arch/ia64/kernel/ivt.S

@@ -181,6 +181,12 @@ ENTRY(vhpt_miss)
 (p7)	itc.d r24
 	;;
 #ifdef CONFIG_SMP
+	/*
+	 * Tell the assemblers dependency-violation checker that the above "itc" instructions
+	 * cannot possibly affect the following loads:
+	 */
+	dv_serialize_data
+
 	/*
 	 * Re-check L2 and L3 pagetable.  If they changed, we may have received a ptc.g
 	 * between reading the pagetable and the "itc".  If so, flush the entry we
@@ -229,6 +235,12 @@ ENTRY(itlb_miss)
 	itc.i r18
 	;;
 #ifdef CONFIG_SMP
+	/*
+	 * Tell the assemblers dependency-violation checker that the above "itc" instructions
+	 * cannot possibly affect the following loads:
+	 */
+	dv_serialize_data
+
 	ld8 r19=[r17]				// read L3 PTE again and see if same
 	mov r20=PAGE_SHIFT<<2			// setup page size for purge
 	;;
@@ -267,6 +279,12 @@ dtlb_fault:
 	itc.d r18
 	;;
 #ifdef CONFIG_SMP
+	/*
+	 * Tell the assemblers dependency-violation checker that the above "itc" instructions
+	 * cannot possibly affect the following loads:
+	 */
+	dv_serialize_data
+
 	ld8 r19=[r17]				// read L3 PTE again and see if same
 	mov r20=PAGE_SHIFT<<2			// setup page size for purge
 	;;
@@ -504,6 +522,12 @@ ENTRY(dirty_bit)
 	;;
 (p6)	itc.d r25				// install updated PTE
 	;;
+	/*
+	 * Tell the assemblers dependency-violation checker that the above "itc" instructions
+	 * cannot possibly affect the following loads:
+	 */
+	dv_serialize_data
+
 	ld8 r18=[r17]				// read PTE again
 	;;
 	cmp.eq p6,p7=r18,r25			// is it same as the newly installed
@@ -563,6 +587,12 @@ ENTRY(iaccess_bit)
 	;;
 (p6)	itc.i r25				// install updated PTE
 	;;
+	/*
+	 * Tell the assemblers dependency-violation checker that the above "itc" instructions
+	 * cannot possibly affect the following loads:
+	 */
+	dv_serialize_data
+
 	ld8 r18=[r17]				// read PTE again
 	;;
 	cmp.eq p6,p7=r18,r25			// is it same as the newly installed
@@ -610,6 +640,11 @@ ENTRY(daccess_bit)
 	cmp.eq p6,p7=r26,r18
 	;;
 (p6)	itc.d r25				// install updated PTE
+	/*
+	 * Tell the assemblers dependency-violation checker that the above "itc" instructions
+	 * cannot possibly affect the following loads:
+	 */
+	dv_serialize_data
 	;;
 	ld8 r18=[r17]				// read PTE again
 	;;

arch/ia64/kernel/perfmon_generic.h

@@ -6,13 +6,6 @@
  *               Stephane Eranian <eranian@hpl.hp.com>
  */
 
-
-#define RDEP(x)	(1UL<<(x))
-
-#if defined(CONFIG_ITANIUM) || defined (CONFIG_MCKINLEY)
-#error "This file should not be used when CONFIG_ITANIUM or CONFIG_MCKINLEY is defined"
-#endif
-
 static pfm_reg_desc_t pfm_gen_pmc_desc[PMU_MAX_PMCS]={
 /* pmc0  */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
 /* pmc1  */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
@@ -40,10 +33,9 @@ static pfm_reg_desc_t pfm_gen_pmd_desc[PMU_MAX_PMDS]={
 /*
  * impl_pmcs, impl_pmds are computed at runtime to minimize errors!
  */
-static pmu_config_t pmu_conf={
+static pmu_config_t pmu_conf_gen={
 	.pmu_name   = "Generic",
 	.pmu_family = 0xff, /* any */
-	.enabled    = 0,
 	.ovfl_val   = (1UL << 32) - 1,
 	.num_ibrs   = 0, /* does not use */
 	.num_dbrs   = 0, /* does not use */

arch/ia64/kernel/perfmon_hpsim.h

-/*
- * This file contains the HP SKI Simulator PMU register description tables
- * and pmc checkers used by perfmon.c.
- *
- * Copyright (C) 2002-2003  Hewlett Packard Co
- *               Stephane Eranian <eranian@hpl.hp.com>
- *
- * File mostly contributed by Ian Wienand <ianw@gelato.unsw.edu.au>
- *
- * This file is included as a dummy template so the kernel does not
- * try to initalize registers the simulator can't handle.
- *
- * Note the simulator does not (currently) implement these registers, i.e.,
- * they do not count anything. But you can read/write them.
- */
-
-#define RDEP(x)	(1UL<<(x))
-
-#ifndef CONFIG_IA64_HP_SIM
-#error "This file should only be included for the HP Simulator"
-#endif
-
-static pfm_reg_desc_t pfm_hpsim_pmc_desc[PMU_MAX_PMCS]={
-/* pmc0  */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL, 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
-/* pmc1  */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL, 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
-/* pmc2  */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL, 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
-/* pmc3  */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL, 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
-/* pmc4  */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(4), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
-/* pmc5  */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(5), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
-/* pmc6  */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(6), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
-/* pmc7  */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(7), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
-/* pmc8  */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
-/* pmc9  */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(9), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
-/* pmc10 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(10), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
-/* pmc11 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(11), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
-/* pmc12 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(12), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
-/* pmc13 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(13), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
-/* pmc14 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(14), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
-/* pmc15 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {RDEP(15), 0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
-	    { PFM_REG_END     , 0, 0x0UL, -1UL, NULL, NULL, {0,}, {0,}}, /* end marker */
-};
-
-static pfm_reg_desc_t pfm_hpsim_pmd_desc[PMU_MAX_PMDS]={
-/* pmd0  */ { PFM_REG_BUFFER, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
-/* pmd1  */ { PFM_REG_BUFFER, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
-/* pmd2  */ { PFM_REG_BUFFER, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
-/* pmd3  */ { PFM_REG_BUFFER, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
-/* pmd4  */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(4),0UL, 0UL, 0UL}},
-/* pmd5  */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(5),0UL, 0UL, 0UL}},
-/* pmd6  */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(6),0UL, 0UL, 0UL}},
-/* pmd7  */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(7),0UL, 0UL, 0UL}},
-/* pmd8  */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(8),0UL, 0UL, 0UL}},
-/* pmd9  */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(9),0UL, 0UL, 0UL}},
-/* pmd10 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(10),0UL, 0UL, 0UL}},
-/* pmd11 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(11),0UL, 0UL, 0UL}},
-/* pmd12 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
-/* pmd13 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(13),0UL, 0UL, 0UL}},
-/* pmd14 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(14),0UL, 0UL, 0UL}},
-/* pmd15 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(15),0UL, 0UL, 0UL}},
-	    { PFM_REG_END     , 0, 0x0UL, -1UL, NULL, NULL, {0,}, {0,}}, /* end marker */
-};
-
-/*
- * impl_pmcs, impl_pmds are computed at runtime to minimize errors!
- */
-static pmu_config_t pmu_conf={
-	.pmu_name   = "hpsim",
-	.pmu_family = 0x7, /* ski emulator reports as Itanium */
-	.enabled    = 0,
-	.ovfl_val   = (1UL << 32) - 1,
-	.num_ibrs   = 0, /* does not use */
-	.num_dbrs   = 0, /* does not use */
-	.pmd_desc   = pfm_hpsim_pmd_desc,
-	.pmc_desc   = pfm_hpsim_pmc_desc
-};

arch/ia64/kernel/perfmon_itanium.h

@@ -5,15 +5,7 @@
  * Copyright (C) 2002-2003  Hewlett Packard Co
  *               Stephane Eranian <eranian@hpl.hp.com>
  */
-
-#define RDEP(x)	(1UL<<(x))
-
-#ifndef CONFIG_ITANIUM
-#error "This file is only valid when CONFIG_ITANIUM is defined"
-#endif
-
 static int pfm_ita_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs);
-static int pfm_write_ibr_dbr(int mode, pfm_context_t *ctx, void *arg, int count, struct pt_regs *regs);
 
 static pfm_reg_desc_t pfm_ita_pmc_desc[PMU_MAX_PMCS]={
 /* pmc0  */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
@@ -55,31 +47,22 @@ static pfm_reg_desc_t pfm_ita_pmd_desc[PMU_MAX_PMDS]={
 	    { PFM_REG_END     , 0, 0UL, -1UL, NULL, NULL, {0,}, {0,}}, /* end marker */
 };
 
-/*
- * impl_pmcs, impl_pmds are computed at runtime to minimize errors!
- */
-static pmu_config_t pmu_conf={
-	.pmu_name      = "Itanium",
-	.pmu_family    = 0x7,
-	.enabled       = 0,
-	.ovfl_val      = (1UL << 32) - 1,
-	.pmd_desc      = pfm_ita_pmd_desc,
-	.pmc_desc      = pfm_ita_pmc_desc,
-	.num_ibrs      = 8,
-	.num_dbrs      = 8,
-	.use_rr_dbregs = 1 /* debug register are use for range retrictions */
-};
-
 static int
 pfm_ita_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs)
 {
 	int ret;
+	int is_loaded;
+
+	/* sanitfy check */
+	if (ctx == NULL) return -EINVAL;
+
+	is_loaded = ctx->ctx_state == PFM_CTX_LOADED || ctx->ctx_state == PFM_CTX_MASKED;
 
 	/*
 	 * we must clear the (instruction) debug registers if pmc13.ta bit is cleared
 	 * before they are written (fl_using_dbreg==0) to avoid picking up stale information.
 	 */
-	if (cnum == 13 && ((*val & 0x1) == 0UL) && ctx->ctx_fl_using_dbreg == 0) {
+	if (cnum == 13 && is_loaded && ((*val & 0x1) == 0UL) && ctx->ctx_fl_using_dbreg == 0) {
 
 		DPRINT(("pmc[%d]=0x%lx has active pmc13.ta cleared, clearing ibr\n", cnum, *val));
 
@@ -98,7 +81,7 @@ pfm_ita_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnu
 	 * we must clear the (data) debug registers if pmc11.pt bit is cleared
 	 * before they are written (fl_using_dbreg==0) to avoid picking up stale information.
 	 */
-	if (cnum == 11 && ((*val >> 28)& 0x1) == 0 && ctx->ctx_fl_using_dbreg == 0) {
+	if (cnum == 11 && is_loaded && ((*val >> 28)& 0x1) == 0 && ctx->ctx_fl_using_dbreg == 0) {
 
 		DPRINT(("pmc[%d]=0x%lx has active pmc11.pt cleared, clearing dbr\n", cnum, *val));
 
@@ -115,3 +98,18 @@ pfm_ita_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnu
 	return 0;
 }
 
+/*
+ * impl_pmcs, impl_pmds are computed at runtime to minimize errors!
+ */
+static pmu_config_t pmu_conf_ita={
+	.pmu_name      = "Itanium",
+	.pmu_family    = 0x7,
+	.ovfl_val      = (1UL << 32) - 1,
+	.pmd_desc      = pfm_ita_pmd_desc,
+	.pmc_desc      = pfm_ita_pmc_desc,
+	.num_ibrs      = 8,
+	.num_dbrs      = 8,
+	.use_rr_dbregs = 1, /* debug register are use for range retrictions */
+};
+
+

arch/ia64/kernel/perfmon_mckinley.h

@@ -5,15 +5,7 @@
  * Copyright (C) 2002-2003  Hewlett Packard Co
  *               Stephane Eranian <eranian@hpl.hp.com>
  */
-
-#define RDEP(x)	(1UL<<(x))
-
-#ifndef CONFIG_MCKINLEY
-#error "This file is only valid when CONFIG_MCKINLEY is defined"
-#endif
-
 static int pfm_mck_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs);
-static int pfm_write_ibr_dbr(int mode, pfm_context_t *ctx, void *arg, int count, struct pt_regs *regs);
 
 static pfm_reg_desc_t pfm_mck_pmc_desc[PMU_MAX_PMCS]={
 /* pmc0  */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
@@ -57,21 +49,6 @@ static pfm_reg_desc_t pfm_mck_pmd_desc[PMU_MAX_PMDS]={
 	    { PFM_REG_END     , 0, 0x0UL, -1UL, NULL, NULL, {0,}, {0,}}, /* end marker */
 };
 
-/*
- * impl_pmcs, impl_pmds are computed at runtime to minimize errors!
- */
-static pmu_config_t pmu_conf={
-	.pmu_name      = "Itanium 2",
-	.pmu_family    = 0x1f,
-	.enabled       = 0,
-	.ovfl_val      = (1UL << 47) - 1,
-	.pmd_desc      = pfm_mck_pmd_desc,
-	.pmc_desc      = pfm_mck_pmc_desc,
-	.num_ibrs       = 8,
-	.num_dbrs       = 8,
-	.use_rr_dbregs = 1 /* debug register are use for range retrictions */
-};
-
 /*
  * PMC reserved fields must have their power-up values preserved
  */
@@ -120,12 +97,11 @@ pfm_mck_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnu
 	 * 	one of the pmc13.cfg_dbrpXX field is different from 0x3
 	 * AND
 	 * 	at the corresponding pmc13.ena_dbrpXX is set.
-	 *
-	 * For now, we just check on cfg_dbrXX != 0x3.
 	 */
 	DPRINT(("cnum=%u val=0x%lx, using_dbreg=%d loaded=%d\n", cnum, *val, ctx->ctx_fl_using_dbreg, is_loaded));
 
-	if (cnum == 13 && is_loaded && ((*val & 0x18181818UL) != 0x18181818UL) && ctx->ctx_fl_using_dbreg == 0) {
+	if (cnum == 13 && is_loaded
+	    && (*val & 0x1e00000000000UL) && (*val & 0x18181818UL) != 0x18181818UL && ctx->ctx_fl_using_dbreg == 0) {
 
 		DPRINT(("pmc[%d]=0x%lx has active pmc13 settings, clearing dbr\n", cnum, *val));
 
@@ -192,3 +168,20 @@ pfm_mck_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnu
 
 	return ret ? -EINVAL : 0;
 }
+
+/*
+ * impl_pmcs, impl_pmds are computed at runtime to minimize errors!
+ */
+static pmu_config_t pmu_conf_mck={
+	.pmu_name      = "Itanium 2",
+	.pmu_family    = 0x1f,
+	.flags	       = PFM_PMU_IRQ_RESEND,
+	.ovfl_val      = (1UL << 47) - 1,
+	.pmd_desc      = pfm_mck_pmd_desc,
+	.pmc_desc      = pfm_mck_pmc_desc,
+	.num_ibrs       = 8,
+	.num_dbrs       = 8,
+	.use_rr_dbregs = 1 /* debug register are use for range retrictions */
+};
+
+

arch/ia64/kernel/smp.c

@@ -28,7 +28,6 @@
 #include <linux/mm.h>
 #include <linux/cache.h>
 #include <linux/delay.h>
-#include <linux/cache.h>
 #include <linux/efi.h>
 
 #include <asm/atomic.h>

arch/ia64/kernel/smpboot.c

@@ -293,11 +293,6 @@ smp_callin (void)
 	 */
 	ia64_init_itm();
 
-	/*
-	 * Set I/O port base per CPU
-	 */
-	ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
-
 	ia64_mca_cmc_vector_setup();	/* Setup vector on AP & enable */
 
 #ifdef CONFIG_PERFMON
@@ -338,6 +333,9 @@ start_secondary (void *unused)
 {
 	extern int cpu_idle (void);
 
+	/* Early console may use I/O ports */
+	ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
+
 	Dprintk("start_secondary: starting CPU 0x%x\n", hard_smp_processor_id());
 	efi_map_pal_code();
 	cpu_init();

arch/ia64/mm/init.c

@@ -343,6 +343,7 @@ ia64_mmu_init (void *my_cpu_data)
 
 #ifdef	CONFIG_HUGETLB_PAGE
 	ia64_set_rr(HPAGE_REGION_BASE, HPAGE_SHIFT << 2);
+	ia64_srlz_d();
 #endif
 
 	cpu = smp_processor_id();

arch/ia64/scripts/check-serialize.S

+	.serialize.data
+	.serialize.instruction

arch/ia64/scripts/toolchain-flags

@@ -40,4 +40,14 @@ then
     CPPFLAGS="$CPPFLAGS -DHAVE_MODEL_SMALL_ATTRIBUTE"
 fi
 rm -f $out
+
+# Check whether assembler supports .serialize.{data,instruction} directive.
+
+$CC -c $dir/check-serialize.S -o $out 2>/dev/null
+res=$?
+rm -f $out
+if [ $res -eq 0 ]; then
+    CPPFLAGS="$CPPFLAGS -DHAVE_SERIALIZE_DIRECTIVE"
+fi
+
 echo $CPPFLAGS

arch/ia64/sn/io/sn2/ml_SN_intr.c

@@ -36,6 +36,25 @@ extern irqpda_t	*irqpdaindr;
 extern cnodeid_t master_node_get(vertex_hdl_t vhdl);
 extern nasid_t master_nasid;
 
+cpuid_t
+sn_get_node_first_cpu(cnodeid_t cnode) {
+	int cpuid = -1, slice;
+
+	for (slice = CPUS_PER_NODE - 1; slice >= 0; slice--) {
+		cpuid = cnode_slice_to_cpuid(cnode, slice);
+		if (cpuid == NR_CPUS)
+			continue;
+		if (!cpu_online(cpuid))
+			continue;
+		break;
+	}
+	if (slice < 0) {
+		return CPU_NONE;
+	}
+	return cpuid;
+}
+
+
 /*  Initialize some shub registers for interrupts, both IO and error. */
 void intr_init_vecblk(cnodeid_t node)
 {
@@ -43,7 +62,6 @@ void intr_init_vecblk(cnodeid_t node)
 	sh_ii_int0_config_u_t		ii_int_config;
 	cpuid_t				cpu;
 	cpuid_t				cpu0, cpu1;
-	nodepda_t			*lnodepda;
 	sh_ii_int0_enable_u_t		ii_int_enable;
 	sh_int_node_id_config_u_t	node_id_config;
 	sh_local_int5_config_u_t	local5_config;
@@ -60,15 +78,13 @@ void intr_init_vecblk(cnodeid_t node)
 		HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_INT_NODE_ID_CONFIG),
 			node_id_config.sh_int_node_id_config_regval);
 		cnode = nasid_to_cnodeid(master_nasid);
-		lnodepda = NODEPDA(cnode);
-		cpu = lnodepda->node_first_cpu;
+		cpu = sn_get_node_first_cpu(cnode);
 		cpu = cpu_physical_id(cpu);
 		SAL_CALL(ret_stuff, SN_SAL_REGISTER_CE, nasid, cpu, master_nasid,0,0,0,0);
 		if (ret_stuff.status < 0)
 			printk("%s: SN_SAL_REGISTER_CE SAL_CALL failed\n",__FUNCTION__);
 	} else {
-		lnodepda = NODEPDA(node);
-		cpu = lnodepda->node_first_cpu;
+		cpu = sn_get_node_first_cpu(node);
 		cpu = cpu_physical_id(cpu);
 	}
 

arch/ia64/sn/kernel/setup.c

@@ -451,10 +451,6 @@ sn_cpu_init(void)
 	}
 	pda->shub_1_1_found = shub_1_1_found;
 	
-	if (local_node_data->active_cpu_count == 1)
-		nodepda->node_first_cpu = cpuid;
-
-
 
 	/*
 	 * We must use different memory allocators for first cpu (bootmem 
@@ -474,7 +470,7 @@ sn_cpu_init(void)
 	pda->mem_write_status_addr = (volatile u64 *)
 			LOCAL_MMR_ADDR((slice < 2 ? SH_MEMORY_WRITE_STATUS_0 : SH_MEMORY_WRITE_STATUS_1 ) );
 
-	if (nodepda->node_first_cpu == cpuid) {
+	if (local_node_data->active_cpu_count++ == 0) {
 		int	buddy_nasid;
 		buddy_nasid = cnodeid_to_nasid(numa_node_id() == numnodes-1 ? 0 : numa_node_id()+ 1);
 		pda->pio_shub_war_cam_addr = (volatile unsigned long*)GLOBAL_MMR_ADDR(nasid, SH_PI_CAM_CONTROL);

arch/ia64/sn/kernel/sn2/prominfo_proc.c

@@ -228,11 +228,9 @@ read_version_entry(char *page, char **start, off_t off, int count, int *eof,
 {
 	int len = 0;
 
-	MOD_INC_USE_COUNT;
 	/* data holds the pointer to this node's FIT */
 	len = dump_version(page, (unsigned long *)data);
 	len = proc_calc_metrics(page, start, off, count, eof, len);
-	MOD_DEC_USE_COUNT;
 	return len;
 }
 
@@ -242,11 +240,9 @@ read_fit_entry(char *page, char **start, off_t off, int count, int *eof,
 {
 	int len = 0;
 
-	MOD_INC_USE_COUNT;
 	/* data holds the pointer to this node's FIT */
 	len = dump_fit(page, (unsigned long *)data);
 	len = proc_calc_metrics(page, start, off, count, eof, len);
-	MOD_DEC_USE_COUNT;
 
 	return len;
 }
@@ -310,6 +306,7 @@ int __init
 prominfo_init(void)
 {
 	struct proc_dir_entry **entp;
+	struct proc_dir_entry *p;
 	cnodeid_t cnodeid;
 	nasid_t nasid;
 	char name[NODE_NAME_LEN];
@@ -333,12 +330,16 @@ prominfo_init(void)
 		sprintf(name, "node%d", cnodeid);
 		*entp = proc_mkdir(name, sgi_prominfo_entry);
 		nasid = cnodeid_to_nasid(cnodeid);
-		create_proc_read_entry(
+		p = create_proc_read_entry(
 			"fit", 0, *entp, read_fit_entry,
 			lookup_fit(nasid));
-		create_proc_read_entry(
+		if (p)
+			p->owner = THIS_MODULE;
+		p = create_proc_read_entry(
 			"version", 0, *entp, read_version_entry,
 			lookup_fit(nasid));
+		if (p)
+			p->owner = THIS_MODULE;
 	}
 
 	return 0;

drivers/char/sn_serial.c

@@ -500,9 +500,10 @@ sn_sal_connect_interrupt(void)
 	nasid_t console_nasid;
 	unsigned int console_irq;
 	int result;
+	extern cpuid_t sn_get_node_first_cpu(cnodeid_t cnode);
 
 	console_nasid = ia64_sn_get_console_nasid();
-	intr_cpuid = NODEPDA(NASID_TO_COMPACT_NODEID(console_nasid))->node_first_cpu;
+	intr_cpuid = sn_get_node_first_cpu(NASID_TO_COMPACT_NODEID(console_nasid));
 	intr_cpuloc = cpu_physical_id(intr_cpuid);
 	console_irq = CPU_VECTOR_TO_IRQ(intr_cpuloc, SGI_UART_VECTOR);
 

include/asm-ia64/asmmacro.h

@@ -100,4 +100,12 @@
 # define TEXT_ALIGN(n)
 #endif
 
+#ifdef HAVE_SERIALIZE_DIRECTIVE
+# define dv_serialize_data		.serialize.data
+# define dv_serialize_instruction	.serialize.instruction
+#else
+# define dv_serialize_data
+# define dv_serialize_instruction
+#endif
+
 #endif /* _ASM_IA64_ASMMACRO_H */

include/asm-ia64/gcc_intrin.h

@@ -377,9 +377,16 @@ register unsigned long ia64_r13 asm ("r13");
 })
 
 #define ia64_srlz_i()	asm volatile (";; srlz.i ;;" ::: "memory")
-
 #define ia64_srlz_d()	asm volatile (";; srlz.d" ::: "memory");
 
+#ifdef HAVE_SERIALIZE_DIRECTIVE
+# define ia64_dv_serialize_data()		asm volatile (".serialize.data");
+# define ia64_dv_serialize_instruction()	asm volatile (".serialize.instruction");
+#else
+# define ia64_dv_serialize_data()
+# define ia64_dv_serialize_instruction()
+#endif
+
 #define ia64_nop(x)	asm volatile ("nop %0"::"i"(x));
 
 #define ia64_itci(addr)	asm volatile ("itc.i %0;;" :: "r"(addr) : "memory")

include/asm-ia64/intel_intrin.h

@@ -204,6 +204,9 @@ __s64 _m64_popcnt(__s64 a);
 #define ia64_srlz_d		__dsrlz
 #define ia64_srlz_i		__isrlz
 
+#define ia64_dv_serialize_data()
+#define ia64_dv_serialize_instruction()
+
 #define ia64_st1_rel		__st1_rel
 #define ia64_st2_rel		__st2_rel
 #define ia64_st4_rel		__st4_rel

include/asm-ia64/sn/arch.h

@@ -20,7 +20,7 @@ typedef u64	hubreg_t;
 typedef u64	mmr_t;
 typedef u64	nic_t;
 
-#define CNODE_TO_CPU_BASE(_cnode)	(NODEPDA(_cnode)->node_first_cpu)
+#define CNODE_TO_CPU_BASE(_cnode)	(sn_get_node_first_cpu(_cnode))
 
 #define NASID_TO_COMPACT_NODEID(nasid)  (nasid_to_cnodeid(nasid))
 #define COMPACT_TO_NASID_NODEID(cnode)  (cnodeid_to_nasid(cnode))

include/asm-ia64/sn/nodepda.h

@@ -36,13 +36,6 @@
 
 
 struct nodepda_s {
-
-
-	cpuid_t         node_first_cpu; /* Starting cpu number for node */
-					/* WARNING: no guarantee that   */
-					/*  the second cpu on a node is */
-					/*  node_first_cpu+1.           */
-
 	vertex_hdl_t 	xbow_vhdl;
 	nasid_t		xbow_peer;	/* NASID of our peer hub on xbow */
 	struct semaphore xbow_sema;	/* Sema for xbow synchronization */

include/asm-ia64/system.h

@@ -114,10 +114,16 @@ extern struct ia64_boot_param {
  */
 /* For spinlocks etc */
 
-/* clearing psr.i is implicitly serialized (visible by next insn) */
-/* setting psr.i requires data serialization */
+/*
+ * - clearing psr.i is implicitly serialized (visible by next insn)
+ * - setting psr.i requires data serialization
+ * - we need a stop-bit before reading PSR because we sometimes
+ *   write a floating-point register right before reading the PSR
+ *   and that writes to PSR.mfl
+ */
 #define __local_irq_save(x)			\
 do {						\
+	ia64_stop();				\
 	(x) = ia64_getreg(_IA64_REG_PSR);	\
 	ia64_stop();				\
 	ia64_rsm(IA64_PSR_I);			\
@@ -166,7 +172,7 @@ do {								\
 #endif /* !CONFIG_IA64_DEBUG_IRQ */
 
 #define local_irq_enable()	({ ia64_ssm(IA64_PSR_I); ia64_srlz_d(); })
-#define local_save_flags(flags)	((flags) = ia64_getreg(_IA64_REG_PSR))
+#define local_save_flags(flags)	({ ia64_stop(); (flags) = ia64_getreg(_IA64_REG_PSR); })
 
 #define irqs_disabled()				\
 ({						\