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Commit 6a55e5aa authored by David Mosberger's avatar David Mosberger
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Merge tiger.hpl.hp.com:/data1/bk/vanilla/linux-2.5 

into tiger.hpl.hp.com:/data1/bk/lia64/to-linus-2.5
parents 498b9cb8 15a0c0ef
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Showing with 362 additions and 386 deletions
arch/ia64/kernel/entry.S
View file @ 6a55e5aa
......@@ -701,7 +701,7 @@ GLOBAL_ENTRY(ia64_leave_kernel)
* NOTE: alloc, loadrs, and cover can't be predicated.
*/
(pNonSys) br.cond.dpnt dont_preserve_current_frame
cover // add current frame into dirty partition
cover // add current frame into dirty partition and set cr.ifs
;;
mov r19=ar.bsp // get new backing store pointer
sub r16=r16,r18 // krbs = old bsp - size of dirty partition
......@@ -727,7 +727,7 @@ dont_preserve_current_frame:
# define Nregs 14
#endif
alloc loc0=ar.pfs,2,Nregs-2,2,0
shr.u loc1=r18,9 // RNaTslots <= dirtySize / (64*8) + 1
shr.u loc1=r18,9 // RNaTslots <= floor(dirtySize / (64*8))
sub r17=r17,r18 // r17 = (physStackedSize + 8) - dirtySize
;;
mov ar.rsc=r19 // load ar.rsc to be used for "loadrs"
......@@ -774,13 +774,13 @@ rse_clear_invalid:
;;
mov loc3=0
mov loc4=0
mov loc9=0
mov loc5=0
mov loc6=0
mov loc7=0
(pRecurse) br.call.sptk.many b6=rse_clear_invalid
;;
mov loc7=0
mov loc8=0
mov loc9=0
cmp.ne pReturn,p0=r0,in1 // if recursion count != 0, we need to do a br.ret
mov loc10=0
mov loc11=0
......@@ -904,13 +904,14 @@ ENTRY(notify_resume_user)
mov r9=ar.unat
mov loc0=rp // save return address
mov out0=0 // there is no "oldset"
adds out1=0,sp // out1=&sigscratch
adds out1=8,sp // out1=&sigscratch->ar_pfs
(pSys) mov out2=1 // out2==1 => we're in a syscall
;;
(pNonSys) mov out2=0 // out2==0 => not a syscall
.fframe 16
.spillpsp ar.unat, 16 // (note that offset is relative to psp+0x10!)
st8 [sp]=r9,-16 // allocate space for ar.unat and save it
st8 [out1]=loc1,-8 // save ar.pfs, out1=&sigscratch
.body
br.call.sptk.many rp=do_notify_resume_user
.ret15: .restore sp
......@@ -931,11 +932,12 @@ GLOBAL_ENTRY(sys_rt_sigsuspend)
mov loc0=rp // save return address
mov out0=in0 // mask
mov out1=in1 // sigsetsize
adds out2=0,sp // out2=&sigscratch
adds out2=8,sp // out2=&sigscratch->ar_pfs
;;
.fframe 16
.spillpsp ar.unat, 16 // (note that offset is relative to psp+0x10!)
st8 [sp]=r9,-16 // allocate space for ar.unat and save it
st8 [out2]=loc1,-8 // save ar.pfs, out2=&sigscratch
.body
br.call.sptk.many rp=ia64_rt_sigsuspend
.ret17: .restore sp
......
arch/ia64/kernel/gate.S
View file @ 6a55e5aa
......@@ -145,11 +145,12 @@ END(fsys_fallback_syscall)
*/
#define SIGTRAMP_SAVES \
.unwabi @svr4, 's' // mark this as a sigtramp handler (saves scratch regs) \
.savesp ar.unat, UNAT_OFF+SIGCONTEXT_OFF \
.savesp ar.fpsr, FPSR_OFF+SIGCONTEXT_OFF \
.savesp pr, PR_OFF+SIGCONTEXT_OFF \
.savesp rp, RP_OFF+SIGCONTEXT_OFF \
.unwabi @svr4, 's'; /* mark this as a sigtramp handler (saves scratch regs) */ \
.savesp ar.unat, UNAT_OFF+SIGCONTEXT_OFF; \
.savesp ar.fpsr, FPSR_OFF+SIGCONTEXT_OFF; \
.savesp pr, PR_OFF+SIGCONTEXT_OFF; \
.savesp rp, RP_OFF+SIGCONTEXT_OFF; \
.savesp ar.pfs, CFM_OFF+SIGCONTEXT_OFF; \
.vframesp SP_OFF+SIGCONTEXT_OFF
GLOBAL_ENTRY(ia64_sigtramp)
......@@ -173,9 +174,7 @@ GLOBAL_ENTRY(ia64_sigtramp)
.spillsp.p p8, ar.rnat, RNAT_OFF+SIGCONTEXT_OFF
(p8) br.cond.spnt setup_rbs // yup -> (clobbers r14, r15, and r16)
back_from_setup_rbs:
.spillreg ar.pfs, r8
alloc r8=ar.pfs,0,0,3,0 // get CFM0, EC0, and CPL0 into r8
alloc r8=ar.pfs,0,0,3,0
ld8 out0=[base0],16 // load arg0 (signum)
adds base1=(ARG1_OFF-(RBS_BASE_OFF+SIGCONTEXT_OFF)),base1
;;
......@@ -184,17 +183,12 @@ back_from_setup_rbs:
;;
ld8 out2=[base0] // load arg2 (sigcontextp)
ld8 gp=[r17] // get signal handler's global pointer
adds base0=(BSP_OFF+SIGCONTEXT_OFF),sp
;;
.spillsp ar.bsp, BSP_OFF+SIGCONTEXT_OFF
st8 [base0]=r9,(CFM_OFF-BSP_OFF) // save sc_ar_bsp
dep r8=0,r8,38,26 // clear EC0, CPL0 and reserved bits
adds base1=(FR6_OFF+16+SIGCONTEXT_OFF),sp
;;
.spillsp ar.pfs, CFM_OFF+SIGCONTEXT_OFF
st8 [base0]=r8 // save CFM0
st8 [base0]=r9 // save sc_ar_bsp
adds base0=(FR6_OFF+SIGCONTEXT_OFF),sp
adds base1=(FR6_OFF+16+SIGCONTEXT_OFF),sp
;;
stf.spill [base0]=f6,32
stf.spill [base1]=f7,32
......@@ -217,7 +211,6 @@ back_from_setup_rbs:
ld8 r15=[base0],(CFM_OFF-BSP_OFF) // fetch sc_ar_bsp and advance to CFM_OFF
mov r14=ar.bsp
;;
ld8 r8=[base0] // restore (perhaps modified) CFM0, EC0, and CPL0
cmp.ne p8,p0=r14,r15 // do we need to restore the rbs?
(p8) br.cond.spnt restore_rbs // yup -> (clobbers r14-r18, f6 & f7)
;;
......
arch/ia64/kernel/sigframe.h
View file @ 6a55e5aa
struct sigscratch {
unsigned long scratch_unat; /* ar.unat for the general registers saved in pt */
unsigned long pad;
unsigned long ar_pfs; /* for syscalls, the user-level function-state */
struct pt_regs pt;
};
......
arch/ia64/kernel/signal.c
View file @ 6a55e5aa
......@@ -315,7 +315,7 @@ ia64_rt_sigreturn (struct sigscratch *scr)
static long
setup_sigcontext (struct sigcontext *sc, sigset_t *mask, struct sigscratch *scr)
{
unsigned long flags = 0, ifs, nat;
unsigned long flags = 0, ifs, cfm, nat;
long err;
ifs = scr->pt.cr_ifs;
......@@ -325,7 +325,9 @@ setup_sigcontext (struct sigcontext *sc, sigset_t *mask, struct sigscratch *scr)
if ((ifs & (1UL << 63)) == 0) {
/* if cr_ifs isn't valid, we got here through a syscall */
flags |= IA64_SC_FLAG_IN_SYSCALL;
}
cfm = scr->ar_pfs & ((1UL << 38) - 1);
} else
cfm = ifs & ((1UL << 38) - 1);
ia64_flush_fph(current);
if ((current->thread.flags & IA64_THREAD_FPH_VALID)) {
flags |= IA64_SC_FLAG_FPH_VALID;
......@@ -344,6 +346,7 @@ setup_sigcontext (struct sigcontext *sc, sigset_t *mask, struct sigscratch *scr)
err |= __put_user(nat, &sc->sc_nat);
err |= PUT_SIGSET(mask, &sc->sc_mask);
err |= __put_user(cfm, &sc->sc_cfm);
err |= __put_user(scr->pt.cr_ipsr & IA64_PSR_UM, &sc->sc_um);
err |= __put_user(scr->pt.ar_rsc, &sc->sc_ar_rsc);
err |= __put_user(scr->pt.ar_ccv, &sc->sc_ar_ccv);
......@@ -422,6 +425,15 @@ setup_frame (int sig, struct k_sigaction *ka, siginfo_t *info, sigset_t *set,
scr->pt.ar_fpsr = FPSR_DEFAULT; /* reset fpsr for signal handler */
scr->pt.cr_iip = tramp_addr;
ia64_psr(&scr->pt)->ri = 0; /* start executing in first slot */
/*
* Force the interruption function mask to zero. This has no effect when a
* system-call got interrupted by a signal (since, in that case, scr->pt_cr_ifs is
* ignored), but it has the desirable effect of making it possible to deliver a
* signal with an incomplete register frame (which happens when a mandatory RSE
* load faults). Furthermore, it has no negative effect on the getting the user's
* dirty partition preserved, because that's governed by scr->pt.loadrs.
*/
scr->pt.cr_ifs = (1UL << 63);
/*
* Note: this affects only the NaT bits of the scratch regs (the ones saved in
......
arch/ia64/tools/print_offsets.c
View file @ 6a55e5aa
......@@ -10,7 +10,7 @@
* gets translated into an assembly file which, in turn, is processed
* by awk to generate offsets.h. So if you make any changes to this
* file, be sure to verify that the awk procedure still works (see
* prin_offsets.awk).
* print_offsets.awk).
*/
#include <linux/config.h>
......
include/asm-ia64/sal.h
View file @ 6a55e5aa
......@@ -10,8 +10,8 @@
* Copyright (C) 2001 Intel
* Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
* Copyright (C) 2001 Fred Lewis <frederick.v.lewis@intel.com>
* Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co
* Copyright (C) 1998, 1999, 2001 David Mosberger-Tang <davidm@hpl.hp.com>
* Copyright (C) 1998, 1999, 2001, 2003 Hewlett-Packard Co
* David Mosberger-Tang <davidm@hpl.hp.com>
* Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
*
* 02/01/04 J. Hall Updated Error Record Structures to conform to July 2001
......@@ -239,52 +239,41 @@ enum {
#define SAL_MC_PARAM_BINIT_ESCALATE 0x10
/*
** Definition of the SAL Error Log from the SAL spec
*/
* Definition of the SAL Error Log from the SAL spec
*/
/* SAL Error Record Section GUID Definitions */
#define SAL_PROC_DEV_ERR_SECT_GUID \
EFI_GUID ( 0xe429faf1, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, \
0xc7, 0x3c, 0x88, 0x81 )
EFI_GUID(0xe429faf1, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
#define SAL_PLAT_MEM_DEV_ERR_SECT_GUID \
EFI_GUID( 0xe429faf2, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, \
0xc7, 0x3c, 0x88, 0x81 )
EFI_GUID(0xe429faf2, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
#define SAL_PLAT_SEL_DEV_ERR_SECT_GUID \
EFI_GUID( 0xe429faf3, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, \
0xc7, 0x3c, 0x88, 0x81 )
EFI_GUID(0xe429faf3, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
#define SAL_PLAT_PCI_BUS_ERR_SECT_GUID \
EFI_GUID( 0xe429faf4, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, \
0xc7, 0x3c, 0x88, 0x81 )
EFI_GUID(0xe429faf4, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
#define SAL_PLAT_SMBIOS_DEV_ERR_SECT_GUID \
EFI_GUID( 0xe429faf5, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, \
0xc7, 0x3c, 0x88, 0x81 )
EFI_GUID(0xe429faf5, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
#define SAL_PLAT_PCI_COMP_ERR_SECT_GUID \
EFI_GUID( 0xe429faf6, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, \
0xc7, 0x3c, 0x88, 0x81 )
EFI_GUID(0xe429faf6, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
#define SAL_PLAT_SPECIFIC_ERR_SECT_GUID \
EFI_GUID( 0xe429faf7, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, \
0xc7, 0x3c, 0x88, 0x81 )
EFI_GUID(0xe429faf7, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
#define SAL_PLAT_HOST_CTLR_ERR_SECT_GUID \
EFI_GUID( 0xe429faf8, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, \
0xc7, 0x3c, 0x88, 0x81 )
EFI_GUID(0xe429faf8, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
#define SAL_PLAT_BUS_ERR_SECT_GUID \
EFI_GUID( 0xe429faf9, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, \
0xc7, 0x3c, 0x88, 0x81 )
EFI_GUID(0xe429faf9, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
#define MAX_CACHE_ERRORS 6
#define MAX_TLB_ERRORS 6
#define MAX_BUS_ERRORS 1
/* Definition of version according to SAL spec for logging purposes */
typedef struct sal_log_revision
{
typedef struct sal_log_revision {
u8 minor; /* BCD (0..99) */
u8 major; /* BCD (0..99) */
} sal_log_revision_t;
/* Definition of timestamp according to SAL spec for logging purposes */
typedef struct sal_log_timestamp
{
typedef struct sal_log_timestamp {
u8 slh_second; /* Second (0..59) */
u8 slh_minute; /* Minute (0..59) */
u8 slh_hour; /* Hour (0..23) */
......@@ -296,8 +285,7 @@ typedef struct sal_log_timestamp
} sal_log_timestamp_t;
/* Definition of log record header structures */
typedef struct sal_log_record_header
{
typedef struct sal_log_record_header {
u64 id; /* Unique monotonically increasing ID */
sal_log_revision_t revision; /* Major and Minor revision of header */
u16 severity; /* Error Severity */
......@@ -307,18 +295,15 @@ typedef struct sal_log_record_header
} sal_log_record_header_t;
/* Definition of log section header structures */
typedef struct sal_log_sec_header
{
typedef struct sal_log_sec_header {
efi_guid_t guid; /* Unique Section ID */
sal_log_revision_t revision; /* Major and Minor revision of Section */
u16 reserved;
u32 len; /* Section length */
} sal_log_section_hdr_t;
typedef struct sal_log_mod_error_info
{
struct
{
typedef struct sal_log_mod_error_info {
struct {
u64 check_info : 1,
requestor_identifier : 1,
responder_identifier : 1,
......@@ -333,10 +318,8 @@ typedef struct sal_log_mod_error_info
u64 precise_ip;
} sal_log_mod_error_info_t;
typedef struct sal_processor_static_info
{
struct
{
typedef struct sal_processor_static_info {
struct {
u64 minstate : 1,
br : 1,
cr : 1,
......@@ -353,11 +336,9 @@ typedef struct sal_processor_static_info
struct ia64_fpreg fr[128];
} sal_processor_static_info_t;
typedef struct sal_log_processor_info
{
typedef struct sal_log_processor_info {
sal_log_section_hdr_t header;
struct
{
struct {
u64 proc_error_map : 1,
proc_state_param : 1,
proc_cr_lid : 1,
......@@ -378,8 +359,7 @@ typedef struct sal_log_processor_info
sal_log_mod_error_info_t bus_check_info[16];
sal_log_mod_error_info_t reg_file_check_info[16];
sal_log_mod_error_info_t ms_check_info[16];
struct
{
struct {
u64 regs[5];
u64 reserved;
} cpuid_info;
......@@ -388,11 +368,9 @@ typedef struct sal_log_processor_info
/* platform error log structures */
typedef struct sal_log_mem_dev_err_info
{
typedef struct sal_log_mem_dev_err_info {
sal_log_section_hdr_t header;
struct
{
struct {
u64 error_status : 1,
physical_addr : 1,
addr_mask : 1,
......@@ -431,11 +409,9 @@ typedef struct sal_log_mem_dev_err_info
u8 oem_data[1]; /* Variable length data */
} sal_log_mem_dev_err_info_t;
typedef struct sal_log_sel_dev_err_info
{
typedef struct sal_log_sel_dev_err_info {
sal_log_section_hdr_t header;
struct
{
struct {
u64 record_id : 1,
record_type : 1,
generator_id : 1,
......@@ -461,11 +437,9 @@ typedef struct sal_log_sel_dev_err_info
u8 event_data3;
} sal_log_sel_dev_err_info_t;
typedef struct sal_log_pci_bus_err_info
{
typedef struct sal_log_pci_bus_err_info {
sal_log_section_hdr_t header;
struct
{
struct {
u64 err_status : 1,
err_type : 1,
bus_id : 1,
......@@ -491,11 +465,9 @@ typedef struct sal_log_pci_bus_err_info
u8 oem_data[1]; /* Variable length data */
} sal_log_pci_bus_err_info_t;
typedef struct sal_log_smbios_dev_err_info
{
typedef struct sal_log_smbios_dev_err_info {
sal_log_section_hdr_t header;
struct
{
struct {
u64 event_type : 1,
length : 1,
time_stamp : 1,
......@@ -505,14 +477,12 @@ typedef struct sal_log_smbios_dev_err_info
u8 event_type;
u8 length;
u8 time_stamp[6];
u8 data[1]; // data of variable length, length == slsmb_length
u8 data[1]; /* data of variable length, length == slsmb_length */
} sal_log_smbios_dev_err_info_t;
typedef struct sal_log_pci_comp_err_info
{
typedef struct sal_log_pci_comp_err_info {
sal_log_section_hdr_t header;
struct
{
struct {
u64 err_status : 1,
comp_info : 1,
num_mem_regs : 1,
......@@ -522,8 +492,7 @@ typedef struct sal_log_pci_comp_err_info
reserved : 58;
} valid;
u64 err_status;
struct
{
struct {
u16 vendor_id;
u16 device_id;
u8 class_code[3];
......@@ -536,18 +505,17 @@ typedef struct sal_log_pci_comp_err_info
u32 num_mem_regs;
u32 num_io_regs;
u64 reg_data_pairs[1];
/* array of address/data register pairs is num_mem_regs + num_io_regs
elements long. Each array element consists of a u64 address followed
by a u64 data value. The oem_data array immediately follows the
reg_data_pairs array */
/*
* array of address/data register pairs is num_mem_regs + num_io_regs elements
* long. Each array element consists of a u64 address followed by a u64 data
* value. The oem_data array immediately follows the reg_data_pairs array
*/
u8 oem_data[1]; /* Variable length data */
} sal_log_pci_comp_err_info_t;
typedef struct sal_log_plat_specific_err_info
{
typedef struct sal_log_plat_specific_err_info {
sal_log_section_hdr_t header;
struct
{
struct {
u64 err_status : 1,
guid : 1,
oem_data : 1,
......@@ -558,11 +526,9 @@ typedef struct sal_log_plat_specific_err_info
u8 oem_data[1]; /* platform specific variable length data */
} sal_log_plat_specific_err_info_t;
typedef struct sal_log_host_ctlr_err_info
{
typedef struct sal_log_host_ctlr_err_info {
sal_log_section_hdr_t header;
struct
{
struct {
u64 err_status : 1,
requestor_id : 1,
responder_id : 1,
......@@ -579,11 +545,9 @@ typedef struct sal_log_host_ctlr_err_info
u8 oem_data[1]; /* Variable length OEM data */
} sal_log_host_ctlr_err_info_t;
typedef struct sal_log_plat_bus_err_info
{
typedef struct sal_log_plat_bus_err_info {
sal_log_section_hdr_t header;
struct
{
struct {
u64 err_status : 1,
requestor_id : 1,
responder_id : 1,
......@@ -601,8 +565,7 @@ typedef struct sal_log_plat_bus_err_info
} sal_log_plat_bus_err_info_t;
/* Overall platform error section structure */
typedef union sal_log_platform_err_info
{
typedef union sal_log_platform_err_info {
sal_log_mem_dev_err_info_t mem_dev_err;
sal_log_sel_dev_err_info_t sel_dev_err;
sal_log_pci_bus_err_info_t pci_bus_err;
......@@ -614,8 +577,7 @@ typedef union sal_log_platform_err_info
} sal_log_platform_err_info_t;
/* SAL log over-all, multi-section error record structure (processor+platform) */
typedef struct err_rec
{
typedef struct err_rec {
sal_log_record_header_t sal_elog_header;
sal_log_processor_info_t proc_err;
sal_log_platform_err_info_t plat_err;
......@@ -648,7 +610,6 @@ ia64_sal_cache_flush (u64 cache_type)
}
/* Initialize all the processor and platform level instruction and data caches */
static inline s64
ia64_sal_cache_init (void)
......@@ -658,8 +619,9 @@ ia64_sal_cache_init (void)
return isrv.status;
}
/* Clear the processor and platform information logged by SAL with respect to the
* machine state at the time of MCA's, INITs, CMCs, or CPEs.
/*
* Clear the processor and platform information logged by SAL with respect to the machine
* state at the time of MCA's, INITs, CMCs, or CPEs.
*/
static inline s64
ia64_sal_clear_state_info (u64 sal_info_type)
......@@ -685,8 +647,10 @@ ia64_sal_get_state_info (u64 sal_info_type, u64 *sal_info)
return isrv.v0;
}
/* Get the maximum size of the information logged by SAL with respect to the machine
* state at the time of MCAs, INITs, CMCs, or CPEs.
/*
* Get the maximum size of the information logged by SAL with respect to the machine state
* at the time of MCAs, INITs, CMCs, or CPEs.
*/
static inline u64
ia64_sal_get_state_info_size (u64 sal_info_type)
......@@ -699,8 +663,9 @@ ia64_sal_get_state_info_size (u64 sal_info_type)
return isrv.v0;
}
/* Causes the processor to go into a spin loop within SAL where SAL awaits a wakeup
* from the monarch processor.
/*
* Causes the processor to go into a spin loop within SAL where SAL awaits a wakeup from
* the monarch processor.
*/
static inline s64
ia64_sal_mc_rendez (void)
......@@ -710,7 +675,8 @@ ia64_sal_mc_rendez (void)
return isrv.status;
}
/* Allow the OS to specify the interrupt number to be used by SAL to interrupt OS during
/*
* Allow the OS to specify the interrupt number to be used by SAL to interrupt OS during
* the machine check rendezvous sequence as well as the mechanism to wake up the
* non-monarch processor at the end of machine check processing.
*/
......@@ -718,7 +684,8 @@ static inline s64
ia64_sal_mc_set_params (u64 param_type, u64 i_or_m, u64 i_or_m_val, u64 timeout, u64 rz_always)
{
struct ia64_sal_retval isrv;
SAL_CALL(isrv, SAL_MC_SET_PARAMS, param_type, i_or_m, i_or_m_val, timeout, rz_always, 0, 0);
SAL_CALL(isrv, SAL_MC_SET_PARAMS, param_type, i_or_m, i_or_m_val,
timeout, rz_always, 0, 0);
return isrv.status;
}
......@@ -744,8 +711,8 @@ ia64_sal_pci_config_write (u64 pci_config_addr, u64 size, u64 value)
}
/*
* Register physical addresses of locations needed by SAL when SAL
* procedures are invoked in virtual mode.
* Register physical addresses of locations needed by SAL when SAL procedures are invoked
* in virtual mode.
*/
static inline s64
ia64_sal_register_physical_addr (u64 phys_entry, u64 phys_addr)
......@@ -756,9 +723,10 @@ ia64_sal_register_physical_addr (u64 phys_entry, u64 phys_addr)
return isrv.status;
}
/* Register software dependent code locations within SAL. These locations are handlers
* or entry points where SAL will pass control for the specified event. These event
* handlers are for the bott rendezvous, MCAs and INIT scenarios.
/*
* Register software dependent code locations within SAL. These locations are handlers or
* entry points where SAL will pass control for the specified event. These event handlers
* are for the bott rendezvous, MCAs and INIT scenarios.
*/
static inline s64
ia64_sal_set_vectors (u64 vector_type,
......@@ -772,6 +740,7 @@ ia64_sal_set_vectors (u64 vector_type,
return isrv.status;
}
/* Update the contents of PAL block in the non-volatile storage device */
static inline s64
ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size,
......
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