Commit 6c1a7867 authored by Mukul Joshi's avatar Mukul Joshi Committed by Alex Deucher

drm/amdkfd: Fix TLB flushing in KFD SVM with no HWS

With no HWS, TLB flushing will not work in SVM code.
Fix this by calling kfd_flush_tlb() which works for both
HWS and no HWS case.
Signed-off-by: default avatarMukul Joshi <mukul.joshi@amd.com>
Reviewed-by: default avatarPhilip Yang <Philip.Yang@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent de7fbd02
...@@ -1229,19 +1229,20 @@ svm_range_unmap_from_gpus(struct svm_range *prange, unsigned long start, ...@@ -1229,19 +1229,20 @@ svm_range_unmap_from_gpus(struct svm_range *prange, unsigned long start,
if (r) if (r)
break; break;
} }
amdgpu_amdkfd_flush_gpu_tlb_pasid(pdd->dev->adev, kfd_flush_tlb(pdd, TLB_FLUSH_HEAVYWEIGHT);
p->pasid, TLB_FLUSH_HEAVYWEIGHT);
} }
return r; return r;
} }
static int static int
svm_range_map_to_gpu(struct amdgpu_device *adev, struct amdgpu_vm *vm, svm_range_map_to_gpu(struct kfd_process_device *pdd, struct svm_range *prange,
struct svm_range *prange, unsigned long offset, unsigned long offset, unsigned long npages, bool readonly,
unsigned long npages, bool readonly, dma_addr_t *dma_addr, dma_addr_t *dma_addr, struct amdgpu_device *bo_adev,
struct amdgpu_device *bo_adev, struct dma_fence **fence) struct dma_fence **fence)
{ {
struct amdgpu_device *adev = pdd->dev->adev;
struct amdgpu_vm *vm = drm_priv_to_vm(pdd->drm_priv);
bool table_freed = false; bool table_freed = false;
uint64_t pte_flags; uint64_t pte_flags;
unsigned long last_start; unsigned long last_start;
...@@ -1305,12 +1306,8 @@ svm_range_map_to_gpu(struct amdgpu_device *adev, struct amdgpu_vm *vm, ...@@ -1305,12 +1306,8 @@ svm_range_map_to_gpu(struct amdgpu_device *adev, struct amdgpu_vm *vm,
if (fence) if (fence)
*fence = dma_fence_get(vm->last_update); *fence = dma_fence_get(vm->last_update);
if (table_freed) { if (table_freed)
struct kfd_process *p; kfd_flush_tlb(pdd, TLB_FLUSH_LEGACY);
p = container_of(prange->svms, struct kfd_process, svms);
amdgpu_amdkfd_flush_gpu_tlb_pasid(adev, p->pasid, TLB_FLUSH_LEGACY);
}
out: out:
return r; return r;
} }
...@@ -1351,8 +1348,7 @@ svm_range_map_to_gpus(struct svm_range *prange, unsigned long offset, ...@@ -1351,8 +1348,7 @@ svm_range_map_to_gpus(struct svm_range *prange, unsigned long offset,
continue; continue;
} }
r = svm_range_map_to_gpu(pdd->dev->adev, drm_priv_to_vm(pdd->drm_priv), r = svm_range_map_to_gpu(pdd, prange, offset, npages, readonly,
prange, offset, npages, readonly,
prange->dma_addr[gpuidx], prange->dma_addr[gpuidx],
bo_adev, wait ? &fence : NULL); bo_adev, wait ? &fence : NULL);
if (r) if (r)
......
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