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Commit 6d508cce authored by David S. Miller's avatar David S. Miller
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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next 

Jeff Kirsher says:

====================
This series contains updates to ixgbe.

Jacob provides a fix for 82599 devices where it can potentially keep link
lights up when the adapter has gone down.

Mark provides a fix to resolve the possible use of uninitialized memory
by checking the return value on EEPROM reads.

Don provides 2 patches, one to fix a issue where we were traversing the
Tx ring with the value of IXGBE_NUM_RX_QUEUES which currently happens
to have the correct value but this is misleading.  A change later, could
easily make this no longer correct so when traversing the Tx ring, use
netdev->num_tx_queues.  His second patch does some minor clean ups of log
messages.

Emil provides the remaining ixgbe patches.  First he fixes the link test
where forcing the laser before the link check can lead to inconsistent
results because it does not guarantee that the link will be negotiated
correctly.  Then he initializes the message buffer array to 0 in order
to avoid using random numbers from the memory as a MAC address for the
VF.  Emil also fixes the read loop for the I2C data to account for the
offset for SFP+ modules.  Lastly, Emil provides several patches to add
support for QSFP modules where 1Gbps support is added as well as support
for older QSFP active direct attach cables which pre-date SFF-8436 v3.6.

v2: Fixed patch 4 description and added blank line based on feedback from
    Sergei Shtylyov
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 322555f5 9a84fea2
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Showing with 239 additions and 90 deletions
drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c
View file @ 6d508cce
......@@ -49,6 +49,7 @@ static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
ixgbe_link_speed speed,
bool autoneg_wait_to_complete);
static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw);
static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
bool autoneg_wait_to_complete);
static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
......@@ -141,11 +142,13 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
goto setup_sfp_out;
}
hw->eeprom.ops.read(hw, ++data_offset, &data_value);
if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
goto setup_sfp_err;
while (data_value != 0xffff) {
IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
IXGBE_WRITE_FLUSH(hw);
hw->eeprom.ops.read(hw, ++data_offset, &data_value);
if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
goto setup_sfp_err;
}
/* Release the semaphore */
......@@ -191,6 +194,17 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
setup_sfp_out:
return ret_val;
setup_sfp_err:
/* Release the semaphore */
hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
/* Delay obtaining semaphore again to allow FW access,
* semaphore_delay is in ms usleep_range needs us.
*/
usleep_range(hw->eeprom.semaphore_delay * 1000,
hw->eeprom.semaphore_delay * 2000);
hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
return IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
}
static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
......@@ -366,6 +380,11 @@ static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
if (hw->phy.multispeed_fiber) {
*speed |= IXGBE_LINK_SPEED_10GB_FULL |
IXGBE_LINK_SPEED_1GB_FULL;
/* QSFP must not enable auto-negotiation */
if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)
*autoneg = false;
else
*autoneg = true;
}
......@@ -431,6 +450,24 @@ static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
return media_type;
}
/**
* ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
* @hw: pointer to hardware structure
*
* Disables link, should be called during D3 power down sequence.
*
*/
static void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
{
u32 autoc2_reg;
if (!hw->mng_fw_enabled && !hw->wol_enabled) {
autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
}
}
/**
* ixgbe_start_mac_link_82599 - Setup MAC link settings
* @hw: pointer to hardware structure
......@@ -668,13 +705,18 @@ static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
goto out;
/* Set the module link speed */
if (hw->phy.media_type == ixgbe_media_type_fiber_fixed) {
ixgbe_set_fiber_fixed_speed(hw,
IXGBE_LINK_SPEED_10GB_FULL);
} else {
switch (hw->phy.media_type) {
case ixgbe_media_type_fiber:
esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
IXGBE_WRITE_FLUSH(hw);
break;
case ixgbe_media_type_fiber_qsfp:
/* QSFP module automatically detects MAC link speed */
break;
default:
hw_dbg(hw, "Unexpected media type.\n");
break;
}
/* Allow module to change analog characteristics (1G->10G) */
......@@ -725,14 +767,23 @@ static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
goto out;
/* Set the module link speed */
if (hw->phy.media_type == ixgbe_media_type_fiber_fixed) {
switch (hw->phy.media_type) {
case ixgbe_media_type_fiber_fixed:
ixgbe_set_fiber_fixed_speed(hw,
IXGBE_LINK_SPEED_1GB_FULL);
} else {
break;
case ixgbe_media_type_fiber:
esdp_reg &= ~IXGBE_ESDP_SDP5;
esdp_reg |= IXGBE_ESDP_SDP5_DIR;
IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
IXGBE_WRITE_FLUSH(hw);
break;
case ixgbe_media_type_fiber_qsfp:
/* QSFP module automatically detects MAC link speed */
break;
default:
hw_dbg(hw, "Unexpected media type.\n");
break;
}
/* Allow module to change analog characteristics (10G->1G) */
......@@ -2161,6 +2212,7 @@ static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
{
s32 status = IXGBE_ERR_EEPROM_VERSION;
u16 fw_offset, fw_ptp_cfg_offset;
u16 offset;
u16 fw_version = 0;
/* firmware check is only necessary for SFI devices */
......@@ -2170,29 +2222,35 @@ static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
}
/* get the offset to the Firmware Module block */
hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
offset = IXGBE_FW_PTR;
if (hw->eeprom.ops.read(hw, offset, &fw_offset))
goto fw_version_err;
if ((fw_offset == 0) || (fw_offset == 0xFFFF))
goto fw_version_out;
/* get the offset to the Pass Through Patch Configuration block */
hw->eeprom.ops.read(hw, (fw_offset +
IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
&fw_ptp_cfg_offset);
offset = fw_offset + IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR;
if (hw->eeprom.ops.read(hw, offset, &fw_ptp_cfg_offset))
goto fw_version_err;
if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
goto fw_version_out;
/* get the firmware version */
hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
IXGBE_FW_PATCH_VERSION_4),
&fw_version);
offset = fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4;
if (hw->eeprom.ops.read(hw, offset, &fw_version))
goto fw_version_err;
if (fw_version > 0x5)
status = 0;
fw_version_out:
return status;
fw_version_err:
hw_err(hw, "eeprom read at offset %d failed\n", offset);
return IXGBE_ERR_EEPROM_VERSION;
}
/**
......@@ -2477,6 +2535,7 @@ static struct ixgbe_mac_operations mac_ops_82599 = {
.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
.read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
.write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
.stop_link_on_d3 = &ixgbe_stop_mac_link_on_d3_82599,
.setup_link = &ixgbe_setup_mac_link_82599,
.set_rxpba = &ixgbe_set_rxpba_generic,
.check_link = &ixgbe_check_mac_link_generic,
......
drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
View file @ 6d508cce
......@@ -2740,13 +2740,19 @@ s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
u16 *san_mac_offset)
{
s32 ret_val;
/*
* First read the EEPROM pointer to see if the MAC addresses are
* available.
*/
hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
san_mac_offset);
if (ret_val)
hw_err(hw, "eeprom read at offset %d failed\n",
IXGBE_SAN_MAC_ADDR_PTR);
return 0;
return ret_val;
}
/**
......@@ -2763,23 +2769,16 @@ s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
{
u16 san_mac_data, san_mac_offset;
u8 i;
s32 ret_val;
/*
* First read the EEPROM pointer to see if the MAC addresses are
* available. If they're not, no point in calling set_lan_id() here.
*/
ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
/*
* No addresses available in this EEPROM. It's not an
* error though, so just wipe the local address and return.
*/
for (i = 0; i < 6; i++)
san_mac_addr[i] = 0xFF;
goto san_mac_addr_out;
}
goto san_mac_addr_clr;
/* make sure we know which port we need to program */
hw->mac.ops.set_lan_id(hw);
......@@ -2787,14 +2786,26 @@ s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
(hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
(san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
for (i = 0; i < 3; i++) {
hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
&san_mac_data);
if (ret_val) {
hw_err(hw, "eeprom read at offset %d failed\n",
san_mac_offset);
goto san_mac_addr_clr;
}
san_mac_addr[i * 2] = (u8)(san_mac_data);
san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
san_mac_offset++;
}
san_mac_addr_out:
return 0;
san_mac_addr_clr:
/* No addresses available in this EEPROM. It's not necessarily an
* error though, so just wipe the local address and return.
*/
for (i = 0; i < 6; i++)
san_mac_addr[i] = 0xFF;
return ret_val;
}
/**
......@@ -3243,8 +3254,9 @@ s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
*wwpn_prefix = 0xFFFF;
/* check if alternative SAN MAC is supported */
hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
&alt_san_mac_blk_offset);
offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
goto wwn_prefix_err;
if ((alt_san_mac_blk_offset == 0) ||
(alt_san_mac_blk_offset == 0xFFFF))
......@@ -3252,19 +3264,26 @@ s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
/* check capability in alternative san mac address block */
offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
hw->eeprom.ops.read(hw, offset, &caps);
if (hw->eeprom.ops.read(hw, offset, &caps))
goto wwn_prefix_err;
if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
goto wwn_prefix_out;
/* get the corresponding prefix for WWNN/WWPN */
offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
hw->eeprom.ops.read(hw, offset, wwnn_prefix);
if (hw->eeprom.ops.read(hw, offset, wwnn_prefix))
hw_err(hw, "eeprom read at offset %d failed\n", offset);
offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
hw->eeprom.ops.read(hw, offset, wwpn_prefix);
if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
goto wwn_prefix_err;
wwn_prefix_out:
return 0;
wwn_prefix_err:
hw_err(hw, "eeprom read at offset %d failed\n", offset);
return 0;
}
/**
......@@ -3778,7 +3797,11 @@ s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
u8 sensor_index;
u8 sensor_location;
hw->eeprom.ops.read(hw, (ets_offset + 1 + i), &ets_sensor);
if (hw->eeprom.ops.read(hw, ets_offset + 1 + i, &ets_sensor)) {
hw_err(hw, "eeprom read at offset %d failed\n",
ets_offset + 1 + i);
continue;
}
sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
IXGBE_ETS_DATA_INDEX_SHIFT);
sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
......
drivers/net/ethernet/intel/ixgbe/ixgbe_common.h
View file @ 6d508cce
......@@ -143,8 +143,12 @@ s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw);
#define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
#define ixgbe_hw_to_netdev(hw) (((struct ixgbe_adapter *)(hw)->back)->netdev)
#define hw_dbg(hw, format, arg...) \
netdev_dbg(((struct ixgbe_adapter *)(hw->back))->netdev, format, ##arg)
netdev_dbg(ixgbe_hw_to_netdev(hw), format, ## arg)
#define hw_err(hw, format, arg...) \
netdev_err(ixgbe_hw_to_netdev(hw), format, ## arg)
#define e_dev_info(format, arg...) \
dev_info(&adapter->pdev->dev, format, ## arg)
#define e_dev_warn(format, arg...) \
......
drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c
View file @ 6d508cce
......@@ -311,9 +311,6 @@ static int ixgbe_set_settings(struct net_device *netdev,
* this function does not support duplex forcing, but can
* limit the advertising of the adapter to the specified speed
*/
if (ecmd->autoneg == AUTONEG_DISABLE)
return -EINVAL;
if (ecmd->advertising & ~ecmd->supported)
return -EINVAL;
......@@ -1049,7 +1046,7 @@ static void ixgbe_get_ethtool_stats(struct net_device *netdev,
data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
}
for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
for (j = 0; j < netdev->num_tx_queues; j++) {
ring = adapter->tx_ring[j];
if (!ring) {
data[i] = 0;
......@@ -1885,11 +1882,12 @@ static void ixgbe_diag_test(struct net_device *netdev,
struct ethtool_test *eth_test, u64 *data)
{
struct ixgbe_adapter *adapter = netdev_priv(netdev);
struct ixgbe_hw *hw = &adapter->hw;
bool if_running = netif_running(netdev);
set_bit(__IXGBE_TESTING, &adapter->state);
if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
struct ixgbe_hw *hw = &adapter->hw;
if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
int i;
for (i = 0; i < adapter->num_vfs; i++) {
......@@ -1913,21 +1911,18 @@ static void ixgbe_diag_test(struct net_device *netdev,
/* Offline tests */
e_info(hw, "offline testing starting\n");
if (if_running)
/* indicate we're in test mode */
dev_close(netdev);
/* bringing adapter down disables SFP+ optics */
if (hw->mac.ops.enable_tx_laser)
hw->mac.ops.enable_tx_laser(hw);
/* Link test performed before hardware reset so autoneg doesn't
* interfere with test result
*/
if (ixgbe_link_test(adapter, &data[4]))
eth_test->flags |= ETH_TEST_FL_FAILED;
if (if_running)
/* indicate we're in test mode */
dev_close(netdev);
else
ixgbe_reset(adapter);
e_info(hw, "register testing starting\n");
if (ixgbe_reg_test(adapter, &data[0]))
eth_test->flags |= ETH_TEST_FL_FAILED;
......@@ -1964,13 +1959,11 @@ static void ixgbe_diag_test(struct net_device *netdev,
clear_bit(__IXGBE_TESTING, &adapter->state);
if (if_running)
dev_open(netdev);
else if (hw->mac.ops.disable_tx_laser)
hw->mac.ops.disable_tx_laser(hw);
} else {
e_info(hw, "online testing starting\n");
/* if adapter is down, SFP+ optics will be disabled */
if (!if_running && hw->mac.ops.enable_tx_laser)
hw->mac.ops.enable_tx_laser(hw);
/* Online tests */
if (ixgbe_link_test(adapter, &data[4]))
eth_test->flags |= ETH_TEST_FL_FAILED;
......@@ -1984,9 +1977,6 @@ static void ixgbe_diag_test(struct net_device *netdev,
clear_bit(__IXGBE_TESTING, &adapter->state);
}
/* if adapter was down, ensure SFP+ optics are disabled again */
if (!if_running && hw->mac.ops.disable_tx_laser)
hw->mac.ops.disable_tx_laser(hw);
skip_ol_tests:
msleep_interruptible(4 * 1000);
}
......@@ -2953,12 +2943,11 @@ static int ixgbe_get_module_eeprom(struct net_device *dev,
u32 status = IXGBE_ERR_PHY_ADDR_INVALID;
u8 databyte = 0xFF;
int i = 0;
int ret_val = 0;
if (ee->len == 0)
return -EINVAL;
for (i = ee->offset; i < ee->len; i++) {
for (i = ee->offset; i < ee->offset + ee->len; i++) {
/* I2C reads can take long time */
if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
return -EBUSY;
......@@ -2969,12 +2958,12 @@ static int ixgbe_get_module_eeprom(struct net_device *dev,
status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
if (status != 0)
ret_val = -EIO;
return -EIO;
data[i - ee->offset] = databyte;
}
return ret_val;
return 0;
}
static const struct ethtool_ops ixgbe_ethtool_ops = {
......
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
View file @ 6d508cce
......@@ -4175,6 +4175,10 @@ static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
case ixgbe_phy_sfp_passive_unknown:
case ixgbe_phy_sfp_active_unknown:
case ixgbe_phy_sfp_ftl_active:
case ixgbe_phy_qsfp_passive_unknown:
case ixgbe_phy_qsfp_active_unknown:
case ixgbe_phy_qsfp_intel:
case ixgbe_phy_qsfp_unknown:
return true;
case ixgbe_phy_nl:
if (hw->mac.type == ixgbe_mac_82598EB)
......@@ -5292,6 +5296,9 @@ static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
return retval;
#endif
if (hw->mac.ops.stop_link_on_d3)
hw->mac.ops.stop_link_on_d3(hw);
if (wufc) {
ixgbe_set_rx_mode(netdev);
......@@ -7602,10 +7609,8 @@ static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
hw->mac.type == ixgbe_mac_82598EB) {
err = 0;
} else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
e_dev_err("failed to load because an unsupported SFP+ "
"module type was detected.\n");
e_dev_err("Reload the driver after installing a supported "
"module.\n");
e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
e_dev_err("Reload the driver after installing a supported module.\n");
goto err_sw_init;
} else if (err) {
e_dev_err("HW Init failed: %d\n", err);
......
drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
View file @ 6d508cce
......@@ -791,6 +791,8 @@ s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
* Read control word from PHY init contents offset
*/
ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
if (ret_val)
goto err_eeprom;
control = (eword & IXGBE_CONTROL_MASK_NL) >>
IXGBE_CONTROL_SHIFT_NL;
edata = eword & IXGBE_DATA_MASK_NL;
......@@ -803,10 +805,15 @@ s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
case IXGBE_DATA_NL:
hw_dbg(hw, "DATA:\n");
data_offset++;
hw->eeprom.ops.read(hw, data_offset++,
ret_val = hw->eeprom.ops.read(hw, data_offset++,
&phy_offset);
if (ret_val)
goto err_eeprom;
for (i = 0; i < edata; i++) {
hw->eeprom.ops.read(hw, data_offset, &eword);
ret_val = hw->eeprom.ops.read(hw, data_offset,
&eword);
if (ret_val)
goto err_eeprom;
hw->phy.ops.write_reg(hw, phy_offset,
MDIO_MMD_PMAPMD, eword);
hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
......@@ -838,6 +845,10 @@ s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
out:
return ret_val;
err_eeprom:
hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
return IXGBE_ERR_PHY;
}
/**
......@@ -1164,6 +1175,10 @@ s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
u8 comp_codes_10g = 0;
u8 oui_bytes[3] = {0, 0, 0};
u16 enforce_sfp = 0;
u8 connector = 0;
u8 cable_length = 0;
u8 device_tech = 0;
bool active_cable = false;
if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
hw->phy.sfp_type = ixgbe_sfp_type_not_present;
......@@ -1194,30 +1209,67 @@ s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
if (status != 0)
goto err_read_i2c_eeprom;
status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
&comp_codes_1g);
if (status != 0)
goto err_read_i2c_eeprom;
if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
if (hw->bus.lan_id == 0)
hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
else
hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
} else if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) {
hw->phy.type = ixgbe_phy_qsfp_active_unknown;
if (hw->bus.lan_id == 0)
hw->phy.sfp_type = ixgbe_sfp_type_da_act_lmt_core0;
else
hw->phy.sfp_type = ixgbe_sfp_type_da_act_lmt_core1;
} else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
IXGBE_SFF_10GBASELR_CAPABLE)) {
if (hw->bus.lan_id == 0)
hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
else
hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
} else {
if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
active_cable = true;
if (!active_cable) {
/* check for active DA cables that pre-date
* SFF-8436 v3.6
*/
hw->phy.ops.read_i2c_eeprom(hw,
IXGBE_SFF_QSFP_CONNECTOR,
&connector);
hw->phy.ops.read_i2c_eeprom(hw,
IXGBE_SFF_QSFP_CABLE_LENGTH,
&cable_length);
hw->phy.ops.read_i2c_eeprom(hw,
IXGBE_SFF_QSFP_DEVICE_TECH,
&device_tech);
if ((connector ==
IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
(cable_length > 0) &&
((device_tech >> 4) ==
IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
active_cable = true;
}
if (active_cable) {
hw->phy.type = ixgbe_phy_qsfp_active_unknown;
if (hw->bus.lan_id == 0)
hw->phy.sfp_type =
ixgbe_sfp_type_da_act_lmt_core0;
else
hw->phy.sfp_type =
ixgbe_sfp_type_da_act_lmt_core1;
} else {
/* unsupported module type */
hw->phy.type = ixgbe_phy_sfp_unsupported;
status = IXGBE_ERR_SFP_NOT_SUPPORTED;
goto out;
}
}
if (hw->phy.sfp_type != stored_sfp_type)
hw->phy.sfp_setup_needed = true;
......@@ -1271,7 +1323,7 @@ s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
status = 0;
} else {
if (hw->allow_unsupported_sfp == true) {
e_warn(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
status = 0;
} else {
hw_dbg(hw,
......@@ -1339,7 +1391,11 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
sfp_type = ixgbe_sfp_type_srlr_core1;
/* Read offset to PHY init contents */
hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
hw_err(hw, "eeprom read at %d failed\n",
IXGBE_PHY_INIT_OFFSET_NL);
return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
}
if ((!*list_offset) || (*list_offset == 0xFFFF))
return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
......@@ -1351,12 +1407,14 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
* Find the matching SFP ID in the EEPROM
* and program the init sequence
*/
hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
goto err_phy;
while (sfp_id != IXGBE_PHY_INIT_END_NL) {
if (sfp_id == sfp_type) {
(*list_offset)++;
hw->eeprom.ops.read(hw, *list_offset, data_offset);
if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
goto err_phy;
if ((!*data_offset) || (*data_offset == 0xFFFF)) {
hw_dbg(hw, "SFP+ module not supported\n");
return IXGBE_ERR_SFP_NOT_SUPPORTED;
......@@ -1366,7 +1424,7 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
} else {
(*list_offset) += 2;
if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
return IXGBE_ERR_PHY;
goto err_phy;
}
}
......@@ -1376,6 +1434,10 @@ s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
}
return 0;
err_phy:
hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
return IXGBE_ERR_PHY;
}
/**
......
drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
View file @ 6d508cce
......@@ -50,8 +50,11 @@
#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5
#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6
#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA7
#define IXGBE_SFF_QSFP_CONNECTOR 0x82
#define IXGBE_SFF_QSFP_10GBE_COMP 0x83
#define IXGBE_SFF_QSFP_1GBE_COMP 0x86
#define IXGBE_SFF_QSFP_CABLE_LENGTH 0x92
#define IXGBE_SFF_QSFP_DEVICE_TECH 0x93
/* Bitmasks */
#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4
......@@ -68,6 +71,8 @@
#define IXGBE_SFF_ADDRESSING_MODE 0x4
#define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE 0x1
#define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8
#define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE 0x23
#define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL 0x0
#define IXGBE_I2C_EEPROM_READ_MASK 0x100
#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3
#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
......
drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c
View file @ 6d508cce
......@@ -639,8 +639,8 @@ static int ixgbe_vf_reset_msg(struct ixgbe_adapter *adapter, u32 vf)
{
struct ixgbe_hw *hw = &adapter->hw;
unsigned char *vf_mac = adapter->vfinfo[vf].vf_mac_addresses;
u32 reg, msgbuf[4];
u32 reg_offset, vf_shift;
u32 reg, reg_offset, vf_shift;
u32 msgbuf[4] = {0, 0, 0, 0};
u8 *addr = (u8 *)(&msgbuf[1]);
e_info(probe, "VF Reset msg received from vf %d\n", vf);
......
drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
View file @ 6d508cce
......@@ -1596,6 +1596,7 @@ enum {
#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
#define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK 0x50000000
#define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000
#define IXGBE_MACC_FLU 0x00000001
......@@ -2847,6 +2848,7 @@ struct ixgbe_mac_operations {
void (*disable_tx_laser)(struct ixgbe_hw *);
void (*enable_tx_laser)(struct ixgbe_hw *);
void (*flap_tx_laser)(struct ixgbe_hw *);
void (*stop_link_on_d3)(struct ixgbe_hw *);
s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
......
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