Commit 6d840d85 authored by Roger Quadros's avatar Roger Quadros Committed by Tony Lindgren

ARM: dts: dm816x: Fix NAND device nodes

Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.

The GPMC node will provide an interrupt controller for the
NAND IRQs.
Signed-off-by: default avatarRoger Quadros <rogerq@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent db0f6852
...@@ -6,6 +6,7 @@ ...@@ -6,6 +6,7 @@
/dts-v1/; /dts-v1/;
#include "dm816x.dtsi" #include "dm816x.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ { / {
model = "DM8168 EVM"; model = "DM8168 EVM";
...@@ -85,8 +86,12 @@ &gpmc { ...@@ -85,8 +86,12 @@ &gpmc {
ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */
nand@0,0 { nand@0,0 {
compatible = "ti,omap2-nand";
linux,mtd-name= "micron,mt29f2g16aadwp"; linux,mtd-name= "micron,mt29f2g16aadwp";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ti,nand-ecc-opt = "bch8"; ti,nand-ecc-opt = "bch8";
......
...@@ -183,6 +183,8 @@ gpmc: gpmc@50000000 { ...@@ -183,6 +183,8 @@ gpmc: gpmc@50000000 {
dma-names = "rxtx"; dma-names = "rxtx";
gpmc,num-cs = <6>; gpmc,num-cs = <6>;
gpmc,num-waitpins = <2>; gpmc,num-waitpins = <2>;
interrupt-controller;
#interrupt-cells = <2>;
}; };
i2c1: i2c@48028000 { i2c1: i2c@48028000 {
......
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