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Commit 6e6aac75 authored by Thomas Abraham's avatar Thomas Abraham Committed by Kukjin Kim
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ARM: EXYNOS: Migrate clock support to common clock framework 

Remove Samsung specific clock support in Exynos4/5 and migrate to
use common clock framework.
Reviewed-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: default avatarTomasz Figa <t.figa@samsung.com>
Tested-by: default avatarTomasz Figa <t.figa@samsung.com>
Signed-off-by: default avatarThomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent f2585b1c
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Showing with 10 additions and 3835 deletions
arch/arm/Kconfig
View file @ 6e6aac75
......@@ -865,6 +865,7 @@ config ARCH_EXYNOS
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_SPARSEMEM_ENABLE
select CLKDEV_LOOKUP
select COMMON_CLK
select CPU_V7
select GENERIC_CLOCKEVENTS
select HAVE_CLK
......
arch/arm/mach-exynos/Makefile
View file @ 6e6aac75
......@@ -13,10 +13,6 @@ obj- :=
# Core
obj-$(CONFIG_ARCH_EXYNOS) += common.o
obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
obj-$(CONFIG_SOC_EXYNOS5250) += clock-exynos5.o
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
......
arch/arm/mach-exynos/clock-exynos4.c deleted 100644 → 0
View file @ f2585b1c
/*
* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4 - Clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/syscore_ops.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/pm.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include "common.h"
#include "clock-exynos4.h"
#ifdef CONFIG_PM_SLEEP
static struct sleep_save exynos4_clock_save[] = {
SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
SAVE_ITEM(EXYNOS4_CLKSRC_TV),
SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
SAVE_ITEM(EXYNOS4_CLKDIV_TV),
SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
};
#endif
static struct clk exynos4_clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m",
.rate = 27000000,
};
static struct clk exynos4_clk_sclk_hdmiphy = {
.name = "sclk_hdmiphy",
};
static struct clk exynos4_clk_sclk_usbphy0 = {
.name = "sclk_usbphy0",
.rate = 27000000,
};
static struct clk exynos4_clk_sclk_usbphy1 = {
.name = "sclk_usbphy1",
};
static struct clk dummy_apb_pclk = {
.name = "apb_pclk",
.id = -1,
};
static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
}
static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
}
static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
}
int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
}
static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
}
static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
}
static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
}
static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
}
static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
}
static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
}
int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
}
static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
}
int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
}
int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
}
static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
}
static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
}
int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
}
static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
}
static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
}
/* Core list of CMU_CPU side */
static struct clksrc_clk exynos4_clk_mout_apll = {
.clk = {
.name = "mout_apll",
},
.sources = &clk_src_apll,
.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
};
static struct clksrc_clk exynos4_clk_sclk_apll = {
.clk = {
.name = "sclk_apll",
.parent = &exynos4_clk_mout_apll.clk,
},
.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
};
static struct clksrc_clk exynos4_clk_mout_epll = {
.clk = {
.name = "mout_epll",
},
.sources = &clk_src_epll,
.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
};
struct clksrc_clk exynos4_clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
},
.sources = &clk_src_mpll,
/* reg_src will be added in each SoCs' clock */
};
static struct clk *exynos4_clkset_moutcore_list[] = {
[0] = &exynos4_clk_mout_apll.clk,
[1] = &exynos4_clk_mout_mpll.clk,
};
static struct clksrc_sources exynos4_clkset_moutcore = {
.sources = exynos4_clkset_moutcore_list,
.nr_sources = ARRAY_SIZE(exynos4_clkset_moutcore_list),
};
static struct clksrc_clk exynos4_clk_moutcore = {
.clk = {
.name = "moutcore",
},
.sources = &exynos4_clkset_moutcore,
.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
};
static struct clksrc_clk exynos4_clk_coreclk = {
.clk = {
.name = "core_clk",
.parent = &exynos4_clk_moutcore.clk,
},
.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
};
static struct clksrc_clk exynos4_clk_armclk = {
.clk = {
.name = "armclk",
.parent = &exynos4_clk_coreclk.clk,
},
};
static struct clksrc_clk exynos4_clk_aclk_corem0 = {
.clk = {
.name = "aclk_corem0",
.parent = &exynos4_clk_coreclk.clk,
},
.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
};
static struct clksrc_clk exynos4_clk_aclk_cores = {
.clk = {
.name = "aclk_cores",
.parent = &exynos4_clk_coreclk.clk,
},
.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
};
static struct clksrc_clk exynos4_clk_aclk_corem1 = {
.clk = {
.name = "aclk_corem1",
.parent = &exynos4_clk_coreclk.clk,
},
.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
};
static struct clksrc_clk exynos4_clk_periphclk = {
.clk = {
.name = "periphclk",
.parent = &exynos4_clk_coreclk.clk,
},
.reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
};
/* Core list of CMU_CORE side */
static struct clk *exynos4_clkset_corebus_list[] = {
[0] = &exynos4_clk_mout_mpll.clk,
[1] = &exynos4_clk_sclk_apll.clk,
};
struct clksrc_sources exynos4_clkset_mout_corebus = {
.sources = exynos4_clkset_corebus_list,
.nr_sources = ARRAY_SIZE(exynos4_clkset_corebus_list),
};
static struct clksrc_clk exynos4_clk_mout_corebus = {
.clk = {
.name = "mout_corebus",
},
.sources = &exynos4_clkset_mout_corebus,
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
};
static struct clksrc_clk exynos4_clk_sclk_dmc = {
.clk = {
.name = "sclk_dmc",
.parent = &exynos4_clk_mout_corebus.clk,
},
.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
};
static struct clksrc_clk exynos4_clk_aclk_cored = {
.clk = {
.name = "aclk_cored",
.parent = &exynos4_clk_sclk_dmc.clk,
},
.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
};
static struct clksrc_clk exynos4_clk_aclk_corep = {
.clk = {
.name = "aclk_corep",
.parent = &exynos4_clk_aclk_cored.clk,
},
.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
};
static struct clksrc_clk exynos4_clk_aclk_acp = {
.clk = {
.name = "aclk_acp",
.parent = &exynos4_clk_mout_corebus.clk,
},
.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
};
static struct clksrc_clk exynos4_clk_pclk_acp = {
.clk = {
.name = "pclk_acp",
.parent = &exynos4_clk_aclk_acp.clk,
},
.reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
};
/* Core list of CMU_TOP side */
struct clk *exynos4_clkset_aclk_top_list[] = {
[0] = &exynos4_clk_mout_mpll.clk,
[1] = &exynos4_clk_sclk_apll.clk,
};
static struct clksrc_sources exynos4_clkset_aclk = {
.sources = exynos4_clkset_aclk_top_list,
.nr_sources = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
};
static struct clksrc_clk exynos4_clk_aclk_200 = {
.clk = {
.name = "aclk_200",
},
.sources = &exynos4_clkset_aclk,
.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
};
static struct clksrc_clk exynos4_clk_aclk_100 = {
.clk = {
.name = "aclk_100",
},
.sources = &exynos4_clkset_aclk,
.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
};
static struct clksrc_clk exynos4_clk_aclk_160 = {
.clk = {
.name = "aclk_160",
},
.sources = &exynos4_clkset_aclk,
.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
};
struct clksrc_clk exynos4_clk_aclk_133 = {
.clk = {
.name = "aclk_133",
},
.sources = &exynos4_clkset_aclk,
.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
.reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
};
static struct clk *exynos4_clkset_vpllsrc_list[] = {
[0] = &clk_fin_vpll,
[1] = &exynos4_clk_sclk_hdmi27m,
};
static struct clksrc_sources exynos4_clkset_vpllsrc = {
.sources = exynos4_clkset_vpllsrc_list,
.nr_sources = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
};
static struct clksrc_clk exynos4_clk_vpllsrc = {
.clk = {
.name = "vpll_src",
.enable = exynos4_clksrc_mask_top_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &exynos4_clkset_vpllsrc,
.reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
};
static struct clk *exynos4_clkset_sclk_vpll_list[] = {
[0] = &exynos4_clk_vpllsrc.clk,
[1] = &clk_fout_vpll,
};
static struct clksrc_sources exynos4_clkset_sclk_vpll = {
.sources = exynos4_clkset_sclk_vpll_list,
.nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
};
static struct clksrc_clk exynos4_clk_sclk_vpll = {
.clk = {
.name = "sclk_vpll",
},
.sources = &exynos4_clkset_sclk_vpll,
.reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
};
static struct clk exynos4_init_clocks_off[] = {
{
.name = "timers",
.parent = &exynos4_clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1<<24),
}, {
.name = "csis",
.devname = "s5p-mipi-csis.0",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "csis",
.devname = "s5p-mipi-csis.1",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "jpeg",
.id = 0,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "fimc",
.devname = "exynos4-fimc.0",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "fimc",
.devname = "exynos4-fimc.1",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "fimc",
.devname = "exynos4-fimc.2",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "fimc",
.devname = "exynos4-fimc.3",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "tsi",
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "hsmmc",
.devname = "exynos4-sdhci.0",
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "hsmmc",
.devname = "exynos4-sdhci.1",
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "hsmmc",
.devname = "exynos4-sdhci.2",
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "hsmmc",
.devname = "exynos4-sdhci.3",
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "biu",
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "onenand",
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "nfcon",
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "dac",
.devname = "s5p-sdo",
.enable = exynos4_clk_ip_tv_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "mixer",
.devname = "s5p-mixer",
.enable = exynos4_clk_ip_tv_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "vp",
.devname = "s5p-mixer",
.enable = exynos4_clk_ip_tv_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "hdmi",
.devname = "exynos4-hdmi",
.enable = exynos4_clk_ip_tv_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "hdmiphy",
.devname = "exynos4-hdmi",
.enable = exynos4_clk_hdmiphy_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "dacphy",
.devname = "s5p-sdo",
.enable = exynos4_clk_dac_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "adc",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "tmu_apbif",
.enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "keypad",
.enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "rtc",
.enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "watchdog",
.parent = &exynos4_clk_aclk_100.clk,
.enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 14),
}, {
.name = "usbhost",
.enable = exynos4_clk_ip_fsys_ctrl ,
.ctrlbit = (1 << 12),
}, {
.name = "otg",
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 13),
}, {
.name = "spi",
.devname = "exynos4210-spi.0",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "spi",
.devname = "exynos4210-spi.1",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "spi",
.devname = "exynos4210-spi.2",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "iis",
.devname = "samsung-i2s.1",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 20),
}, {
.name = "iis",
.devname = "samsung-i2s.2",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "pcm",
.devname = "samsung-pcm.1",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "pcm",
.devname = "samsung-pcm.2",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 23),
}, {
.name = "slimbus",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "spdif",
.devname = "samsung-spdif",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 26),
}, {
.name = "ac97",
.devname = "samsung-ac97",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 27),
}, {
.name = "mfc",
.devname = "s5p-mfc",
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "i2c",
.devname = "s3c2440-i2c.0",
.parent = &exynos4_clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "i2c",
.devname = "s3c2440-i2c.1",
.parent = &exynos4_clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "i2c",
.devname = "s3c2440-i2c.2",
.parent = &exynos4_clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "i2c",
.devname = "s3c2440-i2c.3",
.parent = &exynos4_clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "i2c",
.devname = "s3c2440-i2c.4",
.parent = &exynos4_clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "i2c",
.devname = "s3c2440-i2c.5",
.parent = &exynos4_clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "i2c",
.devname = "s3c2440-i2c.6",
.parent = &exynos4_clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "i2c",
.devname = "s3c2440-i2c.7",
.parent = &exynos4_clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 13),
}, {
.name = "i2c",
.devname = "s3c2440-hdmiphy-i2c",
.parent = &exynos4_clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 14),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.0",
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.1",
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.2",
.enable = exynos4_clk_ip_tv_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.3",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.4",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.5",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.6",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.7",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.8",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.10",
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 4),
}
};
static struct clk exynos4_init_clocks_on[] = {
{
.name = "uart",
.devname = "s5pv210-uart.0",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "uart",
.devname = "s5pv210-uart.1",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
.devname = "s5pv210-uart.2",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
.devname = "s5pv210-uart.3",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
.devname = "s5pv210-uart.4",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "uart",
.devname = "s5pv210-uart.5",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 5),
}
};
static struct clk exynos4_clk_pdma0 = {
.name = "dma",
.devname = "dma-pl330.0",
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 0),
};
static struct clk exynos4_clk_pdma1 = {
.name = "dma",
.devname = "dma-pl330.1",
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 1),
};
static struct clk exynos4_clk_mdma1 = {
.name = "dma",
.devname = "dma-pl330.2",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)),
};
static struct clk exynos4_clk_fimd0 = {
.name = "fimd",
.devname = "exynos4-fb.0",
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 0),
};
struct clk *exynos4_clkset_group_list[] = {
[0] = &clk_ext_xtal_mux,
[1] = &clk_xusbxti,
[2] = &exynos4_clk_sclk_hdmi27m,
[3] = &exynos4_clk_sclk_usbphy0,
[4] = &exynos4_clk_sclk_usbphy1,
[5] = &exynos4_clk_sclk_hdmiphy,
[6] = &exynos4_clk_mout_mpll.clk,
[7] = &exynos4_clk_mout_epll.clk,
[8] = &exynos4_clk_sclk_vpll.clk,
};
struct clksrc_sources exynos4_clkset_group = {
.sources = exynos4_clkset_group_list,
.nr_sources = ARRAY_SIZE(exynos4_clkset_group_list),
};
static struct clk *exynos4_clkset_mout_g2d0_list[] = {
[0] = &exynos4_clk_mout_mpll.clk,
[1] = &exynos4_clk_sclk_apll.clk,
};
struct clksrc_sources exynos4_clkset_mout_g2d0 = {
.sources = exynos4_clkset_mout_g2d0_list,
.nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
};
static struct clk *exynos4_clkset_mout_g2d1_list[] = {
[0] = &exynos4_clk_mout_epll.clk,
[1] = &exynos4_clk_sclk_vpll.clk,
};
struct clksrc_sources exynos4_clkset_mout_g2d1 = {
.sources = exynos4_clkset_mout_g2d1_list,
.nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
};
static struct clk *exynos4_clkset_mout_mfc0_list[] = {
[0] = &exynos4_clk_mout_mpll.clk,
[1] = &exynos4_clk_sclk_apll.clk,
};
static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
.sources = exynos4_clkset_mout_mfc0_list,
.nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
};
static struct clksrc_clk exynos4_clk_mout_mfc0 = {
.clk = {
.name = "mout_mfc0",
},
.sources = &exynos4_clkset_mout_mfc0,
.reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
};
static struct clk *exynos4_clkset_mout_mfc1_list[] = {
[0] = &exynos4_clk_mout_epll.clk,
[1] = &exynos4_clk_sclk_vpll.clk,
};
static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
.sources = exynos4_clkset_mout_mfc1_list,
.nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
};
static struct clksrc_clk exynos4_clk_mout_mfc1 = {
.clk = {
.name = "mout_mfc1",
},
.sources = &exynos4_clkset_mout_mfc1,
.reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
};
static struct clk *exynos4_clkset_mout_mfc_list[] = {
[0] = &exynos4_clk_mout_mfc0.clk,
[1] = &exynos4_clk_mout_mfc1.clk,
};
static struct clksrc_sources exynos4_clkset_mout_mfc = {
.sources = exynos4_clkset_mout_mfc_list,
.nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
};
static struct clk *exynos4_clkset_sclk_dac_list[] = {
[0] = &exynos4_clk_sclk_vpll.clk,
[1] = &exynos4_clk_sclk_hdmiphy,
};
static struct clksrc_sources exynos4_clkset_sclk_dac = {
.sources = exynos4_clkset_sclk_dac_list,
.nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
};
static struct clksrc_clk exynos4_clk_sclk_dac = {
.clk = {
.name = "sclk_dac",
.enable = exynos4_clksrc_mask_tv_ctrl,
.ctrlbit = (1 << 8),
},
.sources = &exynos4_clkset_sclk_dac,
.reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
};
static struct clksrc_clk exynos4_clk_sclk_pixel = {
.clk = {
.name = "sclk_pixel",
.parent = &exynos4_clk_sclk_vpll.clk,
},
.reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
};
static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
[0] = &exynos4_clk_sclk_pixel.clk,
[1] = &exynos4_clk_sclk_hdmiphy,
};
static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
.sources = exynos4_clkset_sclk_hdmi_list,
.nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
};
static struct clksrc_clk exynos4_clk_sclk_hdmi = {
.clk = {
.name = "sclk_hdmi",
.enable = exynos4_clksrc_mask_tv_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &exynos4_clkset_sclk_hdmi,
.reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
};
static struct clk *exynos4_clkset_sclk_mixer_list[] = {
[0] = &exynos4_clk_sclk_dac.clk,
[1] = &exynos4_clk_sclk_hdmi.clk,
};
static struct clksrc_sources exynos4_clkset_sclk_mixer = {
.sources = exynos4_clkset_sclk_mixer_list,
.nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
};
static struct clksrc_clk exynos4_clk_sclk_mixer = {
.clk = {
.name = "sclk_mixer",
.enable = exynos4_clksrc_mask_tv_ctrl,
.ctrlbit = (1 << 4),
},
.sources = &exynos4_clkset_sclk_mixer,
.reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
};
static struct clksrc_clk *exynos4_sclk_tv[] = {
&exynos4_clk_sclk_dac,
&exynos4_clk_sclk_pixel,
&exynos4_clk_sclk_hdmi,
&exynos4_clk_sclk_mixer,
};
static struct clksrc_clk exynos4_clk_dout_mmc0 = {
.clk = {
.name = "dout_mmc0",
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
};
static struct clksrc_clk exynos4_clk_dout_mmc1 = {
.clk = {
.name = "dout_mmc1",
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
};
static struct clksrc_clk exynos4_clk_dout_mmc2 = {
.clk = {
.name = "dout_mmc2",
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
};
static struct clksrc_clk exynos4_clk_dout_mmc3 = {
.clk = {
.name = "dout_mmc3",
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
};
static struct clksrc_clk exynos4_clk_dout_mmc4 = {
.clk = {
.name = "dout_mmc4",
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
};
static struct clksrc_clk exynos4_clksrcs[] = {
{
.clk = {
.name = "sclk_pwm",
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 24),
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_csis",
.devname = "s5p-mipi-csis.0",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 24),
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
}, {
.clk = {
.name = "sclk_csis",
.devname = "s5p-mipi-csis.1",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 28),
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
}, {
.clk = {
.name = "sclk_cam0",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 16),
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
}, {
.clk = {
.name = "sclk_cam1",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 20),
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
}, {
.clk = {
.name = "sclk_fimc",
.devname = "exynos4-fimc.0",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_fimc",
.devname = "exynos4-fimc.1",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 4),
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
}, {
.clk = {
.name = "sclk_fimc",
.devname = "exynos4-fimc.2",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 8),
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
}, {
.clk = {
.name = "sclk_fimc",
.devname = "exynos4-fimc.3",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 12),
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
}, {
.clk = {
.name = "sclk_fimd",
.devname = "exynos4-fb.0",
.enable = exynos4_clksrc_mask_lcd0_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_mfc",
.devname = "s5p-mfc",
},
.sources = &exynos4_clkset_mout_mfc,
.reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
.reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "ciu",
.parent = &exynos4_clk_dout_mmc4.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 16),
},
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
}
};
static struct clksrc_clk exynos4_clk_sclk_uart0 = {
.clk = {
.name = "uclk1",
.devname = "exynos4210-uart.0",
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
};
static struct clksrc_clk exynos4_clk_sclk_uart1 = {
.clk = {
.name = "uclk1",
.devname = "exynos4210-uart.1",
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 4),
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
};
static struct clksrc_clk exynos4_clk_sclk_uart2 = {
.clk = {
.name = "uclk1",
.devname = "exynos4210-uart.2",
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 8),
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
};
static struct clksrc_clk exynos4_clk_sclk_uart3 = {
.clk = {
.name = "uclk1",
.devname = "exynos4210-uart.3",
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 12),
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
};
static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
.clk = {
.name = "sclk_mmc",
.devname = "exynos4-sdhci.0",
.parent = &exynos4_clk_dout_mmc0.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 0),
},
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
};
static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
.clk = {
.name = "sclk_mmc",
.devname = "exynos4-sdhci.1",
.parent = &exynos4_clk_dout_mmc1.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 4),
},
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
};
static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
.clk = {
.name = "sclk_mmc",
.devname = "exynos4-sdhci.2",
.parent = &exynos4_clk_dout_mmc2.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 8),
},
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
};
static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
.clk = {
.name = "sclk_mmc",
.devname = "exynos4-sdhci.3",
.parent = &exynos4_clk_dout_mmc3.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 12),
},
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
};
static struct clksrc_clk exynos4_clk_mdout_spi0 = {
.clk = {
.name = "mdout_spi",
.devname = "exynos4210-spi.0",
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
};
static struct clksrc_clk exynos4_clk_mdout_spi1 = {
.clk = {
.name = "mdout_spi",
.devname = "exynos4210-spi.1",
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
};
static struct clksrc_clk exynos4_clk_mdout_spi2 = {
.clk = {
.name = "mdout_spi",
.devname = "exynos4210-spi.2",
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
};
static struct clksrc_clk exynos4_clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.0",
.parent = &exynos4_clk_mdout_spi0.clk,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 16),
},
.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
};
static struct clksrc_clk exynos4_clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.1",
.parent = &exynos4_clk_mdout_spi1.clk,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 20),
},
.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
};
static struct clksrc_clk exynos4_clk_sclk_spi2 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.2",
.parent = &exynos4_clk_mdout_spi2.clk,
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 24),
},
.reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
};
/* Clock initialization code */
static struct clksrc_clk *exynos4_sysclks[] = {
&exynos4_clk_mout_apll,
&exynos4_clk_sclk_apll,
&exynos4_clk_mout_epll,
&exynos4_clk_mout_mpll,
&exynos4_clk_moutcore,
&exynos4_clk_coreclk,
&exynos4_clk_armclk,
&exynos4_clk_aclk_corem0,
&exynos4_clk_aclk_cores,
&exynos4_clk_aclk_corem1,
&exynos4_clk_periphclk,
&exynos4_clk_mout_corebus,
&exynos4_clk_sclk_dmc,
&exynos4_clk_aclk_cored,
&exynos4_clk_aclk_corep,
&exynos4_clk_aclk_acp,
&exynos4_clk_pclk_acp,
&exynos4_clk_vpllsrc,
&exynos4_clk_sclk_vpll,
&exynos4_clk_aclk_200,
&exynos4_clk_aclk_100,
&exynos4_clk_aclk_160,
&exynos4_clk_aclk_133,
&exynos4_clk_dout_mmc0,
&exynos4_clk_dout_mmc1,
&exynos4_clk_dout_mmc2,
&exynos4_clk_dout_mmc3,
&exynos4_clk_dout_mmc4,
&exynos4_clk_mout_mfc0,
&exynos4_clk_mout_mfc1,
};
static struct clk *exynos4_clk_cdev[] = {
&exynos4_clk_pdma0,
&exynos4_clk_pdma1,
&exynos4_clk_mdma1,
&exynos4_clk_fimd0,
};
static struct clksrc_clk *exynos4_clksrc_cdev[] = {
&exynos4_clk_sclk_uart0,
&exynos4_clk_sclk_uart1,
&exynos4_clk_sclk_uart2,
&exynos4_clk_sclk_uart3,
&exynos4_clk_sclk_mmc0,
&exynos4_clk_sclk_mmc1,
&exynos4_clk_sclk_mmc2,
&exynos4_clk_sclk_mmc3,
&exynos4_clk_sclk_spi0,
&exynos4_clk_sclk_spi1,
&exynos4_clk_sclk_spi2,
&exynos4_clk_mdout_spi0,
&exynos4_clk_mdout_spi1,
&exynos4_clk_mdout_spi2,
};
static struct clk_lookup exynos4_clk_lookup[] = {
CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
};
static int xtal_rate;
static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
{
if (soc_is_exynos4210())
return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
pll_4508);
else if (soc_is_exynos4212() || soc_is_exynos4412())
return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
else
return 0;
}
static struct clk_ops exynos4_fout_apll_ops = {
.get_rate = exynos4_fout_apll_get_rate,
};
static u32 exynos4_vpll_div[][8] = {
{ 54000000, 3, 53, 3, 1024, 0, 17, 0 },
{ 108000000, 3, 53, 2, 1024, 0, 17, 0 },
};
static unsigned long exynos4_vpll_get_rate(struct clk *clk)
{
return clk->rate;
}
static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
{
unsigned int vpll_con0, vpll_con1 = 0;
unsigned int i;
/* Return if nothing changed */
if (clk->rate == rate)
return 0;
vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
vpll_con0 &= ~(0x1 << 27 | \
PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
if (exynos4_vpll_div[i][0] == rate) {
vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
vpll_con0 |= exynos4_vpll_div[i][7] << 27;
break;
}
}
if (i == ARRAY_SIZE(exynos4_vpll_div)) {
printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
__func__);
return -EINVAL;
}
__raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
__raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
/* Wait for VPLL lock */
while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
continue;
clk->rate = rate;
return 0;
}
static struct clk_ops exynos4_vpll_ops = {
.get_rate = exynos4_vpll_get_rate,
.set_rate = exynos4_vpll_set_rate,
};
void __init_or_cpufreq exynos4_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long apll = 0;
unsigned long mpll = 0;
unsigned long epll = 0;
unsigned long vpll = 0;
unsigned long vpllsrc;
unsigned long xtal;
unsigned long armclk;
unsigned long sclk_dmc;
unsigned long aclk_200;
unsigned long aclk_100;
unsigned long aclk_160;
unsigned long aclk_133;
unsigned int ptr;
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
xtal_clk = clk_get(NULL, "xtal");
BUG_ON(IS_ERR(xtal_clk));
xtal = clk_get_rate(xtal_clk);
xtal_rate = xtal;
clk_put(xtal_clk);
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
if (soc_is_exynos4210()) {
apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
pll_4508);
mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
pll_4508);
epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
__raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
__raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
__raw_readl(EXYNOS4_EPLL_CON1));
vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
__raw_readl(EXYNOS4_VPLL_CON1));
} else {
/* nothing */
}
clk_fout_apll.ops = &exynos4_fout_apll_ops;
clk_fout_mpll.rate = mpll;
clk_fout_epll.rate = epll;
clk_fout_vpll.ops = &exynos4_vpll_ops;
clk_fout_vpll.rate = vpll;
printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
apll, mpll, epll, vpll);
armclk = clk_get_rate(&exynos4_clk_armclk.clk);
sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
"ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
armclk, sclk_dmc, aclk_200,
aclk_100, aclk_160, aclk_133);
clk_f.rate = armclk;
clk_h.rate = sclk_dmc;
clk_p.rate = aclk_100;
for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
}
static struct clk *exynos4_clks[] __initdata = {
&exynos4_clk_sclk_hdmi27m,
&exynos4_clk_sclk_hdmiphy,
&exynos4_clk_sclk_usbphy0,
&exynos4_clk_sclk_usbphy1,
};
#ifdef CONFIG_PM_SLEEP
static int exynos4_clock_suspend(void)
{
s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
return 0;
}
static void exynos4_clock_resume(void)
{
s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
}
#else
#define exynos4_clock_suspend NULL
#define exynos4_clock_resume NULL
#endif
static struct syscore_ops exynos4_clock_syscore_ops = {
.suspend = exynos4_clock_suspend,
.resume = exynos4_clock_resume,
};
void __init exynos4_register_clocks(void)
{
int ptr;
s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
s3c_register_clksrc(exynos4_sysclks[ptr], 1);
for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
register_syscore_ops(&exynos4_clock_syscore_ops);
s3c24xx_register_clock(&dummy_apb_pclk);
s3c_pwmclk_init();
}
arch/arm/mach-exynos/clock-exynos4.h deleted 100644 → 0
View file @ f2585b1c
/*
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Header file for exynos4 clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H __FILE__
#include <linux/clk.h>
extern struct clksrc_clk exynos4_clk_aclk_133;
extern struct clksrc_clk exynos4_clk_mout_mpll;
extern struct clksrc_sources exynos4_clkset_mout_corebus;
extern struct clksrc_sources exynos4_clkset_group;
extern struct clk *exynos4_clkset_aclk_top_list[];
extern struct clk *exynos4_clkset_group_list[];
extern struct clksrc_sources exynos4_clkset_mout_g2d0;
extern struct clksrc_sources exynos4_clkset_mout_g2d1;
extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
#endif /* __ASM_ARCH_CLOCK_H */
arch/arm/mach-exynos/clock-exynos4210.c deleted 100644 → 0
View file @ f2585b1c
/*
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4210 - Clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/syscore_ops.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/pm.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include "common.h"
#include "clock-exynos4.h"
#ifdef CONFIG_PM_SLEEP
static struct sleep_save exynos4210_clock_save[] = {
SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
};
#endif
static struct clksrc_clk *sysclks[] = {
/* nothing here yet */
};
static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
.clk = {
.name = "mout_g2d0",
},
.sources = &exynos4_clkset_mout_g2d0,
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
};
static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
.clk = {
.name = "mout_g2d1",
},
.sources = &exynos4_clkset_mout_g2d1,
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
};
static struct clk *exynos4210_clkset_mout_g2d_list[] = {
[0] = &exynos4210_clk_mout_g2d0.clk,
[1] = &exynos4210_clk_mout_g2d1.clk,
};
static struct clksrc_sources exynos4210_clkset_mout_g2d = {
.sources = exynos4210_clkset_mout_g2d_list,
.nr_sources = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),
};
static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
}
static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_sata",
.id = -1,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 24),
},
.sources = &exynos4_clkset_mout_corebus,
.reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
.reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
}, {
.clk = {
.name = "sclk_fimd",
.devname = "exynos4-fb.1",
.enable = exynos4_clksrc_mask_lcd1_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &exynos4_clkset_group,
.reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
.reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
}, {
.clk = {
.name = "sclk_fimg2d",
},
.sources = &exynos4210_clkset_mout_g2d,
.reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
.reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
},
};
static struct clk init_clocks_off[] = {
{
.name = "sataphy",
.id = -1,
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "sata",
.id = -1,
.parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "fimd",
.devname = "exynos4-fb.1",
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.9",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.11",
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "fimg2d",
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 0),
},
};
#ifdef CONFIG_PM_SLEEP
static int exynos4210_clock_suspend(void)
{
s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
return 0;
}
static void exynos4210_clock_resume(void)
{
s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
}
#else
#define exynos4210_clock_suspend NULL
#define exynos4210_clock_resume NULL
#endif
static struct syscore_ops exynos4210_clock_syscore_ops = {
.suspend = exynos4210_clock_suspend,
.resume = exynos4210_clock_resume,
};
void __init exynos4210_register_clocks(void)
{
int ptr;
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
exynos4_clk_mout_mpll.reg_src.shift = 8;
exynos4_clk_mout_mpll.reg_src.size = 1;
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
register_syscore_ops(&exynos4210_clock_syscore_ops);
}
arch/arm/mach-exynos/clock-exynos4212.c deleted 100644 → 0
View file @ f2585b1c
/*
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS4212 - Clock support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/syscore_ops.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/pm.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include "common.h"
#include "clock-exynos4.h"
#ifdef CONFIG_PM_SLEEP
static struct sleep_save exynos4212_clock_save[] = {
SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
};
#endif
static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
}
static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
}
static struct clk *clk_src_mpll_user_list[] = {
[0] = &clk_fin_mpll,
[1] = &exynos4_clk_mout_mpll.clk,
};
static struct clksrc_sources clk_src_mpll_user = {
.sources = clk_src_mpll_user_list,
.nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
};
static struct clksrc_clk clk_mout_mpll_user = {
.clk = {
.name = "mout_mpll_user",
},
.sources = &clk_src_mpll_user,
.reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
};
static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
.clk = {
.name = "mout_g2d0",
},
.sources = &exynos4_clkset_mout_g2d0,
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
};
static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
.clk = {
.name = "mout_g2d1",
},
.sources = &exynos4_clkset_mout_g2d1,
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
};
static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
[0] = &exynos4x12_clk_mout_g2d0.clk,
[1] = &exynos4x12_clk_mout_g2d1.clk,
};
static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
.sources = exynos4x12_clkset_mout_g2d_list,
.nr_sources = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
};
static struct clksrc_clk *sysclks[] = {
&clk_mout_mpll_user,
};
static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_fimg2d",
},
.sources = &exynos4x12_clkset_mout_g2d,
.reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
.reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
},
};
static struct clk init_clocks_off[] = {
{
.name = "sysmmu",
.devname = "exynos-sysmmu.9",
.enable = exynos4_clk_ip_dmc_ctrl,
.ctrlbit = (1 << 24),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.12",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (7 << 8),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.13",
.enable = exynos4212_clk_ip_isp1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.14",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.15",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "flite",
.devname = "exynos-fimc-lite.0",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "flite",
.devname = "exynos-fimc-lite.1",
.enable = exynos4212_clk_ip_isp0_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "fimg2d",
.enable = exynos4_clk_ip_dmc_ctrl,
.ctrlbit = (1 << 23),
},
};
#ifdef CONFIG_PM_SLEEP
static int exynos4212_clock_suspend(void)
{
s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
return 0;
}
static void exynos4212_clock_resume(void)
{
s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
}
#else
#define exynos4212_clock_suspend NULL
#define exynos4212_clock_resume NULL
#endif
static struct syscore_ops exynos4212_clock_syscore_ops = {
.suspend = exynos4212_clock_suspend,
.resume = exynos4212_clock_resume,
};
void __init exynos4212_register_clocks(void)
{
int ptr;
/* usbphy1 is removed */
exynos4_clkset_group_list[4] = NULL;
/* mout_mpll_user is used */
exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
exynos4_clk_mout_mpll.reg_src.shift = 12;
exynos4_clk_mout_mpll.reg_src.size = 1;
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
s3c_register_clksrc(sysclks[ptr], 1);
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
register_syscore_ops(&exynos4212_clock_syscore_ops);
}
arch/arm/mach-exynos/clock-exynos5.c deleted 100644 → 0
View file @ f2585b1c
/*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Clock support for EXYNOS5 SoCs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/syscore_ops.h>
#include <plat/cpu-freq.h>
#include <plat/clock.h>
#include <plat/cpu.h>
#include <plat/pll.h>
#include <plat/s5p-clock.h>
#include <plat/clock-clksrc.h>
#include <plat/pm.h>
#include <mach/map.h>
#include <mach/regs-clock.h>
#include "common.h"
#ifdef CONFIG_PM_SLEEP
static struct sleep_save exynos5_clock_save[] = {
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
SAVE_ITEM(EXYNOS5_EPLL_CON0),
SAVE_ITEM(EXYNOS5_EPLL_CON1),
SAVE_ITEM(EXYNOS5_EPLL_CON2),
SAVE_ITEM(EXYNOS5_VPLL_CON0),
SAVE_ITEM(EXYNOS5_VPLL_CON1),
SAVE_ITEM(EXYNOS5_VPLL_CON2),
SAVE_ITEM(EXYNOS5_PWR_CTRL1),
SAVE_ITEM(EXYNOS5_PWR_CTRL2),
};
#endif
static struct clk exynos5_clk_sclk_dptxphy = {
.name = "sclk_dptx",
};
static struct clk exynos5_clk_sclk_hdmi24m = {
.name = "sclk_hdmi24m",
.rate = 24000000,
};
static struct clk exynos5_clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m",
.rate = 27000000,
};
static struct clk exynos5_clk_sclk_hdmiphy = {
.name = "sclk_hdmiphy",
};
static struct clk exynos5_clk_sclk_usbphy = {
.name = "sclk_usbphy",
.rate = 48000000,
};
static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
}
static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
}
static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
}
static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
}
static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
}
static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
}
static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
}
static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
}
static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
}
static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
}
static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
}
static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
}
static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
}
static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
}
static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
}
static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
}
static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
}
static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
}
static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable)
{
return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
}
/* Core list of CMU_CPU side */
static struct clksrc_clk exynos5_clk_mout_apll = {
.clk = {
.name = "mout_apll",
},
.sources = &clk_src_apll,
.reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
};
static struct clksrc_clk exynos5_clk_sclk_apll = {
.clk = {
.name = "sclk_apll",
.parent = &exynos5_clk_mout_apll.clk,
},
.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
};
static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
.clk = {
.name = "mout_bpll_fout",
},
.sources = &clk_src_bpll_fout,
.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
};
static struct clk *exynos5_clk_src_bpll_list[] = {
[0] = &clk_fin_bpll,
[1] = &exynos5_clk_mout_bpll_fout.clk,
};
static struct clksrc_sources exynos5_clk_src_bpll = {
.sources = exynos5_clk_src_bpll_list,
.nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_list),
};
static struct clksrc_clk exynos5_clk_mout_bpll = {
.clk = {
.name = "mout_bpll",
},
.sources = &exynos5_clk_src_bpll,
.reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
};
static struct clk *exynos5_clk_src_bpll_user_list[] = {
[0] = &clk_fin_mpll,
[1] = &exynos5_clk_mout_bpll.clk,
};
static struct clksrc_sources exynos5_clk_src_bpll_user = {
.sources = exynos5_clk_src_bpll_user_list,
.nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
};
static struct clksrc_clk exynos5_clk_mout_bpll_user = {
.clk = {
.name = "mout_bpll_user",
},
.sources = &exynos5_clk_src_bpll_user,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
};
static struct clksrc_clk exynos5_clk_mout_cpll = {
.clk = {
.name = "mout_cpll",
},
.sources = &clk_src_cpll,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
};
static struct clksrc_clk exynos5_clk_mout_epll = {
.clk = {
.name = "mout_epll",
},
.sources = &clk_src_epll,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
};
static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
.clk = {
.name = "mout_mpll_fout",
},
.sources = &clk_src_mpll_fout,
.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
};
static struct clk *exynos5_clk_src_mpll_list[] = {
[0] = &clk_fin_mpll,
[1] = &exynos5_clk_mout_mpll_fout.clk,
};
static struct clksrc_sources exynos5_clk_src_mpll = {
.sources = exynos5_clk_src_mpll_list,
.nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list),
};
static struct clksrc_clk exynos5_clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
},
.sources = &exynos5_clk_src_mpll,
.reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
};
static struct clk *exynos_clkset_vpllsrc_list[] = {
[0] = &clk_fin_vpll,
[1] = &exynos5_clk_sclk_hdmi27m,
};
static struct clksrc_sources exynos5_clkset_vpllsrc = {
.sources = exynos_clkset_vpllsrc_list,
.nr_sources = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
};
static struct clksrc_clk exynos5_clk_vpllsrc = {
.clk = {
.name = "vpll_src",
.enable = exynos5_clksrc_mask_top_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &exynos5_clkset_vpllsrc,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
};
static struct clk *exynos5_clkset_sclk_vpll_list[] = {
[0] = &exynos5_clk_vpllsrc.clk,
[1] = &clk_fout_vpll,
};
static struct clksrc_sources exynos5_clkset_sclk_vpll = {
.sources = exynos5_clkset_sclk_vpll_list,
.nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
};
static struct clksrc_clk exynos5_clk_sclk_vpll = {
.clk = {
.name = "sclk_vpll",
},
.sources = &exynos5_clkset_sclk_vpll,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
};
static struct clksrc_clk exynos5_clk_sclk_pixel = {
.clk = {
.name = "sclk_pixel",
.parent = &exynos5_clk_sclk_vpll.clk,
},
.reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
};
static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
[0] = &exynos5_clk_sclk_pixel.clk,
[1] = &exynos5_clk_sclk_hdmiphy,
};
static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
.sources = exynos5_clkset_sclk_hdmi_list,
.nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
};
static struct clksrc_clk exynos5_clk_sclk_hdmi = {
.clk = {
.name = "sclk_hdmi",
.enable = exynos5_clksrc_mask_disp1_0_ctrl,
.ctrlbit = (1 << 20),
},
.sources = &exynos5_clkset_sclk_hdmi,
.reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
};
static struct clksrc_clk *exynos5_sclk_tv[] = {
&exynos5_clk_sclk_pixel,
&exynos5_clk_sclk_hdmi,
};
static struct clk *exynos5_clk_src_mpll_user_list[] = {
[0] = &clk_fin_mpll,
[1] = &exynos5_clk_mout_mpll.clk,
};
static struct clksrc_sources exynos5_clk_src_mpll_user = {
.sources = exynos5_clk_src_mpll_user_list,
.nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
};
static struct clksrc_clk exynos5_clk_mout_mpll_user = {
.clk = {
.name = "mout_mpll_user",
},
.sources = &exynos5_clk_src_mpll_user,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
};
static struct clk *exynos5_clkset_mout_cpu_list[] = {
[0] = &exynos5_clk_mout_apll.clk,
[1] = &exynos5_clk_mout_mpll.clk,
};
static struct clksrc_sources exynos5_clkset_mout_cpu = {
.sources = exynos5_clkset_mout_cpu_list,
.nr_sources = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
};
static struct clksrc_clk exynos5_clk_mout_cpu = {
.clk = {
.name = "mout_cpu",
},
.sources = &exynos5_clkset_mout_cpu,
.reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
};
static struct clksrc_clk exynos5_clk_dout_armclk = {
.clk = {
.name = "dout_armclk",
.parent = &exynos5_clk_mout_cpu.clk,
},
.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
};
static struct clksrc_clk exynos5_clk_dout_arm2clk = {
.clk = {
.name = "dout_arm2clk",
.parent = &exynos5_clk_dout_armclk.clk,
},
.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
};
static struct clk exynos5_clk_armclk = {
.name = "armclk",
.parent = &exynos5_clk_dout_arm2clk.clk,
};
/* Core list of CMU_CDREX side */
static struct clk *exynos5_clkset_cdrex_list[] = {
[0] = &exynos5_clk_mout_mpll.clk,
[1] = &exynos5_clk_mout_bpll.clk,
};
static struct clksrc_sources exynos5_clkset_cdrex = {
.sources = exynos5_clkset_cdrex_list,
.nr_sources = ARRAY_SIZE(exynos5_clkset_cdrex_list),
};
static struct clksrc_clk exynos5_clk_cdrex = {
.clk = {
.name = "clk_cdrex",
},
.sources = &exynos5_clkset_cdrex,
.reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
.reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
};
static struct clksrc_clk exynos5_clk_aclk_acp = {
.clk = {
.name = "aclk_acp",
.parent = &exynos5_clk_mout_mpll.clk,
},
.reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
};
static struct clksrc_clk exynos5_clk_pclk_acp = {
.clk = {
.name = "pclk_acp",
.parent = &exynos5_clk_aclk_acp.clk,
},
.reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
};
/* Core list of CMU_TOP side */
static struct clk *exynos5_clkset_aclk_top_list[] = {
[0] = &exynos5_clk_mout_mpll_user.clk,
[1] = &exynos5_clk_mout_bpll_user.clk,
};
static struct clksrc_sources exynos5_clkset_aclk = {
.sources = exynos5_clkset_aclk_top_list,
.nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
};
static struct clksrc_clk exynos5_clk_aclk_400 = {
.clk = {
.name = "aclk_400",
},
.sources = &exynos5_clkset_aclk,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
};
static struct clk *exynos5_clkset_aclk_333_166_list[] = {
[0] = &exynos5_clk_mout_cpll.clk,
[1] = &exynos5_clk_mout_mpll_user.clk,
};
static struct clksrc_sources exynos5_clkset_aclk_333_166 = {
.sources = exynos5_clkset_aclk_333_166_list,
.nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
};
static struct clksrc_clk exynos5_clk_aclk_333 = {
.clk = {
.name = "aclk_333",
},
.sources = &exynos5_clkset_aclk_333_166,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
};
static struct clksrc_clk exynos5_clk_aclk_166 = {
.clk = {
.name = "aclk_166",
},
.sources = &exynos5_clkset_aclk_333_166,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
};
static struct clksrc_clk exynos5_clk_aclk_266 = {
.clk = {
.name = "aclk_266",
.parent = &exynos5_clk_mout_mpll_user.clk,
},
.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
};
static struct clksrc_clk exynos5_clk_aclk_200 = {
.clk = {
.name = "aclk_200",
},
.sources = &exynos5_clkset_aclk,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
};
static struct clksrc_clk exynos5_clk_aclk_66_pre = {
.clk = {
.name = "aclk_66_pre",
.parent = &exynos5_clk_mout_mpll_user.clk,
},
.reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
};
static struct clksrc_clk exynos5_clk_aclk_66 = {
.clk = {
.name = "aclk_66",
.parent = &exynos5_clk_aclk_66_pre.clk,
},
.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
};
static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
.clk = {
.name = "mout_aclk_300_gscl_mid",
},
.sources = &exynos5_clkset_aclk,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
};
static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
[0] = &exynos5_clk_sclk_vpll.clk,
[1] = &exynos5_clk_mout_cpll.clk,
};
static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
.sources = exynos5_clkset_aclk_300_mid1_list,
.nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
};
static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
.clk = {
.name = "mout_aclk_300_gscl_mid1",
},
.sources = &exynos5_clkset_aclk_300_gscl_mid1,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
};
static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
[0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
[1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
};
static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
.sources = exynos5_clkset_aclk_300_gscl_list,
.nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
};
static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
.clk = {
.name = "mout_aclk_300_gscl",
},
.sources = &exynos5_clkset_aclk_300_gscl,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
};
static struct clk *exynos5_clk_src_gscl_300_list[] = {
[0] = &clk_ext_xtal_mux,
[1] = &exynos5_clk_mout_aclk_300_gscl.clk,
};
static struct clksrc_sources exynos5_clk_src_gscl_300 = {
.sources = exynos5_clk_src_gscl_300_list,
.nr_sources = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
};
static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
.clk = {
.name = "aclk_300_gscl",
},
.sources = &exynos5_clk_src_gscl_300,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
};
static struct clk exynos5_init_clocks_off[] = {
{
.name = "timers",
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 24),
}, {
.name = "tmu_apbif",
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peris_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "rtc",
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peris_ctrl,
.ctrlbit = (1 << 20),
}, {
.name = "watchdog",
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peris_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "biu", /* bus interface unit clock */
.devname = "dw_mmc.0",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "biu",
.devname = "dw_mmc.1",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 13),
}, {
.name = "biu",
.devname = "dw_mmc.2",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 14),
}, {
.name = "biu",
.devname = "dw_mmc.3",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "sata",
.devname = "exynos5-sata",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "sata-phy",
.devname = "exynos5-sata-phy",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 24),
}, {
.name = "i2c",
.devname = "exynos5-sata-phy-i2c",
.parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "mfc",
.devname = "s5p-mfc-v6",
.enable = exynos5_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "hdmi",
.devname = "exynos5-hdmi",
.enable = exynos5_clk_ip_disp1_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "hdmiphy",
.devname = "exynos5-hdmi",
.enable = exynos5_clk_hdmiphy_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "mixer",
.devname = "exynos5-mixer",
.enable = exynos5_clk_ip_disp1_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "dp",
.devname = "exynos-dp",
.enable = exynos5_clk_ip_disp1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "jpeg",
.enable = exynos5_clk_ip_gen_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "dsim0",
.enable = exynos5_clk_ip_disp1_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "iis",
.devname = "samsung-i2s.1",
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 20),
}, {
.name = "iis",
.devname = "samsung-i2s.2",
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "pcm",
.devname = "samsung-pcm.1",
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "pcm",
.devname = "samsung-pcm.2",
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 23),
}, {
.name = "spdif",
.devname = "samsung-spdif",
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 26),
}, {
.name = "ac97",
.devname = "samsung-ac97",
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 27),
}, {
.name = "usbhost",
.enable = exynos5_clk_ip_fsys_ctrl ,
.ctrlbit = (1 << 18),
}, {
.name = "usbotg",
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "nfcon",
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "iop",
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = ((1 << 30) | (1 << 26) | (1 << 23)),
}, {
.name = "core_iop",
.enable = exynos5_clk_ip_core_ctrl,
.ctrlbit = ((1 << 21) | (1 << 3)),
}, {
.name = "mcu_iop",
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "i2c",
.devname = "s3c2440-i2c.0",
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "i2c",
.devname = "s3c2440-i2c.1",
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "i2c",
.devname = "s3c2440-i2c.2",
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "i2c",
.devname = "s3c2440-i2c.3",
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "i2c",
.devname = "s3c2440-i2c.4",
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "i2c",
.devname = "s3c2440-i2c.5",
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "i2c",
.devname = "s3c2440-i2c.6",
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "i2c",
.devname = "s3c2440-i2c.7",
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 13),
}, {
.name = "i2c",
.devname = "s3c2440-hdmiphy-i2c",
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 14),
}, {
.name = "spi",
.devname = "exynos4210-spi.0",
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "spi",
.devname = "exynos4210-spi.1",
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "spi",
.devname = "exynos4210-spi.2",
.parent = &exynos5_clk_aclk_66.clk,
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "gscl",
.devname = "exynos-gsc.0",
.enable = exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "gscl",
.devname = "exynos-gsc.1",
.enable = exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "gscl",
.devname = "exynos-gsc.2",
.enable = exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "gscl",
.devname = "exynos-gsc.3",
.enable = exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.1",
.enable = &exynos5_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.0",
.enable = &exynos5_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.2",
.enable = &exynos5_clk_ip_disp1_ctrl,
.ctrlbit = (1 << 9)
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.3",
.enable = &exynos5_clk_ip_gen_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.4",
.enable = &exynos5_clk_ip_gen_ctrl,
.ctrlbit = (1 << 6)
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.5",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.6",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.7",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.8",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.9",
.enable = &exynos5_clk_ip_isp0_ctrl,
.ctrlbit = (0x3F << 8),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.10",
.enable = &exynos5_clk_ip_isp1_ctrl,
.ctrlbit = (0xF << 4),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.11",
.enable = &exynos5_clk_ip_disp1_ctrl,
.ctrlbit = (1 << 8)
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.12",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.13",
.enable = &exynos5_clk_ip_gscl_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "sysmmu",
.devname = "exynos-sysmmu.14",
.enable = &exynos5_clk_ip_acp_ctrl,
.ctrlbit = (1 << 7)
}
};
static struct clk exynos5_init_clocks_on[] = {
{
.name = "uart",
.devname = "s5pv210-uart.0",
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "uart",
.devname = "s5pv210-uart.1",
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
.devname = "s5pv210-uart.2",
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
.devname = "s5pv210-uart.3",
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
.devname = "s5pv210-uart.4",
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "uart",
.devname = "s5pv210-uart.5",
.enable = exynos5_clk_ip_peric_ctrl,
.ctrlbit = (1 << 5),
}
};
static struct clk exynos5_clk_pdma0 = {
.name = "dma",
.devname = "dma-pl330.0",
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 1),
};
static struct clk exynos5_clk_pdma1 = {
.name = "dma",
.devname = "dma-pl330.1",
.enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 2),
};
static struct clk exynos5_clk_mdma1 = {
.name = "dma",
.devname = "dma-pl330.2",
.enable = exynos5_clk_ip_gen_ctrl,
.ctrlbit = (1 << 4),
};
static struct clk exynos5_clk_fimd1 = {
.name = "fimd",
.devname = "exynos5-fb.1",
.enable = exynos5_clk_ip_disp1_ctrl,
.ctrlbit = (1 << 0),
};
static struct clk *exynos5_clkset_group_list[] = {
[0] = &clk_ext_xtal_mux,
[1] = NULL,
[2] = &exynos5_clk_sclk_hdmi24m,
[3] = &exynos5_clk_sclk_dptxphy,
[4] = &exynos5_clk_sclk_usbphy,
[5] = &exynos5_clk_sclk_hdmiphy,
[6] = &exynos5_clk_mout_mpll_user.clk,
[7] = &exynos5_clk_mout_epll.clk,
[8] = &exynos5_clk_sclk_vpll.clk,
[9] = &exynos5_clk_mout_cpll.clk,
};
static struct clksrc_sources exynos5_clkset_group = {
.sources = exynos5_clkset_group_list,
.nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
};
/* Possible clock sources for aclk_266_gscl_sub Mux */
static struct clk *clk_src_gscl_266_list[] = {
[0] = &clk_ext_xtal_mux,
[1] = &exynos5_clk_aclk_266.clk,
};
static struct clksrc_sources clk_src_gscl_266 = {
.sources = clk_src_gscl_266_list,
.nr_sources = ARRAY_SIZE(clk_src_gscl_266_list),
};
static struct clksrc_clk exynos5_clk_dout_mmc0 = {
.clk = {
.name = "dout_mmc0",
},
.sources = &exynos5_clkset_group,
.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
};
static struct clksrc_clk exynos5_clk_dout_mmc1 = {
.clk = {
.name = "dout_mmc1",
},
.sources = &exynos5_clkset_group,
.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
};
static struct clksrc_clk exynos5_clk_dout_mmc2 = {
.clk = {
.name = "dout_mmc2",
},
.sources = &exynos5_clkset_group,
.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
};
static struct clksrc_clk exynos5_clk_dout_mmc3 = {
.clk = {
.name = "dout_mmc3",
},
.sources = &exynos5_clkset_group,
.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
};
static struct clksrc_clk exynos5_clk_dout_mmc4 = {
.clk = {
.name = "dout_mmc4",
},
.sources = &exynos5_clkset_group,
.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
};
static struct clksrc_clk exynos5_clk_sclk_uart0 = {
.clk = {
.name = "uclk1",
.devname = "exynos4210-uart.0",
.enable = exynos5_clksrc_mask_peric0_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &exynos5_clkset_group,
.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
};
static struct clksrc_clk exynos5_clk_sclk_uart1 = {
.clk = {
.name = "uclk1",
.devname = "exynos4210-uart.1",
.enable = exynos5_clksrc_mask_peric0_ctrl,
.ctrlbit = (1 << 4),
},
.sources = &exynos5_clkset_group,
.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
};
static struct clksrc_clk exynos5_clk_sclk_uart2 = {
.clk = {
.name = "uclk1",
.devname = "exynos4210-uart.2",
.enable = exynos5_clksrc_mask_peric0_ctrl,
.ctrlbit = (1 << 8),
},
.sources = &exynos5_clkset_group,
.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
};
static struct clksrc_clk exynos5_clk_sclk_uart3 = {
.clk = {
.name = "uclk1",
.devname = "exynos4210-uart.3",
.enable = exynos5_clksrc_mask_peric0_ctrl,
.ctrlbit = (1 << 12),
},
.sources = &exynos5_clkset_group,
.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
};
static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
.clk = {
.name = "ciu", /* card interface unit clock */
.devname = "dw_mmc.0",
.parent = &exynos5_clk_dout_mmc0.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 0),
},
.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
};
static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
.clk = {
.name = "ciu",
.devname = "dw_mmc.1",
.parent = &exynos5_clk_dout_mmc1.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 4),
},
.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
};
static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
.clk = {
.name = "ciu",
.devname = "dw_mmc.2",
.parent = &exynos5_clk_dout_mmc2.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 8),
},
.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
};
static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
.clk = {
.name = "ciu",
.devname = "dw_mmc.3",
.parent = &exynos5_clk_dout_mmc3.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 12),
},
.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
};
static struct clksrc_clk exynos5_clk_mdout_spi0 = {
.clk = {
.name = "mdout_spi",
.devname = "exynos4210-spi.0",
},
.sources = &exynos5_clkset_group,
.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
};
static struct clksrc_clk exynos5_clk_mdout_spi1 = {
.clk = {
.name = "mdout_spi",
.devname = "exynos4210-spi.1",
},
.sources = &exynos5_clkset_group,
.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
};
static struct clksrc_clk exynos5_clk_mdout_spi2 = {
.clk = {
.name = "mdout_spi",
.devname = "exynos4210-spi.2",
},
.sources = &exynos5_clkset_group,
.reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
};
static struct clksrc_clk exynos5_clk_sclk_spi0 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.0",
.parent = &exynos5_clk_mdout_spi0.clk,
.enable = exynos5_clksrc_mask_peric1_ctrl,
.ctrlbit = (1 << 16),
},
.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
};
static struct clksrc_clk exynos5_clk_sclk_spi1 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.1",
.parent = &exynos5_clk_mdout_spi1.clk,
.enable = exynos5_clksrc_mask_peric1_ctrl,
.ctrlbit = (1 << 20),
},
.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
};
static struct clksrc_clk exynos5_clk_sclk_spi2 = {
.clk = {
.name = "sclk_spi",
.devname = "exynos4210-spi.2",
.parent = &exynos5_clk_mdout_spi2.clk,
.enable = exynos5_clksrc_mask_peric1_ctrl,
.ctrlbit = (1 << 24),
},
.reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
};
static struct clksrc_clk exynos5_clk_sclk_fimd1 = {
.clk = {
.name = "sclk_fimd",
.devname = "exynos5-fb.1",
.enable = exynos5_clksrc_mask_disp1_0_ctrl,
.ctrlbit = (1 << 0),
},
.sources = &exynos5_clkset_group,
.reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
.reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
};
static struct clksrc_clk exynos5_clksrcs[] = {
{
.clk = {
.name = "aclk_266_gscl",
},
.sources = &clk_src_gscl_266,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
}, {
.clk = {
.name = "sclk_g3d",
.devname = "mali-t604.0",
.enable = exynos5_clk_block_ctrl,
.ctrlbit = (1 << 1),
},
.sources = &exynos5_clkset_aclk,
.reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
.reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
}, {
.clk = {
.name = "sclk_sata",
.devname = "exynos5-sata",
.enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 24),
},
.sources = &exynos5_clkset_aclk,
.reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
.reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
}, {
.clk = {
.name = "sclk_gscl_wrap",
.devname = "s5p-mipi-csis.0",
.enable = exynos5_clksrc_mask_gscl_ctrl,
.ctrlbit = (1 << 24),
},
.sources = &exynos5_clkset_group,
.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
}, {
.clk = {
.name = "sclk_gscl_wrap",
.devname = "s5p-mipi-csis.1",
.enable = exynos5_clksrc_mask_gscl_ctrl,
.ctrlbit = (1 << 28),
},
.sources = &exynos5_clkset_group,
.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
}, {
.clk = {
.name = "sclk_cam0",
.enable = exynos5_clksrc_mask_gscl_ctrl,
.ctrlbit = (1 << 16),
},
.sources = &exynos5_clkset_group,
.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
}, {
.clk = {
.name = "sclk_cam1",
.enable = exynos5_clksrc_mask_gscl_ctrl,
.ctrlbit = (1 << 20),
},
.sources = &exynos5_clkset_group,
.reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
.reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
}, {
.clk = {
.name = "sclk_jpeg",
.parent = &exynos5_clk_mout_cpll.clk,
},
.reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
},
};
/* Clock initialization code */
static struct clksrc_clk *exynos5_sysclks[] = {
&exynos5_clk_mout_apll,
&exynos5_clk_sclk_apll,
&exynos5_clk_mout_bpll,
&exynos5_clk_mout_bpll_fout,
&exynos5_clk_mout_bpll_user,
&exynos5_clk_mout_cpll,
&exynos5_clk_mout_epll,
&exynos5_clk_mout_mpll,
&exynos5_clk_mout_mpll_fout,
&exynos5_clk_mout_mpll_user,
&exynos5_clk_vpllsrc,
&exynos5_clk_sclk_vpll,
&exynos5_clk_mout_cpu,
&exynos5_clk_dout_armclk,
&exynos5_clk_dout_arm2clk,
&exynos5_clk_cdrex,
&exynos5_clk_aclk_400,
&exynos5_clk_aclk_333,
&exynos5_clk_aclk_266,
&exynos5_clk_aclk_200,
&exynos5_clk_aclk_166,
&exynos5_clk_aclk_300_gscl,
&exynos5_clk_mout_aclk_300_gscl,
&exynos5_clk_mout_aclk_300_gscl_mid,
&exynos5_clk_mout_aclk_300_gscl_mid1,
&exynos5_clk_aclk_66_pre,
&exynos5_clk_aclk_66,
&exynos5_clk_dout_mmc0,
&exynos5_clk_dout_mmc1,
&exynos5_clk_dout_mmc2,
&exynos5_clk_dout_mmc3,
&exynos5_clk_dout_mmc4,
&exynos5_clk_aclk_acp,
&exynos5_clk_pclk_acp,
&exynos5_clk_sclk_spi0,
&exynos5_clk_sclk_spi1,
&exynos5_clk_sclk_spi2,
&exynos5_clk_mdout_spi0,
&exynos5_clk_mdout_spi1,
&exynos5_clk_mdout_spi2,
&exynos5_clk_sclk_fimd1,
};
static struct clk *exynos5_clk_cdev[] = {
&exynos5_clk_pdma0,
&exynos5_clk_pdma1,
&exynos5_clk_mdma1,
&exynos5_clk_fimd1,
};
static struct clksrc_clk *exynos5_clksrc_cdev[] = {
&exynos5_clk_sclk_uart0,
&exynos5_clk_sclk_uart1,
&exynos5_clk_sclk_uart2,
&exynos5_clk_sclk_uart3,
&exynos5_clk_sclk_mmc0,
&exynos5_clk_sclk_mmc1,
&exynos5_clk_sclk_mmc2,
&exynos5_clk_sclk_mmc3,
};
static struct clk_lookup exynos5_clk_lookup[] = {
CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
};
static unsigned long exynos5_epll_get_rate(struct clk *clk)
{
return clk->rate;
}
static struct clk *exynos5_clks[] __initdata = {
&exynos5_clk_sclk_hdmi27m,
&exynos5_clk_sclk_hdmiphy,
&clk_fout_bpll,
&clk_fout_bpll_div2,
&clk_fout_cpll,
&clk_fout_mpll_div2,
&exynos5_clk_armclk,
};
static u32 epll_div[][6] = {
{ 192000000, 0, 48, 3, 1, 0 },
{ 180000000, 0, 45, 3, 1, 0 },
{ 73728000, 1, 73, 3, 3, 47710 },
{ 67737600, 1, 90, 4, 3, 20762 },
{ 49152000, 0, 49, 3, 3, 9961 },
{ 45158400, 0, 45, 3, 3, 10381 },
{ 180633600, 0, 45, 3, 1, 10381 },
};
static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
{
unsigned int epll_con, epll_con_k;
unsigned int i;
unsigned int tmp;
unsigned int epll_rate;
unsigned int locktime;
unsigned int lockcnt;
/* Return if nothing changed */
if (clk->rate == rate)
return 0;
if (clk->parent)
epll_rate = clk_get_rate(clk->parent);
else
epll_rate = clk_ext_xtal_mux.rate;
if (epll_rate != 24000000) {
pr_err("Invalid Clock : recommended clock is 24MHz.\n");
return -EINVAL;
}
epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
epll_con &= ~(0x1 << 27 | \
PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
if (epll_div[i][0] == rate) {
epll_con_k = epll_div[i][5] << 0;
epll_con |= epll_div[i][1] << 27;
epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
break;
}
}
if (i == ARRAY_SIZE(epll_div)) {
printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
__func__);
return -EINVAL;
}
epll_rate /= 1000000;
/* 3000 max_cycls : specification data */
locktime = 3000 / epll_rate * epll_div[i][3];
lockcnt = locktime * 10000 / (10000 / epll_rate);
__raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
__raw_writel(epll_con, EXYNOS5_EPLL_CON0);
__raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
do {
tmp = __raw_readl(EXYNOS5_EPLL_CON0);
} while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
clk->rate = rate;
return 0;
}
static struct clk_ops exynos5_epll_ops = {
.get_rate = exynos5_epll_get_rate,
.set_rate = exynos5_epll_set_rate,
};
static int xtal_rate;
static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
{
return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
}
static struct clk_ops exynos5_fout_apll_ops = {
.get_rate = exynos5_fout_apll_get_rate,
};
#ifdef CONFIG_PM
static int exynos5_clock_suspend(void)
{
s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
return 0;
}
static void exynos5_clock_resume(void)
{
s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
}
#else
#define exynos5_clock_suspend NULL
#define exynos5_clock_resume NULL
#endif
static struct syscore_ops exynos5_clock_syscore_ops = {
.suspend = exynos5_clock_suspend,
.resume = exynos5_clock_resume,
};
void __init_or_cpufreq exynos5_setup_clocks(void)
{
struct clk *xtal_clk;
unsigned long apll;
unsigned long bpll;
unsigned long cpll;
unsigned long mpll;
unsigned long epll;
unsigned long vpll;
unsigned long vpllsrc;
unsigned long xtal;
unsigned long armclk;
unsigned long mout_cdrex;
unsigned long aclk_400;
unsigned long aclk_333;
unsigned long aclk_266;
unsigned long aclk_200;
unsigned long aclk_166;
unsigned long aclk_66;
unsigned int ptr;
printk(KERN_DEBUG "%s: registering clocks\n", __func__);
xtal_clk = clk_get(NULL, "xtal");
BUG_ON(IS_ERR(xtal_clk));
xtal = clk_get_rate(xtal_clk);
xtal_rate = xtal;
clk_put(xtal_clk);
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
__raw_readl(EXYNOS5_EPLL_CON1));
vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
__raw_readl(EXYNOS5_VPLL_CON1));
clk_fout_apll.ops = &exynos5_fout_apll_ops;
clk_fout_bpll.rate = bpll;
clk_fout_bpll_div2.rate = bpll >> 1;
clk_fout_cpll.rate = cpll;
clk_fout_mpll.rate = mpll;
clk_fout_mpll_div2.rate = mpll >> 1;
clk_fout_epll.rate = epll;
clk_fout_vpll.rate = vpll;
printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
"M=%ld, E=%ld V=%ld",
apll, bpll, cpll, mpll, epll, vpll);
armclk = clk_get_rate(&exynos5_clk_armclk);
mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
"ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
"ACLK166=%ld, ACLK66=%ld\n",
armclk, mout_cdrex, aclk_400,
aclk_333, aclk_266, aclk_200,
aclk_166, aclk_66);
clk_fout_epll.ops = &exynos5_epll_ops;
if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
}
void __init exynos5_register_clocks(void)
{
int ptr;
s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
s3c_register_clksrc(exynos5_sysclks[ptr], 1);
for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
register_syscore_ops(&exynos5_clock_syscore_ops);
s3c_pwmclk_init();
}
arch/arm/mach-exynos/common.c
View file @ 6e6aac75
......@@ -39,7 +39,6 @@
#include <mach/regs-gpio.h>
#include <plat/cpu.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/pm.h>
#include <plat/sdhci.h>
......@@ -65,8 +64,6 @@ static const char name_exynos5440[] = "EXYNOS5440";
static void exynos4_map_io(void);
static void exynos5_map_io(void);
static void exynos5440_map_io(void);
static void exynos4_init_clocks(int xtal);
static void exynos5_init_clocks(int xtal);
static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
static int exynos_init(void);
......@@ -75,7 +72,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = EXYNOS4210_CPU_ID,
.idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io,
.init_clocks = exynos4_init_clocks,
.init_uarts = exynos4_init_uarts,
.init = exynos_init,
.name = name_exynos4210,
......@@ -83,7 +79,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = EXYNOS4212_CPU_ID,
.idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io,
.init_clocks = exynos4_init_clocks,
.init_uarts = exynos4_init_uarts,
.init = exynos_init,
.name = name_exynos4212,
......@@ -91,7 +86,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = EXYNOS4412_CPU_ID,
.idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io,
.init_clocks = exynos4_init_clocks,
.init_uarts = exynos4_init_uarts,
.init = exynos_init,
.name = name_exynos4412,
......@@ -99,7 +93,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = EXYNOS5250_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
.init_clocks = exynos5_init_clocks,
.init = exynos_init,
.name = name_exynos5250,
}, {
......@@ -397,45 +390,11 @@ static void __init exynos5_map_io(void)
iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
}
static void __init exynos4_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
s3c24xx_register_baseclocks(xtal);
s5p_register_clocks(xtal);
if (soc_is_exynos4210())
exynos4210_register_clocks();
else if (soc_is_exynos4212() || soc_is_exynos4412())
exynos4212_register_clocks();
exynos4_register_clocks();
exynos4_setup_clocks();
}
static void __init exynos5440_map_io(void)
{
iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
}
static void __init exynos5_init_clocks(int xtal)
{
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
/* EXYNOS5440 can support only common clock framework */
if (soc_is_exynos5440())
return;
#ifdef CONFIG_SOC_EXYNOS5250
s3c24xx_register_baseclocks(xtal);
s5p_register_clocks(xtal);
exynos5_register_clocks();
exynos5_setup_clocks();
#endif
}
void __init exynos4_init_irq(void)
{
unsigned int gic_bank_offset;
......
arch/arm/mach-exynos/common.h
View file @ 6e6aac75
......@@ -12,7 +12,10 @@
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
#include <linux/of.h>
extern void mct_init(void);
void exynos_init_time(void);
struct map_desc;
void exynos_init_io(struct map_desc *mach_desc, int size);
......@@ -22,6 +25,10 @@ void exynos4_restart(char mode, const char *cmd);
void exynos5_restart(char mode, const char *cmd);
void exynos_init_late(void);
/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
void exynos4_clk_init(struct device_node *np);
void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
#ifdef CONFIG_PM_GENERIC_DOMAINS
int exynos_pm_late_initcall(void);
#else
......
arch/arm/mach-exynos/include/mach/regs-clock.h
View file @ 6e6aac75
......@@ -256,113 +256,6 @@
#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
/* For EXYNOS5250 */
#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000)
#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)
#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)
#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400)
#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)
#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504)
#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600)
#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604)
#define EXYNOS5_PWR_CTRL1 EXYNOS_CLKREG(0x01020)
#define EXYNOS5_PWR_CTRL2 EXYNOS_CLKREG(0x01024)
#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)
#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)
#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)
#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
#define EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138)
#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
#define EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148)
#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
#define EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214)
#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
#define EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240)
#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254)
#define EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270)
#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
#define EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334)
#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354)
#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
#define EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544)
#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C)
#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560)
#define EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564)
#define EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568)
#define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C)
#define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580)
#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800)
#define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804)
#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
#define EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930)
#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)
#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)
#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)
#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)
#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24)
#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28)
#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16)
#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9)
#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8)
#define PWR_CTRL1_USE_CORE1_WFE (1 << 5)
#define PWR_CTRL1_USE_CORE0_WFE (1 << 4)
#define PWR_CTRL1_USE_CORE1_WFI (1 << 1)
#define PWR_CTRL1_USE_CORE0_WFI (1 << 0)
#define PWR_CTRL2_DIV2_UP_EN (1 << 25)
#define PWR_CTRL2_DIV1_UP_EN (1 << 24)
#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16)
#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8)
#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4)
#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0)
/* Compatibility defines and inclusion */
#include <mach/regs-pmu.h>
......
arch/arm/mach-exynos/mach-armlex4210.c
View file @ 6e6aac75
......@@ -177,7 +177,6 @@ static void __init armlex4210_smsc911x_init(void)
static void __init armlex4210_map_io(void)
{
exynos_init_io(NULL, 0);
s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(armlex4210_uartcfgs,
ARRAY_SIZE(armlex4210_uartcfgs));
}
......
arch/arm/mach-exynos/mach-exynos4-dt.c
View file @ 6e6aac75
......@@ -124,7 +124,6 @@ static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
static void __init exynos4_dt_map_io(void)
{
exynos_init_io(NULL, 0);
s3c24xx_init_clocks(24000000);
}
static void __init exynos4_dt_machine_init(void)
......
arch/arm/mach-exynos/mach-exynos5-dt.c
View file @ 6e6aac75
......@@ -152,12 +152,7 @@ static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
static void __init exynos5_dt_map_io(void)
{
unsigned long root = of_get_flat_dt_root();
exynos_init_io(NULL, 0);
if (of_flat_dt_is_compatible(root, "samsung,exynos5250"))
s3c24xx_init_clocks(24000000);
}
static void __init exynos5_dt_machine_init(void)
......
arch/arm/mach-exynos/mach-nuri.c
View file @ 6e6aac75
......@@ -1330,7 +1330,6 @@ static struct platform_device *nuri_devices[] __initdata = {
static void __init nuri_map_io(void)
{
exynos_init_io(NULL, 0);
s3c24xx_init_clocks(clk_xusbxti.rate);
s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
}
......
arch/arm/mach-exynos/mach-origen.c
View file @ 6e6aac75
......@@ -754,7 +754,6 @@ static void s5p_tv_setup(void)
static void __init origen_map_io(void)
{
exynos_init_io(NULL, 0);
s3c24xx_init_clocks(clk_xusbxti.rate);
s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
}
......
arch/arm/mach-exynos/mach-smdk4x12.c
View file @ 6e6aac75
......@@ -322,7 +322,6 @@ static struct platform_device *smdk4x12_devices[] __initdata = {
static void __init smdk4x12_map_io(void)
{
exynos_init_io(NULL, 0);
s3c24xx_init_clocks(clk_xusbxti.rate);
s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
}
......
arch/arm/mach-exynos/mach-smdkv310.c
View file @ 6e6aac75
......@@ -371,7 +371,6 @@ static void s5p_tv_setup(void)
static void __init smdkv310_map_io(void)
{
exynos_init_io(NULL, 0);
s3c24xx_init_clocks(clk_xusbxti.rate);
s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
}
......
arch/arm/mach-exynos/mach-universal_c210.c
View file @ 6e6aac75
......@@ -1092,7 +1092,6 @@ static struct platform_device *universal_devices[] __initdata = {
static void __init universal_map_io(void)
{
exynos_init_io(NULL, 0);
s3c24xx_init_clocks(clk_xusbxti.rate);
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
}
......
arch/arm/plat-samsung/Kconfig
View file @ 6e6aac75
......@@ -25,7 +25,7 @@ config PLAT_S5P
select PLAT_SAMSUNG
select S3C_GPIO_TRACK
select S5P_GPIO_DRVSTR
select SAMSUNG_CLKSRC
select SAMSUNG_CLKSRC if !COMMON_CLK
select SAMSUNG_GPIOLIB_4BIT
select SAMSUNG_IRQ_VIC_TIMER
help
......@@ -89,7 +89,7 @@ config SAMSUNG_CLKSRC
used by newer systems such as the S3C64XX.
config S5P_CLOCK
def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS)
def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
help
Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
......
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