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Commit 7244785e authored by Arnd Bergmann's avatar Arnd Bergmann
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fbdev: remove w100fb driver 

The w100fb was used on various PXA based pocketpc machines,
all of which are now removed, so remove this dirver sd well.

Cc: Helge Deller <deller@gmx.de>
Cc: linux-fbdev@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Acked-by: default avatarRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent aceae784
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drivers/video/fbdev/Kconfig
View file @ 7244785e
......@@ -1841,23 +1841,6 @@ config FB_FSL_DIU
help
Framebuffer driver for the Freescale SoC DIU
config FB_W100
tristate "W100 frame buffer support"
depends on FB && HAS_IOMEM && (ARCH_PXA || COMPILE_TEST)
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
help
Frame buffer driver for the w100 as found on the Sharp SL-Cxx series.
It can also drive the w3220 chip found on iPAQ hx4700.
This driver is also available as a module ( = code which can be
inserted and removed from the running kernel whenever you want). The
module will be called w100fb. If you want to compile it as a module,
say M here and read <file:Documentation/kbuild/modules.rst>.
If unsure, say N.
config FB_SH_MOBILE_LCDC
tristate "SuperH Mobile LCDC framebuffer support"
depends on FB && HAVE_CLK && HAS_IOMEM
......
drivers/video/fbdev/Makefile
View file @ 7244785e
......@@ -84,7 +84,6 @@ obj-$(CONFIG_FB_PXA) += pxafb.o
obj-$(CONFIG_FB_PXA168) += pxa168fb.o
obj-$(CONFIG_PXA3XX_GCU) += pxa3xx-gcu.o
obj-$(CONFIG_MMP_DISP) += mmp/
obj-$(CONFIG_FB_W100) += w100fb.o
obj-$(CONFIG_FB_AU1100) += au1100fb.o
obj-$(CONFIG_FB_AU1200) += au1200fb.o
obj-$(CONFIG_FB_VT8500) += vt8500lcdfb.o
......
drivers/video/fbdev/w100fb.c deleted 100644 → 0
View file @ aceae784
// SPDX-License-Identifier: GPL-2.0-only
/*
* linux/drivers/video/w100fb.c
*
* Frame Buffer Device for ATI Imageon w100 (Wallaby)
*
* Copyright (C) 2002, ATI Corp.
* Copyright (C) 2004-2006 Richard Purdie
* Copyright (c) 2005 Ian Molton
* Copyright (c) 2006 Alberto Mardegan
*
* Rewritten for 2.6 by Richard Purdie <rpurdie@rpsys.net>
*
* Generic platform support by Ian Molton <spyro@f2s.com>
* and Richard Purdie <rpurdie@rpsys.net>
*
* w32xx support by Ian Molton
*
* Hardware acceleration support by Alberto Mardegan
* <mardy@users.sourceforge.net>
*/
#include <linux/delay.h>
#include <linux/fb.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/vmalloc.h>
#include <linux/module.h>
#include <asm/io.h>
#include <linux/uaccess.h>
#include <video/w100fb.h>
#include "w100fb.h"
/*
* Prototypes
*/
static void w100_suspend(u32 mode);
static void w100_vsync(void);
static void w100_hw_init(struct w100fb_par*);
static void w100_pwm_setup(struct w100fb_par*);
static void w100_init_clocks(struct w100fb_par*);
static void w100_setup_memory(struct w100fb_par*);
static void w100_init_lcd(struct w100fb_par*);
static void w100_set_dispregs(struct w100fb_par*);
static void w100_update_enable(void);
static void w100_update_disable(void);
static void calc_hsync(struct w100fb_par *par);
static void w100_init_graphic_engine(struct w100fb_par *par);
struct w100_pll_info *w100_get_xtal_table(unsigned int freq);
/* Pseudo palette size */
#define MAX_PALETTES 16
#define W100_SUSPEND_EXTMEM 0
#define W100_SUSPEND_ALL 1
#define BITS_PER_PIXEL 16
/* Remapped addresses for base cfg, memmapped regs and the frame buffer itself */
static void __iomem *remapped_base;
static void __iomem *remapped_regs;
static void __iomem *remapped_fbuf;
#define REMAPPED_FB_LEN 0x15ffff
/* This is the offset in the w100's address space we map the current
framebuffer memory to. We use the position of external memory as
we can remap internal memory to there if external isn't present. */
#define W100_FB_BASE MEM_EXT_BASE_VALUE
/*
* Sysfs functions
*/
static ssize_t flip_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct fb_info *info = dev_get_drvdata(dev);
struct w100fb_par *par=info->par;
return sprintf(buf, "%d\n",par->flip);
}
static ssize_t flip_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
{
unsigned int flip;
struct fb_info *info = dev_get_drvdata(dev);
struct w100fb_par *par=info->par;
flip = simple_strtoul(buf, NULL, 10);
if (flip > 0)
par->flip = 1;
else
par->flip = 0;
w100_update_disable();
w100_set_dispregs(par);
w100_update_enable();
calc_hsync(par);
return count;
}
static DEVICE_ATTR_RW(flip);
static ssize_t w100fb_reg_read(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
{
unsigned long regs, param;
regs = simple_strtoul(buf, NULL, 16);
param = readl(remapped_regs + regs);
printk("Read Register 0x%08lX: 0x%08lX\n", regs, param);
return count;
}
static DEVICE_ATTR(reg_read, 0200, NULL, w100fb_reg_read);
static ssize_t w100fb_reg_write(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
{
unsigned long regs, param;
sscanf(buf, "%lx %lx", &regs, &param);
if (regs <= 0x2000) {
printk("Write Register 0x%08lX: 0x%08lX\n", regs, param);
writel(param, remapped_regs + regs);
}
return count;
}
static DEVICE_ATTR(reg_write, 0200, NULL, w100fb_reg_write);
static ssize_t fastpllclk_show(struct device *dev, struct device_attribute *attr, char *buf)
{
struct fb_info *info = dev_get_drvdata(dev);
struct w100fb_par *par=info->par;
return sprintf(buf, "%d\n",par->fastpll_mode);
}
static ssize_t fastpllclk_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
{
struct fb_info *info = dev_get_drvdata(dev);
struct w100fb_par *par=info->par;
if (simple_strtoul(buf, NULL, 10) > 0) {
par->fastpll_mode=1;
printk("w100fb: Using fast system clock (if possible)\n");
} else {
par->fastpll_mode=0;
printk("w100fb: Using normal system clock\n");
}
w100_init_clocks(par);
calc_hsync(par);
return count;
}
static DEVICE_ATTR_RW(fastpllclk);
static struct attribute *w100fb_attrs[] = {
&dev_attr_fastpllclk.attr,
&dev_attr_reg_read.attr,
&dev_attr_reg_write.attr,
&dev_attr_flip.attr,
NULL,
};
ATTRIBUTE_GROUPS(w100fb);
/*
* Some touchscreens need hsync information from the video driver to
* function correctly. We export it here.
*/
unsigned long w100fb_get_hsynclen(struct device *dev)
{
struct fb_info *info = dev_get_drvdata(dev);
struct w100fb_par *par=info->par;
/* If display is blanked/suspended, hsync isn't active */
if (par->blanked)
return 0;
else
return par->hsync_len;
}
EXPORT_SYMBOL(w100fb_get_hsynclen);
static void w100fb_clear_screen(struct w100fb_par *par)
{
memset_io(remapped_fbuf + (W100_FB_BASE-MEM_WINDOW_BASE), 0, (par->xres * par->yres * BITS_PER_PIXEL/8));
}
/*
* Set a palette value from rgb components
*/
static int w100fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
u_int trans, struct fb_info *info)
{
unsigned int val;
int ret = 1;
/*
* If greyscale is true, then we convert the RGB value
* to greyscale no matter what visual we are using.
*/
if (info->var.grayscale)
red = green = blue = (19595 * red + 38470 * green + 7471 * blue) >> 16;
/*
* 16-bit True Colour. We encode the RGB value
* according to the RGB bitfield information.
*/
if (regno < MAX_PALETTES) {
u32 *pal = info->pseudo_palette;
val = (red & 0xf800) | ((green & 0xfc00) >> 5) | ((blue & 0xf800) >> 11);
pal[regno] = val;
ret = 0;
}
return ret;
}
/*
* Blank the display based on value in blank_mode
*/
static int w100fb_blank(int blank_mode, struct fb_info *info)
{
struct w100fb_par *par = info->par;
struct w100_tg_info *tg = par->mach->tg;
switch(blank_mode) {
case FB_BLANK_NORMAL: /* Normal blanking */
case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
case FB_BLANK_POWERDOWN: /* Poweroff */
if (par->blanked == 0) {
if(tg && tg->suspend)
tg->suspend(par);
par->blanked = 1;
}
break;
case FB_BLANK_UNBLANK: /* Unblanking */
if (par->blanked != 0) {
if(tg && tg->resume)
tg->resume(par);
par->blanked = 0;
}
break;
}
return 0;
}
static void w100_fifo_wait(int entries)
{
union rbbm_status_u status;
int i;
for (i = 0; i < 2000000; i++) {
status.val = readl(remapped_regs + mmRBBM_STATUS);
if (status.f.cmdfifo_avail >= entries)
return;
udelay(1);
}
printk(KERN_ERR "w100fb: FIFO Timeout!\n");
}
static int w100fb_sync(struct fb_info *info)
{
union rbbm_status_u status;
int i;
for (i = 0; i < 2000000; i++) {
status.val = readl(remapped_regs + mmRBBM_STATUS);
if (!status.f.gui_active)
return 0;
udelay(1);
}
printk(KERN_ERR "w100fb: Graphic engine timeout!\n");
return -EBUSY;
}
static void w100_init_graphic_engine(struct w100fb_par *par)
{
union dp_gui_master_cntl_u gmc;
union dp_mix_u dp_mix;
union dp_datatype_u dp_datatype;
union dp_cntl_u dp_cntl;
w100_fifo_wait(4);
writel(W100_FB_BASE, remapped_regs + mmDST_OFFSET);
writel(par->xres, remapped_regs + mmDST_PITCH);
writel(W100_FB_BASE, remapped_regs + mmSRC_OFFSET);
writel(par->xres, remapped_regs + mmSRC_PITCH);
w100_fifo_wait(3);
writel(0, remapped_regs + mmSC_TOP_LEFT);
writel((par->yres << 16) | par->xres, remapped_regs + mmSC_BOTTOM_RIGHT);
writel(0x1fff1fff, remapped_regs + mmSRC_SC_BOTTOM_RIGHT);
w100_fifo_wait(4);
dp_cntl.val = 0;
dp_cntl.f.dst_x_dir = 1;
dp_cntl.f.dst_y_dir = 1;
dp_cntl.f.src_x_dir = 1;
dp_cntl.f.src_y_dir = 1;
dp_cntl.f.dst_major_x = 1;
dp_cntl.f.src_major_x = 1;
writel(dp_cntl.val, remapped_regs + mmDP_CNTL);
gmc.val = 0;
gmc.f.gmc_src_pitch_offset_cntl = 1;
gmc.f.gmc_dst_pitch_offset_cntl = 1;
gmc.f.gmc_src_clipping = 1;
gmc.f.gmc_dst_clipping = 1;
gmc.f.gmc_brush_datatype = GMC_BRUSH_NONE;
gmc.f.gmc_dst_datatype = 3; /* from DstType_16Bpp_444 */
gmc.f.gmc_src_datatype = SRC_DATATYPE_EQU_DST;
gmc.f.gmc_byte_pix_order = 1;
gmc.f.gmc_default_sel = 0;
gmc.f.gmc_rop3 = ROP3_SRCCOPY;
gmc.f.gmc_dp_src_source = DP_SRC_MEM_RECTANGULAR;
gmc.f.gmc_clr_cmp_fcn_dis = 1;
gmc.f.gmc_wr_msk_dis = 1;
gmc.f.gmc_dp_op = DP_OP_ROP;
writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL);
dp_datatype.val = dp_mix.val = 0;
dp_datatype.f.dp_dst_datatype = gmc.f.gmc_dst_datatype;
dp_datatype.f.dp_brush_datatype = gmc.f.gmc_brush_datatype;
dp_datatype.f.dp_src2_type = 0;
dp_datatype.f.dp_src2_datatype = gmc.f.gmc_src_datatype;
dp_datatype.f.dp_src_datatype = gmc.f.gmc_src_datatype;
dp_datatype.f.dp_byte_pix_order = gmc.f.gmc_byte_pix_order;
writel(dp_datatype.val, remapped_regs + mmDP_DATATYPE);
dp_mix.f.dp_src_source = gmc.f.gmc_dp_src_source;
dp_mix.f.dp_src2_source = 1;
dp_mix.f.dp_rop3 = gmc.f.gmc_rop3;
dp_mix.f.dp_op = gmc.f.gmc_dp_op;
writel(dp_mix.val, remapped_regs + mmDP_MIX);
}
static void w100fb_fillrect(struct fb_info *info,
const struct fb_fillrect *rect)
{
union dp_gui_master_cntl_u gmc;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (info->flags & FBINFO_HWACCEL_DISABLED) {
cfb_fillrect(info, rect);
return;
}
gmc.val = readl(remapped_regs + mmDP_GUI_MASTER_CNTL);
gmc.f.gmc_rop3 = ROP3_PATCOPY;
gmc.f.gmc_brush_datatype = GMC_BRUSH_SOLID_COLOR;
w100_fifo_wait(2);
writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL);
writel(rect->color, remapped_regs + mmDP_BRUSH_FRGD_CLR);
w100_fifo_wait(2);
writel((rect->dy << 16) | (rect->dx & 0xffff), remapped_regs + mmDST_Y_X);
writel((rect->width << 16) | (rect->height & 0xffff),
remapped_regs + mmDST_WIDTH_HEIGHT);
}
static void w100fb_copyarea(struct fb_info *info,
const struct fb_copyarea *area)
{
u32 dx = area->dx, dy = area->dy, sx = area->sx, sy = area->sy;
u32 h = area->height, w = area->width;
union dp_gui_master_cntl_u gmc;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (info->flags & FBINFO_HWACCEL_DISABLED) {
cfb_copyarea(info, area);
return;
}
gmc.val = readl(remapped_regs + mmDP_GUI_MASTER_CNTL);
gmc.f.gmc_rop3 = ROP3_SRCCOPY;
gmc.f.gmc_brush_datatype = GMC_BRUSH_NONE;
w100_fifo_wait(1);
writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL);
w100_fifo_wait(3);
writel((sy << 16) | (sx & 0xffff), remapped_regs + mmSRC_Y_X);
writel((dy << 16) | (dx & 0xffff), remapped_regs + mmDST_Y_X);
writel((w << 16) | (h & 0xffff), remapped_regs + mmDST_WIDTH_HEIGHT);
}
/*
* Change the resolution by calling the appropriate hardware functions
*/
static void w100fb_activate_var(struct w100fb_par *par)
{
struct w100_tg_info *tg = par->mach->tg;
w100_pwm_setup(par);
w100_setup_memory(par);
w100_init_clocks(par);
w100fb_clear_screen(par);
w100_vsync();
w100_update_disable();
w100_init_lcd(par);
w100_set_dispregs(par);
w100_update_enable();
w100_init_graphic_engine(par);
calc_hsync(par);
if (!par->blanked && tg && tg->change)
tg->change(par);
}
/* Select the smallest mode that allows the desired resolution to be
* displayed. If desired, the x and y parameters can be rounded up to
* match the selected mode.
*/
static struct w100_mode *w100fb_get_mode(struct w100fb_par *par, unsigned int *x, unsigned int *y, int saveval)
{
struct w100_mode *mode = NULL;
struct w100_mode *modelist = par->mach->modelist;
unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
unsigned int i;
for (i = 0 ; i < par->mach->num_modes ; i++) {
if (modelist[i].xres >= *x && modelist[i].yres >= *y &&
modelist[i].xres < best_x && modelist[i].yres < best_y) {
best_x = modelist[i].xres;
best_y = modelist[i].yres;
mode = &modelist[i];
} else if(modelist[i].xres >= *y && modelist[i].yres >= *x &&
modelist[i].xres < best_y && modelist[i].yres < best_x) {
best_x = modelist[i].yres;
best_y = modelist[i].xres;
mode = &modelist[i];
}
}
if (mode && saveval) {
*x = best_x;
*y = best_y;
}
return mode;
}
/*
* w100fb_check_var():
* Get the video params out of 'var'. If a value doesn't fit, round it up,
* if it's too big, return -EINVAL.
*/
static int w100fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
{
struct w100fb_par *par=info->par;
if(!w100fb_get_mode(par, &var->xres, &var->yres, 1))
return -EINVAL;
if (par->mach->mem && ((var->xres*var->yres*BITS_PER_PIXEL/8) > (par->mach->mem->size+1)))
return -EINVAL;
if (!par->mach->mem && ((var->xres*var->yres*BITS_PER_PIXEL/8) > (MEM_INT_SIZE+1)))
return -EINVAL;
var->xres_virtual = max(var->xres_virtual, var->xres);
var->yres_virtual = max(var->yres_virtual, var->yres);
if (var->bits_per_pixel > BITS_PER_PIXEL)
return -EINVAL;
else
var->bits_per_pixel = BITS_PER_PIXEL;
var->red.offset = 11;
var->red.length = 5;
var->green.offset = 5;
var->green.length = 6;
var->blue.offset = 0;
var->blue.length = 5;
var->transp.offset = var->transp.length = 0;
var->nonstd = 0;
var->height = -1;
var->width = -1;
var->vmode = FB_VMODE_NONINTERLACED;
var->sync = 0;
var->pixclock = 0x04; /* 171521; */
return 0;
}
/*
* w100fb_set_par():
* Set the user defined part of the display for the specified console
* by looking at the values in info.var
*/
static int w100fb_set_par(struct fb_info *info)
{
struct w100fb_par *par=info->par;
if (par->xres != info->var.xres || par->yres != info->var.yres) {
par->xres = info->var.xres;
par->yres = info->var.yres;
par->mode = w100fb_get_mode(par, &par->xres, &par->yres, 0);
info->fix.visual = FB_VISUAL_TRUECOLOR;
info->fix.ypanstep = 0;
info->fix.ywrapstep = 0;
info->fix.line_length = par->xres * BITS_PER_PIXEL / 8;
mutex_lock(&info->mm_lock);
if ((par->xres*par->yres*BITS_PER_PIXEL/8) > (MEM_INT_SIZE+1)) {
par->extmem_active = 1;
info->fix.smem_len = par->mach->mem->size+1;
} else {
par->extmem_active = 0;
info->fix.smem_len = MEM_INT_SIZE+1;
}
mutex_unlock(&info->mm_lock);
w100fb_activate_var(par);
}
return 0;
}
/*
* Frame buffer operations
*/
static const struct fb_ops w100fb_ops = {
.owner = THIS_MODULE,
.fb_check_var = w100fb_check_var,
.fb_set_par = w100fb_set_par,
.fb_setcolreg = w100fb_setcolreg,
.fb_blank = w100fb_blank,
.fb_fillrect = w100fb_fillrect,
.fb_copyarea = w100fb_copyarea,
.fb_imageblit = cfb_imageblit,
.fb_sync = w100fb_sync,
};
#ifdef CONFIG_PM
static void w100fb_save_vidmem(struct w100fb_par *par)
{
int memsize;
if (par->extmem_active) {
memsize=par->mach->mem->size;
par->saved_extmem = vmalloc(memsize);
if (par->saved_extmem)
memcpy_fromio(par->saved_extmem, remapped_fbuf + (W100_FB_BASE-MEM_WINDOW_BASE), memsize);
}
memsize=MEM_INT_SIZE;
par->saved_intmem = vmalloc(memsize);
if (par->saved_intmem && par->extmem_active)
memcpy_fromio(par->saved_intmem, remapped_fbuf + (W100_FB_BASE-MEM_INT_BASE_VALUE), memsize);
else if (par->saved_intmem)
memcpy_fromio(par->saved_intmem, remapped_fbuf + (W100_FB_BASE-MEM_WINDOW_BASE), memsize);
}
static void w100fb_restore_vidmem(struct w100fb_par *par)
{
int memsize;
if (par->extmem_active && par->saved_extmem) {
memsize=par->mach->mem->size;
memcpy_toio(remapped_fbuf + (W100_FB_BASE-MEM_WINDOW_BASE), par->saved_extmem, memsize);
vfree(par->saved_extmem);
par->saved_extmem = NULL;
}
if (par->saved_intmem) {
memsize=MEM_INT_SIZE;
if (par->extmem_active)
memcpy_toio(remapped_fbuf + (W100_FB_BASE-MEM_INT_BASE_VALUE), par->saved_intmem, memsize);
else
memcpy_toio(remapped_fbuf + (W100_FB_BASE-MEM_WINDOW_BASE), par->saved_intmem, memsize);
vfree(par->saved_intmem);
par->saved_intmem = NULL;
}
}
static int w100fb_suspend(struct platform_device *dev, pm_message_t state)
{
struct fb_info *info = platform_get_drvdata(dev);
struct w100fb_par *par=info->par;
struct w100_tg_info *tg = par->mach->tg;
w100fb_save_vidmem(par);
if(tg && tg->suspend)
tg->suspend(par);
w100_suspend(W100_SUSPEND_ALL);
par->blanked = 1;
return 0;
}
static int w100fb_resume(struct platform_device *dev)
{
struct fb_info *info = platform_get_drvdata(dev);
struct w100fb_par *par=info->par;
struct w100_tg_info *tg = par->mach->tg;
w100_hw_init(par);
w100fb_activate_var(par);
w100fb_restore_vidmem(par);
if(tg && tg->resume)
tg->resume(par);
par->blanked = 0;
return 0;
}
#else
#define w100fb_suspend NULL
#define w100fb_resume NULL
#endif
static int w100fb_probe(struct platform_device *pdev)
{
int err = -EIO;
struct w100fb_mach_info *inf;
struct fb_info *info = NULL;
struct w100fb_par *par;
struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
unsigned int chip_id;
if (!mem)
return -EINVAL;
/* Remap the chip base address */
remapped_base = ioremap(mem->start+W100_CFG_BASE, W100_CFG_LEN);
if (remapped_base == NULL)
goto out;
/* Map the register space */
remapped_regs = ioremap(mem->start+W100_REG_BASE, W100_REG_LEN);
if (remapped_regs == NULL)
goto out;
/* Identify the chip */
printk("Found ");
chip_id = readl(remapped_regs + mmCHIP_ID);
switch(chip_id) {
case CHIP_ID_W100: printk("w100"); break;
case CHIP_ID_W3200: printk("w3200"); break;
case CHIP_ID_W3220: printk("w3220"); break;
default:
printk("Unknown imageon chip ID\n");
err = -ENODEV;
goto out;
}
printk(" at 0x%08lx.\n", (unsigned long) mem->start+W100_CFG_BASE);
/* Remap the framebuffer */
remapped_fbuf = ioremap(mem->start+MEM_WINDOW_BASE, MEM_WINDOW_SIZE);
if (remapped_fbuf == NULL)
goto out;
info=framebuffer_alloc(sizeof(struct w100fb_par), &pdev->dev);
if (!info) {
err = -ENOMEM;
goto out;
}
par = info->par;
platform_set_drvdata(pdev, info);
inf = dev_get_platdata(&pdev->dev);
par->chip_id = chip_id;
par->mach = inf;
par->fastpll_mode = 0;
par->blanked = 0;
par->pll_table=w100_get_xtal_table(inf->xtal_freq);
if (!par->pll_table) {
printk(KERN_ERR "No matching Xtal definition found\n");
err = -EINVAL;
goto out;
}
info->pseudo_palette = kmalloc_array(MAX_PALETTES, sizeof(u32),
GFP_KERNEL);
if (!info->pseudo_palette) {
err = -ENOMEM;
goto out;
}
info->fbops = &w100fb_ops;
info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
FBINFO_HWACCEL_FILLRECT;
info->node = -1;
info->screen_base = remapped_fbuf + (W100_FB_BASE-MEM_WINDOW_BASE);
info->screen_size = REMAPPED_FB_LEN;
strcpy(info->fix.id, "w100fb");
info->fix.type = FB_TYPE_PACKED_PIXELS;
info->fix.type_aux = 0;
info->fix.accel = FB_ACCEL_NONE;
info->fix.smem_start = mem->start+W100_FB_BASE;
info->fix.mmio_start = mem->start+W100_REG_BASE;
info->fix.mmio_len = W100_REG_LEN;
if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
err = -ENOMEM;
goto out;
}
par->mode = &inf->modelist[0];
if(inf->init_mode & INIT_MODE_ROTATED) {
info->var.xres = par->mode->yres;
info->var.yres = par->mode->xres;
}
else {
info->var.xres = par->mode->xres;
info->var.yres = par->mode->yres;
}
if(inf->init_mode &= INIT_MODE_FLIPPED)
par->flip = 1;
else
par->flip = 0;
info->var.xres_virtual = info->var.xres;
info->var.yres_virtual = info->var.yres;
info->var.pixclock = 0x04; /* 171521; */
info->var.sync = 0;
info->var.grayscale = 0;
info->var.xoffset = info->var.yoffset = 0;
info->var.accel_flags = 0;
info->var.activate = FB_ACTIVATE_NOW;
w100_hw_init(par);
if (w100fb_check_var(&info->var, info) < 0) {
err = -EINVAL;
goto out;
}
if (register_framebuffer(info) < 0) {
err = -EINVAL;
goto out;
}
fb_info(info, "%s frame buffer device\n", info->fix.id);
return 0;
out:
if (info) {
fb_dealloc_cmap(&info->cmap);
kfree(info->pseudo_palette);
}
if (remapped_fbuf != NULL) {
iounmap(remapped_fbuf);
remapped_fbuf = NULL;
}
if (remapped_regs != NULL) {
iounmap(remapped_regs);
remapped_regs = NULL;
}
if (remapped_base != NULL) {
iounmap(remapped_base);
remapped_base = NULL;
}
if (info)
framebuffer_release(info);
return err;
}
static int w100fb_remove(struct platform_device *pdev)
{
struct fb_info *info = platform_get_drvdata(pdev);
struct w100fb_par *par=info->par;
unregister_framebuffer(info);
vfree(par->saved_intmem);
vfree(par->saved_extmem);
kfree(info->pseudo_palette);
fb_dealloc_cmap(&info->cmap);
iounmap(remapped_base);
remapped_base = NULL;
iounmap(remapped_regs);
remapped_regs = NULL;
iounmap(remapped_fbuf);
remapped_fbuf = NULL;
framebuffer_release(info);
return 0;
}
/* ------------------- chipset specific functions -------------------------- */
static void w100_soft_reset(void)
{
u16 val = readw((u16 __iomem *)remapped_base + cfgSTATUS);
writew(val | 0x08, (u16 __iomem *)remapped_base + cfgSTATUS);
udelay(100);
writew(0x00, (u16 __iomem *)remapped_base + cfgSTATUS);
udelay(100);
}
static void w100_update_disable(void)
{
union disp_db_buf_cntl_wr_u disp_db_buf_wr_cntl;
/* Prevent display updates */
disp_db_buf_wr_cntl.f.db_buf_cntl = 0x1e;
disp_db_buf_wr_cntl.f.update_db_buf = 0;
disp_db_buf_wr_cntl.f.en_db_buf = 0;
writel((u32) (disp_db_buf_wr_cntl.val), remapped_regs + mmDISP_DB_BUF_CNTL);
}
static void w100_update_enable(void)
{
union disp_db_buf_cntl_wr_u disp_db_buf_wr_cntl;
/* Enable display updates */
disp_db_buf_wr_cntl.f.db_buf_cntl = 0x1e;
disp_db_buf_wr_cntl.f.update_db_buf = 1;
disp_db_buf_wr_cntl.f.en_db_buf = 1;
writel((u32) (disp_db_buf_wr_cntl.val), remapped_regs + mmDISP_DB_BUF_CNTL);
}
unsigned long w100fb_gpio_read(int port)
{
unsigned long value;
if (port==W100_GPIO_PORT_A)
value = readl(remapped_regs + mmGPIO_DATA);
else
value = readl(remapped_regs + mmGPIO_DATA2);
return value;
}
void w100fb_gpio_write(int port, unsigned long value)
{
if (port==W100_GPIO_PORT_A)
writel(value, remapped_regs + mmGPIO_DATA);
else
writel(value, remapped_regs + mmGPIO_DATA2);
}
EXPORT_SYMBOL(w100fb_gpio_read);
EXPORT_SYMBOL(w100fb_gpio_write);
/*
* Initialization of critical w100 hardware
*/
static void w100_hw_init(struct w100fb_par *par)
{
u32 temp32;
union cif_cntl_u cif_cntl;
union intf_cntl_u intf_cntl;
union cfgreg_base_u cfgreg_base;
union wrap_top_dir_u wrap_top_dir;
union cif_read_dbg_u cif_read_dbg;
union cpu_defaults_u cpu_default;
union cif_write_dbg_u cif_write_dbg;
union wrap_start_dir_u wrap_start_dir;
union cif_io_u cif_io;
struct w100_gpio_regs *gpio = par->mach->gpio;
w100_soft_reset();
/* This is what the fpga_init code does on reset. May be wrong
but there is little info available */
writel(0x31, remapped_regs + mmSCRATCH_UMSK);
for (temp32 = 0; temp32 < 10000; temp32++)
readl(remapped_regs + mmSCRATCH_UMSK);
writel(0x30, remapped_regs + mmSCRATCH_UMSK);
/* Set up CIF */
cif_io.val = defCIF_IO;
writel((u32)(cif_io.val), remapped_regs + mmCIF_IO);
cif_write_dbg.val = readl(remapped_regs + mmCIF_WRITE_DBG);
cif_write_dbg.f.dis_packer_ful_during_rbbm_timeout = 0;
cif_write_dbg.f.en_dword_split_to_rbbm = 1;
cif_write_dbg.f.dis_timeout_during_rbbm = 1;
writel((u32) (cif_write_dbg.val), remapped_regs + mmCIF_WRITE_DBG);
cif_read_dbg.val = readl(remapped_regs + mmCIF_READ_DBG);
cif_read_dbg.f.dis_rd_same_byte_to_trig_fetch = 1;
writel((u32) (cif_read_dbg.val), remapped_regs + mmCIF_READ_DBG);
cif_cntl.val = readl(remapped_regs + mmCIF_CNTL);
cif_cntl.f.dis_system_bits = 1;
cif_cntl.f.dis_mr = 1;
cif_cntl.f.en_wait_to_compensate_dq_prop_dly = 0;
cif_cntl.f.intb_oe = 1;
cif_cntl.f.interrupt_active_high = 1;
writel((u32) (cif_cntl.val), remapped_regs + mmCIF_CNTL);
/* Setup cfgINTF_CNTL and cfgCPU defaults */
intf_cntl.val = defINTF_CNTL;
intf_cntl.f.ad_inc_a = 1;
intf_cntl.f.ad_inc_b = 1;
intf_cntl.f.rd_data_rdy_a = 0;
intf_cntl.f.rd_data_rdy_b = 0;
writeb((u8) (intf_cntl.val), remapped_base + cfgINTF_CNTL);
cpu_default.val = defCPU_DEFAULTS;
cpu_default.f.access_ind_addr_a = 1;
cpu_default.f.access_ind_addr_b = 1;
cpu_default.f.access_scratch_reg = 1;
cpu_default.f.transition_size = 0;
writeb((u8) (cpu_default.val), remapped_base + cfgCPU_DEFAULTS);
/* set up the apertures */
writeb((u8) (W100_REG_BASE >> 16), remapped_base + cfgREG_BASE);
cfgreg_base.val = defCFGREG_BASE;
cfgreg_base.f.cfgreg_base = W100_CFG_BASE;
writel((u32) (cfgreg_base.val), remapped_regs + mmCFGREG_BASE);
wrap_start_dir.val = defWRAP_START_DIR;
wrap_start_dir.f.start_addr = WRAP_BUF_BASE_VALUE >> 1;
writel((u32) (wrap_start_dir.val), remapped_regs + mmWRAP_START_DIR);
wrap_top_dir.val = defWRAP_TOP_DIR;
wrap_top_dir.f.top_addr = WRAP_BUF_TOP_VALUE >> 1;
writel((u32) (wrap_top_dir.val), remapped_regs + mmWRAP_TOP_DIR);
writel((u32) 0x2440, remapped_regs + mmRBBM_CNTL);
/* Set the hardware to 565 colour */
temp32 = readl(remapped_regs + mmDISP_DEBUG2);
temp32 &= 0xff7fffff;
temp32 |= 0x00800000;
writel(temp32, remapped_regs + mmDISP_DEBUG2);
/* Initialise the GPIO lines */
if (gpio) {
writel(gpio->init_data1, remapped_regs + mmGPIO_DATA);
writel(gpio->init_data2, remapped_regs + mmGPIO_DATA2);
writel(gpio->gpio_dir1, remapped_regs + mmGPIO_CNTL1);
writel(gpio->gpio_oe1, remapped_regs + mmGPIO_CNTL2);
writel(gpio->gpio_dir2, remapped_regs + mmGPIO_CNTL3);
writel(gpio->gpio_oe2, remapped_regs + mmGPIO_CNTL4);
}
}
struct power_state {
union clk_pin_cntl_u clk_pin_cntl;
union pll_ref_fb_div_u pll_ref_fb_div;
union pll_cntl_u pll_cntl;
union sclk_cntl_u sclk_cntl;
union pclk_cntl_u pclk_cntl;
union pwrmgt_cntl_u pwrmgt_cntl;
int auto_mode; /* system clock auto changing? */
};
static struct power_state w100_pwr_state;
/* The PLL Fout is determined by (XtalFreq/(M+1)) * ((N_int+1) + (N_fac/8)) */
/* 12.5MHz Crystal PLL Table */
static struct w100_pll_info xtal_12500000[] = {
/*freq M N_int N_fac tfgoal lock_time */
{ 50, 0, 1, 0, 0xe0, 56}, /* 50.00 MHz */
{ 75, 0, 5, 0, 0xde, 37}, /* 75.00 MHz */
{100, 0, 7, 0, 0xe0, 28}, /* 100.00 MHz */
{125, 0, 9, 0, 0xe0, 22}, /* 125.00 MHz */
{150, 0, 11, 0, 0xe0, 17}, /* 150.00 MHz */
{ 0, 0, 0, 0, 0, 0}, /* Terminator */
};
/* 14.318MHz Crystal PLL Table */
static struct w100_pll_info xtal_14318000[] = {
/*freq M N_int N_fac tfgoal lock_time */
{ 40, 4, 13, 0, 0xe0, 80}, /* tfgoal guessed */
{ 50, 1, 6, 0, 0xe0, 64}, /* 50.05 MHz */
{ 57, 2, 11, 0, 0xe0, 53}, /* tfgoal guessed */
{ 75, 0, 4, 3, 0xe0, 43}, /* 75.08 MHz */
{100, 0, 6, 0, 0xe0, 32}, /* 100.10 MHz */
{ 0, 0, 0, 0, 0, 0},
};
/* 16MHz Crystal PLL Table */
static struct w100_pll_info xtal_16000000[] = {
/*freq M N_int N_fac tfgoal lock_time */
{ 72, 1, 8, 0, 0xe0, 48}, /* tfgoal guessed */
{ 80, 1, 9, 0, 0xe0, 13}, /* tfgoal guessed */
{ 95, 1, 10, 7, 0xe0, 38}, /* tfgoal guessed */
{ 96, 1, 11, 0, 0xe0, 36}, /* tfgoal guessed */
{ 0, 0, 0, 0, 0, 0},
};
static struct pll_entries {
int xtal_freq;
struct w100_pll_info *pll_table;
} w100_pll_tables[] = {
{ 12500000, &xtal_12500000[0] },
{ 14318000, &xtal_14318000[0] },
{ 16000000, &xtal_16000000[0] },
{ 0 },
};
struct w100_pll_info *w100_get_xtal_table(unsigned int freq)
{
struct pll_entries *pll_entry = w100_pll_tables;
do {
if (freq == pll_entry->xtal_freq)
return pll_entry->pll_table;
pll_entry++;
} while (pll_entry->xtal_freq);
return NULL;
}
static unsigned int w100_get_testcount(unsigned int testclk_sel)
{
union clk_test_cntl_u clk_test_cntl;
udelay(5);
/* Select the test clock source and reset */
clk_test_cntl.f.start_check_freq = 0x0;
clk_test_cntl.f.testclk_sel = testclk_sel;
clk_test_cntl.f.tstcount_rst = 0x1; /* set reset */
writel((u32) (clk_test_cntl.val), remapped_regs + mmCLK_TEST_CNTL);
clk_test_cntl.f.tstcount_rst = 0x0; /* clear reset */
writel((u32) (clk_test_cntl.val), remapped_regs + mmCLK_TEST_CNTL);
/* Run clock test */
clk_test_cntl.f.start_check_freq = 0x1;
writel((u32) (clk_test_cntl.val), remapped_regs + mmCLK_TEST_CNTL);
/* Give the test time to complete */
udelay(20);
/* Return the result */
clk_test_cntl.val = readl(remapped_regs + mmCLK_TEST_CNTL);
clk_test_cntl.f.start_check_freq = 0x0;
writel((u32) (clk_test_cntl.val), remapped_regs + mmCLK_TEST_CNTL);
return clk_test_cntl.f.test_count;
}
static int w100_pll_adjust(struct w100_pll_info *pll)
{
unsigned int tf80;
unsigned int tf20;
/* Initial Settings */
w100_pwr_state.pll_cntl.f.pll_pwdn = 0x0; /* power down */
w100_pwr_state.pll_cntl.f.pll_reset = 0x0; /* not reset */
w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x1; /* Hi-Z */
w100_pwr_state.pll_cntl.f.pll_pvg = 0x0; /* VCO gain = 0 */
w100_pwr_state.pll_cntl.f.pll_vcofr = 0x0; /* VCO frequency range control = off */
w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0; /* current offset inside VCO = 0 */
w100_pwr_state.pll_cntl.f.pll_ring_off = 0x0;
/* Wai Ming 80 percent of VDD 1.3V gives 1.04V, minimum operating voltage is 1.08V
* therefore, commented out the following lines
* tf80 meant tf100
*/
do {
/* set VCO input = 0.8 * VDD */
w100_pwr_state.pll_cntl.f.pll_dactal = 0xd;
writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
tf80 = w100_get_testcount(TESTCLK_SRC_PLL);
if (tf80 >= (pll->tfgoal)) {
/* set VCO input = 0.2 * VDD */
w100_pwr_state.pll_cntl.f.pll_dactal = 0x7;
writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
tf20 = w100_get_testcount(TESTCLK_SRC_PLL);
if (tf20 <= (pll->tfgoal))
return 1; /* Success */
if ((w100_pwr_state.pll_cntl.f.pll_vcofr == 0x0) &&
((w100_pwr_state.pll_cntl.f.pll_pvg == 0x7) ||
(w100_pwr_state.pll_cntl.f.pll_ioffset == 0x0))) {
/* slow VCO config */
w100_pwr_state.pll_cntl.f.pll_vcofr = 0x1;
w100_pwr_state.pll_cntl.f.pll_pvg = 0x0;
w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0;
continue;
}
}
if ((w100_pwr_state.pll_cntl.f.pll_ioffset) < 0x3) {
w100_pwr_state.pll_cntl.f.pll_ioffset += 0x1;
} else if ((w100_pwr_state.pll_cntl.f.pll_pvg) < 0x7) {
w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0;
w100_pwr_state.pll_cntl.f.pll_pvg += 0x1;
} else {
return 0; /* Error */
}
} while(1);
}
/*
* w100_pll_calibration
*/
static int w100_pll_calibration(struct w100_pll_info *pll)
{
int status;
status = w100_pll_adjust(pll);
/* PLL Reset And Lock */
/* set VCO input = 0.5 * VDD */
w100_pwr_state.pll_cntl.f.pll_dactal = 0xa;
writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
udelay(1); /* reset time */
/* enable charge pump */
w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x0; /* normal */
writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
/* set VCO input = Hi-Z, disable DAC */
w100_pwr_state.pll_cntl.f.pll_dactal = 0x0;
writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
udelay(400); /* lock time */
/* PLL locked */
return status;
}
static int w100_pll_set_clk(struct w100_pll_info *pll)
{
int status;
if (w100_pwr_state.auto_mode == 1) /* auto mode */
{
w100_pwr_state.pwrmgt_cntl.f.pwm_fast_noml_hw_en = 0x0; /* disable fast to normal */
w100_pwr_state.pwrmgt_cntl.f.pwm_noml_fast_hw_en = 0x0; /* disable normal to fast */
writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL);
}
/* Set system clock source to XTAL whilst adjusting the PLL! */
w100_pwr_state.sclk_cntl.f.sclk_src_sel = CLK_SRC_XTAL;
writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL);
w100_pwr_state.pll_ref_fb_div.f.pll_ref_div = pll->M;
w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_int = pll->N_int;
w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_frac = pll->N_fac;
w100_pwr_state.pll_ref_fb_div.f.pll_lock_time = pll->lock_time;
writel((u32) (w100_pwr_state.pll_ref_fb_div.val), remapped_regs + mmPLL_REF_FB_DIV);
w100_pwr_state.pwrmgt_cntl.f.pwm_mode_req = 0;
writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL);
status = w100_pll_calibration(pll);
if (w100_pwr_state.auto_mode == 1) /* auto mode */
{
w100_pwr_state.pwrmgt_cntl.f.pwm_fast_noml_hw_en = 0x1; /* reenable fast to normal */
w100_pwr_state.pwrmgt_cntl.f.pwm_noml_fast_hw_en = 0x1; /* reenable normal to fast */
writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL);
}
return status;
}
/* freq = target frequency of the PLL */
static int w100_set_pll_freq(struct w100fb_par *par, unsigned int freq)
{
struct w100_pll_info *pll = par->pll_table;
do {
if (freq == pll->freq) {
return w100_pll_set_clk(pll);
}
pll++;
} while(pll->freq);
return 0;
}
/* Set up an initial state. Some values/fields set
here will be overwritten. */
static void w100_pwm_setup(struct w100fb_par *par)
{
w100_pwr_state.clk_pin_cntl.f.osc_en = 0x1;
w100_pwr_state.clk_pin_cntl.f.osc_gain = 0x1f;
w100_pwr_state.clk_pin_cntl.f.dont_use_xtalin = 0x0;
w100_pwr_state.clk_pin_cntl.f.xtalin_pm_en = 0x0;
w100_pwr_state.clk_pin_cntl.f.xtalin_dbl_en = par->mach->xtal_dbl ? 1 : 0;
w100_pwr_state.clk_pin_cntl.f.cg_debug = 0x0;
writel((u32) (w100_pwr_state.clk_pin_cntl.val), remapped_regs + mmCLK_PIN_CNTL);
w100_pwr_state.sclk_cntl.f.sclk_src_sel = CLK_SRC_XTAL;
w100_pwr_state.sclk_cntl.f.sclk_post_div_fast = 0x0; /* Pfast = 1 */
w100_pwr_state.sclk_cntl.f.sclk_clkon_hys = 0x3;
w100_pwr_state.sclk_cntl.f.sclk_post_div_slow = 0x0; /* Pslow = 1 */
w100_pwr_state.sclk_cntl.f.disp_cg_ok2switch_en = 0x0;
w100_pwr_state.sclk_cntl.f.sclk_force_reg = 0x0; /* Dynamic */
w100_pwr_state.sclk_cntl.f.sclk_force_disp = 0x0; /* Dynamic */
w100_pwr_state.sclk_cntl.f.sclk_force_mc = 0x0; /* Dynamic */
w100_pwr_state.sclk_cntl.f.sclk_force_extmc = 0x0; /* Dynamic */
w100_pwr_state.sclk_cntl.f.sclk_force_cp = 0x0; /* Dynamic */
w100_pwr_state.sclk_cntl.f.sclk_force_e2 = 0x0; /* Dynamic */
w100_pwr_state.sclk_cntl.f.sclk_force_e3 = 0x0; /* Dynamic */
w100_pwr_state.sclk_cntl.f.sclk_force_idct = 0x0; /* Dynamic */
w100_pwr_state.sclk_cntl.f.sclk_force_bist = 0x0; /* Dynamic */
w100_pwr_state.sclk_cntl.f.busy_extend_cp = 0x0;
w100_pwr_state.sclk_cntl.f.busy_extend_e2 = 0x0;
w100_pwr_state.sclk_cntl.f.busy_extend_e3 = 0x0;
w100_pwr_state.sclk_cntl.f.busy_extend_idct = 0x0;
writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL);
w100_pwr_state.pclk_cntl.f.pclk_src_sel = CLK_SRC_XTAL;
w100_pwr_state.pclk_cntl.f.pclk_post_div = 0x1; /* P = 2 */
w100_pwr_state.pclk_cntl.f.pclk_force_disp = 0x0; /* Dynamic */
writel((u32) (w100_pwr_state.pclk_cntl.val), remapped_regs + mmPCLK_CNTL);
w100_pwr_state.pll_ref_fb_div.f.pll_ref_div = 0x0; /* M = 1 */
w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_int = 0x0; /* N = 1.0 */
w100_pwr_state.pll_ref_fb_div.f.pll_fb_div_frac = 0x0;
w100_pwr_state.pll_ref_fb_div.f.pll_reset_time = 0x5;
w100_pwr_state.pll_ref_fb_div.f.pll_lock_time = 0xff;
writel((u32) (w100_pwr_state.pll_ref_fb_div.val), remapped_regs + mmPLL_REF_FB_DIV);
w100_pwr_state.pll_cntl.f.pll_pwdn = 0x1;
w100_pwr_state.pll_cntl.f.pll_reset = 0x1;
w100_pwr_state.pll_cntl.f.pll_pm_en = 0x0;
w100_pwr_state.pll_cntl.f.pll_mode = 0x0; /* uses VCO clock */
w100_pwr_state.pll_cntl.f.pll_refclk_sel = 0x0;
w100_pwr_state.pll_cntl.f.pll_fbclk_sel = 0x0;
w100_pwr_state.pll_cntl.f.pll_tcpoff = 0x0;
w100_pwr_state.pll_cntl.f.pll_pcp = 0x4;
w100_pwr_state.pll_cntl.f.pll_pvg = 0x0;
w100_pwr_state.pll_cntl.f.pll_vcofr = 0x0;
w100_pwr_state.pll_cntl.f.pll_ioffset = 0x0;
w100_pwr_state.pll_cntl.f.pll_pecc_mode = 0x0;
w100_pwr_state.pll_cntl.f.pll_pecc_scon = 0x0;
w100_pwr_state.pll_cntl.f.pll_dactal = 0x0; /* Hi-Z */
w100_pwr_state.pll_cntl.f.pll_cp_clip = 0x3;
w100_pwr_state.pll_cntl.f.pll_conf = 0x2;
w100_pwr_state.pll_cntl.f.pll_mbctrl = 0x2;
w100_pwr_state.pll_cntl.f.pll_ring_off = 0x0;
writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL);
w100_pwr_state.pwrmgt_cntl.f.pwm_enable = 0x0;
w100_pwr_state.pwrmgt_cntl.f.pwm_mode_req = 0x1; /* normal mode (0, 1, 3) */
w100_pwr_state.pwrmgt_cntl.f.pwm_wakeup_cond = 0x0;
w100_pwr_state.pwrmgt_cntl.f.pwm_fast_noml_hw_en = 0x0;
w100_pwr_state.pwrmgt_cntl.f.pwm_noml_fast_hw_en = 0x0;
w100_pwr_state.pwrmgt_cntl.f.pwm_fast_noml_cond = 0x1; /* PM4,ENG */
w100_pwr_state.pwrmgt_cntl.f.pwm_noml_fast_cond = 0x1; /* PM4,ENG */
w100_pwr_state.pwrmgt_cntl.f.pwm_idle_timer = 0xFF;
w100_pwr_state.pwrmgt_cntl.f.pwm_busy_timer = 0xFF;
writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL);
w100_pwr_state.auto_mode = 0; /* manual mode */
}
/*
* Setup the w100 clocks for the specified mode
*/
static void w100_init_clocks(struct w100fb_par *par)
{
struct w100_mode *mode = par->mode;
if (mode->pixclk_src == CLK_SRC_PLL || mode->sysclk_src == CLK_SRC_PLL)
w100_set_pll_freq(par, (par->fastpll_mode && mode->fast_pll_freq) ? mode->fast_pll_freq : mode->pll_freq);
w100_pwr_state.sclk_cntl.f.sclk_src_sel = mode->sysclk_src;
w100_pwr_state.sclk_cntl.f.sclk_post_div_fast = mode->sysclk_divider;
w100_pwr_state.sclk_cntl.f.sclk_post_div_slow = mode->sysclk_divider;
writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL);
}
static void w100_init_lcd(struct w100fb_par *par)
{
u32 temp32;
struct w100_mode *mode = par->mode;
struct w100_gen_regs *regs = par->mach->regs;
union active_h_disp_u active_h_disp;
union active_v_disp_u active_v_disp;
union graphic_h_disp_u graphic_h_disp;
union graphic_v_disp_u graphic_v_disp;
union crtc_total_u crtc_total;
/* w3200 doesn't like undefined bits being set so zero register values first */
active_h_disp.val = 0;
active_h_disp.f.active_h_start=mode->left_margin;
active_h_disp.f.active_h_end=mode->left_margin + mode->xres;
writel(active_h_disp.val, remapped_regs + mmACTIVE_H_DISP);
active_v_disp.val = 0;
active_v_disp.f.active_v_start=mode->upper_margin;
active_v_disp.f.active_v_end=mode->upper_margin + mode->yres;
writel(active_v_disp.val, remapped_regs + mmACTIVE_V_DISP);
graphic_h_disp.val = 0;
graphic_h_disp.f.graphic_h_start=mode->left_margin;
graphic_h_disp.f.graphic_h_end=mode->left_margin + mode->xres;
writel(graphic_h_disp.val, remapped_regs + mmGRAPHIC_H_DISP);
graphic_v_disp.val = 0;
graphic_v_disp.f.graphic_v_start=mode->upper_margin;
graphic_v_disp.f.graphic_v_end=mode->upper_margin + mode->yres;
writel(graphic_v_disp.val, remapped_regs + mmGRAPHIC_V_DISP);
crtc_total.val = 0;
crtc_total.f.crtc_h_total=mode->left_margin + mode->xres + mode->right_margin;
crtc_total.f.crtc_v_total=mode->upper_margin + mode->yres + mode->lower_margin;
writel(crtc_total.val, remapped_regs + mmCRTC_TOTAL);
writel(mode->crtc_ss, remapped_regs + mmCRTC_SS);
writel(mode->crtc_ls, remapped_regs + mmCRTC_LS);
writel(mode->crtc_gs, remapped_regs + mmCRTC_GS);
writel(mode->crtc_vpos_gs, remapped_regs + mmCRTC_VPOS_GS);
writel(mode->crtc_rev, remapped_regs + mmCRTC_REV);
writel(mode->crtc_dclk, remapped_regs + mmCRTC_DCLK);
writel(mode->crtc_gclk, remapped_regs + mmCRTC_GCLK);
writel(mode->crtc_goe, remapped_regs + mmCRTC_GOE);
writel(mode->crtc_ps1_active, remapped_regs + mmCRTC_PS1_ACTIVE);
writel(regs->lcd_format, remapped_regs + mmLCD_FORMAT);
writel(regs->lcdd_cntl1, remapped_regs + mmLCDD_CNTL1);
writel(regs->lcdd_cntl2, remapped_regs + mmLCDD_CNTL2);
writel(regs->genlcd_cntl1, remapped_regs + mmGENLCD_CNTL1);
writel(regs->genlcd_cntl2, remapped_regs + mmGENLCD_CNTL2);
writel(regs->genlcd_cntl3, remapped_regs + mmGENLCD_CNTL3);
writel(0x00000000, remapped_regs + mmCRTC_FRAME);
writel(0x00000000, remapped_regs + mmCRTC_FRAME_VPOS);
writel(0x00000000, remapped_regs + mmCRTC_DEFAULT_COUNT);
writel(0x0000FF00, remapped_regs + mmLCD_BACKGROUND_COLOR);
/* Hack for overlay in ext memory */
temp32 = readl(remapped_regs + mmDISP_DEBUG2);
temp32 |= 0xc0000000;
writel(temp32, remapped_regs + mmDISP_DEBUG2);
}
static void w100_setup_memory(struct w100fb_par *par)
{
union mc_ext_mem_location_u extmem_location;
union mc_fb_location_u intmem_location;
struct w100_mem_info *mem = par->mach->mem;
struct w100_bm_mem_info *bm_mem = par->mach->bm_mem;
if (!par->extmem_active) {
w100_suspend(W100_SUSPEND_EXTMEM);
/* Map Internal Memory at FB Base */
intmem_location.f.mc_fb_start = W100_FB_BASE >> 8;
intmem_location.f.mc_fb_top = (W100_FB_BASE+MEM_INT_SIZE) >> 8;
writel((u32) (intmem_location.val), remapped_regs + mmMC_FB_LOCATION);
/* Unmap External Memory - value is *probably* irrelevant but may have meaning
to acceleration libraries */
extmem_location.f.mc_ext_mem_start = MEM_EXT_BASE_VALUE >> 8;
extmem_location.f.mc_ext_mem_top = (MEM_EXT_BASE_VALUE-1) >> 8;
writel((u32) (extmem_location.val), remapped_regs + mmMC_EXT_MEM_LOCATION);
} else {
/* Map Internal Memory to its default location */
intmem_location.f.mc_fb_start = MEM_INT_BASE_VALUE >> 8;
intmem_location.f.mc_fb_top = (MEM_INT_BASE_VALUE+MEM_INT_SIZE) >> 8;
writel((u32) (intmem_location.val), remapped_regs + mmMC_FB_LOCATION);
/* Map External Memory at FB Base */
extmem_location.f.mc_ext_mem_start = W100_FB_BASE >> 8;
extmem_location.f.mc_ext_mem_top = (W100_FB_BASE+par->mach->mem->size) >> 8;
writel((u32) (extmem_location.val), remapped_regs + mmMC_EXT_MEM_LOCATION);
writel(0x00007800, remapped_regs + mmMC_BIST_CTRL);
writel(mem->ext_cntl, remapped_regs + mmMEM_EXT_CNTL);
writel(0x00200021, remapped_regs + mmMEM_SDRAM_MODE_REG);
udelay(100);
writel(0x80200021, remapped_regs + mmMEM_SDRAM_MODE_REG);
udelay(100);
writel(mem->sdram_mode_reg, remapped_regs + mmMEM_SDRAM_MODE_REG);
udelay(100);
writel(mem->ext_timing_cntl, remapped_regs + mmMEM_EXT_TIMING_CNTL);
writel(mem->io_cntl, remapped_regs + mmMEM_IO_CNTL);
if (bm_mem) {
writel(bm_mem->ext_mem_bw, remapped_regs + mmBM_EXT_MEM_BANDWIDTH);
writel(bm_mem->offset, remapped_regs + mmBM_OFFSET);
writel(bm_mem->ext_timing_ctl, remapped_regs + mmBM_MEM_EXT_TIMING_CNTL);
writel(bm_mem->ext_cntl, remapped_regs + mmBM_MEM_EXT_CNTL);
writel(bm_mem->mode_reg, remapped_regs + mmBM_MEM_MODE_REG);
writel(bm_mem->io_cntl, remapped_regs + mmBM_MEM_IO_CNTL);
writel(bm_mem->config, remapped_regs + mmBM_CONFIG);
}
}
}
static void w100_set_dispregs(struct w100fb_par *par)
{
unsigned long rot=0, divider, offset=0;
union graphic_ctrl_u graphic_ctrl;
/* See if the mode has been rotated */
if (par->xres == par->mode->xres) {
if (par->flip) {
rot=3; /* 180 degree */
offset=(par->xres * par->yres) - 1;
} /* else 0 degree */
divider = par->mode->pixclk_divider;
} else {
if (par->flip) {
rot=2; /* 270 degree */
offset=par->xres - 1;
} else {
rot=1; /* 90 degree */
offset=par->xres * (par->yres - 1);
}
divider = par->mode->pixclk_divider_rotated;
}
graphic_ctrl.val = 0; /* w32xx doesn't like undefined bits */
switch (par->chip_id) {
case CHIP_ID_W100:
graphic_ctrl.f_w100.color_depth=6;
graphic_ctrl.f_w100.en_crtc=1;
graphic_ctrl.f_w100.en_graphic_req=1;
graphic_ctrl.f_w100.en_graphic_crtc=1;
graphic_ctrl.f_w100.lcd_pclk_on=1;
graphic_ctrl.f_w100.lcd_sclk_on=1;
graphic_ctrl.f_w100.low_power_on=0;
graphic_ctrl.f_w100.req_freq=0;
graphic_ctrl.f_w100.portrait_mode=rot;
/* Zaurus needs this */
switch(par->xres) {
case 240:
case 320:
default:
graphic_ctrl.f_w100.total_req_graphic=0xa0;
break;
case 480:
case 640:
switch(rot) {
case 0: /* 0 */
case 3: /* 180 */
graphic_ctrl.f_w100.low_power_on=1;
graphic_ctrl.f_w100.req_freq=5;
break;
case 1: /* 90 */
case 2: /* 270 */
graphic_ctrl.f_w100.req_freq=4;
break;
default:
break;
}
graphic_ctrl.f_w100.total_req_graphic=0xf0;
break;
}
break;
case CHIP_ID_W3200:
case CHIP_ID_W3220:
graphic_ctrl.f_w32xx.color_depth=6;
graphic_ctrl.f_w32xx.en_crtc=1;
graphic_ctrl.f_w32xx.en_graphic_req=1;
graphic_ctrl.f_w32xx.en_graphic_crtc=1;
graphic_ctrl.f_w32xx.lcd_pclk_on=1;
graphic_ctrl.f_w32xx.lcd_sclk_on=1;
graphic_ctrl.f_w32xx.low_power_on=0;
graphic_ctrl.f_w32xx.req_freq=0;
graphic_ctrl.f_w32xx.total_req_graphic=par->mode->xres >> 1; /* panel xres, not mode */
graphic_ctrl.f_w32xx.portrait_mode=rot;
break;
}
/* Set the pixel clock source and divider */
w100_pwr_state.pclk_cntl.f.pclk_src_sel = par->mode->pixclk_src;
w100_pwr_state.pclk_cntl.f.pclk_post_div = divider;
writel((u32) (w100_pwr_state.pclk_cntl.val), remapped_regs + mmPCLK_CNTL);
writel(graphic_ctrl.val, remapped_regs + mmGRAPHIC_CTRL);
writel(W100_FB_BASE + ((offset * BITS_PER_PIXEL/8)&~0x03UL), remapped_regs + mmGRAPHIC_OFFSET);
writel((par->xres*BITS_PER_PIXEL/8), remapped_regs + mmGRAPHIC_PITCH);
}
/*
* Work out how long the sync pulse lasts
* Value is 1/(time in seconds)
*/
static void calc_hsync(struct w100fb_par *par)
{
unsigned long hsync;
struct w100_mode *mode = par->mode;
union crtc_ss_u crtc_ss;
if (mode->pixclk_src == CLK_SRC_XTAL)
hsync=par->mach->xtal_freq;
else
hsync=((par->fastpll_mode && mode->fast_pll_freq) ? mode->fast_pll_freq : mode->pll_freq)*100000;
hsync /= (w100_pwr_state.pclk_cntl.f.pclk_post_div + 1);
crtc_ss.val = readl(remapped_regs + mmCRTC_SS);
if (crtc_ss.val)
par->hsync_len = hsync / (crtc_ss.f.ss_end-crtc_ss.f.ss_start);
else
par->hsync_len = 0;
}
static void w100_suspend(u32 mode)
{
u32 val;
writel(0x7FFF8000, remapped_regs + mmMC_EXT_MEM_LOCATION);
writel(0x00FF0000, remapped_regs + mmMC_PERF_MON_CNTL);
val = readl(remapped_regs + mmMEM_EXT_TIMING_CNTL);
val &= ~(0x00100000); /* bit20=0 */
val |= 0xFF000000; /* bit31:24=0xff */
writel(val, remapped_regs + mmMEM_EXT_TIMING_CNTL);
val = readl(remapped_regs + mmMEM_EXT_CNTL);
val &= ~(0x00040000); /* bit18=0 */
val |= 0x00080000; /* bit19=1 */
writel(val, remapped_regs + mmMEM_EXT_CNTL);
udelay(1); /* wait 1us */
if (mode == W100_SUSPEND_EXTMEM) {
/* CKE: Tri-State */
val = readl(remapped_regs + mmMEM_EXT_CNTL);
val |= 0x40000000; /* bit30=1 */
writel(val, remapped_regs + mmMEM_EXT_CNTL);
/* CLK: Stop */
val = readl(remapped_regs + mmMEM_EXT_CNTL);
val &= ~(0x00000001); /* bit0=0 */
writel(val, remapped_regs + mmMEM_EXT_CNTL);
} else {
writel(0x00000000, remapped_regs + mmSCLK_CNTL);
writel(0x000000BF, remapped_regs + mmCLK_PIN_CNTL);
writel(0x00000015, remapped_regs + mmPWRMGT_CNTL);
udelay(5);
val = readl(remapped_regs + mmPLL_CNTL);
val |= 0x00000004; /* bit2=1 */
writel(val, remapped_regs + mmPLL_CNTL);
writel(0x00000000, remapped_regs + mmLCDD_CNTL1);
writel(0x00000000, remapped_regs + mmLCDD_CNTL2);
writel(0x00000000, remapped_regs + mmGENLCD_CNTL1);
writel(0x00000000, remapped_regs + mmGENLCD_CNTL2);
writel(0x00000000, remapped_regs + mmGENLCD_CNTL3);
val = readl(remapped_regs + mmMEM_EXT_CNTL);
val |= 0xF0000000;
val &= ~(0x00000001);
writel(val, remapped_regs + mmMEM_EXT_CNTL);
writel(0x0000001d, remapped_regs + mmPWRMGT_CNTL);
}
}
static void w100_vsync(void)
{
u32 tmp;
int timeout = 30000; /* VSync timeout = 30[ms] > 16.8[ms] */
tmp = readl(remapped_regs + mmACTIVE_V_DISP);
/* set vline pos */
writel((tmp >> 16) & 0x3ff, remapped_regs + mmDISP_INT_CNTL);
/* disable vline irq */
tmp = readl(remapped_regs + mmGEN_INT_CNTL);
tmp &= ~0x00000002;
writel(tmp, remapped_regs + mmGEN_INT_CNTL);
/* clear vline irq status */
writel(0x00000002, remapped_regs + mmGEN_INT_STATUS);
/* enable vline irq */
writel((tmp | 0x00000002), remapped_regs + mmGEN_INT_CNTL);
/* clear vline irq status */
writel(0x00000002, remapped_regs + mmGEN_INT_STATUS);
while(timeout > 0) {
if (readl(remapped_regs + mmGEN_INT_STATUS) & 0x00000002)
break;
udelay(1);
timeout--;
}
/* disable vline irq */
writel(tmp, remapped_regs + mmGEN_INT_CNTL);
/* clear vline irq status */
writel(0x00000002, remapped_regs + mmGEN_INT_STATUS);
}
static struct platform_driver w100fb_driver = {
.probe = w100fb_probe,
.remove = w100fb_remove,
.suspend = w100fb_suspend,
.resume = w100fb_resume,
.driver = {
.name = "w100fb",
.dev_groups = w100fb_groups,
},
};
module_platform_driver(w100fb_driver);
MODULE_DESCRIPTION("ATI Imageon w100 framebuffer driver");
MODULE_LICENSE("GPL");
drivers/video/fbdev/w100fb.h deleted 100644 → 0
View file @ aceae784
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* linux/drivers/video/w100fb.h
*
* Frame Buffer Device for ATI w100 (Wallaby)
*
* Copyright (C) 2002, ATI Corp.
* Copyright (C) 2004-2005 Richard Purdie
* Copyright (c) 2005 Ian Molton <spyro@f2s.com>
*
* Modified to work with 2.6 by Richard Purdie <rpurdie@rpsys.net>
*
* w32xx support by Ian Molton
*/
#if !defined (_W100FB_H)
#define _W100FB_H
/* Block CIF Start: */
#define mmCHIP_ID 0x0000
#define mmREVISION_ID 0x0004
#define mmWRAP_BUF_A 0x0008
#define mmWRAP_BUF_B 0x000C
#define mmWRAP_TOP_DIR 0x0010
#define mmWRAP_START_DIR 0x0014
#define mmCIF_CNTL 0x0018
#define mmCFGREG_BASE 0x001C
#define mmCIF_IO 0x0020
#define mmCIF_READ_DBG 0x0024
#define mmCIF_WRITE_DBG 0x0028
#define cfgIND_ADDR_A_0 0x0000
#define cfgIND_ADDR_A_1 0x0001
#define cfgIND_ADDR_A_2 0x0002
#define cfgIND_DATA_A 0x0003
#define cfgREG_BASE 0x0004
#define cfgINTF_CNTL 0x0005
#define cfgSTATUS 0x0006
#define cfgCPU_DEFAULTS 0x0007
#define cfgIND_ADDR_B_0 0x0008
#define cfgIND_ADDR_B_1 0x0009
#define cfgIND_ADDR_B_2 0x000A
#define cfgIND_DATA_B 0x000B
#define cfgPM4_RPTR 0x000C
#define cfgSCRATCH 0x000D
#define cfgPM4_WRPTR_0 0x000E
#define cfgPM4_WRPTR_1 0x000F
/* Block CIF End: */
/* Block CP Start: */
#define mmSCRATCH_UMSK 0x0280
#define mmSCRATCH_ADDR 0x0284
#define mmGEN_INT_CNTL 0x0200
#define mmGEN_INT_STATUS 0x0204
/* Block CP End: */
/* Block DISPLAY Start: */
#define mmLCD_FORMAT 0x0410
#define mmGRAPHIC_CTRL 0x0414
#define mmGRAPHIC_OFFSET 0x0418
#define mmGRAPHIC_PITCH 0x041C
#define mmCRTC_TOTAL 0x0420
#define mmACTIVE_H_DISP 0x0424
#define mmACTIVE_V_DISP 0x0428
#define mmGRAPHIC_H_DISP 0x042C
#define mmGRAPHIC_V_DISP 0x0430
#define mmVIDEO_CTRL 0x0434
#define mmGRAPHIC_KEY 0x0438
#define mmBRIGHTNESS_CNTL 0x045C
#define mmDISP_INT_CNTL 0x0488
#define mmCRTC_SS 0x048C
#define mmCRTC_LS 0x0490
#define mmCRTC_REV 0x0494
#define mmCRTC_DCLK 0x049C
#define mmCRTC_GS 0x04A0
#define mmCRTC_VPOS_GS 0x04A4
#define mmCRTC_GCLK 0x04A8
#define mmCRTC_GOE 0x04AC
#define mmCRTC_FRAME 0x04B0
#define mmCRTC_FRAME_VPOS 0x04B4
#define mmGPIO_DATA 0x04B8
#define mmGPIO_CNTL1 0x04BC
#define mmGPIO_CNTL2 0x04C0
#define mmLCDD_CNTL1 0x04C4
#define mmLCDD_CNTL2 0x04C8
#define mmGENLCD_CNTL1 0x04CC
#define mmGENLCD_CNTL2 0x04D0
#define mmDISP_DEBUG 0x04D4
#define mmDISP_DB_BUF_CNTL 0x04D8
#define mmDISP_CRC_SIG 0x04DC
#define mmCRTC_DEFAULT_COUNT 0x04E0
#define mmLCD_BACKGROUND_COLOR 0x04E4
#define mmCRTC_PS2 0x04E8
#define mmCRTC_PS2_VPOS 0x04EC
#define mmCRTC_PS1_ACTIVE 0x04F0
#define mmCRTC_PS1_NACTIVE 0x04F4
#define mmCRTC_GCLK_EXT 0x04F8
#define mmCRTC_ALW 0x04FC
#define mmCRTC_ALW_VPOS 0x0500
#define mmCRTC_PSK 0x0504
#define mmCRTC_PSK_HPOS 0x0508
#define mmCRTC_CV4_START 0x050C
#define mmCRTC_CV4_END 0x0510
#define mmCRTC_CV4_HPOS 0x0514
#define mmCRTC_ECK 0x051C
#define mmREFRESH_CNTL 0x0520
#define mmGENLCD_CNTL3 0x0524
#define mmGPIO_DATA2 0x0528
#define mmGPIO_CNTL3 0x052C
#define mmGPIO_CNTL4 0x0530
#define mmCHIP_STRAP 0x0534
#define mmDISP_DEBUG2 0x0538
#define mmDEBUG_BUS_CNTL 0x053C
#define mmGAMMA_VALUE1 0x0540
#define mmGAMMA_VALUE2 0x0544
#define mmGAMMA_SLOPE 0x0548
#define mmGEN_STATUS 0x054C
#define mmHW_INT 0x0550
/* Block DISPLAY End: */
/* Block GFX Start: */
#define mmDST_OFFSET 0x1004
#define mmDST_PITCH 0x1008
#define mmDST_Y_X 0x1038
#define mmDST_WIDTH_HEIGHT 0x1198
#define mmDP_GUI_MASTER_CNTL 0x106C
#define mmBRUSH_OFFSET 0x108C
#define mmBRUSH_Y_X 0x1074
#define mmDP_BRUSH_FRGD_CLR 0x107C
#define mmSRC_OFFSET 0x11AC
#define mmSRC_PITCH 0x11B0
#define mmSRC_Y_X 0x1034
#define mmDEFAULT_PITCH_OFFSET 0x10A0
#define mmDEFAULT_SC_BOTTOM_RIGHT 0x10A8
#define mmDEFAULT2_SC_BOTTOM_RIGHT 0x10AC
#define mmSC_TOP_LEFT 0x11BC
#define mmSC_BOTTOM_RIGHT 0x11C0
#define mmSRC_SC_BOTTOM_RIGHT 0x11C4
#define mmGLOBAL_ALPHA 0x1210
#define mmFILTER_COEF 0x1214
#define mmMVC_CNTL_START 0x11E0
#define mmE2_ARITHMETIC_CNTL 0x1220
#define mmDP_CNTL 0x11C8
#define mmDP_CNTL_DST_DIR 0x11CC
#define mmDP_DATATYPE 0x12C4
#define mmDP_MIX 0x12C8
#define mmDP_WRITE_MSK 0x12CC
#define mmENG_CNTL 0x13E8
#define mmENG_PERF_CNT 0x13F0
/* Block GFX End: */
/* Block IDCT Start: */
#define mmIDCT_RUNS 0x0C00
#define mmIDCT_LEVELS 0x0C04
#define mmIDCT_CONTROL 0x0C3C
#define mmIDCT_AUTH_CONTROL 0x0C08
#define mmIDCT_AUTH 0x0C0C
/* Block IDCT End: */
/* Block MC Start: */
#define mmMEM_CNTL 0x0180
#define mmMEM_ARB 0x0184
#define mmMC_FB_LOCATION 0x0188
#define mmMEM_EXT_CNTL 0x018C
#define mmMC_EXT_MEM_LOCATION 0x0190
#define mmMEM_EXT_TIMING_CNTL 0x0194
#define mmMEM_SDRAM_MODE_REG 0x0198
#define mmMEM_IO_CNTL 0x019C
#define mmMC_DEBUG 0x01A0
#define mmMC_BIST_CTRL 0x01A4
#define mmMC_BIST_COLLAR_READ 0x01A8
#define mmTC_MISMATCH 0x01AC
#define mmMC_PERF_MON_CNTL 0x01B0
#define mmMC_PERF_COUNTERS 0x01B4
/* Block MC End: */
/* Block BM Start: */
#define mmBM_EXT_MEM_BANDWIDTH 0x0A00
#define mmBM_OFFSET 0x0A04
#define mmBM_MEM_EXT_TIMING_CNTL 0x0A08
#define mmBM_MEM_EXT_CNTL 0x0A0C
#define mmBM_MEM_MODE_REG 0x0A10
#define mmBM_MEM_IO_CNTL 0x0A18
#define mmBM_CONFIG 0x0A1C
#define mmBM_STATUS 0x0A20
#define mmBM_DEBUG 0x0A24
#define mmBM_PERF_MON_CNTL 0x0A28
#define mmBM_PERF_COUNTERS 0x0A2C
#define mmBM_PERF2_MON_CNTL 0x0A30
#define mmBM_PERF2_COUNTERS 0x0A34
/* Block BM End: */
/* Block RBBM Start: */
#define mmWAIT_UNTIL 0x1400
#define mmISYNC_CNTL 0x1404
#define mmRBBM_STATUS 0x0140
#define mmRBBM_CNTL 0x0144
#define mmNQWAIT_UNTIL 0x0150
/* Block RBBM End: */
/* Block CG Start: */
#define mmCLK_PIN_CNTL 0x0080
#define mmPLL_REF_FB_DIV 0x0084
#define mmPLL_CNTL 0x0088
#define mmSCLK_CNTL 0x008C
#define mmPCLK_CNTL 0x0090
#define mmCLK_TEST_CNTL 0x0094
#define mmPWRMGT_CNTL 0x0098
#define mmPWRMGT_STATUS 0x009C
/* Block CG End: */
/* default value definitions */
#define defWRAP_TOP_DIR 0x00000000
#define defWRAP_START_DIR 0x00000000
#define defCFGREG_BASE 0x00000000
#define defCIF_IO 0x000C0902
#define defINTF_CNTL 0x00000011
#define defCPU_DEFAULTS 0x00000006
#define defHW_INT 0x00000000
#define defMC_EXT_MEM_LOCATION 0x07ff0000
#define defTC_MISMATCH 0x00000000
#define W100_CFG_BASE 0x0
#define W100_CFG_LEN 0x10
#define W100_REG_BASE 0x10000
#define W100_REG_LEN 0x2000
#define MEM_INT_BASE_VALUE 0x100000
#define MEM_EXT_BASE_VALUE 0x800000
#define MEM_INT_SIZE 0x05ffff
#define MEM_WINDOW_BASE 0x100000
#define MEM_WINDOW_SIZE 0xf00000
#define WRAP_BUF_BASE_VALUE 0x80000
#define WRAP_BUF_TOP_VALUE 0xbffff
#define CHIP_ID_W100 0x57411002
#define CHIP_ID_W3200 0x56441002
#define CHIP_ID_W3220 0x57441002
/* Register structure definitions */
struct wrap_top_dir_t {
u32 top_addr : 23;
u32 : 9;
} __attribute__((packed));
union wrap_top_dir_u {
u32 val : 32;
struct wrap_top_dir_t f;
} __attribute__((packed));
struct wrap_start_dir_t {
u32 start_addr : 23;
u32 : 9;
} __attribute__((packed));
union wrap_start_dir_u {
u32 val : 32;
struct wrap_start_dir_t f;
} __attribute__((packed));
struct cif_cntl_t {
u32 swap_reg : 2;
u32 swap_fbuf_1 : 2;
u32 swap_fbuf_2 : 2;
u32 swap_fbuf_3 : 2;
u32 pmi_int_disable : 1;
u32 pmi_schmen_disable : 1;
u32 intb_oe : 1;
u32 en_wait_to_compensate_dq_prop_dly : 1;
u32 compensate_wait_rd_size : 2;
u32 wait_asserted_timeout_val : 2;
u32 wait_masked_val : 2;
u32 en_wait_timeout : 1;
u32 en_one_clk_setup_before_wait : 1;
u32 interrupt_active_high : 1;
u32 en_overwrite_straps : 1;
u32 strap_wait_active_hi : 1;
u32 lat_busy_count : 2;
u32 lat_rd_pm4_sclk_busy : 1;
u32 dis_system_bits : 1;
u32 dis_mr : 1;
u32 cif_spare_1 : 4;
} __attribute__((packed));
union cif_cntl_u {
u32 val : 32;
struct cif_cntl_t f;
} __attribute__((packed));
struct cfgreg_base_t {
u32 cfgreg_base : 24;
u32 : 8;
} __attribute__((packed));
union cfgreg_base_u {
u32 val : 32;
struct cfgreg_base_t f;
} __attribute__((packed));
struct cif_io_t {
u32 dq_srp : 1;
u32 dq_srn : 1;
u32 dq_sp : 4;
u32 dq_sn : 4;
u32 waitb_srp : 1;
u32 waitb_srn : 1;
u32 waitb_sp : 4;
u32 waitb_sn : 4;
u32 intb_srp : 1;
u32 intb_srn : 1;
u32 intb_sp : 4;
u32 intb_sn : 4;
u32 : 2;
} __attribute__((packed));
union cif_io_u {
u32 val : 32;
struct cif_io_t f;
} __attribute__((packed));
struct cif_read_dbg_t {
u32 unpacker_pre_fetch_trig_gen : 2;
u32 dly_second_rd_fetch_trig : 1;
u32 rst_rd_burst_id : 1;
u32 dis_rd_burst_id : 1;
u32 en_block_rd_when_packer_is_not_emp : 1;
u32 dis_pre_fetch_cntl_sm : 1;
u32 rbbm_chrncy_dis : 1;
u32 rbbm_rd_after_wr_lat : 2;
u32 dis_be_during_rd : 1;
u32 one_clk_invalidate_pulse : 1;
u32 dis_chnl_priority : 1;
u32 rst_read_path_a_pls : 1;
u32 rst_read_path_b_pls : 1;
u32 dis_reg_rd_fetch_trig : 1;
u32 dis_rd_fetch_trig_from_ind_addr : 1;
u32 dis_rd_same_byte_to_trig_fetch : 1;
u32 dis_dir_wrap : 1;
u32 dis_ring_buf_to_force_dec : 1;
u32 dis_addr_comp_in_16bit : 1;
u32 clr_w : 1;
u32 err_rd_tag_is_3 : 1;
u32 err_load_when_ful_a : 1;
u32 err_load_when_ful_b : 1;
u32 : 7;
} __attribute__((packed));
union cif_read_dbg_u {
u32 val : 32;
struct cif_read_dbg_t f;
} __attribute__((packed));
struct cif_write_dbg_t {
u32 packer_timeout_count : 2;
u32 en_upper_load_cond : 1;
u32 en_chnl_change_cond : 1;
u32 dis_addr_comp_cond : 1;
u32 dis_load_same_byte_addr_cond : 1;
u32 dis_timeout_cond : 1;
u32 dis_timeout_during_rbbm : 1;
u32 dis_packer_ful_during_rbbm_timeout : 1;
u32 en_dword_split_to_rbbm : 1;
u32 en_dummy_val : 1;
u32 dummy_val_sel : 1;
u32 mask_pm4_wrptr_dec : 1;
u32 dis_mc_clean_cond : 1;
u32 err_two_reqi_during_ful : 1;
u32 err_reqi_during_idle_clk : 1;
u32 err_global : 1;
u32 en_wr_buf_dbg_load : 1;
u32 en_wr_buf_dbg_path : 1;
u32 sel_wr_buf_byte : 3;
u32 dis_rd_flush_wr : 1;
u32 dis_packer_ful_cond : 1;
u32 dis_invalidate_by_ops_chnl : 1;
u32 en_halt_when_reqi_err : 1;
u32 cif_spare_2 : 5;
u32 : 1;
} __attribute__((packed));
union cif_write_dbg_u {
u32 val : 32;
struct cif_write_dbg_t f;
} __attribute__((packed));
struct intf_cntl_t {
unsigned char ad_inc_a : 1;
unsigned char ring_buf_a : 1;
unsigned char rd_fetch_trigger_a : 1;
unsigned char rd_data_rdy_a : 1;
unsigned char ad_inc_b : 1;
unsigned char ring_buf_b : 1;
unsigned char rd_fetch_trigger_b : 1;
unsigned char rd_data_rdy_b : 1;
} __attribute__((packed));
union intf_cntl_u {
unsigned char val : 8;
struct intf_cntl_t f;
} __attribute__((packed));
struct cpu_defaults_t {
unsigned char unpack_rd_data : 1;
unsigned char access_ind_addr_a : 1;
unsigned char access_ind_addr_b : 1;
unsigned char access_scratch_reg : 1;
unsigned char pack_wr_data : 1;
unsigned char transition_size : 1;
unsigned char en_read_buf_mode : 1;
unsigned char rd_fetch_scratch : 1;
} __attribute__((packed));
union cpu_defaults_u {
unsigned char val : 8;
struct cpu_defaults_t f;
} __attribute__((packed));
struct crtc_total_t {
u32 crtc_h_total : 10;
u32 : 6;
u32 crtc_v_total : 10;
u32 : 6;
} __attribute__((packed));
union crtc_total_u {
u32 val : 32;
struct crtc_total_t f;
} __attribute__((packed));
struct crtc_ss_t {
u32 ss_start : 10;
u32 : 6;
u32 ss_end : 10;
u32 : 2;
u32 ss_align : 1;
u32 ss_pol : 1;
u32 ss_run_mode : 1;
u32 ss_en : 1;
} __attribute__((packed));
union crtc_ss_u {
u32 val : 32;
struct crtc_ss_t f;
} __attribute__((packed));
struct active_h_disp_t {
u32 active_h_start : 10;
u32 : 6;
u32 active_h_end : 10;
u32 : 6;
} __attribute__((packed));
union active_h_disp_u {
u32 val : 32;
struct active_h_disp_t f;
} __attribute__((packed));
struct active_v_disp_t {
u32 active_v_start : 10;
u32 : 6;
u32 active_v_end : 10;
u32 : 6;
} __attribute__((packed));
union active_v_disp_u {
u32 val : 32;
struct active_v_disp_t f;
} __attribute__((packed));
struct graphic_h_disp_t {
u32 graphic_h_start : 10;
u32 : 6;
u32 graphic_h_end : 10;
u32 : 6;
} __attribute__((packed));
union graphic_h_disp_u {
u32 val : 32;
struct graphic_h_disp_t f;
} __attribute__((packed));
struct graphic_v_disp_t {
u32 graphic_v_start : 10;
u32 : 6;
u32 graphic_v_end : 10;
u32 : 6;
} __attribute__((packed));
union graphic_v_disp_u{
u32 val : 32;
struct graphic_v_disp_t f;
} __attribute__((packed));
struct graphic_ctrl_t_w100 {
u32 color_depth : 3;
u32 portrait_mode : 2;
u32 low_power_on : 1;
u32 req_freq : 4;
u32 en_crtc : 1;
u32 en_graphic_req : 1;
u32 en_graphic_crtc : 1;
u32 total_req_graphic : 9;
u32 lcd_pclk_on : 1;
u32 lcd_sclk_on : 1;
u32 pclk_running : 1;
u32 sclk_running : 1;
u32 : 6;
} __attribute__((packed));
struct graphic_ctrl_t_w32xx {
u32 color_depth : 3;
u32 portrait_mode : 2;
u32 low_power_on : 1;
u32 req_freq : 4;
u32 en_crtc : 1;
u32 en_graphic_req : 1;
u32 en_graphic_crtc : 1;
u32 total_req_graphic : 10;
u32 lcd_pclk_on : 1;
u32 lcd_sclk_on : 1;
u32 pclk_running : 1;
u32 sclk_running : 1;
u32 : 5;
} __attribute__((packed));
union graphic_ctrl_u {
u32 val : 32;
struct graphic_ctrl_t_w100 f_w100;
struct graphic_ctrl_t_w32xx f_w32xx;
} __attribute__((packed));
struct video_ctrl_t {
u32 video_mode : 1;
u32 keyer_en : 1;
u32 en_video_req : 1;
u32 en_graphic_req_video : 1;
u32 en_video_crtc : 1;
u32 video_hor_exp : 2;
u32 video_ver_exp : 2;
u32 uv_combine : 1;
u32 total_req_video : 9;
u32 video_ch_sel : 1;
u32 video_portrait : 2;
u32 yuv2rgb_en : 1;
u32 yuv2rgb_option : 1;
u32 video_inv_hor : 1;
u32 video_inv_ver : 1;
u32 gamma_sel : 2;
u32 dis_limit : 1;
u32 en_uv_hblend : 1;
u32 rgb_gamma_sel : 2;
} __attribute__((packed));
union video_ctrl_u {
u32 val : 32;
struct video_ctrl_t f;
} __attribute__((packed));
struct disp_db_buf_cntl_rd_t {
u32 en_db_buf : 1;
u32 update_db_buf_done : 1;
u32 db_buf_cntl : 6;
u32 : 24;
} __attribute__((packed));
union disp_db_buf_cntl_rd_u {
u32 val : 32;
struct disp_db_buf_cntl_rd_t f;
} __attribute__((packed));
struct disp_db_buf_cntl_wr_t {
u32 en_db_buf : 1;
u32 update_db_buf : 1;
u32 db_buf_cntl : 6;
u32 : 24;
} __attribute__((packed));
union disp_db_buf_cntl_wr_u {
u32 val : 32;
struct disp_db_buf_cntl_wr_t f;
} __attribute__((packed));
struct gamma_value1_t {
u32 gamma1 : 8;
u32 gamma2 : 8;
u32 gamma3 : 8;
u32 gamma4 : 8;
} __attribute__((packed));
union gamma_value1_u {
u32 val : 32;
struct gamma_value1_t f;
} __attribute__((packed));
struct gamma_value2_t {
u32 gamma5 : 8;
u32 gamma6 : 8;
u32 gamma7 : 8;
u32 gamma8 : 8;
} __attribute__((packed));
union gamma_value2_u {
u32 val : 32;
struct gamma_value2_t f;
} __attribute__((packed));
struct gamma_slope_t {
u32 slope1 : 3;
u32 slope2 : 3;
u32 slope3 : 3;
u32 slope4 : 3;
u32 slope5 : 3;
u32 slope6 : 3;
u32 slope7 : 3;
u32 slope8 : 3;
u32 : 8;
} __attribute__((packed));
union gamma_slope_u {
u32 val : 32;
struct gamma_slope_t f;
} __attribute__((packed));
struct mc_ext_mem_location_t {
u32 mc_ext_mem_start : 16;
u32 mc_ext_mem_top : 16;
} __attribute__((packed));
union mc_ext_mem_location_u {
u32 val : 32;
struct mc_ext_mem_location_t f;
} __attribute__((packed));
struct mc_fb_location_t {
u32 mc_fb_start : 16;
u32 mc_fb_top : 16;
} __attribute__((packed));
union mc_fb_location_u {
u32 val : 32;
struct mc_fb_location_t f;
} __attribute__((packed));
struct clk_pin_cntl_t {
u32 osc_en : 1;
u32 osc_gain : 5;
u32 dont_use_xtalin : 1;
u32 xtalin_pm_en : 1;
u32 xtalin_dbl_en : 1;
u32 : 7;
u32 cg_debug : 16;
} __attribute__((packed));
union clk_pin_cntl_u {
u32 val : 32;
struct clk_pin_cntl_t f;
} __attribute__((packed));
struct pll_ref_fb_div_t {
u32 pll_ref_div : 4;
u32 : 4;
u32 pll_fb_div_int : 6;
u32 : 2;
u32 pll_fb_div_frac : 3;
u32 : 1;
u32 pll_reset_time : 4;
u32 pll_lock_time : 8;
} __attribute__((packed));
union pll_ref_fb_div_u {
u32 val : 32;
struct pll_ref_fb_div_t f;
} __attribute__((packed));
struct pll_cntl_t {
u32 pll_pwdn : 1;
u32 pll_reset : 1;
u32 pll_pm_en : 1;
u32 pll_mode : 1;
u32 pll_refclk_sel : 1;
u32 pll_fbclk_sel : 1;
u32 pll_tcpoff : 1;
u32 pll_pcp : 3;
u32 pll_pvg : 3;
u32 pll_vcofr : 1;
u32 pll_ioffset : 2;
u32 pll_pecc_mode : 2;
u32 pll_pecc_scon : 2;
u32 pll_dactal : 4;
u32 pll_cp_clip : 2;
u32 pll_conf : 3;
u32 pll_mbctrl : 2;
u32 pll_ring_off : 1;
} __attribute__((packed));
union pll_cntl_u {
u32 val : 32;
struct pll_cntl_t f;
} __attribute__((packed));
struct sclk_cntl_t {
u32 sclk_src_sel : 2;
u32 : 2;
u32 sclk_post_div_fast : 4;
u32 sclk_clkon_hys : 3;
u32 sclk_post_div_slow : 4;
u32 disp_cg_ok2switch_en : 1;
u32 sclk_force_reg : 1;
u32 sclk_force_disp : 1;
u32 sclk_force_mc : 1;
u32 sclk_force_extmc : 1;
u32 sclk_force_cp : 1;
u32 sclk_force_e2 : 1;
u32 sclk_force_e3 : 1;
u32 sclk_force_idct : 1;
u32 sclk_force_bist : 1;
u32 busy_extend_cp : 1;
u32 busy_extend_e2 : 1;
u32 busy_extend_e3 : 1;
u32 busy_extend_idct : 1;
u32 : 3;
} __attribute__((packed));
union sclk_cntl_u {
u32 val : 32;
struct sclk_cntl_t f;
} __attribute__((packed));
struct pclk_cntl_t {
u32 pclk_src_sel : 2;
u32 : 2;
u32 pclk_post_div : 4;
u32 : 8;
u32 pclk_force_disp : 1;
u32 : 15;
} __attribute__((packed));
union pclk_cntl_u {
u32 val : 32;
struct pclk_cntl_t f;
} __attribute__((packed));
#define TESTCLK_SRC_PLL 0x01
#define TESTCLK_SRC_SCLK 0x02
#define TESTCLK_SRC_PCLK 0x03
/* 4 and 5 seem to by XTAL/M */
#define TESTCLK_SRC_XTAL 0x06
struct clk_test_cntl_t {
u32 testclk_sel : 4;
u32 : 3;
u32 start_check_freq : 1;
u32 tstcount_rst : 1;
u32 : 15;
u32 test_count : 8;
} __attribute__((packed));
union clk_test_cntl_u {
u32 val : 32;
struct clk_test_cntl_t f;
} __attribute__((packed));
struct pwrmgt_cntl_t {
u32 pwm_enable : 1;
u32 : 1;
u32 pwm_mode_req : 2;
u32 pwm_wakeup_cond : 2;
u32 pwm_fast_noml_hw_en : 1;
u32 pwm_noml_fast_hw_en : 1;
u32 pwm_fast_noml_cond : 4;
u32 pwm_noml_fast_cond : 4;
u32 pwm_idle_timer : 8;
u32 pwm_busy_timer : 8;
} __attribute__((packed));
union pwrmgt_cntl_u {
u32 val : 32;
struct pwrmgt_cntl_t f;
} __attribute__((packed));
#define SRC_DATATYPE_EQU_DST 3
#define ROP3_SRCCOPY 0xcc
#define ROP3_PATCOPY 0xf0
#define GMC_BRUSH_SOLID_COLOR 13
#define GMC_BRUSH_NONE 15
#define DP_SRC_MEM_RECTANGULAR 2
#define DP_OP_ROP 0
struct dp_gui_master_cntl_t {
u32 gmc_src_pitch_offset_cntl : 1;
u32 gmc_dst_pitch_offset_cntl : 1;
u32 gmc_src_clipping : 1;
u32 gmc_dst_clipping : 1;
u32 gmc_brush_datatype : 4;
u32 gmc_dst_datatype : 4;
u32 gmc_src_datatype : 3;
u32 gmc_byte_pix_order : 1;
u32 gmc_default_sel : 1;
u32 gmc_rop3 : 8;
u32 gmc_dp_src_source : 3;
u32 gmc_clr_cmp_fcn_dis : 1;
u32 : 1;
u32 gmc_wr_msk_dis : 1;
u32 gmc_dp_op : 1;
} __attribute__((packed));
union dp_gui_master_cntl_u {
u32 val : 32;
struct dp_gui_master_cntl_t f;
} __attribute__((packed));
struct rbbm_status_t {
u32 cmdfifo_avail : 7;
u32 : 1;
u32 hirq_on_rbb : 1;
u32 cprq_on_rbb : 1;
u32 cfrq_on_rbb : 1;
u32 hirq_in_rtbuf : 1;
u32 cprq_in_rtbuf : 1;
u32 cfrq_in_rtbuf : 1;
u32 cf_pipe_busy : 1;
u32 eng_ev_busy : 1;
u32 cp_cmdstrm_busy : 1;
u32 e2_busy : 1;
u32 rb2d_busy : 1;
u32 rb3d_busy : 1;
u32 se_busy : 1;
u32 re_busy : 1;
u32 tam_busy : 1;
u32 tdm_busy : 1;
u32 pb_busy : 1;
u32 : 6;
u32 gui_active : 1;
} __attribute__((packed));
union rbbm_status_u {
u32 val : 32;
struct rbbm_status_t f;
} __attribute__((packed));
struct dp_datatype_t {
u32 dp_dst_datatype : 4;
u32 : 4;
u32 dp_brush_datatype : 4;
u32 dp_src2_type : 1;
u32 dp_src2_datatype : 3;
u32 dp_src_datatype : 3;
u32 : 11;
u32 dp_byte_pix_order : 1;
u32 : 1;
} __attribute__((packed));
union dp_datatype_u {
u32 val : 32;
struct dp_datatype_t f;
} __attribute__((packed));
struct dp_mix_t {
u32 : 8;
u32 dp_src_source : 3;
u32 dp_src2_source : 3;
u32 : 2;
u32 dp_rop3 : 8;
u32 dp_op : 1;
u32 : 7;
} __attribute__((packed));
union dp_mix_u {
u32 val : 32;
struct dp_mix_t f;
} __attribute__((packed));
struct eng_cntl_t {
u32 erc_reg_rd_ws : 1;
u32 erc_reg_wr_ws : 1;
u32 erc_idle_reg_wr : 1;
u32 dis_engine_triggers : 1;
u32 dis_rop_src_uses_dst_w_h : 1;
u32 dis_src_uses_dst_dirmaj : 1;
u32 : 6;
u32 force_3dclk_when_2dclk : 1;
u32 : 19;
} __attribute__((packed));
union eng_cntl_u {
u32 val : 32;
struct eng_cntl_t f;
} __attribute__((packed));
struct dp_cntl_t {
u32 dst_x_dir : 1;
u32 dst_y_dir : 1;
u32 src_x_dir : 1;
u32 src_y_dir : 1;
u32 dst_major_x : 1;
u32 src_major_x : 1;
u32 : 26;
} __attribute__((packed));
union dp_cntl_u {
u32 val : 32;
struct dp_cntl_t f;
} __attribute__((packed));
struct dp_cntl_dst_dir_t {
u32 : 15;
u32 dst_y_dir : 1;
u32 : 15;
u32 dst_x_dir : 1;
} __attribute__((packed));
union dp_cntl_dst_dir_u {
u32 val : 32;
struct dp_cntl_dst_dir_t f;
} __attribute__((packed));
#endif
include/video/w100fb.h deleted 100644 → 0
View file @ aceae784
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Support for the w100 frame buffer.
*
* Copyright (c) 2004-2005 Richard Purdie
* Copyright (c) 2005 Ian Molton
*/
#define W100_GPIO_PORT_A 0
#define W100_GPIO_PORT_B 1
#define CLK_SRC_XTAL 0
#define CLK_SRC_PLL 1
struct w100fb_par;
unsigned long w100fb_gpio_read(int port);
void w100fb_gpio_write(int port, unsigned long value);
unsigned long w100fb_get_hsynclen(struct device *dev);
/* LCD Specific Routines and Config */
struct w100_tg_info {
void (*change)(struct w100fb_par*);
void (*suspend)(struct w100fb_par*);
void (*resume)(struct w100fb_par*);
};
/* General Platform Specific w100 Register Values */
struct w100_gen_regs {
unsigned long lcd_format;
unsigned long lcdd_cntl1;
unsigned long lcdd_cntl2;
unsigned long genlcd_cntl1;
unsigned long genlcd_cntl2;
unsigned long genlcd_cntl3;
};
struct w100_gpio_regs {
unsigned long init_data1;
unsigned long init_data2;
unsigned long gpio_dir1;
unsigned long gpio_oe1;
unsigned long gpio_dir2;
unsigned long gpio_oe2;
};
/* Optional External Memory Configuration */
struct w100_mem_info {
unsigned long ext_cntl;
unsigned long sdram_mode_reg;
unsigned long ext_timing_cntl;
unsigned long io_cntl;
unsigned int size;
};
struct w100_bm_mem_info {
unsigned long ext_mem_bw;
unsigned long offset;
unsigned long ext_timing_ctl;
unsigned long ext_cntl;
unsigned long mode_reg;
unsigned long io_cntl;
unsigned long config;
};
/* LCD Mode definition */
struct w100_mode {
unsigned int xres;
unsigned int yres;
unsigned short left_margin;
unsigned short right_margin;
unsigned short upper_margin;
unsigned short lower_margin;
unsigned long crtc_ss;
unsigned long crtc_ls;
unsigned long crtc_gs;
unsigned long crtc_vpos_gs;
unsigned long crtc_rev;
unsigned long crtc_dclk;
unsigned long crtc_gclk;
unsigned long crtc_goe;
unsigned long crtc_ps1_active;
char pll_freq;
char fast_pll_freq;
int sysclk_src;
int sysclk_divider;
int pixclk_src;
int pixclk_divider;
int pixclk_divider_rotated;
};
struct w100_pll_info {
uint16_t freq; /* desired Fout for PLL (Mhz) */
uint8_t M; /* input divider */
uint8_t N_int; /* VCO multiplier */
uint8_t N_fac; /* VCO multiplier fractional part */
uint8_t tfgoal;
uint8_t lock_time;
};
/* Initial Video mode orientation flags */
#define INIT_MODE_ROTATED 0x1
#define INIT_MODE_FLIPPED 0x2
/*
* This structure describes the machine which we are running on.
* It is set by machine specific code and used in the probe routine
* of drivers/video/w100fb.c
*/
struct w100fb_mach_info {
/* General Platform Specific Registers */
struct w100_gen_regs *regs;
/* Table of modes the LCD is capable of */
struct w100_mode *modelist;
unsigned int num_modes;
/* Hooks for any platform specific tg/lcd code (optional) */
struct w100_tg_info *tg;
/* External memory definition (if present) */
struct w100_mem_info *mem;
/* Additional External memory definition (if present) */
struct w100_bm_mem_info *bm_mem;
/* GPIO definitions (optional) */
struct w100_gpio_regs *gpio;
/* Initial Mode flags */
unsigned int init_mode;
/* Xtal Frequency */
unsigned int xtal_freq;
/* Enable Xtal input doubler (1 == enable) */
unsigned int xtal_dbl;
};
/* General frame buffer data structure */
struct w100fb_par {
unsigned int chip_id;
unsigned int xres;
unsigned int yres;
unsigned int extmem_active;
unsigned int flip;
unsigned int blanked;
unsigned int fastpll_mode;
unsigned long hsync_len;
struct w100_mode *mode;
struct w100_pll_info *pll_table;
struct w100fb_mach_info *mach;
uint32_t *saved_intmem;
uint32_t *saved_extmem;
};
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