Skip to content

L
linux
Commit 7246a035 authored by Paul Mackerras's avatar Paul Mackerras
Browse files
Options

Merge bk://stop.crashing.org/linux-2.5-misc 

into samba.org:/home/paulus/kernel/for-linus-ppc
parents 5bb4ee47 a9e6fe83
Hide whitespace changes
Inline Side-by-side
Showing with 1093 additions and 336 deletions
arch/ppc/Kconfig
View file @ 7246a035
......@@ -470,6 +470,10 @@ config PRPMC800
config SANDPOINT
bool "Motorola-Sandpoint"
help
Select SANDPOINT if configuring for a Motorola Sandpoint X3
or X3(b).
X3 (any flavor).
config ADIR
bool "SBS-Adirondack"
......@@ -494,6 +498,11 @@ config PPC_CHRP
depends on PPC_MULTIPLATFORM
default y
config PPC_GEN550
bool
depends on SANDPOINT
default y
config PPC_PMAC
bool
depends on PPC_MULTIPLATFORM
......@@ -509,10 +518,6 @@ config PPC_OF
depends on PPC_PMAC || PPC_CHRP
default y
config SANDPOINT_X3
bool "Sandpoint X3"
depends on SANDPOINT
config FORCE
bool
depends on 6xx && !8260 && (PCORE || POWERPMC250)
......@@ -520,7 +525,7 @@ config FORCE
config EPIC_SERIAL_MODE
bool
depends on 6xx && !8260 && (LOPEC || SANDPOINT_X3)
depends on 6xx && !8260 && (LOPEC || SANDPOINT)
default y
config WILLOW
......
arch/ppc/configs/sandpoint_defconfig
View file @ 7246a035
......@@ -66,7 +66,7 @@ CONFIG_SANDPOINT=y
# CONFIG_K2 is not set
# CONFIG_PAL4 is not set
# CONFIG_GEMINI is not set
CONFIG_SANDPOINT_X3=y
CONFIG_PPC_GEN550=y
CONFIG_EPIC_SERIAL_MODE=y
# CONFIG_MPC10X_STORE_GATHERING is not set
# CONFIG_SMP is not set
......@@ -82,8 +82,8 @@ CONFIG_ALTIVEC=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_KCORE_ELF=y
CONFIG_BINFMT_ELF=y
CONFIG_KERNEL_ELF=y
CONFIG_BINFMT_ELF=y
CONFIG_BINFMT_MISC=m
# CONFIG_PCI_LEGACY_PROC is not set
# CONFIG_PCI_NAMES is not set
......@@ -115,6 +115,11 @@ CONFIG_KERNEL_START=0xc0000000
CONFIG_TASK_SIZE=0x80000000
CONFIG_BOOT_LOAD=0x00800000
#
# Generic Driver Options
#
# CONFIG_FW_LOADER is not set
#
# Memory Technology Devices (MTD)
#
......@@ -145,7 +150,7 @@ CONFIG_BLK_DEV_INITRD=y
# CONFIG_MD is not set
#
# ATA/IDE/MFM/RLL support
# ATA/ATAPI/MFM/RLL support
#
CONFIG_IDE=y
......@@ -164,6 +169,7 @@ CONFIG_BLK_DEV_IDEDISK=y
CONFIG_BLK_DEV_IDECD=y
# CONFIG_BLK_DEV_IDEFLOPPY is not set
# CONFIG_IDE_TASK_IOCTL is not set
CONFIG_IDE_TASKFILE_IO=y
#
# IDE chipset support/bugfixes
......@@ -171,7 +177,7 @@ CONFIG_BLK_DEV_IDECD=y
# CONFIG_BLK_DEV_IDEPCI is not set
#
# SCSI support
# SCSI device support
#
# CONFIG_SCSI is not set
......@@ -290,6 +296,7 @@ CONFIG_NET_PCI=y
# CONFIG_AMD8111_ETH is not set
# CONFIG_ADAPTEC_STARFIRE is not set
# CONFIG_B44 is not set
# CONFIG_TC35815 is not set
# CONFIG_DGRS is not set
# CONFIG_EEPRO100 is not set
CONFIG_E100=y
......@@ -410,11 +417,6 @@ CONFIG_FONT_8x16=y
#
# CONFIG_LOGO is not set
#
# Old CD-ROM drivers (not SCSI, not IDE)
#
# CONFIG_CD_NO_IDESCSI is not set
#
# Input device support
#
......@@ -441,6 +443,7 @@ CONFIG_SERIO=y
CONFIG_SERIO_I8042=y
# CONFIG_SERIO_SERPORT is not set
# CONFIG_SERIO_CT82C710 is not set
# CONFIG_SERIO_PCIPS2 is not set
#
# Input Device Drivers
......@@ -729,6 +732,7 @@ CONFIG_USB_SE401=m
#
# USB Network adaptors
#
# CONFIG_USB_AX8817X is not set
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
......
arch/ppc/kernel/ppc-stub.c
View file @ 7246a035
......@@ -851,14 +851,4 @@ kgdb_output_string (const char* s, unsigned int count)
putpacket(buffer);
return 1;
}
#if defined(CONFIG_6xx) || defined(CONFIG_POWER3)
/* This is used on arches which don't have a serial driver that maps
* the ports for us */
void
kgdb_map_scc(void)
{
}
#endif
arch/ppc/kernel/ppc_ksyms.c
View file @ 7246a035
......@@ -272,8 +272,10 @@ EXPORT_SYMBOL(kd_mksound);
#ifdef CONFIG_NVRAM
EXPORT_SYMBOL(nvram_read_byte);
EXPORT_SYMBOL(nvram_write_byte);
#ifdef CONFIG_PPC_PMAC
EXPORT_SYMBOL(pmac_xpram_read);
EXPORT_SYMBOL(pmac_xpram_write);
#endif
#endif /* CONFIG_NVRAM */
EXPORT_SYMBOL(to_tm);
......
arch/ppc/kernel/setup.c
View file @ 7246a035
......@@ -619,6 +619,8 @@ void __init setup_arch(char **cmdline_p)
if (strstr(cmd_line, "nokgdb"))
printk("kgdb default breakpoint deactivated on command line\n");
else {
if (ppc_md.progress)
ppc_md.progress("setup_arch: kgdb breakpoint", 0x4000);
printk("kgdb default breakpoint activated\n");
breakpoint();
}
......
arch/ppc/platforms/Makefile
View file @ 7246a035
......@@ -43,7 +43,7 @@ obj-$(CONFIG_POWERPMC250) += powerpmc250.o
obj-$(CONFIG_PPLUS) += pplus_pci.o pplus_setup.o
obj-$(CONFIG_PRPMC750) += prpmc750_setup.o prpmc750_pci.o
obj-$(CONFIG_PRPMC800) += prpmc800_setup.o prpmc800_pci.o
obj-$(CONFIG_SANDPOINT) += sandpoint_setup.o sandpoint_pci.o
obj-$(CONFIG_SANDPOINT) += sandpoint.o
obj-$(CONFIG_SPRUCE) += spruce_setup.o spruce_pci.o
ifeq ($(CONFIG_SMP),y)
......
arch/ppc/platforms/sandpoint_setup.c → arch/ppc/platforms/sandpoint.c
View file @ 7246a035
/*
* arch/ppc/platforms/sandpoint_setup.c
*
*
* Board setup routines for the Motorola SPS Sandpoint Test Platform.
*
* Author: Mark A. Greer
* mgreer@mvista.com
* mgreer@mvista.com
*
* 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
* 2000-2003 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
......@@ -54,7 +54,19 @@
* 7 Winbond INTC (IDE interrupt)
* 8 Winbond INTD (IDE interrupt)
*
*
* Motorola has finally released a version of DINK32 that correctly
* (seemingly) initalizes the memory controller correctly, regardless
* of the amount of memory in the system. Once a method of determining
* what version of DINK initializes the system for us, if applicable, is
* found, we can hopefully stop hardcoding 32MB of RAM.
*
* It is important to note that this code only supports the Sandpoint X3
* (all flavors) platform, and it does not support the X2 anymore. Code
* that at one time worked on the X2 can be found at:
* ftp://source.mvista.com/pub/linuxppc/obsolete/sandpoint/
*/
#include <linux/config.h>
#include <linux/stddef.h>
#include <linux/kernel.h>
......@@ -71,6 +83,9 @@
#include <linux/ide.h>
#include <linux/seq_file.h>
#include <linux/root_dev.h>
#include <linux/serial.h>
#include <linux/tty.h> /* for linux/serial_core.h */
#include <linux/serial_core.h>
#include <asm/system.h>
#include <asm/pgtable.h>
......@@ -91,59 +106,186 @@
#include "sandpoint.h"
extern u_int openpic_irq(void);
extern void openpic_eoi(void);
extern void gen550_progress(char *, unsigned short);
extern void gen550_init(int, struct uart_port *);
static void sandpoint_halt(void);
unsigned char __res[sizeof(bd_t)];
static void sandpoint_halt(void);
/*
* *** IMPORTANT ***
*
* The first 16 entries of 'sandpoint_openpic_initsenses[]' are there and
* initialized to 0 on purpose. DO NOT REMOVE THEM as the 'offset' parameter
* of 'openpic_init()' does not work for the sandpoint because the 8259
* interrupt is NOT routed to the EPIC's IRQ 0 AND the EPIC's IRQ 0's offset is
* the same as a normal openpic's IRQ 16 offset.
* Define all of the IRQ senses and polarities. Taken from the
* Sandpoint X3 User's manual.
*/
static u_char sandpoint_openpic_initsenses[] __initdata = {
0, /* 0-15 not used by EPCI but by 8259 (std PC-type IRQs) */
0, /* 1 */
0, /* 2 */
0, /* 3 */
0, /* 4 */
0, /* 5 */
0, /* 6 */
0, /* 7 */
0, /* 8 */
0, /* 9 */
0, /* 10 */
0, /* 11 */
0, /* 12 */
0, /* 13 */
0, /* 14 */
0, /* 15 */
#ifdef CONFIG_SANDPOINT_X3
1, /* 16: EPIC IRQ 0: Active Low -- SIOINT (8259) */
0, /* AACK! Shouldn't need this.....see sandpoint_pci.c for more info */
1, /* 17: EPIC IRQ 1: Active Low -- PCI Slot 1 */
1, /* 18: EPIC IRQ 2: Active Low -- PCI Slot 2 */
1, /* 19: EPIC IRQ 3: Active Low -- PCI Slot 3 */
1, /* 20: EPIC IRQ 4: Active Low -- PCI Slot 4 */
0, /* 21 -- Unused */
0, /* 22 -- Unused */
1, /* 23 -- IDE (Winbond INT C) */
1, /* 24 -- IDE (Winbond INT D) */
/* 35 - 31 (EPIC 9 - 15) Unused */
#else
1, /* 16: EPIC IRQ 0: Active Low -- PCI intrs */
1, /* 17: EPIC IRQ 1: Active Low -- PCI (possibly 8259) intrs */
1, /* 18: EPIC IRQ 2: Active Low -- PCI (possibly 8259) intrs */
1 /* 19: EPIC IRQ 3: Active Low -- PCI intrs */
/* 20: EPIC IRQ 4: Not used */
#endif
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 0: SIOINT */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 2: PCI Slot 1 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 3: PCI Slot 2 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 4: PCI Slot 3 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 5: PCI Slot 4 */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 8: IDE (INT C) */
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE) /* 9: IDE (INT D) */
};
/*
* Motorola SPS Sandpoint interrupt routing.
*/
static inline int
sandpoint_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
static char pci_irq_table[][4] =
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
{ 16, 0, 0, 0 }, /* IDSEL 11 - i8259 on Winbond */
{ 0, 0, 0, 0 }, /* IDSEL 12 - unused */
{ 18, 21, 20, 19 }, /* IDSEL 13 - PCI slot 1 */
{ 19, 18, 21, 20 }, /* IDSEL 14 - PCI slot 2 */
{ 20, 19, 18, 21 }, /* IDSEL 15 - PCI slot 3 */
{ 21, 20, 19, 18 }, /* IDSEL 16 - PCI slot 4 */
};
const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
}
static void __init
sandpoint_setup_winbond_83553(struct pci_controller *hose)
{
int devfn;
/*
* Route IDE interrupts directly to the 8259's IRQ 14 & 15.
* We can't route the IDE interrupt to PCI INTC# or INTD# because those
* woule interfere with the PMC's INTC# and INTD# lines.
*/
/*
* Winbond Fcn 0
*/
devfn = PCI_DEVFN(11,0);
early_write_config_byte(hose,
0,
devfn,
0x43, /* IDE Interrupt Routing Control */
0xef);
early_write_config_word(hose,
0,
devfn,
0x44, /* PCI Interrupt Routing Control */
0x0000);
/* Want ISA memory cycles to be forwarded to PCI bus */
early_write_config_byte(hose,
0,
devfn,
0x48, /* ISA-to-PCI Addr Decoder Control */
0xf0);
/* Enable RTC and Keyboard address locations. */
early_write_config_byte(hose,
0,
devfn,
0x4d, /* Chip Select Control Register */
0x00);
/* Enable Port 92. */
early_write_config_byte(hose,
0,
devfn,
0x4e, /* AT System Control Register */
0x06);
/*
* Winbond Fcn 1
*/
devfn = PCI_DEVFN(11,1);
/* Put IDE controller into native mode. */
early_write_config_byte(hose,
0,
devfn,
0x09, /* Programming interface Register */
0x8f);
/* Init IRQ routing, enable both ports, disable fast 16 */
early_write_config_dword(hose,
0,
devfn,
0x40, /* IDE Control/Status Register */
0x00ff0011);
return;
}
static void __init
sandpoint_find_bridges(void)
{
struct pci_controller *hose;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
if (mpc10x_bridge_init(hose,
MPC10X_MEM_MAP_B,
MPC10X_MEM_MAP_B,
MPC10X_MAPB_EUMB_BASE) == 0) {
/* Do early winbond init, then scan PCI bus */
sandpoint_setup_winbond_83553(hose);
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = NULL;
ppc_md.pcibios_fixup_bus = NULL;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = sandpoint_map_irq;
}
else {
if (ppc_md.progress)
ppc_md.progress("Bridge init failed", 0x100);
printk("Host bridge init failed\n");
}
return;
}
#if defined(CONFIG_SERIAL_8250) && \
(defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG))
static void __init
sandpoint_early_serial_map(void)
{
struct uart_port serial_req;
/* Setup serial port access */
memset(&serial_req, 0, sizeof(serial_req));
serial_req.uartclk = UART_CLK;
serial_req.irq = 4;
serial_req.flags = STD_COM_FLAGS;
serial_req.iotype = SERIAL_IO_MEM;
serial_req.membase = (u_char *)SANDPOINT_SERIAL_0;
gen550_init(0, &serial_req);
if (early_serial_setup(&serial_req) != 0)
printk(KERN_ERR "Early serial init of port 0 failed\n");
/* Assume early_serial_setup() doesn't modify serial_req */
serial_req.line = 1;
serial_req.irq = 3; /* XXXX */
serial_req.membase = (u_char *)SANDPOINT_SERIAL_1;
gen550_init(1, &serial_req);
if (early_serial_setup(&serial_req) != 0)
printk(KERN_ERR "Early serial init of port 1 failed\n");
}
#endif
static void __init
sandpoint_setup_arch(void)
{
......@@ -167,24 +309,29 @@ sandpoint_setup_arch(void)
conswitchp = &dummy_con;
#endif
printk("Motorola SPS Sandpoint Test Platform\n");
printk("Sandpoint port (MontaVista Software, Inc. (source@mvista.com))\n");
printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n");
printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
/* The Sandpoint rom doesn't enable any caches. Do that now.
* The 7450 portion will also set up the L3s once I get enough
* information do do so. If the processor running doesn't have
* and L2, the _set_L2CR is a no-op.
/* DINK32 12.3 and below do not correctly enable any caches.
* We will do this now with good known values. Future versions
* of DINK32 are supposed to get this correct.
*/
if (cur_cpu_spec[0]->cpu_features & CPU_FTR_SPEC7450) {
/* Just enable L2, the bits are different from others.
*/
if (cur_cpu_spec[0]->cpu_features & CPU_FTR_SPEC7450)
/* 745x is different. We only want to pass along enable. */
_set_L2CR(L2CR_L2E);
else if (cur_cpu_spec[0]->cpu_features & CPU_FTR_L2CR)
/* All modules have 1MB of L2. We also assume that an
* L2 divisor of 3 will work.
*/
_set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
| L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);
#if 0
/* Untested right now. */
if (cur_cpu_spec[0]->cpu_features & CPU_FTR_L3CR) {
/* Magic value. */
_set_L3CR(0x8f032000);
}
else {
/* The magic number for Sandpoint/74xx PrPMCs.
*/
_set_L2CR(0xbd014000);
}
#endif
}
#define SANDPOINT_87308_CFG_ADDR 0x15c
......@@ -212,7 +359,7 @@ sandpoint_setup_arch(void)
/*
* Initialize the ISA devices on the Nat'l PC87308VUL SuperIO chip.
*/
static void __init
static int __init
sandpoint_setup_natl_87308(void)
{
u_char reg;
......@@ -237,31 +384,31 @@ sandpoint_setup_natl_87308(void)
reg = inb(SIO_CONFIG_RD);
reg = (reg & 0x3F) | 0x40;
outb(reg, SIO_CONFIG_RD);
outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
return;
return 0;
}
arch_initcall(sandpoint_setup_natl_87308);
/*
* Fix IDE interrupts.
*/
static void __init
static int __init
sandpoint_fix_winbond_83553(void)
{
/* Make all 8259 interrupt level sensitive */
outb(0xf8, 0x4d0);
outb(0xde, 0x4d1);
return;
return 0;
}
static void __init
sandpoint_init2(void)
{
/* Do Sandpoint board specific initialization. */
sandpoint_fix_winbond_83553();
sandpoint_setup_natl_87308();
arch_initcall(sandpoint_fix_winbond_83553);
static int __init
sandpoint_request_io(void)
{
request_region(0x00,0x20,"dma1");
request_region(0x20,0x20,"pic1");
request_region(0x40,0x20,"timer");
......@@ -269,110 +416,77 @@ sandpoint_init2(void)
request_region(0xa0,0x20,"pic2");
request_region(0xc0,0x20,"dma2");
return;
return 0;
}
arch_initcall(sandpoint_request_io);
/*
* Interrupt setup and service. Interrrupts on the Sandpoint come
* from the four PCI slots plus the 8259 in the Winbond Super I/O (SIO).
* These interrupts are sent to one of four IRQs on the EPIC.
* The SIO shares its interrupt with either slot 2 or slot 3 (INTA#).
* Slot numbering is confusing. Sometimes in the documentation they
* use 0,1,2,3 and others 1,2,3,4. We will use slots 1,2,3,4 and
* map this to IRQ 16, 17, 18, 19.
* For Sandpoint X3, this has been better designed. The 8259 is
* cascaded from EPIC IRQ0, IRQ1-4 map to PCI slots 1-4, IDE is on
* EPIC 7 and 8.
* The 8259 is cascaded from EPIC IRQ0, IRQ1-4 map to PCI slots 1-4,
* IDE is on EPIC 7 and 8.
*/
static void __init
sandpoint_init_IRQ(void)
{
int i;
/*
* 3 things cause us to jump through some hoops:
* 1) the EPIC on the 8240 & 107 are not full-blown openpic pic's
* 2) the 8259 is NOT cascaded on the openpic IRQ 0
* 3) the 8259 shares its interrupt line with some PCI interrupts.
*
* What we'll do is set up the 8259 to be level sensitive, active low
* just like a PCI device. Then, when an interrupt on the IRQ that is
* shared with the 8259 comes in, we'll take a peek at the 8259 to see
* it its generating an interrupt. If it is, we'll handle the 8259
* interrupt. Otherwise, we'll handle it just like a normal PCI
* interrupt. This does give the 8259 interrupts a higher priority
* than the EPIC ones--hopefully, not a problem.
*/
OpenPIC_InitSenses = sandpoint_openpic_initsenses;
OpenPIC_NumInitSenses = sizeof(sandpoint_openpic_initsenses);
openpic_init(1, 0, NULL, -1);
/*
* openpic_init() has set up irq_desc[0-23] to be openpic
* interrupts. We need to set irq_desc[0-15] to be 8259 interrupts.
* We then need to request and enable the 8259 irq.
* We need to tell openpic_set_sources where things actually are.
* mpc10x_common will setup OpenPIC_Addr at ioremap(EUMB phys base +
* EPIC offset (0x40000)); The EPIC IRQ Register Address Map -
* Interrupt Source Configuration Registers gives these numbers
* as offsets starting at 0x50200, we need to adjust occordinly.
*/
for(i=0; i < NUM_8259_INTERRUPTS; i++)
irq_desc[i].handler = &i8259_pic;
if (request_irq(SANDPOINT_SIO_IRQ, no_action, SA_INTERRUPT,
"8259 cascade to EPIC", NULL)) {
printk("Unable to get OpenPIC IRQ %d for cascade\n",
SANDPOINT_SIO_IRQ);
}
i8259_init(NULL);
}
static int
sandpoint_get_irq(struct pt_regs *regs)
{
int irq, cascade_irq;
irq = openpic_irq();
/* Map serial interrupts 0-15 */
openpic_set_sources(0, 16, OpenPIC_Addr + 0x10200);
if (irq == SANDPOINT_SIO_IRQ) {
cascade_irq = i8259_irq(regs);
openpic_init(NUM_8259_INTERRUPTS);
if (cascade_irq != -1) {
irq = cascade_irq;
openpic_eoi();
}
}
else if (irq == OPENPIC_VEC_SPURIOUS) {
irq = -1;
}
/*
* openpic_init() has set up irq_desc[16-31] to be openpic
* interrupts. We need to set irq_desc[0-15] to be i8259
* interrupts.
*/
for(i=0; i < NUM_8259_INTERRUPTS; i++)
irq_desc[i].handler = &i8259_pic;
return irq;
/*
* The EPIC allows for a read in the range of 0xFEF00000 ->
* 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
*/
i8259_init(0xfef00000);
}
static u32
sandpoint_irq_canonicalize(u32 irq)
{
if (irq == 2)
{
return 9;
}
else
{
return irq;
}
}
static ulong __init
static unsigned long __init
sandpoint_find_end_of_memory(void)
{
ulong size = 0;
bd_t *bp = (bd_t *)__res;
if (bp->bi_memsize)
return bp->bi_memsize;
#if 0 /* Leave out until DINK sets mem ctlr correctly */
size = mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
/* DINK32 13.0 correctly initalizes things, so iff you use
* this you _should_ be able to change this instead of a
* hardcoded value. */
#if 0
return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
#else
size = 32*1024*1024;
return 32*1024*1024;
#endif
return size;
}
static void __init
......@@ -381,9 +495,6 @@ sandpoint_map_io(void)
io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
}
/*
* Due to Sandpoint X2 errata, the Port 92 will not work.
*/
static void
sandpoint_restart(char *cmd)
{
......@@ -402,7 +513,7 @@ static void
sandpoint_power_off(void)
{
local_irq_disable();
for(;;); /* No way to shut power off with software */
for(;;); /* No way to shut power off with software */
/* NOTREACHED */
}
......@@ -416,14 +527,8 @@ sandpoint_halt(void)
static int
sandpoint_show_cpuinfo(struct seq_file *m)
{
uint pvid;
pvid = mfspr(PVR);
seq_printf(m, "vendor\t\t: Motorola SPS\n");
seq_printf(m, "machine\t\t: Sandpoint\n");
seq_printf(m, "processor\t: PVID: 0x%x, vendor: %s\n",
pvid, (pvid & (1<<15) ? "IBM" : "Motorola"));
return 0;
}
......@@ -440,27 +545,25 @@ static unsigned long sandpoint_idedma_regbase;
static void
sandpoint_ide_probe(void)
{
struct pci_dev *pdev = pci_find_device(PCI_VENDOR_ID_WINBOND,
PCI_DEVICE_ID_WINBOND_82C105,
NULL);
if(pdev) {
sandpoint_ide_regbase[0]=pdev->resource[0].start;
sandpoint_ide_regbase[1]=pdev->resource[2].start;
sandpoint_ide_ctl_regbase[0]=pdev->resource[1].start;
sandpoint_ide_ctl_regbase[1]=pdev->resource[3].start;
sandpoint_idedma_regbase=pdev->resource[4].start;
}
sandpoint_ide_ports_known = 1;
return;
struct pci_dev *pdev = pci_find_device(PCI_VENDOR_ID_WINBOND,
PCI_DEVICE_ID_WINBOND_82C105, NULL);
if (pdev) {
sandpoint_ide_regbase[0]=pdev->resource[0].start;
sandpoint_ide_regbase[1]=pdev->resource[2].start;
sandpoint_ide_ctl_regbase[0]=pdev->resource[1].start;
sandpoint_ide_ctl_regbase[1]=pdev->resource[3].start;
sandpoint_idedma_regbase=pdev->resource[4].start;
}
sandpoint_ide_ports_known = 1;
}
static int
sandpoint_ide_default_irq(unsigned long base)
{
if (sandpoint_ide_ports_known == 0)
sandpoint_ide_probe();
if (sandpoint_ide_ports_known == 0)
sandpoint_ide_probe();
if (base == sandpoint_ide_regbase[0])
return SANDPOINT_IDE_INT0;
......@@ -473,15 +576,15 @@ sandpoint_ide_default_irq(unsigned long base)
static unsigned long
sandpoint_ide_default_io_base(int index)
{
if (sandpoint_ide_ports_known == 0)
sandpoint_ide_probe();
if (sandpoint_ide_ports_known == 0)
sandpoint_ide_probe();
return sandpoint_ide_regbase[index];
}
static void __init
sandpoint_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port,
unsigned long ctrl_port, int *irq)
unsigned long ctrl_port, int *irq)
{
unsigned long reg = data_port;
uint alt_status_base;
......@@ -513,8 +616,6 @@ sandpoint_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port,
if (irq != NULL) {
*irq = hw->irq;
}
return;
}
#endif
......@@ -524,72 +625,52 @@ sandpoint_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port,
static __inline__ void
sandpoint_set_bat(void)
{
unsigned long bat3u, bat3l;
static int mapping_set = 0;
if (!mapping_set) {
__asm__ __volatile__(
" lis %0,0xf800\n \
ori %1,%0,0x002a\n \
ori %0,%0,0x0ffe\n \
mtspr 0x21e,%0\n \
mtspr 0x21f,%1\n \
isync\n \
sync "
: "=r" (bat3u), "=r" (bat3l));
mapping_set = 1;
}
return;
unsigned long bat3u, bat3l;
__asm__ __volatile__(
" lis %0,0xf800\n \
ori %1,%0,0x002a\n \
ori %0,%0,0x0ffe\n \
mtspr 0x21e,%0\n \
mtspr 0x21f,%1\n \
isync\n \
sync "
: "=r" (bat3u), "=r" (bat3l));
}
#ifdef CONFIG_SERIAL_TEXT_DEBUG
#include <linux/serialP.h>
#include <linux/serial_reg.h>
#include <asm/serial.h>
static struct serial_state rs_table[RS_TABLE_SIZE] = {
SERIAL_PORT_DFNS /* Defined in <asm/serial.h> */
};
static void
sandpoint_progress(char *s, unsigned short hex)
{
volatile char c;
volatile unsigned long com_port;
u16 shift;
com_port = rs_table[0].port;
shift = rs_table[0].iomem_reg_shift;
while ((c = *s++) != 0) {
while ((*((volatile unsigned char *)com_port +
(UART_LSR << shift)) & UART_LSR_THRE) == 0)
;
*(volatile unsigned char *)com_port = c;
if (c == '\n') {
while ((*((volatile unsigned char *)com_port +
(UART_LSR << shift)) & UART_LSR_THRE) == 0)
;
*(volatile unsigned char *)com_port = '\r';
}
}
}
#endif /* CONFIG_SERIAL_TEXT_DEBUG */
__init void sandpoint_setup_pci_ptrs(void);
TODC_ALLOC();
void __init
platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7)
unsigned long r6, unsigned long r7)
{
parse_bootinfo(find_bootinfo());
/* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
* are non-zero, then we should use the board info from the bd_t
* structure and the cmdline pointed to by r6 instead of the
* information from birecs, if any. Otherwise, use the information
* from birecs as discovered by the preceeding call to
* parse_bootinfo(). This rule should work with both PPCBoot, which
* uses a bd_t board info structure, and the kernel boot wrapper,
* which uses birecs.
*/
if (r3 && r6) {
/* copy board info structure */
memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
/* copy command line */
*(char *)(r7+KERNELBASE) = 0;
strcpy(cmd_line, (char *)(r6+KERNELBASE));
}
#ifdef CONFIG_BLK_DEV_INITRD
/* take care of initrd if we have one */
if (r4) {
initrd_start = r4 + KERNELBASE;
initrd_end = r5 + KERNELBASE;
}
#endif /* CONFIG_BLK_DEV_INITRD */
/* Map in board regs, etc. */
sandpoint_set_bat();
......@@ -604,8 +685,7 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
ppc_md.show_cpuinfo = sandpoint_show_cpuinfo;
ppc_md.irq_canonicalize = sandpoint_irq_canonicalize;
ppc_md.init_IRQ = sandpoint_init_IRQ;
ppc_md.get_irq = sandpoint_get_irq;
ppc_md.init = sandpoint_init2;
ppc_md.get_irq = openpic_get_irq;
ppc_md.restart = sandpoint_restart;
ppc_md.power_off = sandpoint_power_off;
......@@ -623,21 +703,17 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
ppc_md.nvram_read_val = todc_mc146818_read_val;
ppc_md.nvram_write_val = todc_mc146818_write_val;
ppc_md.heartbeat = NULL;
ppc_md.heartbeat_reset = 0;
ppc_md.heartbeat_count = 0;
#ifdef CONFIG_SERIAL_TEXT_DEBUG
ppc_md.progress = sandpoint_progress;
#else /* !CONFIG_SERIAL_TEXT_DEBUG */
ppc_md.progress = NULL;
#endif /* CONFIG_SERIAL_TEXT_DEBUG */
#if defined(CONFIG_SERIAL_8250) && \
(defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG))
sandpoint_early_serial_map();
#ifdef CONFIG_SERIAL_TEXT_DEBUG
ppc_md.progress = gen550_progress;
#endif
#endif
#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
ppc_ide_md.default_irq = sandpoint_ide_default_irq;
ppc_ide_md.default_io_base = sandpoint_ide_default_io_base;
ppc_ide_md.ide_init_hwif = sandpoint_ide_init_hwif_ports;
ppc_ide_md.default_irq = sandpoint_ide_default_irq;
ppc_ide_md.default_io_base = sandpoint_ide_default_io_base;
ppc_ide_md.ide_init_hwif = sandpoint_ide_init_hwif_ports;
#endif
return;
}
arch/ppc/platforms/sandpoint.h
View file @ 7246a035
......@@ -6,7 +6,7 @@
* Author: Mark A. Greer
* mgreer@mvista.com
*
* 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under
* 2000-2003 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
......@@ -19,8 +19,8 @@
#ifndef __PPC_PLATFORMS_SANDPOINT_H
#define __PPC_PLATFORMS_SANDPOINT_H
#ifdef CONFIG_SANDPOINT_X3
#define SANDPOINT_SIO_SLOT 0 /* Cascaded from EPIC IRQ 0 */
#include <asm/ppcboot.h>
#if 0
/* The Sandpoint X3 allows the IDE interrupt to be directly connected
* from the Windbond (PCI INTC or INTD) to the serial EPIC. Someday
......@@ -28,27 +28,13 @@
* initialization than change it to route the different interrupts :-).
* -- Dan
*/
#define SANDPOINT_IDE_INT0 23 /* EPIC 7 */
#define SANDPOINT_IDE_INT1 24 /* EPIC 8 */
#else
#define SANDPOINT_IDE_INT0 14 /* 8259 Test */
#define SANDPOINT_IDE_INT1 15 /* 8259 Test */
#endif
#define SANDPOINT_IDE_INT0 23 /* EPIC 7 */
#define SANDPOINT_IDE_INT1 24 /* EPIC 8 */
#else
/*
* Define the PCI slot that the 8259 is sharing interrupts with.
* Valid values are 1 (PCI slot 2) and 2 (PCI slot 3).
*/
#define SANDPOINT_SIO_SLOT 1
/* ...and for the IDE from the 8259....
*/
#define SANDPOINT_IDE_INT0 14
#define SANDPOINT_IDE_INT1 15
#define SANDPOINT_IDE_INT0 14 /* 8259 Test */
#define SANDPOINT_IDE_INT1 15 /* 8259 Test */
#endif
#define SANDPOINT_SIO_IRQ (SANDPOINT_SIO_SLOT + NUM_8259_INTERRUPTS)
/*
* The sandpoint boards have processor modules that either have an 8240 or
* an MPC107 host bridge on them. These bridges have an IDSEL line that allows
......@@ -62,7 +48,33 @@
*/
#define SANDPOINT_HOST_BRIDGE_IDSEL 12
/*
* Serial defines.
*/
#define SANDPOINT_SERIAL_0 0xfe0003f8
#define SANDPOINT_SERIAL_1 0xfe0002f8
#define RS_TABLE_SIZE 2
/* Rate for the 1.8432 Mhz clock for the onboard serial chip */
#define BASE_BAUD ( 1843200 / 16 )
#define UART_CLK 1843200
#ifdef CONFIG_SERIAL_DETECT_IRQ
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
#else
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
#endif
#define STD_SERIAL_PORT_DFNS \
{ 0, BASE_BAUD, SANDPOINT_SERIAL_0, 4, STD_COM_FLAGS, /* ttyS0 */ \
iomem_base: (u8 *)SANDPOINT_SERIAL_0, \
io_type: SERIAL_IO_MEM }, \
{ 0, BASE_BAUD, SANDPOINT_SERIAL_1, 3, STD_COM_FLAGS, /* ttyS1 */ \
iomem_base: (u8 *)SANDPOINT_SERIAL_1, \
io_type: SERIAL_IO_MEM },
void sandpoint_find_bridges(void);
#define SERIAL_PORT_DFNS \
STD_SERIAL_PORT_DFNS
#endif /* __PPC_PLATFORMS_SANDPOINT_H */
arch/ppc/platforms/sandpoint_pci.c deleted 100644 → 0
View file @ 5bb4ee47
/*
* arch/ppc/platforms/sandpoint_pci.c
*
* PCI setup routines for the Motorola SPS Sandpoint Test Platform
*
* Author: Mark A. Greer
* mgreer@mvista.com
*
* 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/mpc10x.h>
#include "sandpoint.h"
/*
* Motorola SPS Sandpoint interrupt routing.
*/
static inline int
sandpoint_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
static char pci_irq_table[][4] =
/*
* PCI IDSEL/INTPIN->INTLINE
* A B C D
*/
{
{ SANDPOINT_SIO_IRQ,
0, 0, 0 }, /* IDSEL 11 - i8259 on Winbond */
{ 0, 0, 0, 0 }, /* IDSEL 12 - unused */
#ifdef CONFIG_SANDPOINT_X3
#if 0 /* This is what it _should_ look like -- Dan */
{ 17, 20, 19, 18 }, /* IDSEL 13 - PCI slot 1 */
{ 18, 17, 20, 19 }, /* IDSEL 14 - PCI slot 2 */
{ 19, 18, 17, 20 }, /* IDSEL 15 - PCI slot 3 */
{ 20, 19, 18, 17 }, /* IDSEL 16 - PCI slot 4 */
#else
{ 18, 21, 20, 19 }, /* IDSEL 13 - PCI slot 1 */
{ 19, 18, 21, 20 }, /* IDSEL 14 - PCI slot 2 */
{ 20, 19, 18, 21 }, /* IDSEL 15 - PCI slot 3 */
{ 21, 20, 19, 18 }, /* IDSEL 16 - PCI slot 4 */
#endif
#else
{ 16, 19, 18, 17 }, /* IDSEL 13 - PCI slot 1 */
{ 17, 16, 19, 18 }, /* IDSEL 14 - PCI slot 2 */
{ 18, 17, 16, 19 }, /* IDSEL 15 - PCI slot 3 */
{ 19, 18, 17, 16 }, /* IDSEL 16 - PCI slot 4 */
#endif
};
const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
}
static void __init
sandpoint_setup_winbond_83553(struct pci_controller *hose)
{
int devfn;
/*
* Route IDE interrupts directly to the 8259's IRQ 14 & 15.
* We can't route the IDE interrupt to PCI INTC# or INTD# because those
* woule interfere with the PMC's INTC# and INTD# lines.
*/
/*
* Winbond Fcn 0
*/
devfn = PCI_DEVFN(11,0);
early_write_config_byte(hose,
0,
devfn,
0x43, /* IDE Interrupt Routing Control */
0xef);
early_write_config_word(hose,
0,
devfn,
0x44, /* PCI Interrupt Routing Control */
0x0000);
/* Want ISA memory cycles to be forwarded to PCI bus */
early_write_config_byte(hose,
0,
devfn,
0x48, /* ISA-to-PCI Addr Decoder Control */
0xf0);
/* Enable RTC and Keyboard address locations. */
early_write_config_byte(hose,
0,
devfn,
0x4d, /* Chip Select Control Register */
0x00);
/* Enable Port 92. */
early_write_config_byte(hose,
0,
devfn,
0x4e, /* AT System Control Register */
0x06);
/*
* Winbond Fcn 1
*/
devfn = PCI_DEVFN(11,1);
/* Put IDE controller into native mode. */
early_write_config_byte(hose,
0,
devfn,
0x09, /* Programming interface Register */
0x8f);
/* Init IRQ routing, enable both ports, disable fast 16 */
early_write_config_dword(hose,
0,
devfn,
0x40, /* IDE Control/Status Register */
0x00ff0011);
return;
}
static int
sandpoint_exclude_device(u_char bus, u_char devfn)
{
if ((bus == 0) && (PCI_SLOT(devfn) == SANDPOINT_HOST_BRIDGE_IDSEL)) {
return PCIBIOS_DEVICE_NOT_FOUND;
}
else {
return PCIBIOS_SUCCESSFUL;
}
}
void __init
sandpoint_find_bridges(void)
{
struct pci_controller *hose;
hose = pcibios_alloc_controller();
if (!hose)
return;
hose->first_busno = 0;
hose->last_busno = 0xff;
if (mpc10x_bridge_init(hose,
MPC10X_MEM_MAP_B,
MPC10X_MEM_MAP_B,
MPC10X_MAPB_EUMB_BASE) == 0) {
/* Do early winbond init, then scan PCI bus */
sandpoint_setup_winbond_83553(hose);
ppc_md.pci_exclude_device = sandpoint_exclude_device;
hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
ppc_md.pcibios_fixup = NULL;
ppc_md.pcibios_fixup_bus = NULL;
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = sandpoint_map_irq;
}
else {
if (ppc_md.progress)
ppc_md.progress("Bridge init failed", 0x100);
printk("Host bridge init failed\n");
}
return;
}
arch/ppc/platforms/sandpoint_serial.h deleted 100644 → 0
View file @ 5bb4ee47
/*
* include/asm-ppc/sandpoint_serial.h
*
* Definitions for Motorola SPS Sandpoint Test Platform
*
* Author: Mark A. Greer
* mgreer@mvista.com
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASMPPC_SANDPOINT_SERIAL_H
#define __ASMPPC_SANDPOINT_SERIAL_H
#include <linux/config.h>
#define SANDPOINT_SERIAL_0 0xfe0003f8
#define SANDPOINT_SERIAL_1 0xfe0002f8
#ifdef CONFIG_SERIAL_MANY_PORTS
#define RS_TABLE_SIZE 64
#else
#define RS_TABLE_SIZE 2
#endif
/* Rate for the 1.8432 Mhz clock for the onboard serial chip */
#define BASE_BAUD ( 1843200 / 16 )
#ifdef CONFIG_SERIAL_DETECT_IRQ
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
#else
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
#endif
#define STD_SERIAL_PORT_DFNS \
{ 0, BASE_BAUD, SANDPOINT_SERIAL_0, 4, STD_COM_FLAGS, /* ttyS0 */ \
iomem_base: (u8 *)SANDPOINT_SERIAL_0, \
io_type: SERIAL_IO_MEM }, \
{ 0, BASE_BAUD, SANDPOINT_SERIAL_1, 3, STD_COM_FLAGS, /* ttyS1 */ \
iomem_base: (u8 *)SANDPOINT_SERIAL_1, \
io_type: SERIAL_IO_MEM },
#define SERIAL_PORT_DFNS \
STD_SERIAL_PORT_DFNS
#endif /* __ASMPPC_SANDPOINT_SERIAL_H */
arch/ppc/syslib/Makefile
View file @ 7246a035
......@@ -62,5 +62,8 @@ obj-$(CONFIG_SANDPOINT) += i8259.o open_pic.o mpc10x_common.o \
obj-$(CONFIG_SPRUCE) += cpc700_pic.o indirect_pci.o pci_auto.o \
todc_time.o
obj-$(CONFIG_8260) += m8260_setup.o ppc8260_pic.o
ifeq ($(CONFIG_SERIAL_8250)$(CONFIG_PPC_GEN550),yy)
obj-$(CONFIG_KGDB) += gen550_kgdb.o gen550_dbg.o
obj-$(CONFIG_SERIAL_TEXT_DEBUG) += gen550_dbg.o
endif
obj-$(CONFIG_BOOTX_TEXT) += btext.o
arch/ppc/syslib/gen550_dbg.c 0 → 100644
View file @ 7246a035
/*
* arch/ppc/syslib/gen550_dbg.c
*
* A library of polled 16550 serial routines. These are intended to
* be used to support progress messages, xmon, kgdb, etc. on a
* variety of platforms.
*
* Adapted from lots of code ripped from the arch/ppc/boot/ polled
* 16550 support.
*
* Author: Matt Porter <mporter@mvista.com>
*
* 2002-2003 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/config.h>
#include <linux/tty.h> /* For linux/serial_core.h */
#include <linux/serial_core.h>
#include <linux/serialP.h>
#include <linux/serial_reg.h>
#include <asm/machdep.h>
#include <asm/serial.h>
#include <asm/io.h>
#define SERIAL_BAUD 9600
static struct serial_state rs_table[RS_TABLE_SIZE] = {
SERIAL_PORT_DFNS /* defined in <asm/serial.h> */
};
static void (*serial_outb)(unsigned long, unsigned char);
static unsigned long (*serial_inb)(unsigned long);
static int shift;
unsigned long direct_inb(unsigned long addr)
{
return readb(addr);
}
void direct_outb(unsigned long addr, unsigned char val)
{
writeb(val, addr);
}
unsigned long io_inb(unsigned long port)
{
return inb(port);
}
void io_outb(unsigned long port, unsigned char val)
{
outb(val, port);
}
unsigned long serial_init(int chan, void *ignored)
{
unsigned long com_port;
unsigned char lcr, dlm;
/* We need to find out which type io we're expecting. If it's
* 'SERIAL_IO_PORT', we get an offset from the isa_io_base.
* If it's 'SERIAL_IO_MEM', we can the exact location. -- Tom */
switch (rs_table[chan].io_type) {
case SERIAL_IO_PORT:
com_port = rs_table[chan].port;
serial_outb = io_outb;
serial_inb = io_inb;
break;
case SERIAL_IO_MEM:
com_port = (unsigned long)rs_table[chan].iomem_base;
serial_outb = direct_outb;
serial_inb = direct_inb;
break;
default:
/* We can't deal with it. */
return -1;
}
/* How far apart the registers are. */
shift = rs_table[chan].iomem_reg_shift;
/* save the LCR */
lcr = serial_inb(com_port + (UART_LCR << shift));
/* Access baud rate */
serial_outb(com_port + (UART_LCR << shift), UART_LCR_DLAB);
dlm = serial_inb(com_port + (UART_DLM << shift));
/*
* Test if serial port is unconfigured
* We assume that no-one uses less than 110 baud or
* less than 7 bits per character these days.
* -- paulus.
*/
if ((dlm <= 4) && (lcr & 2)) {
/* port is configured, put the old LCR back */
serial_outb(com_port + (UART_LCR << shift), lcr);
}
else {
/* Input clock. */
serial_outb(com_port + (UART_DLL << shift),
(rs_table[chan].baud_base / SERIAL_BAUD) & 0xFF);
serial_outb(com_port + (UART_DLM << shift),
(rs_table[chan].baud_base / SERIAL_BAUD) >> 8);
/* 8 data, 1 stop, no parity */
serial_outb(com_port + (UART_LCR << shift), 0x03);
/* RTS/DTR */
serial_outb(com_port + (UART_MCR << shift), 0x03);
/* Clear & enable FIFOs */
serial_outb(com_port + (UART_FCR << shift), 0x07);
}
return (com_port);
}
void
serial_putc(unsigned long com_port, unsigned char c)
{
while ((serial_inb(com_port + (UART_LSR << shift)) & UART_LSR_THRE) == 0)
;
serial_outb(com_port, c);
}
unsigned char
serial_getc(unsigned long com_port)
{
while ((serial_inb(com_port + (UART_LSR << shift)) & UART_LSR_DR) == 0)
;
return serial_inb(com_port);
}
int
serial_tstc(unsigned long com_port)
{
return ((serial_inb(com_port + (UART_LSR << shift)) & UART_LSR_DR) != 0);
}
void
serial_close(unsigned long com_port)
{
}
void
gen550_init(int i, struct uart_port *serial_req)
{
rs_table[i].io_type = serial_req->iotype;
rs_table[i].port = serial_req->line;
rs_table[i].iomem_base = serial_req->membase;
rs_table[i].iomem_reg_shift = serial_req->regshift;
}
#ifdef CONFIG_SERIAL_TEXT_DEBUG
void
gen550_progress(char *s, unsigned short hex)
{
volatile unsigned int progress_debugport;
volatile char c;
progress_debugport = serial_init(0, NULL);
serial_putc(progress_debugport, '\r');
while ((c = *s++) != 0)
serial_putc(progress_debugport, c);
serial_putc(progress_debugport, '\n');
serial_putc(progress_debugport, '\r');
}
#endif /* CONFIG_SERIAL_TEXT_DEBUG */
arch/ppc/syslib/gen550_kgdb.c 0 → 100644
View file @ 7246a035
/*
* arch/ppc/syslib/gen550_kgdb.c
*
* Generic 16550 kgdb support intended to be useful on a variety
* of platforms. To enable this support, it is necessary to set
* the CONFIG_GEN550 option. Any virtual mapping of the serial
* port(s) to be used can be accomplished by setting
* ppc_md.early_serial_map to a platform-specific mapping function.
*
* Adapted from ppc4xx_kgdb.c.
*
* Author: Matt Porter <mporter@mvista.com>
*
* 2002-2003 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#include <linux/config.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <asm/machdep.h>
extern unsigned long serial_init(int, void *);
extern unsigned long serial_getc(unsigned long);
extern unsigned long serial_putc(unsigned long, unsigned char);
#if defined(CONFIG_KGDB_TTYS0)
#define KGDB_PORT 0
#elif defined(CONFIG_KGDB_TTYS1)
#define KGDB_PORT 1
#elif defined(CONFIG_KGDB_TTYS2)
#define KGDB_PORT 2
#elif defined(CONFIG_KGDB_TTYS3)
#define KGDB_PORT 3
#else
#error "invalid kgdb_tty port"
#endif
static volatile unsigned int kgdb_debugport;
void putDebugChar(unsigned char c)
{
if (kgdb_debugport == 0)
kgdb_debugport = serial_init(KGDB_PORT, NULL);
serial_putc(kgdb_debugport, c);
}
int getDebugChar(void)
{
if (kgdb_debugport == 0)
kgdb_debugport = serial_init(KGDB_PORT, NULL);
return(serial_getc(kgdb_debugport));
}
void kgdb_interruptible(int enable)
{
return;
}
void putDebugString(char* str)
{
while (*str != '\0') {
putDebugChar(*str);
str++;
}
putDebugChar('\r');
return;
}
/*
* Note: gen550_init() must be called already on the port we are going
* to use.
*/
void
kgdb_map_scc(void)
{
printk(KERN_DEBUG "kgdb init\n");
kgdb_debugport = serial_init(KGDB_PORT, NULL);
}
arch/ppc/syslib/open_pic.c
View file @ 7246a035
......@@ -33,6 +33,7 @@
void* OpenPIC_Addr;
static volatile struct OpenPIC *OpenPIC = NULL;
/*
* We define OpenPIC_InitSenses table thusly:
* bit 0x1: sense, 0 for edge and 1 for level.
......@@ -261,32 +262,32 @@ static void openpic_safe_writefield_IPI(volatile u_int *addr, u_int mask, u_int
}
#endif /* CONFIG_SMP */
#if defined(CONFIG_EPIC_SERIAL_MODE) || defined(CONFIG_PMAC_PBOOK)
static void openpic_reset(void)
#ifdef CONFIG_EPIC_SERIAL_MODE
static void __init openpic_eicr_set_clk(u_int clkval)
{
openpic_setfield(&OpenPIC->Global.Global_Configuration0,
OPENPIC_CONFIG_RESET);
while (openpic_readfield(&OpenPIC->Global.Global_Configuration0,
OPENPIC_CONFIG_RESET))
mb();
openpic_writefield(&OpenPIC->Global.Global_Configuration1,
OPENPIC_EICR_S_CLK_MASK, (clkval << 28));
}
#endif
#ifdef CONFIG_EPIC_SERIAL_MODE
static void openpic_enable_sie(void)
static void __init openpic_enable_sie(void)
{
openpic_setfield(&OpenPIC->Global.Global_Configuration1,
OPENPIC_EICR_SIE);
OPENPIC_EICR_SIE);
}
#endif
static void openpic_eicr_set_clk(u_int clkval)
#if defined(CONFIG_EPIC_SERIAL_MODE) || defined(CONFIG_PMAC_PBOOK)
static void openpic_reset(void)
{
openpic_writefield(&OpenPIC->Global.Global_Configuration1,
OPENPIC_EICR_S_CLK_MASK, (clkval << 28));
openpic_setfield(&OpenPIC->Global.Global_Configuration0,
OPENPIC_CONFIG_RESET);
while (openpic_readfield(&OpenPIC->Global.Global_Configuration0,
OPENPIC_CONFIG_RESET))
mb();
}
#endif
void openpic_set_sources(int first_irq, int num_irqs, void *first_ISR)
void __init openpic_set_sources(int first_irq, int num_irqs, void *first_ISR)
{
volatile OpenPIC_Source *src = first_ISR;
int i, last_irq;
......@@ -300,7 +301,14 @@ void openpic_set_sources(int first_irq, int num_irqs, void *first_ISR)
ISR[i] = src;
}
void __init openpic_init(int linux_irq_offset)
/*
* The `offset' parameter defines where the interrupts handled by the
* OpenPIC start in the space of interrupt numbers that the kernel knows
* about. In other words, the OpenPIC's IRQ0 is numbered `offset' in the
* kernel's interrupt numbering scheme.
* We assume there is only one OpenPIC.
*/
void __init openpic_init(int offset)
{
u_int t, i;
u_int timerfreq;
......@@ -349,13 +357,13 @@ void __init openpic_init(int linux_irq_offset)
printk("OpenPIC timer frequency is %d.%06d MHz\n",
timerfreq / 1000000, timerfreq % 1000000);
open_pic_irq_offset = linux_irq_offset;
open_pic_irq_offset = offset;
/* Initialize timer interrupts */
if ( ppc_md.progress ) ppc_md.progress("openpic: timer",0x3ba);
for (i = 0; i < OPENPIC_NUM_TIMERS; i++) {
/* Disabled, Priority 0 */
openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i+linux_irq_offset);
openpic_inittimer(i, 0, OPENPIC_VEC_TIMER+i+offset);
/* No processor */
openpic_maptimer(i, 0);
}
......@@ -365,12 +373,10 @@ void __init openpic_init(int linux_irq_offset)
if ( ppc_md.progress ) ppc_md.progress("openpic: ipi",0x3bb);
for (i = 0; i < OPENPIC_NUM_IPI; i++) {
/* Disabled, Priority 10..13 */
openpic_initipi(i, 10+i, OPENPIC_VEC_IPI+i+linux_irq_offset);
openpic_initipi(i, 10+i, OPENPIC_VEC_IPI+i+offset);
/* IPIs are per-CPU */
irq_desc[OPENPIC_VEC_IPI+i+linux_irq_offset].status |=
IRQ_PER_CPU;
irq_desc[OPENPIC_VEC_IPI+i+linux_irq_offset].handler =
&open_pic_ipi;
irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU;
irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi;
}
#endif
......@@ -387,40 +393,36 @@ void __init openpic_init(int linux_irq_offset)
continue;
/* the bootloader may have left it enabled (bad !) */
openpic_disable_irq(i+linux_irq_offset);
openpic_disable_irq(i+offset);
/*
* We find the value from either the InitSenses table
* or assume a negative polarity level interrupt.
*/
sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: 1;
sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: \
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE);
if ((sense & IRQ_SENSE_MASK) == 1)
irq_desc[i+linux_irq_offset].status = IRQ_LEVEL;
if (sense & IRQ_SENSE_MASK)
irq_desc[i+offset].status = IRQ_LEVEL;
/* Enabled, Priority 8 */
openpic_initirq(i, 8, i + linux_irq_offset,
(sense & IRQ_POLARITY_MASK),
openpic_initirq(i, 8, i+offset, (sense & IRQ_POLARITY_MASK),
(sense & IRQ_SENSE_MASK));
/* Processor 0 */
openpic_mapirq(i, 1<<0, 0);
}
/* Init descriptors */
for (i = linux_irq_offset; i < NumSources + linux_irq_offset; i++)
for (i = offset; i < NumSources + offset; i++)
irq_desc[i].handler = &open_pic;
/* Initialize the spurious interrupt */
if (ppc_md.progress) ppc_md.progress("openpic: spurious",0x3bd);
openpic_set_spurious(OPENPIC_VEC_SPURIOUS+linux_irq_offset);
openpic_set_spurious(OPENPIC_VEC_SPURIOUS+offset);
/* Initialize the cascade */
if (linux_irq_offset) {
if (request_irq(linux_irq_offset, no_action, SA_INTERRUPT,
if (offset) {
if (request_irq(offset, no_action, SA_INTERRUPT,
"82c59 cascade", NULL))
printk("Unable to get OpenPIC IRQ 0 for cascade\n");
}
openpic_disable_8259_pass_through();
openpic_disable_8259_pass_through();
#ifdef CONFIG_EPIC_SERIAL_MODE
openpic_eicr_set_clk(7); /* Slowest value until we know better */
openpic_enable_sie();
......@@ -479,7 +481,7 @@ static u_int openpic_get_priority(void)
}
#endif /* notused */
static void openpic_set_priority(u_int pri)
static void __init openpic_set_priority(u_int pri)
{
DECL_THIS_CPU;
......@@ -656,29 +658,18 @@ static void __init openpic_maptimer(u_int timer, u_int cpumask)
}
/*
* Initalize the interrupt source which will generate an NMI (and disable it).
* Initalize the interrupt source which will generate an NMI.
* This raises the interrupt's priority from 8 to 9.
*
* irq: The logical IRQ which generates an NMI.
*/
void __init
openpic_init_nmi_irq(u_int irq)
{
int sense;
/* If this wasn't given, assume a level, negative polarity interrupt. */
sense = (irq < OpenPIC_NumInitSenses) ? OpenPIC_InitSenses[irq] :
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE);
openpic_safe_writefield(&ISR[irq]->Vector_Priority,
OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK,
(9 << OPENPIC_PRIORITY_SHIFT) |
(irq + open_pic_irq_offset) |
((sense & IRQ_POLARITY_MASK) ?
OPENPIC_POLARITY_POSITIVE :
OPENPIC_POLARITY_NEGATIVE) |
((sense & IRQ_SENSE_MASK) ? OPENPIC_SENSE_LEVEL
: OPENPIC_SENSE_EDGE));
check_arg_irq(irq);
openpic_safe_writefield(&ISR[irq - open_pic_irq_offset]->Vector_Priority,
OPENPIC_PRIORITY_MASK,
9 << OPENPIC_PRIORITY_SHIFT);
}
/*
......@@ -752,7 +743,8 @@ void openpic_disable_ipi(u_int irq)
* pol: polarity (1 for positive, 0 for negative)
* sense: 1 for level, 0 for edge
*/
static void openpic_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense)
static void __init
openpic_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense)
{
openpic_safe_writefield(&ISR[irq]->Vector_Priority,
OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
......
include/asm-ppc/serial.h
View file @ 7246a035
......@@ -25,7 +25,7 @@
#elif defined(CONFIG_PRPMC800)
#include <platforms/prpmc800_serial.h>
#elif defined(CONFIG_SANDPOINT)
#include <platforms/sandpoint_serial.h>
#include <platforms/sandpoint.h>
#elif defined(CONFIG_SPRUCE)
#include <platforms/spruce_serial.h>
#elif defined(CONFIG_40x)
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7