Skip to content

L
linux
Commit 73444723 authored by Bard Liao's avatar Bard Liao Committed by Mark Brown
Browse files
Options

ASoC: rt5663: rename rt5668 as rt5663 v2 

The "rt5668" codec supported in this driver is actually a revision
of "rt5663". So the patch is renamed to "rt5663 v2"
Signed-off-by: default avatarBard Liao <bardliao@realtek.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 7e7e76bd
Hide whitespace changes
Inline Side-by-side
Showing with 1140 additions and 1150 deletions
Documentation/devicetree/bindings/sound/rt5663.txt
View file @ 73444723
RT5663/RT5668 audio CODEC
RT5663 audio CODEC
This device supports I2C only.
Required properties:
- compatible : One of "realtek,rt5663" or "realtek,rt5668".
- compatible : "realtek,rt5663".
- reg : The I2C address of the device.
......@@ -12,7 +12,7 @@ Required properties:
Optional properties:
Pins on the device (for linking into audio routes) for RT5663/RT5668:
Pins on the device (for linking into audio routes) for RT5663:
* IN1P
* IN1N
......
sound/soc/codecs/rt5663.c
View file @ 73444723
/*
* rt5663.c -- RT5668/RT5663 ALSA SoC audio codec driver
* rt5663.c -- RT5663 ALSA SoC audio codec driver
*
* Copyright 2016 Realtek Semiconductor Corp.
* Author: Jack Yu <jack.yu@realtek.com>
......@@ -30,12 +30,12 @@
#include "rt5663.h"
#include "rl6231.h"
#define RT5668_DEVICE_ID 0x6451
#define RT5663_DEVICE_ID 0x6406
#define RT5663_DEVICE_ID_2 0x6451
#define RT5663_DEVICE_ID_1 0x6406
enum {
CODEC_TYPE_RT5668,
CODEC_TYPE_RT5663,
CODEC_VER_1,
CODEC_VER_0,
};
struct rt5663_priv {
......@@ -45,7 +45,7 @@ struct rt5663_priv {
struct snd_soc_jack *hs_jack;
struct timer_list btn_check_timer;
int codec_type;
int codec_ver;
int sysclk;
int sysclk_src;
int lrck;
......@@ -57,7 +57,7 @@ struct rt5663_priv {
int jack_type;
};
static const struct reg_default rt5668_reg[] = {
static const struct reg_default rt5663_v2_reg[] = {
{ 0x0000, 0x0000 },
{ 0x0001, 0xc8c8 },
{ 0x0002, 0x8080 },
......@@ -730,7 +730,7 @@ static bool rt5663_volatile_register(struct device *dev, unsigned int reg)
case RT5663_ADC_EQ_1:
case RT5663_INT_ST_1:
case RT5663_INT_ST_2:
case RT5663_GPIO_STA:
case RT5663_GPIO_STA1:
case RT5663_SIN_GEN_1:
case RT5663_IL_CMD_1:
case RT5663_IL_CMD_5:
......@@ -846,7 +846,7 @@ static bool rt5663_readable_register(struct device *dev, unsigned int reg)
case RT5663_INT_ST_2:
case RT5663_GPIO_1:
case RT5663_GPIO_2:
case RT5663_GPIO_STA:
case RT5663_GPIO_STA1:
case RT5663_SIN_GEN_1:
case RT5663_SIN_GEN_2:
case RT5663_SIN_GEN_3:
......@@ -1036,23 +1036,23 @@ static bool rt5663_readable_register(struct device *dev, unsigned int reg)
}
}
static bool rt5668_volatile_register(struct device *dev, unsigned int reg)
static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5663_RESET:
case RT5668_CBJ_TYPE_2:
case RT5668_PDM_OUT_CTL:
case RT5668_PDM_I2C_DATA_CTL1:
case RT5668_PDM_I2C_DATA_CTL4:
case RT5668_ALC_BK_GAIN:
case RT5663_CBJ_TYPE_2:
case RT5663_PDM_OUT_CTL:
case RT5663_PDM_I2C_DATA_CTL1:
case RT5663_PDM_I2C_DATA_CTL4:
case RT5663_ALC_BK_GAIN:
case RT5663_PLL_2:
case RT5663_MICBIAS_1:
case RT5663_ADC_EQ_1:
case RT5663_INT_ST_1:
case RT5668_GPIO_STA:
case RT5663_GPIO_STA2:
case RT5663_IL_CMD_1:
case RT5663_IL_CMD_5:
case RT5668_A_JD_CTRL:
case RT5663_A_JD_CTRL:
case RT5663_JD_CTRL2:
case RT5663_VENDOR_ID:
case RT5663_VENDOR_ID_1:
......@@ -1061,15 +1061,15 @@ static bool rt5668_volatile_register(struct device *dev, unsigned int reg)
case RT5663_STO_DRE_5:
case RT5663_STO_DRE_6:
case RT5663_STO_DRE_7:
case RT5668_MONO_DYNA_6:
case RT5668_STO1_SIL_DET:
case RT5668_MONOL_SIL_DET:
case RT5668_MONOR_SIL_DET:
case RT5668_STO2_DAC_SIL:
case RT5668_MONO_AMP_CAL_ST1:
case RT5668_MONO_AMP_CAL_ST2:
case RT5668_MONO_AMP_CAL_ST3:
case RT5668_MONO_AMP_CAL_ST4:
case RT5663_MONO_DYNA_6:
case RT5663_STO1_SIL_DET:
case RT5663_MONOL_SIL_DET:
case RT5663_MONOR_SIL_DET:
case RT5663_STO2_DAC_SIL:
case RT5663_MONO_AMP_CAL_ST1:
case RT5663_MONO_AMP_CAL_ST2:
case RT5663_MONO_AMP_CAL_ST3:
case RT5663_MONO_AMP_CAL_ST4:
case RT5663_HP_IMP_SEN_2:
case RT5663_HP_IMP_SEN_3:
case RT5663_HP_IMP_SEN_4:
......@@ -1083,218 +1083,218 @@ static bool rt5668_volatile_register(struct device *dev, unsigned int reg)
case RT5663_HP_CALIB_ST7:
case RT5663_HP_CALIB_ST8:
case RT5663_HP_CALIB_ST9:
case RT5668_HP_CALIB_ST10:
case RT5668_HP_CALIB_ST11:
case RT5663_HP_CALIB_ST10:
case RT5663_HP_CALIB_ST11:
return true;
default:
return false;
}
}
static bool rt5668_readable_register(struct device *dev, unsigned int reg)
static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case RT5668_LOUT_CTRL:
case RT5668_HP_AMP_2:
case RT5668_MONO_OUT:
case RT5668_MONO_GAIN:
case RT5668_AEC_BST:
case RT5668_IN1_IN2:
case RT5668_IN3_IN4:
case RT5668_INL1_INR1:
case RT5668_CBJ_TYPE_2:
case RT5668_CBJ_TYPE_3:
case RT5668_CBJ_TYPE_4:
case RT5668_CBJ_TYPE_5:
case RT5668_CBJ_TYPE_8:
case RT5668_DAC3_DIG_VOL:
case RT5668_DAC3_CTRL:
case RT5668_MONO_ADC_DIG_VOL:
case RT5668_STO2_ADC_DIG_VOL:
case RT5668_MONO_ADC_BST_GAIN:
case RT5668_STO2_ADC_BST_GAIN:
case RT5668_SIDETONE_CTRL:
case RT5668_MONO1_ADC_MIXER:
case RT5668_STO2_ADC_MIXER:
case RT5668_MONO_DAC_MIXER:
case RT5668_DAC2_SRC_CTRL:
case RT5668_IF_3_4_DATA_CTL:
case RT5668_IF_5_DATA_CTL:
case RT5668_PDM_OUT_CTL:
case RT5668_PDM_I2C_DATA_CTL1:
case RT5668_PDM_I2C_DATA_CTL2:
case RT5668_PDM_I2C_DATA_CTL3:
case RT5668_PDM_I2C_DATA_CTL4:
case RT5668_RECMIX1_NEW:
case RT5668_RECMIX1L_0:
case RT5668_RECMIX1L:
case RT5668_RECMIX1R_0:
case RT5668_RECMIX1R:
case RT5668_RECMIX2_NEW:
case RT5668_RECMIX2_L_2:
case RT5668_RECMIX2_R:
case RT5668_RECMIX2_R_2:
case RT5668_CALIB_REC_LR:
case RT5668_ALC_BK_GAIN:
case RT5668_MONOMIX_GAIN:
case RT5668_MONOMIX_IN_GAIN:
case RT5668_OUT_MIXL_GAIN:
case RT5668_OUT_LMIX_IN_GAIN:
case RT5668_OUT_RMIX_IN_GAIN:
case RT5668_OUT_RMIX_IN_GAIN1:
case RT5668_LOUT_MIXER_CTRL:
case RT5668_PWR_VOL:
case RT5668_ADCDAC_RST:
case RT5668_I2S34_SDP:
case RT5668_I2S5_SDP:
case RT5668_TDM_5:
case RT5668_TDM_6:
case RT5668_TDM_7:
case RT5668_TDM_8:
case RT5668_ASRC_3:
case RT5668_ASRC_6:
case RT5668_ASRC_7:
case RT5668_PLL_TRK_13:
case RT5668_I2S_M_CLK_CTL:
case RT5668_FDIV_I2S34_M_CLK:
case RT5668_FDIV_I2S34_M_CLK2:
case RT5668_FDIV_I2S5_M_CLK:
case RT5668_FDIV_I2S5_M_CLK2:
case RT5668_IRQ_4:
case RT5668_GPIO_3:
case RT5668_GPIO_4:
case RT5668_GPIO_STA:
case RT5668_HP_AMP_DET1:
case RT5668_HP_AMP_DET2:
case RT5668_HP_AMP_DET3:
case RT5668_MID_BD_HP_AMP:
case RT5668_LOW_BD_HP_AMP:
case RT5668_SOF_VOL_ZC2:
case RT5668_ADC_STO2_ADJ1:
case RT5668_ADC_STO2_ADJ2:
case RT5668_A_JD_CTRL:
case RT5668_JD1_TRES_CTRL:
case RT5668_JD2_TRES_CTRL:
case RT5668_JD_CTRL2:
case RT5668_DUM_REG_2:
case RT5668_DUM_REG_3:
case RT5663_LOUT_CTRL:
case RT5663_HP_AMP_2:
case RT5663_MONO_OUT:
case RT5663_MONO_GAIN:
case RT5663_AEC_BST:
case RT5663_IN1_IN2:
case RT5663_IN3_IN4:
case RT5663_INL1_INR1:
case RT5663_CBJ_TYPE_2:
case RT5663_CBJ_TYPE_3:
case RT5663_CBJ_TYPE_4:
case RT5663_CBJ_TYPE_5:
case RT5663_CBJ_TYPE_8:
case RT5663_DAC3_DIG_VOL:
case RT5663_DAC3_CTRL:
case RT5663_MONO_ADC_DIG_VOL:
case RT5663_STO2_ADC_DIG_VOL:
case RT5663_MONO_ADC_BST_GAIN:
case RT5663_STO2_ADC_BST_GAIN:
case RT5663_SIDETONE_CTRL:
case RT5663_MONO1_ADC_MIXER:
case RT5663_STO2_ADC_MIXER:
case RT5663_MONO_DAC_MIXER:
case RT5663_DAC2_SRC_CTRL:
case RT5663_IF_3_4_DATA_CTL:
case RT5663_IF_5_DATA_CTL:
case RT5663_PDM_OUT_CTL:
case RT5663_PDM_I2C_DATA_CTL1:
case RT5663_PDM_I2C_DATA_CTL2:
case RT5663_PDM_I2C_DATA_CTL3:
case RT5663_PDM_I2C_DATA_CTL4:
case RT5663_RECMIX1_NEW:
case RT5663_RECMIX1L_0:
case RT5663_RECMIX1L:
case RT5663_RECMIX1R_0:
case RT5663_RECMIX1R:
case RT5663_RECMIX2_NEW:
case RT5663_RECMIX2_L_2:
case RT5663_RECMIX2_R:
case RT5663_RECMIX2_R_2:
case RT5663_CALIB_REC_LR:
case RT5663_ALC_BK_GAIN:
case RT5663_MONOMIX_GAIN:
case RT5663_MONOMIX_IN_GAIN:
case RT5663_OUT_MIXL_GAIN:
case RT5663_OUT_LMIX_IN_GAIN:
case RT5663_OUT_RMIX_IN_GAIN:
case RT5663_OUT_RMIX_IN_GAIN1:
case RT5663_LOUT_MIXER_CTRL:
case RT5663_PWR_VOL:
case RT5663_ADCDAC_RST:
case RT5663_I2S34_SDP:
case RT5663_I2S5_SDP:
case RT5663_TDM_6:
case RT5663_TDM_7:
case RT5663_TDM_8:
case RT5663_TDM_9:
case RT5663_ASRC_3:
case RT5663_ASRC_6:
case RT5663_ASRC_7:
case RT5663_PLL_TRK_13:
case RT5663_I2S_M_CLK_CTL:
case RT5663_FDIV_I2S34_M_CLK:
case RT5663_FDIV_I2S34_M_CLK2:
case RT5663_FDIV_I2S5_M_CLK:
case RT5663_FDIV_I2S5_M_CLK2:
case RT5663_V2_IRQ_4:
case RT5663_GPIO_3:
case RT5663_GPIO_4:
case RT5663_GPIO_STA2:
case RT5663_HP_AMP_DET1:
case RT5663_HP_AMP_DET2:
case RT5663_HP_AMP_DET3:
case RT5663_MID_BD_HP_AMP:
case RT5663_LOW_BD_HP_AMP:
case RT5663_SOF_VOL_ZC2:
case RT5663_ADC_STO2_ADJ1:
case RT5663_ADC_STO2_ADJ2:
case RT5663_A_JD_CTRL:
case RT5663_JD1_TRES_CTRL:
case RT5663_JD2_TRES_CTRL:
case RT5663_V2_JD_CTRL2:
case RT5663_DUM_REG_2:
case RT5663_DUM_REG_3:
case RT5663_VENDOR_ID:
case RT5663_VENDOR_ID_1:
case RT5663_VENDOR_ID_2:
case RT5668_DACADC_DIG_VOL2:
case RT5668_DIG_IN_PIN2:
case RT5668_PAD_DRV_CTL1:
case RT5668_SOF_RAM_DEPOP:
case RT5668_VOL_TEST:
case RT5668_TEST_MODE_3:
case RT5668_TEST_MODE_4:
case RT5663_DACADC_DIG_VOL2:
case RT5663_DIG_IN_PIN2:
case RT5663_PAD_DRV_CTL1:
case RT5663_SOF_RAM_DEPOP:
case RT5663_VOL_TEST:
case RT5663_TEST_MODE_4:
case RT5663_TEST_MODE_5:
case RT5663_STO_DRE_9:
case RT5668_MONO_DYNA_1:
case RT5668_MONO_DYNA_2:
case RT5668_MONO_DYNA_3:
case RT5668_MONO_DYNA_4:
case RT5668_MONO_DYNA_5:
case RT5668_MONO_DYNA_6:
case RT5668_STO1_SIL_DET:
case RT5668_MONOL_SIL_DET:
case RT5668_MONOR_SIL_DET:
case RT5668_STO2_DAC_SIL:
case RT5668_PWR_SAV_CTL1:
case RT5668_PWR_SAV_CTL2:
case RT5668_PWR_SAV_CTL3:
case RT5668_PWR_SAV_CTL4:
case RT5668_PWR_SAV_CTL5:
case RT5668_PWR_SAV_CTL6:
case RT5668_MONO_AMP_CAL1:
case RT5668_MONO_AMP_CAL2:
case RT5668_MONO_AMP_CAL3:
case RT5668_MONO_AMP_CAL4:
case RT5668_MONO_AMP_CAL5:
case RT5668_MONO_AMP_CAL6:
case RT5668_MONO_AMP_CAL7:
case RT5668_MONO_AMP_CAL_ST1:
case RT5668_MONO_AMP_CAL_ST2:
case RT5668_MONO_AMP_CAL_ST3:
case RT5668_MONO_AMP_CAL_ST4:
case RT5668_MONO_AMP_CAL_ST5:
case RT5668_HP_IMP_SEN_13:
case RT5668_HP_IMP_SEN_14:
case RT5668_HP_IMP_SEN_6:
case RT5668_HP_IMP_SEN_7:
case RT5668_HP_IMP_SEN_8:
case RT5668_HP_IMP_SEN_9:
case RT5668_HP_IMP_SEN_10:
case RT5668_HP_LOGIC_3:
case RT5668_HP_CALIB_ST10:
case RT5668_HP_CALIB_ST11:
case RT5668_PRO_REG_TBL_4:
case RT5668_PRO_REG_TBL_5:
case RT5668_PRO_REG_TBL_6:
case RT5668_PRO_REG_TBL_7:
case RT5668_PRO_REG_TBL_8:
case RT5668_PRO_REG_TBL_9:
case RT5668_SAR_ADC_INL_1:
case RT5668_SAR_ADC_INL_2:
case RT5668_SAR_ADC_INL_3:
case RT5668_SAR_ADC_INL_4:
case RT5668_SAR_ADC_INL_5:
case RT5668_SAR_ADC_INL_6:
case RT5668_SAR_ADC_INL_7:
case RT5668_SAR_ADC_INL_8:
case RT5668_SAR_ADC_INL_9:
case RT5668_SAR_ADC_INL_10:
case RT5668_SAR_ADC_INL_11:
case RT5668_SAR_ADC_INL_12:
case RT5668_DRC_CTRL_1:
case RT5668_DRC1_CTRL_2:
case RT5668_DRC1_CTRL_3:
case RT5668_DRC1_CTRL_4:
case RT5668_DRC1_CTRL_5:
case RT5668_DRC1_CTRL_6:
case RT5668_DRC1_HD_CTRL_1:
case RT5668_DRC1_HD_CTRL_2:
case RT5668_DRC1_PRI_REG_1:
case RT5668_DRC1_PRI_REG_2:
case RT5668_DRC1_PRI_REG_3:
case RT5668_DRC1_PRI_REG_4:
case RT5668_DRC1_PRI_REG_5:
case RT5668_DRC1_PRI_REG_6:
case RT5668_DRC1_PRI_REG_7:
case RT5668_DRC1_PRI_REG_8:
case RT5668_ALC_PGA_CTL_1:
case RT5668_ALC_PGA_CTL_2:
case RT5668_ALC_PGA_CTL_3:
case RT5668_ALC_PGA_CTL_4:
case RT5668_ALC_PGA_CTL_5:
case RT5668_ALC_PGA_CTL_6:
case RT5668_ALC_PGA_CTL_7:
case RT5668_ALC_PGA_CTL_8:
case RT5668_ALC_PGA_REG_1:
case RT5668_ALC_PGA_REG_2:
case RT5668_ALC_PGA_REG_3:
case RT5668_ADC_EQ_RECOV_1:
case RT5668_ADC_EQ_RECOV_2:
case RT5668_ADC_EQ_RECOV_3:
case RT5668_ADC_EQ_RECOV_4:
case RT5668_ADC_EQ_RECOV_5:
case RT5668_ADC_EQ_RECOV_6:
case RT5668_ADC_EQ_RECOV_7:
case RT5668_ADC_EQ_RECOV_8:
case RT5668_ADC_EQ_RECOV_9:
case RT5668_ADC_EQ_RECOV_10:
case RT5668_ADC_EQ_RECOV_11:
case RT5668_ADC_EQ_RECOV_12:
case RT5668_ADC_EQ_RECOV_13:
case RT5668_VID_HIDDEN:
case RT5668_VID_CUSTOMER:
case RT5668_SCAN_MODE:
case RT5668_I2C_BYPA:
case RT5663_MONO_DYNA_1:
case RT5663_MONO_DYNA_2:
case RT5663_MONO_DYNA_3:
case RT5663_MONO_DYNA_4:
case RT5663_MONO_DYNA_5:
case RT5663_MONO_DYNA_6:
case RT5663_STO1_SIL_DET:
case RT5663_MONOL_SIL_DET:
case RT5663_MONOR_SIL_DET:
case RT5663_STO2_DAC_SIL:
case RT5663_PWR_SAV_CTL1:
case RT5663_PWR_SAV_CTL2:
case RT5663_PWR_SAV_CTL3:
case RT5663_PWR_SAV_CTL4:
case RT5663_PWR_SAV_CTL5:
case RT5663_PWR_SAV_CTL6:
case RT5663_MONO_AMP_CAL1:
case RT5663_MONO_AMP_CAL2:
case RT5663_MONO_AMP_CAL3:
case RT5663_MONO_AMP_CAL4:
case RT5663_MONO_AMP_CAL5:
case RT5663_MONO_AMP_CAL6:
case RT5663_MONO_AMP_CAL7:
case RT5663_MONO_AMP_CAL_ST1:
case RT5663_MONO_AMP_CAL_ST2:
case RT5663_MONO_AMP_CAL_ST3:
case RT5663_MONO_AMP_CAL_ST4:
case RT5663_MONO_AMP_CAL_ST5:
case RT5663_V2_HP_IMP_SEN_13:
case RT5663_V2_HP_IMP_SEN_14:
case RT5663_V2_HP_IMP_SEN_6:
case RT5663_V2_HP_IMP_SEN_7:
case RT5663_V2_HP_IMP_SEN_8:
case RT5663_V2_HP_IMP_SEN_9:
case RT5663_V2_HP_IMP_SEN_10:
case RT5663_HP_LOGIC_3:
case RT5663_HP_CALIB_ST10:
case RT5663_HP_CALIB_ST11:
case RT5663_PRO_REG_TBL_4:
case RT5663_PRO_REG_TBL_5:
case RT5663_PRO_REG_TBL_6:
case RT5663_PRO_REG_TBL_7:
case RT5663_PRO_REG_TBL_8:
case RT5663_PRO_REG_TBL_9:
case RT5663_SAR_ADC_INL_1:
case RT5663_SAR_ADC_INL_2:
case RT5663_SAR_ADC_INL_3:
case RT5663_SAR_ADC_INL_4:
case RT5663_SAR_ADC_INL_5:
case RT5663_SAR_ADC_INL_6:
case RT5663_SAR_ADC_INL_7:
case RT5663_SAR_ADC_INL_8:
case RT5663_SAR_ADC_INL_9:
case RT5663_SAR_ADC_INL_10:
case RT5663_SAR_ADC_INL_11:
case RT5663_SAR_ADC_INL_12:
case RT5663_DRC_CTRL_1:
case RT5663_DRC1_CTRL_2:
case RT5663_DRC1_CTRL_3:
case RT5663_DRC1_CTRL_4:
case RT5663_DRC1_CTRL_5:
case RT5663_DRC1_CTRL_6:
case RT5663_DRC1_HD_CTRL_1:
case RT5663_DRC1_HD_CTRL_2:
case RT5663_DRC1_PRI_REG_1:
case RT5663_DRC1_PRI_REG_2:
case RT5663_DRC1_PRI_REG_3:
case RT5663_DRC1_PRI_REG_4:
case RT5663_DRC1_PRI_REG_5:
case RT5663_DRC1_PRI_REG_6:
case RT5663_DRC1_PRI_REG_7:
case RT5663_DRC1_PRI_REG_8:
case RT5663_ALC_PGA_CTL_1:
case RT5663_ALC_PGA_CTL_2:
case RT5663_ALC_PGA_CTL_3:
case RT5663_ALC_PGA_CTL_4:
case RT5663_ALC_PGA_CTL_5:
case RT5663_ALC_PGA_CTL_6:
case RT5663_ALC_PGA_CTL_7:
case RT5663_ALC_PGA_CTL_8:
case RT5663_ALC_PGA_REG_1:
case RT5663_ALC_PGA_REG_2:
case RT5663_ALC_PGA_REG_3:
case RT5663_ADC_EQ_RECOV_1:
case RT5663_ADC_EQ_RECOV_2:
case RT5663_ADC_EQ_RECOV_3:
case RT5663_ADC_EQ_RECOV_4:
case RT5663_ADC_EQ_RECOV_5:
case RT5663_ADC_EQ_RECOV_6:
case RT5663_ADC_EQ_RECOV_7:
case RT5663_ADC_EQ_RECOV_8:
case RT5663_ADC_EQ_RECOV_9:
case RT5663_ADC_EQ_RECOV_10:
case RT5663_ADC_EQ_RECOV_11:
case RT5663_ADC_EQ_RECOV_12:
case RT5663_ADC_EQ_RECOV_13:
case RT5663_VID_HIDDEN:
case RT5663_VID_CUSTOMER:
case RT5663_SCAN_MODE:
case RT5663_I2C_BYPA:
return true;
case RT5663_TDM_1:
case RT5663_DEPOP_3:
case RT5663_ASRC_11_2:
case RT5663_INT_ST_2:
case RT5663_GPIO_STA:
case RT5663_GPIO_STA1:
case RT5663_SIN_GEN_1:
case RT5663_SIN_GEN_2:
case RT5663_SIN_GEN_3:
......@@ -1344,7 +1344,7 @@ static bool rt5668_readable_register(struct device *dev, unsigned int reg)
}
static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
static const DECLARE_TLV_DB_SCALE(rt5668_hp_vol_tlv, -2250, 150, 0);
static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0);
static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
......@@ -1374,57 +1374,57 @@ static void rt5663_enable_push_button_irq(struct snd_soc_codec *codec,
if (enable) {
snd_soc_update_bits(codec, RT5663_IL_CMD_6,
RT5668_EN_4BTN_INL_MASK, RT5668_EN_4BTN_INL_EN);
RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN);
/* reset in-line command */
snd_soc_update_bits(codec, RT5663_IL_CMD_6,
RT5668_RESET_4BTN_INL_MASK,
RT5668_RESET_4BTN_INL_RESET);
RT5663_RESET_4BTN_INL_MASK,
RT5663_RESET_4BTN_INL_RESET);
snd_soc_update_bits(codec, RT5663_IL_CMD_6,
RT5668_RESET_4BTN_INL_MASK,
RT5668_RESET_4BTN_INL_NOR);
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
RT5663_RESET_4BTN_INL_MASK,
RT5663_RESET_4BTN_INL_NOR);
switch (rt5663->codec_ver) {
case CODEC_VER_1:
snd_soc_update_bits(codec, RT5663_IRQ_3,
RT5668_EN_IRQ_INLINE_MASK,
RT5668_EN_IRQ_INLINE_NOR);
RT5663_V2_EN_IRQ_INLINE_MASK,
RT5663_V2_EN_IRQ_INLINE_NOR);
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
snd_soc_update_bits(codec, RT5663_IRQ_2,
RT5663_EN_IRQ_INLINE_MASK,
RT5663_EN_IRQ_INLINE_NOR);
break;
default:
dev_err(codec->dev, "Unknown CODEC_TYPE\n");
dev_err(codec->dev, "Unknown CODEC Version\n");
}
} else {
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
switch (rt5663->codec_ver) {
case CODEC_VER_1:
snd_soc_update_bits(codec, RT5663_IRQ_3,
RT5668_EN_IRQ_INLINE_MASK,
RT5668_EN_IRQ_INLINE_BYP);
RT5663_V2_EN_IRQ_INLINE_MASK,
RT5663_V2_EN_IRQ_INLINE_BYP);
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
snd_soc_update_bits(codec, RT5663_IRQ_2,
RT5663_EN_IRQ_INLINE_MASK,
RT5663_EN_IRQ_INLINE_BYP);
break;
default:
dev_err(codec->dev, "Unknown CODEC_TYPE\n");
dev_err(codec->dev, "Unknown CODEC Version\n");
}
snd_soc_update_bits(codec, RT5663_IL_CMD_6,
RT5668_EN_4BTN_INL_MASK, RT5668_EN_4BTN_INL_DIS);
RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS);
/* reset in-line command */
snd_soc_update_bits(codec, RT5663_IL_CMD_6,
RT5668_RESET_4BTN_INL_MASK,
RT5668_RESET_4BTN_INL_RESET);
RT5663_RESET_4BTN_INL_MASK,
RT5663_RESET_4BTN_INL_RESET);
snd_soc_update_bits(codec, RT5663_IL_CMD_6,
RT5668_RESET_4BTN_INL_MASK,
RT5668_RESET_4BTN_INL_NOR);
RT5663_RESET_4BTN_INL_MASK,
RT5663_RESET_4BTN_INL_NOR);
}
}
/**
* rt5668_jack_detect - Detect headset.
* rt5663_v2_jack_detect - Detect headset.
* @codec: SoC audio codec device.
* @jack_insert: Jack insert or not.
*
......@@ -1433,16 +1433,16 @@ static void rt5663_enable_push_button_irq(struct snd_soc_codec *codec,
* Returns detect status.
*/
static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
static int rt5663_v2_jack_detect(struct snd_soc_codec *codec, int jack_insert)
{
struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
struct rt5663_priv *rt5668 = snd_soc_codec_get_drvdata(codec);
struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
if (jack_insert) {
snd_soc_write(codec, RT5668_CBJ_TYPE_2, 0x8040);
snd_soc_write(codec, RT5668_CBJ_TYPE_3, 0x1484);
snd_soc_write(codec, RT5663_CBJ_TYPE_2, 0x8040);
snd_soc_write(codec, RT5663_CBJ_TYPE_3, 0x1484);
snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
......@@ -1450,12 +1450,12 @@ static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
snd_soc_dapm_sync(dapm);
snd_soc_update_bits(codec, RT5663_RC_CLK,
RT5668_DIG_1M_CLK_MASK, RT5668_DIG_1M_CLK_EN);
RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN);
snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x8);
while (i < 5) {
msleep(sleep_time[i]);
val = snd_soc_read(codec, RT5668_CBJ_TYPE_2) & 0x0003;
val = snd_soc_read(codec, RT5663_CBJ_TYPE_2) & 0x0003;
if (val == 0x1 || val == 0x2 || val == 0x3)
break;
dev_dbg(codec->dev, "%s: MX-0011 val=%x sleep %d\n",
......@@ -1466,7 +1466,7 @@ static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
switch (val) {
case 1:
case 2:
rt5668->jack_type = SND_JACK_HEADSET;
rt5663->jack_type = SND_JACK_HEADSET;
rt5663_enable_push_button_irq(codec, true);
break;
default:
......@@ -1475,13 +1475,13 @@ static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
snd_soc_dapm_disable_pin(dapm, "CBJ Power");
snd_soc_dapm_sync(dapm);
rt5668->jack_type = SND_JACK_HEADPHONE;
rt5663->jack_type = SND_JACK_HEADPHONE;
break;
}
} else {
snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x0);
if (rt5668->jack_type == SND_JACK_HEADSET) {
if (rt5663->jack_type == SND_JACK_HEADSET) {
rt5663_enable_push_button_irq(codec, false);
snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
......@@ -1489,11 +1489,11 @@ static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
snd_soc_dapm_disable_pin(dapm, "CBJ Power");
snd_soc_dapm_sync(dapm);
}
rt5668->jack_type = 0;
rt5663->jack_type = 0;
}
dev_dbg(codec->dev, "jack_type = %d\n", rt5668->jack_type);
return rt5668->jack_type;
dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type);
return rt5663->jack_type;
}
/**
......@@ -1514,11 +1514,11 @@ static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert)
if (jack_insert) {
snd_soc_update_bits(codec, RT5663_DIG_MISC,
RT5668_DIG_GATE_CTRL_MASK, RT5668_DIG_GATE_CTRL_EN);
RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
RT5663_SI_HP_MASK | RT5668_OSW_HP_L_MASK |
RT5668_OSW_HP_R_MASK, RT5663_SI_HP_EN |
RT5668_OSW_HP_L_DIS | RT5668_OSW_HP_R_DIS);
RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK |
RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN |
RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS);
snd_soc_update_bits(codec, RT5663_DUMMY_1,
RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK |
RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN |
......@@ -1530,17 +1530,17 @@ static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert)
RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON);
/* BST1 power on for JD */
snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
RT5668_PWR_BST1_MASK, RT5668_PWR_BST1_ON);
RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON);
snd_soc_update_bits(codec, RT5663_EM_JACK_TYPE_1,
RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK |
RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN |
RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN);
snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
RT5668_PWR_MB_MASK | RT5668_LDO1_DVO_MASK |
RT5668_AMP_HP_MASK, RT5668_PWR_MB |
RT5668_LDO1_DVO_0_9V | RT5668_AMP_HP_3X);
RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK |
RT5663_AMP_HP_MASK, RT5663_PWR_MB |
RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
snd_soc_update_bits(codec, RT5663_AUTO_1MRC_CLK,
RT5668_IRQ_POW_SAV_MASK, RT5668_IRQ_POW_SAV_EN);
RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
snd_soc_update_bits(codec, RT5663_IRQ_1,
RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
while (i < 5) {
......@@ -1619,13 +1619,13 @@ static bool rt5663_check_jd_status(struct snd_soc_codec *codec)
dev_dbg(codec->dev, "%s val=%x\n", __func__, val);
/* JD1 */
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
switch (rt5663->codec_ver) {
case CODEC_VER_1:
return !(val & 0x2000);
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
return !(val & 0x1000);
default:
dev_err(codec->dev, "Unknown CODEC_TYPE\n");
dev_err(codec->dev, "Unknown CODEC Version\n");
}
return false;
......@@ -1645,15 +1645,16 @@ static void rt5663_jack_detect_work(struct work_struct *work)
/* jack in */
if (rt5663->jack_type == 0) {
/* jack was out, report jack type */
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
report = rt5668_jack_detect(rt5663->codec, 1);
switch (rt5663->codec_ver) {
case CODEC_VER_1:
report = rt5663_v2_jack_detect(
rt5663->codec, 1);
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
report = rt5663_jack_detect(rt5663->codec, 1);
break;
default:
dev_err(codec->dev, "Unknown CODEC_TYPE\n");
dev_err(codec->dev, "Unknown CODEC Version\n");
}
} else {
/* jack is already in, report button event */
......@@ -1702,15 +1703,15 @@ static void rt5663_jack_detect_work(struct work_struct *work)
}
} else {
/* jack out */
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
report = rt5668_jack_detect(rt5663->codec, 0);
switch (rt5663->codec_ver) {
case CODEC_VER_1:
report = rt5663_v2_jack_detect(rt5663->codec, 0);
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
report = rt5663_jack_detect(rt5663->codec, 0);
break;
default:
dev_err(codec->dev, "Unknown CODEC_TYPE\n");
dev_err(codec->dev, "Unknown CODEC Version\n");
}
}
dev_dbg(codec->dev, "%s jack report: 0x%04x\n", __func__, report);
......@@ -1722,24 +1723,24 @@ static void rt5663_jack_detect_work(struct work_struct *work)
static const struct snd_kcontrol_new rt5663_snd_controls[] = {
/* DAC Digital Volume */
SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL,
RT5668_DAC_L1_VOL_SHIFT + 1, RT5668_DAC_R1_VOL_SHIFT + 1,
RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1,
87, 0, dac_vol_tlv),
/* ADC Digital Volume Control */
SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL,
RT5668_ADC_L_MUTE_SHIFT, RT5668_ADC_R_MUTE_SHIFT, 1, 1),
RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1),
SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL,
RT5668_ADC_L_VOL_SHIFT + 1, RT5668_ADC_R_VOL_SHIFT + 1,
RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1,
63, 0, adc_vol_tlv),
};
static const struct snd_kcontrol_new rt5668_specific_controls[] = {
static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = {
/* Headphone Output Volume */
SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE,
RT5663_HP_RCH_DRE, RT5668_GAIN_HP_SHIFT, 15, 1,
rt5668_hp_vol_tlv),
RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1,
rt5663_v2_hp_vol_tlv),
/* Mic Boost Volume */
SOC_SINGLE_TLV("IN1 Capture Volume", RT5668_AEC_BST,
RT5668_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST,
RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
};
static const struct snd_kcontrol_new rt5663_specific_controls[] = {
......@@ -1775,15 +1776,15 @@ static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w,
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
if (rt5663->codec_type == CODEC_TYPE_RT5668) {
if (rt5663->codec_ver == CODEC_VER_1) {
switch (w->shift) {
case RT5668_ADC_STO1_ASRC_SHIFT:
reg = RT5668_ASRC_3;
shift = RT5668_AD_STO1_TRACK_SHIFT;
case RT5663_ADC_STO1_ASRC_SHIFT:
reg = RT5663_ASRC_3;
shift = RT5663_V2_AD_STO1_TRACK_SHIFT;
break;
case RT5668_DAC_STO1_ASRC_SHIFT:
case RT5663_DAC_STO1_ASRC_SHIFT:
reg = RT5663_ASRC_2;
shift = RT5668_DA_STO1_TRACK_SHIFT;
shift = RT5663_DA_STO1_TRACK_SHIFT;
break;
default:
return 0;
......@@ -1820,17 +1821,17 @@ static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
da_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
RT5663_DA_STO1_TRACK_MASK) ? 1 : 0;
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
ad_asrc_en = (snd_soc_read(codec, RT5668_ASRC_3) &
RT5668_AD_STO1_TRACK_MASK) ? 1 : 0;
switch (rt5663->codec_ver) {
case CODEC_VER_1:
ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_3) &
RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0;
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
RT5663_AD_STO1_TRACK_MASK) ? 1 : 0;
break;
default:
dev_err(codec->dev, "Unknown CODEC_TYPE\n");
dev_err(codec->dev, "Unknown CODEC Version\n");
return 1;
}
......@@ -1849,7 +1850,7 @@ static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
* @filter_mask: mask of filters.
* @clk_src: clock source
*
* The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5668 can
* The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can
* only support standard 32fs or 64fs i2s format, ASRC should be enabled to
* support special i2s clock format such as Intel's 100fs(100 * sampling rate).
* ASRC function will track i2s clock and generate a corresponding system clock
......@@ -1860,7 +1861,7 @@ static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
unsigned int filter_mask, unsigned int clk_src)
{
struct rt5663_priv *rt5668 = snd_soc_codec_get_drvdata(codec);
struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
unsigned int asrc2_mask = 0;
unsigned int asrc2_value = 0;
unsigned int asrc3_mask = 0;
......@@ -1876,22 +1877,22 @@ int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
}
if (filter_mask & RT5663_DA_STEREO_FILTER) {
asrc2_mask |= RT5668_DA_STO1_TRACK_MASK;
asrc2_value |= clk_src << RT5668_DA_STO1_TRACK_SHIFT;
asrc2_mask |= RT5663_DA_STO1_TRACK_MASK;
asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT;
}
if (filter_mask & RT5663_AD_STEREO_FILTER) {
switch (rt5668->codec_type) {
case CODEC_TYPE_RT5668:
asrc3_mask |= RT5668_AD_STO1_TRACK_MASK;
asrc3_value |= clk_src << RT5668_AD_STO1_TRACK_SHIFT;
switch (rt5663->codec_ver) {
case CODEC_VER_1:
asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK;
asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT;
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
asrc2_mask |= RT5663_AD_STO1_TRACK_MASK;
asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT;
break;
default:
dev_err(codec->dev, "Unknown CODEC_TYPE\n");
dev_err(codec->dev, "Unknown CODEC Version\n");
}
}
......@@ -1900,7 +1901,7 @@ int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
asrc2_value);
if (asrc3_mask)
snd_soc_update_bits(codec, RT5668_ASRC_3, asrc3_mask,
snd_soc_update_bits(codec, RT5663_ASRC_3, asrc3_mask,
asrc3_value);
return 0;
......@@ -1908,82 +1909,82 @@ int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src);
/* Analog Mixer */
static const struct snd_kcontrol_new rt5668_recmix1l[] = {
SOC_DAPM_SINGLE("BST2 Switch", RT5668_RECMIX1L,
RT5668_RECMIX1L_BST2_SHIFT, 1, 1),
SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5668_RECMIX1L,
RT5668_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
static const struct snd_kcontrol_new rt5663_recmix1l[] = {
SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L,
RT5663_RECMIX1L_BST2_SHIFT, 1, 1),
SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L,
RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5668_recmix1r[] = {
SOC_DAPM_SINGLE("BST2 Switch", RT5668_RECMIX1R,
RT5668_RECMIX1R_BST2_SHIFT, 1, 1),
static const struct snd_kcontrol_new rt5663_recmix1r[] = {
SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R,
RT5663_RECMIX1R_BST2_SHIFT, 1, 1),
};
/* Digital Mixer */
static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
RT5668_M_STO1_ADC_L1_SHIFT, 1, 1),
RT5663_M_STO1_ADC_L1_SHIFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
RT5668_M_STO1_ADC_L2_SHIFT, 1, 1),
RT5663_M_STO1_ADC_L2_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5668_sto1_adc_r_mix[] = {
static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = {
SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
RT5668_M_STO1_ADC_R1_SHIFT, 1, 1),
RT5663_M_STO1_ADC_R1_SHIFT, 1, 1),
SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
RT5668_M_STO1_ADC_R2_SHIFT, 1, 1),
RT5663_M_STO1_ADC_R2_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5663_adda_l_mix[] = {
SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER,
RT5668_M_ADCMIX_L_SHIFT, 1, 1),
RT5663_M_ADCMIX_L_SHIFT, 1, 1),
SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER,
RT5668_M_DAC1_L_SHIFT, 1, 1),
RT5663_M_DAC1_L_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER,
RT5668_M_ADCMIX_R_SHIFT, 1, 1),
RT5663_M_ADCMIX_R_SHIFT, 1, 1),
SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER,
RT5668_M_DAC1_R_SHIFT, 1, 1),
RT5663_M_DAC1_R_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
RT5668_M_DAC_L1_STO_L_SHIFT, 1, 1),
RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1),
SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
RT5668_M_DAC_R1_STO_L_SHIFT, 1, 1),
RT5663_M_DAC_R1_STO_L_SHIFT, 1, 1),
};
static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
RT5668_M_DAC_L1_STO_R_SHIFT, 1, 1),
RT5663_M_DAC_L1_STO_R_SHIFT, 1, 1),
SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
RT5668_M_DAC_R1_STO_R_SHIFT, 1, 1),
RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1),
};
/* Out Switch */
static const struct snd_kcontrol_new rt5668_hpo_switch =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_AMP_2,
RT5668_EN_DAC_HPO_SHIFT, 1, 0);
static const struct snd_kcontrol_new rt5663_hpo_switch =
SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2,
RT5663_EN_DAC_HPO_SHIFT, 1, 0);
/* Stereo ADC source */
static const char * const rt5668_sto1_adc_src[] = {
static const char * const rt5663_sto1_adc_src[] = {
"ADC L", "ADC R"
};
static SOC_ENUM_SINGLE_DECL(rt5668_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
RT5668_STO1_ADC_L_SRC_SHIFT, rt5668_sto1_adc_src);
static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src);
static const struct snd_kcontrol_new rt5668_sto1_adcl_mux =
SOC_DAPM_ENUM("STO1 ADC L Mux", rt5668_sto1_adcl_enum);
static const struct snd_kcontrol_new rt5663_sto1_adcl_mux =
SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum);
static SOC_ENUM_SINGLE_DECL(rt5668_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
RT5668_STO1_ADC_R_SRC_SHIFT, rt5668_sto1_adc_src);
static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src);
static const struct snd_kcontrol_new rt5668_sto1_adcr_mux =
SOC_DAPM_ENUM("STO1 ADC R Mux", rt5668_sto1_adcr_enum);
static const struct snd_kcontrol_new rt5663_sto1_adcr_mux =
SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum);
/* RT5663: Analog DACL1 input source */
static const char * const rt5663_alg_dacl_src[] = {
......@@ -2015,12 +2016,12 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
switch (event) {
case SND_SOC_DAPM_POST_PMU:
if (rt5663->codec_type == CODEC_TYPE_RT5668) {
if (rt5663->codec_ver == CODEC_VER_1) {
snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
RT5668_SEL_PM_HP_SHIFT, RT5668_SEL_PM_HP_HIGH);
RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH);
snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
RT5668_HP_SIG_SRC1_MASK,
RT5668_HP_SIG_SRC1_SILENCE);
RT5663_HP_SIG_SRC1_MASK,
RT5663_HP_SIG_SRC1_SILENCE);
} else {
snd_soc_write(codec, RT5663_DEPOP_2, 0x3003);
snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x000b,
......@@ -2028,7 +2029,7 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030,
0x0030);
snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
RT5668_OVCD_HP_MASK, RT5668_OVCD_HP_DIS);
RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS);
snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_2, 0x1371);
snd_soc_write(codec, RT5663_HP_BIAS, 0xabba);
snd_soc_write(codec, RT5663_CHARGE_PUMP_1, 0x2224);
......@@ -2041,14 +2042,14 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
break;
case SND_SOC_DAPM_PRE_PMD:
if (rt5663->codec_type == CODEC_TYPE_RT5668) {
if (rt5663->codec_ver == CODEC_VER_1) {
snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
RT5668_HP_SIG_SRC1_MASK,
RT5668_HP_SIG_SRC1_REG);
RT5663_HP_SIG_SRC1_MASK,
RT5663_HP_SIG_SRC1_REG);
} else {
snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0x0);
snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
RT5668_OVCD_HP_MASK, RT5668_OVCD_HP_EN);
RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN);
snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0x0);
snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x000b,
0x000b);
......@@ -2062,7 +2063,7 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
return 0;
}
static int rt5668_bst2_power(struct snd_soc_dapm_widget *w,
static int rt5663_bst2_power(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
......@@ -2070,13 +2071,13 @@ static int rt5668_bst2_power(struct snd_soc_dapm_widget *w,
switch (event) {
case SND_SOC_DAPM_POST_PMU:
snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
RT5668_PWR_BST2_MASK | RT5668_PWR_BST2_OP_MASK,
RT5668_PWR_BST2 | RT5668_PWR_BST2_OP);
RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK,
RT5663_PWR_BST2 | RT5663_PWR_BST2_OP);
break;
case SND_SOC_DAPM_PRE_PMD:
snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
RT5668_PWR_BST2_MASK | RT5668_PWR_BST2_OP_MASK, 0);
RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0);
break;
default:
......@@ -2110,14 +2111,14 @@ static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w,
}
static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5668_PWR_PLL_SHIFT, 0,
SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0,
NULL, 0),
/* micbias */
SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2,
RT5668_PWR_MB1_SHIFT, 0),
RT5663_PWR_MB1_SHIFT, 0),
SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2,
RT5668_PWR_MB2_SHIFT, 0),
RT5663_PWR_MB2_SHIFT, 0),
/* Input Lines */
SND_SOC_DAPM_INPUT("IN1P"),
......@@ -2125,14 +2126,14 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
/* REC Mixer Power */
SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2,
RT5668_PWR_RECMIX1_SHIFT, 0, NULL, 0),
RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0),
/* ADCs */
SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1,
RT5668_PWR_ADC_L1_SHIFT, 0, NULL, 0),
RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC,
RT5668_CKGEN_ADCC_SHIFT, 0, NULL, 0),
RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0),
/* ADC Mixer */
SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM,
......@@ -2141,10 +2142,10 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
/* ADC Filter Power */
SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2,
RT5668_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
/* Digital Interface */
SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5668_PWR_I2S1_SHIFT, 0,
SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0,
NULL, 0),
SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
......@@ -2166,7 +2167,7 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
/* DAC Mixer */
SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2,
RT5668_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0,
rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)),
SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0,
......@@ -2174,9 +2175,9 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
/* DACs */
SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1,
RT5668_PWR_DAC_L1_SHIFT, 0, NULL, 0),
RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1,
RT5668_PWR_DAC_R1_SHIFT, 0, NULL, 0),
RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
......@@ -2189,21 +2190,21 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
SND_SOC_DAPM_OUTPUT("HPOR"),
};
static const struct snd_soc_dapm_widget rt5668_specific_dapm_widgets[] = {
static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = {
SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3,
RT5668_PWR_LDO2_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5668_PWR_VOL,
RT5668_PWR_MIC_DET_SHIFT, 0, NULL, 0),
RT5663_PWR_LDO2_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL,
RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1,
RT5668_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
/* ASRC */
SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
RT5668_I2S1_ASRC_SHIFT, 0, NULL, 0),
RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
RT5668_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
RT5668_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
/* Input Lines */
SND_SOC_DAPM_INPUT("IN2P"),
......@@ -2212,51 +2213,51 @@ static const struct snd_soc_dapm_widget rt5668_specific_dapm_widgets[] = {
/* Boost */
SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3,
RT5668_PWR_CBJ_SHIFT, 0, NULL, 0),
RT5663_PWR_CBJ_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0),
SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0,
rt5668_bst2_power, SND_SOC_DAPM_PRE_PMD |
rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD |
SND_SOC_DAPM_POST_PMU),
/* REC Mixer */
SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5668_recmix1l,
ARRAY_SIZE(rt5668_recmix1l)),
SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5668_recmix1r,
ARRAY_SIZE(rt5668_recmix1r)),
SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l,
ARRAY_SIZE(rt5663_recmix1l)),
SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r,
ARRAY_SIZE(rt5663_recmix1r)),
SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2,
RT5668_PWR_RECMIX2_SHIFT, 0, NULL, 0),
RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0),
/* ADC */
SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1,
RT5668_PWR_ADC_R1_SHIFT, 0, NULL, 0),
RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0),
/* ADC Mux */
SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER,
RT5668_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER,
RT5668_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER,
RT5668_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER,
RT5668_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0,
&rt5668_sto1_adcl_mux),
&rt5663_sto1_adcl_mux),
SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0,
&rt5668_sto1_adcr_mux),
&rt5663_sto1_adcr_mux),
/* ADC Mix */
SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0,
rt5668_sto1_adc_r_mix, ARRAY_SIZE(rt5668_sto1_adc_r_mix)),
rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)),
/* Analog DAC Clock */
SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L,
RT5668_CKGEN_DAC1_SHIFT, 0, NULL, 0),
RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0),
/* Headphone out */
SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
&rt5668_hpo_switch),
&rt5663_hpo_switch),
};
static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
......@@ -2267,7 +2268,7 @@ static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
/* LDO */
SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1,
RT5668_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
/* ASRC */
SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
......@@ -2341,7 +2342,7 @@ static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
{ "HP Amp", NULL, "DAC R" },
};
static const struct snd_soc_dapm_route rt5668_specific_dapm_routes[] = {
static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = {
{ "MICBIAS1", NULL, "LDO2" },
{ "MICBIAS2", NULL, "LDO2" },
......@@ -2440,26 +2441,26 @@ static int rt5663_hw_params(struct snd_pcm_substream *substream,
switch (params_width(params)) {
case 8:
val_len = RT5668_I2S_DL_8;
val_len = RT5663_I2S_DL_8;
break;
case 16:
val_len = RT5668_I2S_DL_16;
val_len = RT5663_I2S_DL_16;
break;
case 20:
val_len = RT5668_I2S_DL_20;
val_len = RT5663_I2S_DL_20;
break;
case 24:
val_len = RT5668_I2S_DL_24;
val_len = RT5663_I2S_DL_24;
break;
default:
return -EINVAL;
}
snd_soc_update_bits(codec, RT5663_I2S1_SDP,
RT5668_I2S_DL_MASK, val_len);
RT5663_I2S_DL_MASK, val_len);
snd_soc_update_bits(codec, RT5663_ADDA_CLK_1,
RT5668_I2S_PD1_MASK, pre_div << RT5668_I2S_PD1_SHIFT);
RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT);
return 0;
}
......@@ -2473,7 +2474,7 @@ static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
case SND_SOC_DAIFMT_CBM_CFM:
break;
case SND_SOC_DAIFMT_CBS_CFS:
reg_val |= RT5668_I2S_MS_S;
reg_val |= RT5663_I2S_MS_S;
break;
default:
return -EINVAL;
......@@ -2483,7 +2484,7 @@ static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
reg_val |= RT5668_I2S_BP_INV;
reg_val |= RT5663_I2S_BP_INV;
break;
default:
return -EINVAL;
......@@ -2493,20 +2494,20 @@ static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
case SND_SOC_DAIFMT_I2S:
break;
case SND_SOC_DAIFMT_LEFT_J:
reg_val |= RT5668_I2S_DF_LEFT;
reg_val |= RT5663_I2S_DF_LEFT;
break;
case SND_SOC_DAIFMT_DSP_A:
reg_val |= RT5668_I2S_DF_PCM_A;
reg_val |= RT5663_I2S_DF_PCM_A;
break;
case SND_SOC_DAIFMT_DSP_B:
reg_val |= RT5668_I2S_DF_PCM_B;
reg_val |= RT5663_I2S_DF_PCM_B;
break;
default:
return -EINVAL;
}
snd_soc_update_bits(codec, RT5663_I2S1_SDP, RT5668_I2S_MS_MASK |
RT5668_I2S_BP_MASK | RT5668_I2S_DF_MASK, reg_val);
snd_soc_update_bits(codec, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK |
RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val);
return 0;
}
......@@ -2535,7 +2536,7 @@ static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
return -EINVAL;
}
snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5668_SCLK_SRC_MASK,
snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
reg_val);
rt5663->sysclk = freq;
rt5663->sysclk_src = clk_id;
......@@ -2569,17 +2570,17 @@ static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
return 0;
}
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
mask = RT5668_PLL1_SRC_MASK;
shift = RT5668_PLL1_SRC_SHIFT;
switch (rt5663->codec_ver) {
case CODEC_VER_1:
mask = RT5663_V2_PLL1_SRC_MASK;
shift = RT5663_V2_PLL1_SRC_SHIFT;
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
mask = RT5663_PLL1_SRC_MASK;
shift = RT5663_PLL1_SRC_SHIFT;
break;
default:
dev_err(codec->dev, "Unknown CODEC_TYPE\n");
dev_err(codec->dev, "Unknown CODEC Version\n");
return -EINVAL;
}
......@@ -2607,10 +2608,10 @@ static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
pll_code.k_code);
snd_soc_write(codec, RT5663_PLL_1,
pll_code.n_code << RT5668_PLL_N_SHIFT | pll_code.k_code);
pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code);
snd_soc_write(codec, RT5663_PLL_2,
(pll_code.m_bp ? 0 : pll_code.m_code) << RT5668_PLL_M_SHIFT |
pll_code.m_bp << RT5668_PLL_M_BP_SHIFT);
(pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT |
pll_code.m_bp << RT5663_PLL_M_BP_SHIFT);
rt5663->pll_in = freq_in;
rt5663->pll_out = freq_out;
......@@ -2627,20 +2628,20 @@ static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
unsigned int val = 0, reg;
if (rx_mask || tx_mask)
val |= RT5668_TDM_MODE_TDM;
val |= RT5663_TDM_MODE_TDM;
switch (slots) {
case 4:
val |= RT5668_TDM_IN_CH_4;
val |= RT5668_TDM_OUT_CH_4;
val |= RT5663_TDM_IN_CH_4;
val |= RT5663_TDM_OUT_CH_4;
break;
case 6:
val |= RT5668_TDM_IN_CH_6;
val |= RT5668_TDM_OUT_CH_6;
val |= RT5663_TDM_IN_CH_6;
val |= RT5663_TDM_OUT_CH_6;
break;
case 8:
val |= RT5668_TDM_IN_CH_8;
val |= RT5668_TDM_OUT_CH_8;
val |= RT5663_TDM_IN_CH_8;
val |= RT5663_TDM_OUT_CH_8;
break;
case 2:
break;
......@@ -2650,16 +2651,16 @@ static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
switch (slot_width) {
case 20:
val |= RT5668_TDM_IN_LEN_20;
val |= RT5668_TDM_OUT_LEN_20;
val |= RT5663_TDM_IN_LEN_20;
val |= RT5663_TDM_OUT_LEN_20;
break;
case 24:
val |= RT5668_TDM_IN_LEN_24;
val |= RT5668_TDM_OUT_LEN_24;
val |= RT5663_TDM_IN_LEN_24;
val |= RT5663_TDM_OUT_LEN_24;
break;
case 32:
val |= RT5668_TDM_IN_LEN_32;
val |= RT5668_TDM_OUT_LEN_32;
val |= RT5663_TDM_IN_LEN_32;
val |= RT5663_TDM_OUT_LEN_32;
break;
case 16:
break;
......@@ -2667,21 +2668,21 @@ static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
return -EINVAL;
}
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
switch (rt5663->codec_ver) {
case CODEC_VER_1:
reg = RT5663_TDM_2;
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
reg = RT5663_TDM_1;
break;
default:
dev_err(codec->dev, "Unknown CODEC_TYPE\n");
dev_err(codec->dev, "Unknown CODEC Version\n");
return -EINVAL;
}
snd_soc_update_bits(codec, reg, RT5668_TDM_MODE_MASK |
RT5668_TDM_IN_CH_MASK | RT5668_TDM_OUT_CH_MASK |
RT5668_TDM_IN_LEN_MASK | RT5668_TDM_OUT_LEN_MASK, val);
snd_soc_update_bits(codec, reg, RT5663_TDM_MODE_MASK |
RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK |
RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val);
return 0;
}
......@@ -2694,8 +2695,8 @@ static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
dev_dbg(codec->dev, "%s ratio = %d\n", __func__, ratio);
if (rt5663->codec_type == CODEC_TYPE_RT5668)
reg = RT5668_TDM_8;
if (rt5663->codec_ver == CODEC_VER_1)
reg = RT5663_TDM_9;
else
reg = RT5663_TDM_5;
......@@ -2736,47 +2737,47 @@ static int rt5663_set_bias_level(struct snd_soc_codec *codec,
switch (level) {
case SND_SOC_BIAS_ON:
snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
RT5668_PWR_FV1_MASK | RT5668_PWR_FV2_MASK,
RT5668_PWR_FV1 | RT5668_PWR_FV2);
RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
RT5663_PWR_FV1 | RT5663_PWR_FV2);
break;
case SND_SOC_BIAS_PREPARE:
if (rt5663->codec_type == CODEC_TYPE_RT5668) {
if (rt5663->codec_ver == CODEC_VER_1) {
snd_soc_update_bits(codec, RT5663_DIG_MISC,
RT5668_DIG_GATE_CTRL_MASK,
RT5668_DIG_GATE_CTRL_EN);
RT5663_DIG_GATE_CTRL_MASK,
RT5663_DIG_GATE_CTRL_EN);
snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
RT5668_EN_ANA_CLK_DET_MASK |
RT5668_PWR_CLK_DET_MASK,
RT5668_EN_ANA_CLK_DET_AUTO |
RT5668_PWR_CLK_DET_EN);
RT5663_EN_ANA_CLK_DET_MASK |
RT5663_PWR_CLK_DET_MASK,
RT5663_EN_ANA_CLK_DET_AUTO |
RT5663_PWR_CLK_DET_EN);
}
break;
case SND_SOC_BIAS_STANDBY:
if (rt5663->codec_type == CODEC_TYPE_RT5668)
if (rt5663->codec_ver == CODEC_VER_1)
snd_soc_update_bits(codec, RT5663_DIG_MISC,
RT5668_DIG_GATE_CTRL_MASK,
RT5668_DIG_GATE_CTRL_DIS);
RT5663_DIG_GATE_CTRL_MASK,
RT5663_DIG_GATE_CTRL_DIS);
snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
RT5668_PWR_VREF1_MASK | RT5668_PWR_VREF2_MASK |
RT5668_PWR_FV1_MASK | RT5668_PWR_FV2_MASK |
RT5668_PWR_MB_MASK, RT5668_PWR_VREF1 |
RT5668_PWR_VREF2 | RT5668_PWR_MB);
RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK |
RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 |
RT5663_PWR_VREF2 | RT5663_PWR_MB);
usleep_range(10000, 10005);
if (rt5663->codec_type == CODEC_TYPE_RT5668) {
if (rt5663->codec_ver == CODEC_VER_1) {
snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
RT5668_EN_ANA_CLK_DET_MASK |
RT5668_PWR_CLK_DET_MASK,
RT5668_EN_ANA_CLK_DET_DIS |
RT5668_PWR_CLK_DET_DIS);
RT5663_EN_ANA_CLK_DET_MASK |
RT5663_PWR_CLK_DET_MASK,
RT5663_EN_ANA_CLK_DET_DIS |
RT5663_PWR_CLK_DET_DIS);
}
break;
case SND_SOC_BIAS_OFF:
snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
RT5668_PWR_VREF1_MASK | RT5668_PWR_VREF2_MASK |
RT5668_PWR_FV1 | RT5668_PWR_FV2, 0x0);
RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
RT5663_PWR_FV1 | RT5663_PWR_FV2, 0x0);
break;
default:
......@@ -2793,18 +2794,18 @@ static int rt5663_probe(struct snd_soc_codec *codec)
rt5663->codec = codec;
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
switch (rt5663->codec_ver) {
case CODEC_VER_1:
snd_soc_dapm_new_controls(dapm,
rt5668_specific_dapm_widgets,
ARRAY_SIZE(rt5668_specific_dapm_widgets));
rt5663_v2_specific_dapm_widgets,
ARRAY_SIZE(rt5663_v2_specific_dapm_widgets));
snd_soc_dapm_add_routes(dapm,
rt5668_specific_dapm_routes,
ARRAY_SIZE(rt5668_specific_dapm_routes));
snd_soc_add_codec_controls(codec, rt5668_specific_controls,
ARRAY_SIZE(rt5668_specific_controls));
rt5663_v2_specific_dapm_routes,
ARRAY_SIZE(rt5663_v2_specific_dapm_routes));
snd_soc_add_codec_controls(codec, rt5663_v2_specific_controls,
ARRAY_SIZE(rt5663_v2_specific_controls));
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
snd_soc_dapm_new_controls(dapm,
rt5663_specific_dapm_widgets,
ARRAY_SIZE(rt5663_specific_dapm_widgets));
......@@ -2905,16 +2906,16 @@ static struct snd_soc_codec_driver soc_codec_dev_rt5663 = {
}
};
static const struct regmap_config rt5668_regmap = {
static const struct regmap_config rt5663_v2_regmap = {
.reg_bits = 16,
.val_bits = 16,
.use_single_rw = true,
.max_register = 0x07fa,
.volatile_reg = rt5668_volatile_register,
.readable_reg = rt5668_readable_register,
.volatile_reg = rt5663_v2_volatile_register,
.readable_reg = rt5663_v2_readable_register,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = rt5668_reg,
.num_reg_defaults = ARRAY_SIZE(rt5668_reg),
.reg_defaults = rt5663_v2_reg,
.num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg),
};
static const struct regmap_config rt5663_regmap = {
......@@ -2939,7 +2940,6 @@ static const struct regmap_config temp_regmap = {
};
static const struct i2c_device_id rt5663_i2c_id[] = {
{ "rt5668", 0 },
{ "rt5663", 0 },
{}
};
......@@ -2947,7 +2947,6 @@ MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id rt5663_of_match[] = {
{ .compatible = "realtek,rt5668", },
{ .compatible = "realtek,rt5663", },
{},
};
......@@ -2956,80 +2955,79 @@ MODULE_DEVICE_TABLE(of, rt5663_of_match);
#ifdef CONFIG_ACPI
static struct acpi_device_id rt5663_acpi_match[] = {
{ "10EC5668", 0},
{ "10EC5663", 0},
{},
};
MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match);
#endif
static void rt5668_calibrate(struct rt5663_priv *rt5668)
static void rt5663_v2_calibrate(struct rt5663_priv *rt5663)
{
regmap_write(rt5668->regmap, RT5663_BIAS_CUR_8, 0xa402);
regmap_write(rt5668->regmap, RT5663_PWR_DIG_1, 0x0100);
regmap_write(rt5668->regmap, RT5663_RECMIX, 0x4040);
regmap_write(rt5668->regmap, RT5663_DIG_MISC, 0x0001);
regmap_write(rt5668->regmap, RT5663_RC_CLK, 0x0380);
regmap_write(rt5668->regmap, RT5663_GLB_CLK, 0x8000);
regmap_write(rt5668->regmap, RT5663_ADDA_CLK_1, 0x1000);
regmap_write(rt5668->regmap, RT5663_CHOP_DAC_L, 0x3030);
regmap_write(rt5668->regmap, RT5663_CALIB_ADC, 0x3c05);
regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xa23e);
regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100);
regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040);
regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001);
regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030);
regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e);
msleep(40);
regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xf23e);
regmap_write(rt5668->regmap, RT5663_HP_CALIB_2, 0x0321);
regmap_write(rt5668->regmap, RT5663_HP_CALIB_1, 0xfc00);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00);
msleep(500);
}
static void rt5663_calibrate(struct rt5663_priv *rt5668)
static void rt5663_calibrate(struct rt5663_priv *rt5663)
{
int value, count;
regmap_write(rt5668->regmap, RT5663_RC_CLK, 0x0280);
regmap_write(rt5668->regmap, RT5663_GLB_CLK, 0x8000);
regmap_write(rt5668->regmap, RT5663_DIG_MISC, 0x8001);
regmap_write(rt5668->regmap, RT5663_VREF_RECMIX, 0x0032);
regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xa2be);
regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0280);
regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001);
regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa2be);
msleep(20);
regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xf2be);
regmap_write(rt5668->regmap, RT5663_PWR_DIG_2, 0x8400);
regmap_write(rt5668->regmap, RT5663_CHOP_ADC, 0x3000);
regmap_write(rt5668->regmap, RT5663_DEPOP_1, 0x003b);
regmap_write(rt5668->regmap, RT5663_PWR_DIG_1, 0x8df8);
regmap_write(rt5668->regmap, RT5663_PWR_ANLG_2, 0x0003);
regmap_write(rt5668->regmap, RT5663_PWR_ANLG_3, 0x018c);
regmap_write(rt5668->regmap, RT5663_ADDA_CLK_1, 0x1111);
regmap_write(rt5668->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
regmap_write(rt5668->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
regmap_write(rt5668->regmap, RT5663_DEPOP_2, 0x3003);
regmap_write(rt5668->regmap, RT5663_DEPOP_1, 0x003b);
regmap_write(rt5668->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
regmap_write(rt5668->regmap, RT5663_HP_CHARGE_PUMP_2, 0x1371);
regmap_write(rt5668->regmap, RT5663_DACREF_LDO, 0x3b0b);
regmap_write(rt5668->regmap, RT5663_STO_DAC_MIXER, 0x2080);
regmap_write(rt5668->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
regmap_write(rt5668->regmap, RT5663_HP_BIAS, 0xabba);
regmap_write(rt5668->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
regmap_write(rt5668->regmap, RT5663_HP_OUT_EN, 0x8088);
regmap_write(rt5668->regmap, RT5663_STO_DRE_9, 0x0017);
regmap_write(rt5668->regmap, RT5663_STO_DRE_10, 0x0017);
regmap_write(rt5668->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
regmap_write(rt5668->regmap, RT5663_RECMIX, 0x0005);
regmap_write(rt5668->regmap, RT5663_ADDA_RST, 0xc000);
regmap_write(rt5668->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
regmap_write(rt5668->regmap, RT5663_HP_CALIB_2, 0x00c9);
regmap_write(rt5668->regmap, RT5663_DUMMY_1, 0x004c);
regmap_write(rt5668->regmap, RT5663_ANA_BIAS_CUR_1, 0x7766);
regmap_write(rt5668->regmap, RT5663_BIAS_CUR_8, 0x4702);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf2be);
regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400);
regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000);
regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0003);
regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c);
regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1111);
regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003);
regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_2, 0x1371);
regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b);
regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x2080);
regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xabba);
regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088);
regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017);
regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017);
regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005);
regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000);
regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9);
regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c);
regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x7766);
regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4702);
msleep(200);
regmap_write(rt5668->regmap, RT5663_HP_CALIB_1, 0x0069);
regmap_write(rt5668->regmap, RT5663_HP_CALIB_3, 0x06c2);
regmap_write(rt5668->regmap, RT5663_HP_CALIB_1_1, 0x7b00);
regmap_write(rt5668->regmap, RT5663_HP_CALIB_1_1, 0xfb00);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06c2);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x7b00);
regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xfb00);
count = 0;
while (true) {
regmap_read(rt5668->regmap, RT5663_HP_CALIB_1_1, &value);
regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
if (value & 0x8000)
usleep_range(10000, 10005);
else
......@@ -3066,17 +3064,17 @@ static int rt5663_i2c_probe(struct i2c_client *i2c,
}
regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
switch (val) {
case RT5668_DEVICE_ID:
rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5668_regmap);
rt5663->codec_type = CODEC_TYPE_RT5668;
case RT5663_DEVICE_ID_2:
rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap);
rt5663->codec_ver = CODEC_VER_1;
break;
case RT5663_DEVICE_ID:
case RT5663_DEVICE_ID_1:
rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap);
rt5663->codec_type = CODEC_TYPE_RT5663;
rt5663->codec_ver = CODEC_VER_0;
break;
default:
dev_err(&i2c->dev,
"Device with ID register %#x is not rt5663 or rt5668\n",
"Device with ID register %#x is not rt5663\n",
val);
return -ENODEV;
}
......@@ -3091,11 +3089,11 @@ static int rt5663_i2c_probe(struct i2c_client *i2c,
/* reset and calibrate */
regmap_write(rt5663->regmap, RT5663_RESET, 0);
regcache_cache_bypass(rt5663->regmap, true);
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
rt5668_calibrate(rt5663);
switch (rt5663->codec_ver) {
case CODEC_VER_1:
rt5663_v2_calibrate(rt5663);
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
rt5663_calibrate(rt5663);
break;
default:
......@@ -3106,44 +3104,44 @@ static int rt5663_i2c_probe(struct i2c_client *i2c,
dev_dbg(&i2c->dev, "calibrate done\n");
/* GPIO1 as IRQ */
regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5668_GP1_PIN_MASK,
RT5668_GP1_PIN_IRQ);
regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK,
RT5663_GP1_PIN_IRQ);
/* 4btn inline command debounce */
regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5,
RT5668_4BTN_CLK_DEB_MASK, RT5668_4BTN_CLK_DEB_65MS);
RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS);
switch (rt5663->codec_type) {
case CODEC_TYPE_RT5668:
switch (rt5663->codec_ver) {
case CODEC_VER_1:
regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
/* JD1 */
regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
RT5668_IRQ_POW_SAV_MASK | RT5668_IRQ_POW_SAV_JD1_MASK,
RT5668_IRQ_POW_SAV_EN | RT5668_IRQ_POW_SAV_JD1_EN);
RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK,
RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN);
regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2,
RT5668_PWR_JD1_MASK, RT5668_PWR_JD1);
RT5663_PWR_JD1_MASK, RT5663_PWR_JD1);
regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
RT5668_EN_CB_JD_MASK, RT5668_EN_CB_JD_EN);
RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN);
regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2,
RT5668_HP_SIG_SRC1_MASK, RT5668_HP_SIG_SRC1_REG);
RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG);
regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
RT5668_VREF_BIAS_MASK | RT5668_CBJ_DET_MASK |
RT5668_DET_TYPE_MASK, RT5668_VREF_BIAS_REG |
RT5668_CBJ_DET_EN | RT5668_DET_TYPE_QFN);
RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK |
RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG |
RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN);
/* Set GPIO4 and GPIO8 as input for combo jack */
regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
RT5668_GP4_PIN_CONF_MASK, RT5668_GP4_PIN_CONF_INPUT);
regmap_update_bits(rt5663->regmap, RT5668_GPIO_3,
RT5668_GP8_PIN_CONF_MASK, RT5668_GP8_PIN_CONF_INPUT);
RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT);
regmap_update_bits(rt5663->regmap, RT5663_GPIO_3,
RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT);
regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1,
RT5668_LDO1_DVO_MASK | RT5668_AMP_HP_MASK,
RT5668_LDO1_DVO_0_9V | RT5668_AMP_HP_3X);
RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK,
RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
break;
case CODEC_TYPE_RT5663:
case CODEC_VER_0:
regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC,
RT5668_DIG_GATE_CTRL_MASK, RT5668_DIG_GATE_CTRL_EN);
RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
RT5668_IRQ_POW_SAV_MASK, RT5668_IRQ_POW_SAV_EN);
RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
regmap_update_bits(rt5663->regmap, RT5663_GPIO_1,
......
sound/soc/codecs/rt5663.h
View file @ 73444723
......@@ -18,655 +18,652 @@
#define RT5663_VENDOR_ID_1 0x00fe
#define RT5663_VENDOR_ID_2 0x00ff
#define RT5668_LOUT_CTRL 0x0001
#define RT5668_HP_AMP_2 0x0003
#define RT5668_MONO_OUT 0x0004
#define RT5668_MONO_GAIN 0x0007
#define RT5668_AEC_BST 0x000b
#define RT5668_IN1_IN2 0x000c
#define RT5668_IN3_IN4 0x000d
#define RT5668_INL1_INR1 0x000f
#define RT5668_CBJ_TYPE_2 0x0011
#define RT5668_CBJ_TYPE_3 0x0012
#define RT5668_CBJ_TYPE_4 0x0013
#define RT5668_CBJ_TYPE_5 0x0014
#define RT5668_CBJ_TYPE_8 0x0017
#define RT5663_LOUT_CTRL 0x0001
#define RT5663_HP_AMP_2 0x0003
#define RT5663_MONO_OUT 0x0004
#define RT5663_MONO_GAIN 0x0007
#define RT5663_AEC_BST 0x000b
#define RT5663_IN1_IN2 0x000c
#define RT5663_IN3_IN4 0x000d
#define RT5663_INL1_INR1 0x000f
#define RT5663_CBJ_TYPE_2 0x0011
#define RT5663_CBJ_TYPE_3 0x0012
#define RT5663_CBJ_TYPE_4 0x0013
#define RT5663_CBJ_TYPE_5 0x0014
#define RT5663_CBJ_TYPE_8 0x0017
/* I/O - ADC/DAC/DMIC */
#define RT5668_DAC3_DIG_VOL 0x001a
#define RT5668_DAC3_CTRL 0x001b
#define RT5668_MONO_ADC_DIG_VOL 0x001d
#define RT5668_STO2_ADC_DIG_VOL 0x001e
#define RT5668_MONO_ADC_BST_GAIN 0x0020
#define RT5668_STO2_ADC_BST_GAIN 0x0021
#define RT5668_SIDETONE_CTRL 0x0024
#define RT5663_DAC3_DIG_VOL 0x001a
#define RT5663_DAC3_CTRL 0x001b
#define RT5663_MONO_ADC_DIG_VOL 0x001d
#define RT5663_STO2_ADC_DIG_VOL 0x001e
#define RT5663_MONO_ADC_BST_GAIN 0x0020
#define RT5663_STO2_ADC_BST_GAIN 0x0021
#define RT5663_SIDETONE_CTRL 0x0024
/* Mixer - D-D */
#define RT5668_MONO1_ADC_MIXER 0x0027
#define RT5668_STO2_ADC_MIXER 0x0028
#define RT5668_MONO_DAC_MIXER 0x002b
#define RT5668_DAC2_SRC_CTRL 0x002e
#define RT5668_IF_3_4_DATA_CTL 0x002f
#define RT5668_IF_5_DATA_CTL 0x0030
#define RT5668_PDM_OUT_CTL 0x0031
#define RT5668_PDM_I2C_DATA_CTL1 0x0032
#define RT5668_PDM_I2C_DATA_CTL2 0x0033
#define RT5668_PDM_I2C_DATA_CTL3 0x0034
#define RT5668_PDM_I2C_DATA_CTL4 0x0035
#define RT5663_MONO1_ADC_MIXER 0x0027
#define RT5663_STO2_ADC_MIXER 0x0028
#define RT5663_MONO_DAC_MIXER 0x002b
#define RT5663_DAC2_SRC_CTRL 0x002e
#define RT5663_IF_3_4_DATA_CTL 0x002f
#define RT5663_IF_5_DATA_CTL 0x0030
#define RT5663_PDM_OUT_CTL 0x0031
#define RT5663_PDM_I2C_DATA_CTL1 0x0032
#define RT5663_PDM_I2C_DATA_CTL2 0x0033
#define RT5663_PDM_I2C_DATA_CTL3 0x0034
#define RT5663_PDM_I2C_DATA_CTL4 0x0035
/*Mixer - Analog*/
#define RT5668_RECMIX1_NEW 0x003a
#define RT5668_RECMIX1L_0 0x003b
#define RT5668_RECMIX1L 0x003c
#define RT5668_RECMIX1R_0 0x003d
#define RT5668_RECMIX1R 0x003e
#define RT5668_RECMIX2_NEW 0x003f
#define RT5668_RECMIX2_L_2 0x0041
#define RT5668_RECMIX2_R 0x0042
#define RT5668_RECMIX2_R_2 0x0043
#define RT5668_CALIB_REC_LR 0x0044
#define RT5668_ALC_BK_GAIN 0x0049
#define RT5668_MONOMIX_GAIN 0x004a
#define RT5668_MONOMIX_IN_GAIN 0x004b
#define RT5668_OUT_MIXL_GAIN 0x004d
#define RT5668_OUT_LMIX_IN_GAIN 0x004e
#define RT5668_OUT_RMIX_IN_GAIN 0x004f
#define RT5668_OUT_RMIX_IN_GAIN1 0x0050
#define RT5668_LOUT_MIXER_CTRL 0x0052
#define RT5663_RECMIX1_NEW 0x003a
#define RT5663_RECMIX1L_0 0x003b
#define RT5663_RECMIX1L 0x003c
#define RT5663_RECMIX1R_0 0x003d
#define RT5663_RECMIX1R 0x003e
#define RT5663_RECMIX2_NEW 0x003f
#define RT5663_RECMIX2_L_2 0x0041
#define RT5663_RECMIX2_R 0x0042
#define RT5663_RECMIX2_R_2 0x0043
#define RT5663_CALIB_REC_LR 0x0044
#define RT5663_ALC_BK_GAIN 0x0049
#define RT5663_MONOMIX_GAIN 0x004a
#define RT5663_MONOMIX_IN_GAIN 0x004b
#define RT5663_OUT_MIXL_GAIN 0x004d
#define RT5663_OUT_LMIX_IN_GAIN 0x004e
#define RT5663_OUT_RMIX_IN_GAIN 0x004f
#define RT5663_OUT_RMIX_IN_GAIN1 0x0050
#define RT5663_LOUT_MIXER_CTRL 0x0052
/* Power */
#define RT5668_PWR_VOL 0x0067
#define RT5663_PWR_VOL 0x0067
#define RT5668_ADCDAC_RST 0x006d
#define RT5663_ADCDAC_RST 0x006d
/* Format - ADC/DAC */
#define RT5668_I2S34_SDP 0x0071
#define RT5668_I2S5_SDP 0x0072
/* Format - TDM Control */
#define RT5668_TDM_5 0x007c
#define RT5668_TDM_6 0x007d
#define RT5668_TDM_7 0x007e
#define RT5668_TDM_8 0x007f
#define RT5663_I2S34_SDP 0x0071
#define RT5663_I2S5_SDP 0x0072
/* Function - Analog */
#define RT5668_ASRC_3 0x0085
#define RT5668_ASRC_6 0x0088
#define RT5668_ASRC_7 0x0089
#define RT5668_PLL_TRK_13 0x0099
#define RT5668_I2S_M_CLK_CTL 0x00a0
#define RT5668_FDIV_I2S34_M_CLK 0x00a1
#define RT5668_FDIV_I2S34_M_CLK2 0x00a2
#define RT5668_FDIV_I2S5_M_CLK 0x00a3
#define RT5668_FDIV_I2S5_M_CLK2 0x00a4
#define RT5663_ASRC_3 0x0085
#define RT5663_ASRC_6 0x0088
#define RT5663_ASRC_7 0x0089
#define RT5663_PLL_TRK_13 0x0099
#define RT5663_I2S_M_CLK_CTL 0x00a0
#define RT5663_FDIV_I2S34_M_CLK 0x00a1
#define RT5663_FDIV_I2S34_M_CLK2 0x00a2
#define RT5663_FDIV_I2S5_M_CLK 0x00a3
#define RT5663_FDIV_I2S5_M_CLK2 0x00a4
/* Function - Digital */
#define RT5668_IRQ_4 0x00b9
#define RT5668_GPIO_3 0x00c2
#define RT5668_GPIO_4 0x00c3
#define RT5668_GPIO_STA 0x00c4
#define RT5668_HP_AMP_DET1 0x00d0
#define RT5668_HP_AMP_DET2 0x00d1
#define RT5668_HP_AMP_DET3 0x00d2
#define RT5668_MID_BD_HP_AMP 0x00d3
#define RT5668_LOW_BD_HP_AMP 0x00d4
#define RT5668_SOF_VOL_ZC2 0x00da
#define RT5668_ADC_STO2_ADJ1 0x00ee
#define RT5668_ADC_STO2_ADJ2 0x00ef
#define RT5663_V2_IRQ_4 0x00b9
#define RT5663_GPIO_3 0x00c2
#define RT5663_GPIO_4 0x00c3
#define RT5663_GPIO_STA2 0x00c4
#define RT5663_HP_AMP_DET1 0x00d0
#define RT5663_HP_AMP_DET2 0x00d1
#define RT5663_HP_AMP_DET3 0x00d2
#define RT5663_MID_BD_HP_AMP 0x00d3
#define RT5663_LOW_BD_HP_AMP 0x00d4
#define RT5663_SOF_VOL_ZC2 0x00da
#define RT5663_ADC_STO2_ADJ1 0x00ee
#define RT5663_ADC_STO2_ADJ2 0x00ef
/* General Control */
#define RT5668_A_JD_CTRL 0x00f0
#define RT5668_JD1_TRES_CTRL 0x00f1
#define RT5668_JD2_TRES_CTRL 0x00f2
#define RT5668_JD_CTRL2 0x00f7
#define RT5668_DUM_REG_2 0x00fb
#define RT5668_DUM_REG_3 0x00fc
#define RT5668_DACADC_DIG_VOL2 0x0101
#define RT5668_DIG_IN_PIN2 0x0133
#define RT5668_PAD_DRV_CTL1 0x0136
#define RT5668_SOF_RAM_DEPOP 0x0138
#define RT5668_VOL_TEST 0x013f
#define RT5668_TEST_MODE_3 0x0147
#define RT5668_TEST_MODE_4 0x0148
#define RT5668_MONO_DYNA_1 0x0170
#define RT5668_MONO_DYNA_2 0x0171
#define RT5668_MONO_DYNA_3 0x0172
#define RT5668_MONO_DYNA_4 0x0173
#define RT5668_MONO_DYNA_5 0x0174
#define RT5668_MONO_DYNA_6 0x0175
#define RT5668_STO1_SIL_DET 0x0190
#define RT5668_MONOL_SIL_DET 0x0191
#define RT5668_MONOR_SIL_DET 0x0192
#define RT5668_STO2_DAC_SIL 0x0193
#define RT5668_PWR_SAV_CTL1 0x0194
#define RT5668_PWR_SAV_CTL2 0x0195
#define RT5668_PWR_SAV_CTL3 0x0196
#define RT5668_PWR_SAV_CTL4 0x0197
#define RT5668_PWR_SAV_CTL5 0x0198
#define RT5668_PWR_SAV_CTL6 0x0199
#define RT5668_MONO_AMP_CAL1 0x01a0
#define RT5668_MONO_AMP_CAL2 0x01a1
#define RT5668_MONO_AMP_CAL3 0x01a2
#define RT5668_MONO_AMP_CAL4 0x01a3
#define RT5668_MONO_AMP_CAL5 0x01a4
#define RT5668_MONO_AMP_CAL6 0x01a5
#define RT5668_MONO_AMP_CAL7 0x01a6
#define RT5668_MONO_AMP_CAL_ST1 0x01a7
#define RT5668_MONO_AMP_CAL_ST2 0x01a8
#define RT5668_MONO_AMP_CAL_ST3 0x01a9
#define RT5668_MONO_AMP_CAL_ST4 0x01aa
#define RT5668_MONO_AMP_CAL_ST5 0x01ab
#define RT5668_HP_IMP_SEN_13 0x01b9
#define RT5668_HP_IMP_SEN_14 0x01ba
#define RT5668_HP_IMP_SEN_6 0x01bb
#define RT5668_HP_IMP_SEN_7 0x01bc
#define RT5668_HP_IMP_SEN_8 0x01bd
#define RT5668_HP_IMP_SEN_9 0x01be
#define RT5668_HP_IMP_SEN_10 0x01bf
#define RT5668_HP_LOGIC_3 0x01dc
#define RT5668_HP_CALIB_ST10 0x01f3
#define RT5668_HP_CALIB_ST11 0x01f4
#define RT5668_PRO_REG_TBL_4 0x0203
#define RT5668_PRO_REG_TBL_5 0x0204
#define RT5668_PRO_REG_TBL_6 0x0205
#define RT5668_PRO_REG_TBL_7 0x0206
#define RT5668_PRO_REG_TBL_8 0x0207
#define RT5668_PRO_REG_TBL_9 0x0208
#define RT5668_SAR_ADC_INL_1 0x0210
#define RT5668_SAR_ADC_INL_2 0x0211
#define RT5668_SAR_ADC_INL_3 0x0212
#define RT5668_SAR_ADC_INL_4 0x0213
#define RT5668_SAR_ADC_INL_5 0x0214
#define RT5668_SAR_ADC_INL_6 0x0215
#define RT5668_SAR_ADC_INL_7 0x0216
#define RT5668_SAR_ADC_INL_8 0x0217
#define RT5668_SAR_ADC_INL_9 0x0218
#define RT5668_SAR_ADC_INL_10 0x0219
#define RT5668_SAR_ADC_INL_11 0x021a
#define RT5668_SAR_ADC_INL_12 0x021b
#define RT5668_DRC_CTRL_1 0x02ff
#define RT5668_DRC1_CTRL_2 0x0301
#define RT5668_DRC1_CTRL_3 0x0302
#define RT5668_DRC1_CTRL_4 0x0303
#define RT5668_DRC1_CTRL_5 0x0304
#define RT5668_DRC1_CTRL_6 0x0305
#define RT5668_DRC1_HD_CTRL_1 0x0306
#define RT5668_DRC1_HD_CTRL_2 0x0307
#define RT5668_DRC1_PRI_REG_1 0x0310
#define RT5668_DRC1_PRI_REG_2 0x0311
#define RT5668_DRC1_PRI_REG_3 0x0312
#define RT5668_DRC1_PRI_REG_4 0x0313
#define RT5668_DRC1_PRI_REG_5 0x0314
#define RT5668_DRC1_PRI_REG_6 0x0315
#define RT5668_DRC1_PRI_REG_7 0x0316
#define RT5668_DRC1_PRI_REG_8 0x0317
#define RT5668_ALC_PGA_CTL_1 0x0330
#define RT5668_ALC_PGA_CTL_2 0x0331
#define RT5668_ALC_PGA_CTL_3 0x0332
#define RT5668_ALC_PGA_CTL_4 0x0333
#define RT5668_ALC_PGA_CTL_5 0x0334
#define RT5668_ALC_PGA_CTL_6 0x0335
#define RT5668_ALC_PGA_CTL_7 0x0336
#define RT5668_ALC_PGA_CTL_8 0x0337
#define RT5668_ALC_PGA_REG_1 0x0338
#define RT5668_ALC_PGA_REG_2 0x0339
#define RT5668_ALC_PGA_REG_3 0x033a
#define RT5668_ADC_EQ_RECOV_1 0x03c0
#define RT5668_ADC_EQ_RECOV_2 0x03c1
#define RT5668_ADC_EQ_RECOV_3 0x03c2
#define RT5668_ADC_EQ_RECOV_4 0x03c3
#define RT5668_ADC_EQ_RECOV_5 0x03c4
#define RT5668_ADC_EQ_RECOV_6 0x03c5
#define RT5668_ADC_EQ_RECOV_7 0x03c6
#define RT5668_ADC_EQ_RECOV_8 0x03c7
#define RT5668_ADC_EQ_RECOV_9 0x03c8
#define RT5668_ADC_EQ_RECOV_10 0x03c9
#define RT5668_ADC_EQ_RECOV_11 0x03ca
#define RT5668_ADC_EQ_RECOV_12 0x03cb
#define RT5668_ADC_EQ_RECOV_13 0x03cc
#define RT5668_VID_HIDDEN 0x03fe
#define RT5668_VID_CUSTOMER 0x03ff
#define RT5668_SCAN_MODE 0x07f0
#define RT5668_I2C_BYPA 0x07fa
#define RT5663_A_JD_CTRL 0x00f0
#define RT5663_JD1_TRES_CTRL 0x00f1
#define RT5663_JD2_TRES_CTRL 0x00f2
#define RT5663_V2_JD_CTRL2 0x00f7
#define RT5663_DUM_REG_2 0x00fb
#define RT5663_DUM_REG_3 0x00fc
#define RT5663_DACADC_DIG_VOL2 0x0101
#define RT5663_DIG_IN_PIN2 0x0133
#define RT5663_PAD_DRV_CTL1 0x0136
#define RT5663_SOF_RAM_DEPOP 0x0138
#define RT5663_VOL_TEST 0x013f
#define RT5663_MONO_DYNA_1 0x0170
#define RT5663_MONO_DYNA_2 0x0171
#define RT5663_MONO_DYNA_3 0x0172
#define RT5663_MONO_DYNA_4 0x0173
#define RT5663_MONO_DYNA_5 0x0174
#define RT5663_MONO_DYNA_6 0x0175
#define RT5663_STO1_SIL_DET 0x0190
#define RT5663_MONOL_SIL_DET 0x0191
#define RT5663_MONOR_SIL_DET 0x0192
#define RT5663_STO2_DAC_SIL 0x0193
#define RT5663_PWR_SAV_CTL1 0x0194
#define RT5663_PWR_SAV_CTL2 0x0195
#define RT5663_PWR_SAV_CTL3 0x0196
#define RT5663_PWR_SAV_CTL4 0x0197
#define RT5663_PWR_SAV_CTL5 0x0198
#define RT5663_PWR_SAV_CTL6 0x0199
#define RT5663_MONO_AMP_CAL1 0x01a0
#define RT5663_MONO_AMP_CAL2 0x01a1
#define RT5663_MONO_AMP_CAL3 0x01a2
#define RT5663_MONO_AMP_CAL4 0x01a3
#define RT5663_MONO_AMP_CAL5 0x01a4
#define RT5663_MONO_AMP_CAL6 0x01a5
#define RT5663_MONO_AMP_CAL7 0x01a6
#define RT5663_MONO_AMP_CAL_ST1 0x01a7
#define RT5663_MONO_AMP_CAL_ST2 0x01a8
#define RT5663_MONO_AMP_CAL_ST3 0x01a9
#define RT5663_MONO_AMP_CAL_ST4 0x01aa
#define RT5663_MONO_AMP_CAL_ST5 0x01ab
#define RT5663_V2_HP_IMP_SEN_13 0x01b9
#define RT5663_V2_HP_IMP_SEN_14 0x01ba
#define RT5663_V2_HP_IMP_SEN_6 0x01bb
#define RT5663_V2_HP_IMP_SEN_7 0x01bc
#define RT5663_V2_HP_IMP_SEN_8 0x01bd
#define RT5663_V2_HP_IMP_SEN_9 0x01be
#define RT5663_V2_HP_IMP_SEN_10 0x01bf
#define RT5663_HP_LOGIC_3 0x01dc
#define RT5663_HP_CALIB_ST10 0x01f3
#define RT5663_HP_CALIB_ST11 0x01f4
#define RT5663_PRO_REG_TBL_4 0x0203
#define RT5663_PRO_REG_TBL_5 0x0204
#define RT5663_PRO_REG_TBL_6 0x0205
#define RT5663_PRO_REG_TBL_7 0x0206
#define RT5663_PRO_REG_TBL_8 0x0207
#define RT5663_PRO_REG_TBL_9 0x0208
#define RT5663_SAR_ADC_INL_1 0x0210
#define RT5663_SAR_ADC_INL_2 0x0211
#define RT5663_SAR_ADC_INL_3 0x0212
#define RT5663_SAR_ADC_INL_4 0x0213
#define RT5663_SAR_ADC_INL_5 0x0214
#define RT5663_SAR_ADC_INL_6 0x0215
#define RT5663_SAR_ADC_INL_7 0x0216
#define RT5663_SAR_ADC_INL_8 0x0217
#define RT5663_SAR_ADC_INL_9 0x0218
#define RT5663_SAR_ADC_INL_10 0x0219
#define RT5663_SAR_ADC_INL_11 0x021a
#define RT5663_SAR_ADC_INL_12 0x021b
#define RT5663_DRC_CTRL_1 0x02ff
#define RT5663_DRC1_CTRL_2 0x0301
#define RT5663_DRC1_CTRL_3 0x0302
#define RT5663_DRC1_CTRL_4 0x0303
#define RT5663_DRC1_CTRL_5 0x0304
#define RT5663_DRC1_CTRL_6 0x0305
#define RT5663_DRC1_HD_CTRL_1 0x0306
#define RT5663_DRC1_HD_CTRL_2 0x0307
#define RT5663_DRC1_PRI_REG_1 0x0310
#define RT5663_DRC1_PRI_REG_2 0x0311
#define RT5663_DRC1_PRI_REG_3 0x0312
#define RT5663_DRC1_PRI_REG_4 0x0313
#define RT5663_DRC1_PRI_REG_5 0x0314
#define RT5663_DRC1_PRI_REG_6 0x0315
#define RT5663_DRC1_PRI_REG_7 0x0316
#define RT5663_DRC1_PRI_REG_8 0x0317
#define RT5663_ALC_PGA_CTL_1 0x0330
#define RT5663_ALC_PGA_CTL_2 0x0331
#define RT5663_ALC_PGA_CTL_3 0x0332
#define RT5663_ALC_PGA_CTL_4 0x0333
#define RT5663_ALC_PGA_CTL_5 0x0334
#define RT5663_ALC_PGA_CTL_6 0x0335
#define RT5663_ALC_PGA_CTL_7 0x0336
#define RT5663_ALC_PGA_CTL_8 0x0337
#define RT5663_ALC_PGA_REG_1 0x0338
#define RT5663_ALC_PGA_REG_2 0x0339
#define RT5663_ALC_PGA_REG_3 0x033a
#define RT5663_ADC_EQ_RECOV_1 0x03c0
#define RT5663_ADC_EQ_RECOV_2 0x03c1
#define RT5663_ADC_EQ_RECOV_3 0x03c2
#define RT5663_ADC_EQ_RECOV_4 0x03c3
#define RT5663_ADC_EQ_RECOV_5 0x03c4
#define RT5663_ADC_EQ_RECOV_6 0x03c5
#define RT5663_ADC_EQ_RECOV_7 0x03c6
#define RT5663_ADC_EQ_RECOV_8 0x03c7
#define RT5663_ADC_EQ_RECOV_9 0x03c8
#define RT5663_ADC_EQ_RECOV_10 0x03c9
#define RT5663_ADC_EQ_RECOV_11 0x03ca
#define RT5663_ADC_EQ_RECOV_12 0x03cb
#define RT5663_ADC_EQ_RECOV_13 0x03cc
#define RT5663_VID_HIDDEN 0x03fe
#define RT5663_VID_CUSTOMER 0x03ff
#define RT5663_SCAN_MODE 0x07f0
#define RT5663_I2C_BYPA 0x07fa
/* Headphone Amp Control 2 (0x0003) */
#define RT5668_EN_DAC_HPO_MASK (0x1 << 14)
#define RT5668_EN_DAC_HPO_SHIFT 14
#define RT5668_EN_DAC_HPO_DIS (0x0 << 14)
#define RT5668_EN_DAC_HPO_EN (0x1 << 14)
#define RT5663_EN_DAC_HPO_MASK (0x1 << 14)
#define RT5663_EN_DAC_HPO_SHIFT 14
#define RT5663_EN_DAC_HPO_DIS (0x0 << 14)
#define RT5663_EN_DAC_HPO_EN (0x1 << 14)
/*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
#define RT5668_GAIN_HP (0x1f << 8)
#define RT5668_GAIN_HP_SHIFT 8
#define RT5663_GAIN_HP (0x1f << 8)
#define RT5663_GAIN_HP_SHIFT 8
/* AEC BST Control (0x000b) */
#define RT5668_GAIN_CBJ_MASK (0xf << 8)
#define RT5668_GAIN_CBJ_SHIFT 8
#define RT5663_GAIN_CBJ_MASK (0xf << 8)
#define RT5663_GAIN_CBJ_SHIFT 8
/* IN1 Control / MIC GND REF (0x000c) */
#define RT5668_IN1_DF_MASK (0x1 << 15)
#define RT5668_IN1_DF_SHIFT 15
#define RT5663_IN1_DF_MASK (0x1 << 15)
#define RT5663_IN1_DF_SHIFT 15
/* Combo Jack and Type Detection Control 1 (0x0010) */
#define RT5668_CBJ_DET_MASK (0x1 << 15)
#define RT5668_CBJ_DET_SHIFT 15
#define RT5668_CBJ_DET_DIS (0x0 << 15)
#define RT5668_CBJ_DET_EN (0x1 << 15)
#define RT5668_DET_TYPE_MASK (0x1 << 12)
#define RT5668_DET_TYPE_SHIFT 12
#define RT5668_DET_TYPE_WLCSP (0x0 << 12)
#define RT5668_DET_TYPE_QFN (0x1 << 12)
#define RT5668_VREF_BIAS_MASK (0x1 << 6)
#define RT5668_VREF_BIAS_SHIFT 6
#define RT5668_VREF_BIAS_FSM (0x0 << 6)
#define RT5668_VREF_BIAS_REG (0x1 << 6)
#define RT5663_CBJ_DET_MASK (0x1 << 15)
#define RT5663_CBJ_DET_SHIFT 15
#define RT5663_CBJ_DET_DIS (0x0 << 15)
#define RT5663_CBJ_DET_EN (0x1 << 15)
#define RT5663_DET_TYPE_MASK (0x1 << 12)
#define RT5663_DET_TYPE_SHIFT 12
#define RT5663_DET_TYPE_WLCSP (0x0 << 12)
#define RT5663_DET_TYPE_QFN (0x1 << 12)
#define RT5663_VREF_BIAS_MASK (0x1 << 6)
#define RT5663_VREF_BIAS_SHIFT 6
#define RT5663_VREF_BIAS_FSM (0x0 << 6)
#define RT5663_VREF_BIAS_REG (0x1 << 6)
/* REC Left Mixer Control 2 (0x003c) */
#define RT5668_RECMIX1L_BST1_CBJ (0x1 << 7)
#define RT5668_RECMIX1L_BST1_CBJ_SHIFT 7
#define RT5668_RECMIX1L_BST2 (0x1 << 4)
#define RT5668_RECMIX1L_BST2_SHIFT 4
#define RT5663_RECMIX1L_BST1_CBJ (0x1 << 7)
#define RT5663_RECMIX1L_BST1_CBJ_SHIFT 7
#define RT5663_RECMIX1L_BST2 (0x1 << 4)
#define RT5663_RECMIX1L_BST2_SHIFT 4
/* REC Right Mixer Control 2 (0x003e) */
#define RT5668_RECMIX1R_BST2 (0x1 << 4)
#define RT5668_RECMIX1R_BST2_SHIFT 4
#define RT5663_RECMIX1R_BST2 (0x1 << 4)
#define RT5663_RECMIX1R_BST2_SHIFT 4
/* DAC1 Digital Volume (0x0019) */
#define RT5668_DAC_L1_VOL_MASK (0xff << 8)
#define RT5668_DAC_L1_VOL_SHIFT 8
#define RT5668_DAC_R1_VOL_MASK (0xff)
#define RT5668_DAC_R1_VOL_SHIFT 0
#define RT5663_DAC_L1_VOL_MASK (0xff << 8)
#define RT5663_DAC_L1_VOL_SHIFT 8
#define RT5663_DAC_R1_VOL_MASK (0xff)
#define RT5663_DAC_R1_VOL_SHIFT 0
/* ADC Digital Volume Control (0x001c) */
#define RT5668_ADC_L_MUTE_MASK (0x1 << 15)
#define RT5668_ADC_L_MUTE_SHIFT 15
#define RT5668_ADC_L_VOL_MASK (0x7f << 8)
#define RT5668_ADC_L_VOL_SHIFT 8
#define RT5668_ADC_R_MUTE_MASK (0x1 << 7)
#define RT5668_ADC_R_MUTE_SHIFT 7
#define RT5668_ADC_R_VOL_MASK (0x7f)
#define RT5668_ADC_R_VOL_SHIFT 0
#define RT5663_ADC_L_MUTE_MASK (0x1 << 15)
#define RT5663_ADC_L_MUTE_SHIFT 15
#define RT5663_ADC_L_VOL_MASK (0x7f << 8)
#define RT5663_ADC_L_VOL_SHIFT 8
#define RT5663_ADC_R_MUTE_MASK (0x1 << 7)
#define RT5663_ADC_R_MUTE_SHIFT 7
#define RT5663_ADC_R_VOL_MASK (0x7f)
#define RT5663_ADC_R_VOL_SHIFT 0
/* Stereo ADC Mixer Control (0x0026) */
#define RT5668_M_STO1_ADC_L1 (0x1 << 15)
#define RT5668_M_STO1_ADC_L1_SHIFT 15
#define RT5668_M_STO1_ADC_L2 (0x1 << 14)
#define RT5668_M_STO1_ADC_L2_SHIFT 14
#define RT5668_STO1_ADC_L1_SRC (0x1 << 13)
#define RT5668_STO1_ADC_L1_SRC_SHIFT 13
#define RT5668_STO1_ADC_L2_SRC (0x1 << 12)
#define RT5668_STO1_ADC_L2_SRC_SHIFT 12
#define RT5668_STO1_ADC_L_SRC (0x3 << 10)
#define RT5668_STO1_ADC_L_SRC_SHIFT 10
#define RT5668_M_STO1_ADC_R1 (0x1 << 7)
#define RT5668_M_STO1_ADC_R1_SHIFT 7
#define RT5668_M_STO1_ADC_R2 (0x1 << 6)
#define RT5668_M_STO1_ADC_R2_SHIFT 6
#define RT5668_STO1_ADC_R1_SRC (0x1 << 5)
#define RT5668_STO1_ADC_R1_SRC_SHIFT 5
#define RT5668_STO1_ADC_R2_SRC (0x1 << 4)
#define RT5668_STO1_ADC_R2_SRC_SHIFT 4
#define RT5668_STO1_ADC_R_SRC (0x3 << 2)
#define RT5668_STO1_ADC_R_SRC_SHIFT 2
#define RT5663_M_STO1_ADC_L1 (0x1 << 15)
#define RT5663_M_STO1_ADC_L1_SHIFT 15
#define RT5663_M_STO1_ADC_L2 (0x1 << 14)
#define RT5663_M_STO1_ADC_L2_SHIFT 14
#define RT5663_STO1_ADC_L1_SRC (0x1 << 13)
#define RT5663_STO1_ADC_L1_SRC_SHIFT 13
#define RT5663_STO1_ADC_L2_SRC (0x1 << 12)
#define RT5663_STO1_ADC_L2_SRC_SHIFT 12
#define RT5663_STO1_ADC_L_SRC (0x3 << 10)
#define RT5663_STO1_ADC_L_SRC_SHIFT 10
#define RT5663_M_STO1_ADC_R1 (0x1 << 7)
#define RT5663_M_STO1_ADC_R1_SHIFT 7
#define RT5663_M_STO1_ADC_R2 (0x1 << 6)
#define RT5663_M_STO1_ADC_R2_SHIFT 6
#define RT5663_STO1_ADC_R1_SRC (0x1 << 5)
#define RT5663_STO1_ADC_R1_SRC_SHIFT 5
#define RT5663_STO1_ADC_R2_SRC (0x1 << 4)
#define RT5663_STO1_ADC_R2_SRC_SHIFT 4
#define RT5663_STO1_ADC_R_SRC (0x3 << 2)
#define RT5663_STO1_ADC_R_SRC_SHIFT 2
/* ADC Mixer to DAC Mixer Control (0x0029) */
#define RT5668_M_ADCMIX_L (0x1 << 15)
#define RT5668_M_ADCMIX_L_SHIFT 15
#define RT5668_M_DAC1_L (0x1 << 14)
#define RT5668_M_DAC1_L_SHIFT 14
#define RT5668_M_ADCMIX_R (0x1 << 7)
#define RT5668_M_ADCMIX_R_SHIFT 7
#define RT5668_M_DAC1_R (0x1 << 6)
#define RT5668_M_DAC1_R_SHIFT 6
#define RT5663_M_ADCMIX_L (0x1 << 15)
#define RT5663_M_ADCMIX_L_SHIFT 15
#define RT5663_M_DAC1_L (0x1 << 14)
#define RT5663_M_DAC1_L_SHIFT 14
#define RT5663_M_ADCMIX_R (0x1 << 7)
#define RT5663_M_ADCMIX_R_SHIFT 7
#define RT5663_M_DAC1_R (0x1 << 6)
#define RT5663_M_DAC1_R_SHIFT 6
/* Stereo DAC Mixer Control (0x002a) */
#define RT5668_M_DAC_L1_STO_L (0x1 << 15)
#define RT5668_M_DAC_L1_STO_L_SHIFT 15
#define RT5668_M_DAC_R1_STO_L (0x1 << 13)
#define RT5668_M_DAC_R1_STO_L_SHIFT 13
#define RT5668_M_DAC_L1_STO_R (0x1 << 7)
#define RT5668_M_DAC_L1_STO_R_SHIFT 7
#define RT5668_M_DAC_R1_STO_R (0x1 << 5)
#define RT5668_M_DAC_R1_STO_R_SHIFT 5
#define RT5663_M_DAC_L1_STO_L (0x1 << 15)
#define RT5663_M_DAC_L1_STO_L_SHIFT 15
#define RT5663_M_DAC_R1_STO_L (0x1 << 13)
#define RT5663_M_DAC_R1_STO_L_SHIFT 13
#define RT5663_M_DAC_L1_STO_R (0x1 << 7)
#define RT5663_M_DAC_L1_STO_R_SHIFT 7
#define RT5663_M_DAC_R1_STO_R (0x1 << 5)
#define RT5663_M_DAC_R1_STO_R_SHIFT 5
/* Power Management for Digital 1 (0x0061) */
#define RT5668_PWR_I2S1 (0x1 << 15)
#define RT5668_PWR_I2S1_SHIFT 15
#define RT5668_PWR_DAC_L1 (0x1 << 11)
#define RT5668_PWR_DAC_L1_SHIFT 11
#define RT5668_PWR_DAC_R1 (0x1 << 10)
#define RT5668_PWR_DAC_R1_SHIFT 10
#define RT5668_PWR_LDO_DACREF_MASK (0x1 << 8)
#define RT5668_PWR_LDO_DACREF_SHIFT 8
#define RT5668_PWR_LDO_DACREF_ON (0x1 << 8)
#define RT5668_PWR_LDO_DACREF_DOWN (0x0 << 8)
#define RT5668_PWR_LDO_SHIFT 8
#define RT5668_PWR_ADC_L1 (0x1 << 4)
#define RT5668_PWR_ADC_L1_SHIFT 4
#define RT5668_PWR_ADC_R1 (0x1 << 3)
#define RT5668_PWR_ADC_R1_SHIFT 3
#define RT5663_PWR_I2S1 (0x1 << 15)
#define RT5663_PWR_I2S1_SHIFT 15
#define RT5663_PWR_DAC_L1 (0x1 << 11)
#define RT5663_PWR_DAC_L1_SHIFT 11
#define RT5663_PWR_DAC_R1 (0x1 << 10)
#define RT5663_PWR_DAC_R1_SHIFT 10
#define RT5663_PWR_LDO_DACREF_MASK (0x1 << 8)
#define RT5663_PWR_LDO_DACREF_SHIFT 8
#define RT5663_PWR_LDO_DACREF_ON (0x1 << 8)
#define RT5663_PWR_LDO_DACREF_DOWN (0x0 << 8)
#define RT5663_PWR_LDO_SHIFT 8
#define RT5663_PWR_ADC_L1 (0x1 << 4)
#define RT5663_PWR_ADC_L1_SHIFT 4
#define RT5663_PWR_ADC_R1 (0x1 << 3)
#define RT5663_PWR_ADC_R1_SHIFT 3
/* Power Management for Digital 2 (0x0062) */
#define RT5668_PWR_ADC_S1F (0x1 << 15)
#define RT5668_PWR_ADC_S1F_SHIFT 15
#define RT5668_PWR_DAC_S1F (0x1 << 10)
#define RT5668_PWR_DAC_S1F_SHIFT 10
#define RT5663_PWR_ADC_S1F (0x1 << 15)
#define RT5663_PWR_ADC_S1F_SHIFT 15
#define RT5663_PWR_DAC_S1F (0x1 << 10)
#define RT5663_PWR_DAC_S1F_SHIFT 10
/* Power Management for Analog 1 (0x0063) */
#define RT5668_PWR_VREF1 (0x1 << 15)
#define RT5668_PWR_VREF1_MASK (0x1 << 15)
#define RT5668_PWR_VREF1_SHIFT 15
#define RT5668_PWR_FV1 (0x1 << 14)
#define RT5668_PWR_FV1_MASK (0x1 << 14)
#define RT5668_PWR_FV1_SHIFT 14
#define RT5668_PWR_VREF2 (0x1 << 13)
#define RT5668_PWR_VREF2_MASK (0x1 << 13)
#define RT5668_PWR_VREF2_SHIFT 13
#define RT5668_PWR_FV2 (0x1 << 12)
#define RT5668_PWR_FV2_MASK (0x1 << 12)
#define RT5668_PWR_FV2_SHIFT 12
#define RT5668_PWR_MB (0x1 << 9)
#define RT5668_PWR_MB_MASK (0x1 << 9)
#define RT5668_PWR_MB_SHIFT 9
#define RT5668_AMP_HP_MASK (0x3 << 2)
#define RT5668_AMP_HP_SHIFT 2
#define RT5668_AMP_HP_1X (0x0 << 2)
#define RT5668_AMP_HP_3X (0x1 << 2)
#define RT5668_AMP_HP_5X (0x3 << 2)
#define RT5668_LDO1_DVO_MASK (0x3)
#define RT5668_LDO1_DVO_SHIFT 0
#define RT5668_LDO1_DVO_0_9V (0x0)
#define RT5668_LDO1_DVO_1_0V (0x1)
#define RT5668_LDO1_DVO_1_2V (0x2)
#define RT5668_LDO1_DVO_1_4V (0x3)
#define RT5663_PWR_VREF1 (0x1 << 15)
#define RT5663_PWR_VREF1_MASK (0x1 << 15)
#define RT5663_PWR_VREF1_SHIFT 15
#define RT5663_PWR_FV1 (0x1 << 14)
#define RT5663_PWR_FV1_MASK (0x1 << 14)
#define RT5663_PWR_FV1_SHIFT 14
#define RT5663_PWR_VREF2 (0x1 << 13)
#define RT5663_PWR_VREF2_MASK (0x1 << 13)
#define RT5663_PWR_VREF2_SHIFT 13
#define RT5663_PWR_FV2 (0x1 << 12)
#define RT5663_PWR_FV2_MASK (0x1 << 12)
#define RT5663_PWR_FV2_SHIFT 12
#define RT5663_PWR_MB (0x1 << 9)
#define RT5663_PWR_MB_MASK (0x1 << 9)
#define RT5663_PWR_MB_SHIFT 9
#define RT5663_AMP_HP_MASK (0x3 << 2)
#define RT5663_AMP_HP_SHIFT 2
#define RT5663_AMP_HP_1X (0x0 << 2)
#define RT5663_AMP_HP_3X (0x1 << 2)
#define RT5663_AMP_HP_5X (0x3 << 2)
#define RT5663_LDO1_DVO_MASK (0x3)
#define RT5663_LDO1_DVO_SHIFT 0
#define RT5663_LDO1_DVO_0_9V (0x0)
#define RT5663_LDO1_DVO_1_0V (0x1)
#define RT5663_LDO1_DVO_1_2V (0x2)
#define RT5663_LDO1_DVO_1_4V (0x3)
/* Power Management for Analog 2 (0x0064) */
#define RT5668_PWR_BST1 (0x1 << 15)
#define RT5668_PWR_BST1_MASK (0x1 << 15)
#define RT5668_PWR_BST1_SHIFT 15
#define RT5668_PWR_BST1_OFF (0x0 << 15)
#define RT5668_PWR_BST1_ON (0x1 << 15)
#define RT5668_PWR_BST2 (0x1 << 14)
#define RT5668_PWR_BST2_MASK (0x1 << 14)
#define RT5668_PWR_BST2_SHIFT 14
#define RT5668_PWR_MB1 (0x1 << 11)
#define RT5668_PWR_MB1_SHIFT 11
#define RT5668_PWR_MB2 (0x1 << 10)
#define RT5668_PWR_MB2_SHIFT 10
#define RT5668_PWR_BST2_OP (0x1 << 6)
#define RT5668_PWR_BST2_OP_MASK (0x1 << 6)
#define RT5668_PWR_BST2_OP_SHIFT 6
#define RT5668_PWR_JD1 (0x1 << 3)
#define RT5668_PWR_JD1_MASK (0x1 << 3)
#define RT5668_PWR_JD1_SHIFT 3
#define RT5668_PWR_JD2 (0x1 << 2)
#define RT5668_PWR_JD2_MASK (0x1 << 2)
#define RT5668_PWR_JD2_SHIFT 2
#define RT5668_PWR_RECMIX1 (0x1 << 1)
#define RT5668_PWR_RECMIX1_SHIFT 1
#define RT5668_PWR_RECMIX2 (0x1)
#define RT5668_PWR_RECMIX2_SHIFT 0
#define RT5663_PWR_BST1 (0x1 << 15)
#define RT5663_PWR_BST1_MASK (0x1 << 15)
#define RT5663_PWR_BST1_SHIFT 15
#define RT5663_PWR_BST1_OFF (0x0 << 15)
#define RT5663_PWR_BST1_ON (0x1 << 15)
#define RT5663_PWR_BST2 (0x1 << 14)
#define RT5663_PWR_BST2_MASK (0x1 << 14)
#define RT5663_PWR_BST2_SHIFT 14
#define RT5663_PWR_MB1 (0x1 << 11)
#define RT5663_PWR_MB1_SHIFT 11
#define RT5663_PWR_MB2 (0x1 << 10)
#define RT5663_PWR_MB2_SHIFT 10
#define RT5663_PWR_BST2_OP (0x1 << 6)
#define RT5663_PWR_BST2_OP_MASK (0x1 << 6)
#define RT5663_PWR_BST2_OP_SHIFT 6
#define RT5663_PWR_JD1 (0x1 << 3)
#define RT5663_PWR_JD1_MASK (0x1 << 3)
#define RT5663_PWR_JD1_SHIFT 3
#define RT5663_PWR_JD2 (0x1 << 2)
#define RT5663_PWR_JD2_MASK (0x1 << 2)
#define RT5663_PWR_JD2_SHIFT 2
#define RT5663_PWR_RECMIX1 (0x1 << 1)
#define RT5663_PWR_RECMIX1_SHIFT 1
#define RT5663_PWR_RECMIX2 (0x1)
#define RT5663_PWR_RECMIX2_SHIFT 0
/* Power Management for Analog 3 (0x0065) */
#define RT5668_PWR_CBJ_MASK (0x1 << 9)
#define RT5668_PWR_CBJ_SHIFT 9
#define RT5668_PWR_CBJ_OFF (0x0 << 9)
#define RT5668_PWR_CBJ_ON (0x1 << 9)
#define RT5668_PWR_PLL (0x1 << 6)
#define RT5668_PWR_PLL_SHIFT 6
#define RT5668_PWR_LDO2 (0x1 << 2)
#define RT5668_PWR_LDO2_SHIFT 2
#define RT5663_PWR_CBJ_MASK (0x1 << 9)
#define RT5663_PWR_CBJ_SHIFT 9
#define RT5663_PWR_CBJ_OFF (0x0 << 9)
#define RT5663_PWR_CBJ_ON (0x1 << 9)
#define RT5663_PWR_PLL (0x1 << 6)
#define RT5663_PWR_PLL_SHIFT 6
#define RT5663_PWR_LDO2 (0x1 << 2)
#define RT5663_PWR_LDO2_SHIFT 2
/* Power Management for Volume (0x0067) */
#define RT5668_PWR_MIC_DET (0x1 << 5)
#define RT5668_PWR_MIC_DET_SHIFT 5
#define RT5663_V2_PWR_MIC_DET (0x1 << 5)
#define RT5663_V2_PWR_MIC_DET_SHIFT 5
/* MCLK and System Clock Detection Control (0x006b) */
#define RT5668_EN_ANA_CLK_DET_MASK (0x1 << 15)
#define RT5668_EN_ANA_CLK_DET_SHIFT 15
#define RT5668_EN_ANA_CLK_DET_DIS (0x0 << 15)
#define RT5668_EN_ANA_CLK_DET_AUTO (0x1 << 15)
#define RT5668_PWR_CLK_DET_MASK (0x1)
#define RT5668_PWR_CLK_DET_SHIFT 0
#define RT5668_PWR_CLK_DET_DIS (0x0)
#define RT5668_PWR_CLK_DET_EN (0x1)
#define RT5663_EN_ANA_CLK_DET_MASK (0x1 << 15)
#define RT5663_EN_ANA_CLK_DET_SHIFT 15
#define RT5663_EN_ANA_CLK_DET_DIS (0x0 << 15)
#define RT5663_EN_ANA_CLK_DET_AUTO (0x1 << 15)
#define RT5663_PWR_CLK_DET_MASK (0x1)
#define RT5663_PWR_CLK_DET_SHIFT 0
#define RT5663_PWR_CLK_DET_DIS (0x0)
#define RT5663_PWR_CLK_DET_EN (0x1)
/* I2S1 Audio Serial Data Port Control (0x0070) */
#define RT5668_I2S_MS_MASK (0x1 << 15)
#define RT5668_I2S_MS_SHIFT 15
#define RT5668_I2S_MS_M (0x0 << 15)
#define RT5668_I2S_MS_S (0x1 << 15)
#define RT5668_I2S_BP_MASK (0x1 << 8)
#define RT5668_I2S_BP_SHIFT 8
#define RT5668_I2S_BP_NOR (0x0 << 8)
#define RT5668_I2S_BP_INV (0x1 << 8)
#define RT5668_I2S_DL_MASK (0x3 << 4)
#define RT5668_I2S_DL_SHIFT 4
#define RT5668_I2S_DL_16 (0x0 << 4)
#define RT5668_I2S_DL_20 (0x1 << 4)
#define RT5668_I2S_DL_24 (0x2 << 4)
#define RT5668_I2S_DL_8 (0x3 << 4)
#define RT5668_I2S_DF_MASK (0x7)
#define RT5668_I2S_DF_SHIFT 0
#define RT5668_I2S_DF_I2S (0x0)
#define RT5668_I2S_DF_LEFT (0x1)
#define RT5668_I2S_DF_PCM_A (0x2)
#define RT5668_I2S_DF_PCM_B (0x3)
#define RT5668_I2S_DF_PCM_A_N (0x6)
#define RT5668_I2S_DF_PCM_B_N (0x7)
#define RT5663_I2S_MS_MASK (0x1 << 15)
#define RT5663_I2S_MS_SHIFT 15
#define RT5663_I2S_MS_M (0x0 << 15)
#define RT5663_I2S_MS_S (0x1 << 15)
#define RT5663_I2S_BP_MASK (0x1 << 8)
#define RT5663_I2S_BP_SHIFT 8
#define RT5663_I2S_BP_NOR (0x0 << 8)
#define RT5663_I2S_BP_INV (0x1 << 8)
#define RT5663_I2S_DL_MASK (0x3 << 4)
#define RT5663_I2S_DL_SHIFT 4
#define RT5663_I2S_DL_16 (0x0 << 4)
#define RT5663_I2S_DL_20 (0x1 << 4)
#define RT5663_I2S_DL_24 (0x2 << 4)
#define RT5663_I2S_DL_8 (0x3 << 4)
#define RT5663_I2S_DF_MASK (0x7)
#define RT5663_I2S_DF_SHIFT 0
#define RT5663_I2S_DF_I2S (0x0)
#define RT5663_I2S_DF_LEFT (0x1)
#define RT5663_I2S_DF_PCM_A (0x2)
#define RT5663_I2S_DF_PCM_B (0x3)
#define RT5663_I2S_DF_PCM_A_N (0x6)
#define RT5663_I2S_DF_PCM_B_N (0x7)
/* ADC/DAC Clock Control 1 (0x0073) */
#define RT5668_I2S_PD1_MASK (0x7 << 12)
#define RT5668_I2S_PD1_SHIFT 12
#define RT5668_M_I2S_DIV_MASK (0x7 << 8)
#define RT5668_M_I2S_DIV_SHIFT 8
#define RT5668_CLK_SRC_MASK (0x3 << 4)
#define RT5668_CLK_SRC_MCLK (0x0 << 4)
#define RT5668_CLK_SRC_PLL_OUT (0x1 << 4)
#define RT5668_CLK_SRC_DIV (0x2 << 4)
#define RT5668_CLK_SRC_RC (0x3 << 4)
#define RT5668_DAC_OSR_MASK (0x3 << 2)
#define RT5668_DAC_OSR_SHIFT 2
#define RT5668_DAC_OSR_128 (0x0 << 2)
#define RT5668_DAC_OSR_64 (0x1 << 2)
#define RT5668_DAC_OSR_32 (0x2 << 2)
#define RT5668_ADC_OSR_MASK (0x3)
#define RT5668_ADC_OSR_SHIFT 0
#define RT5668_ADC_OSR_128 (0x0)
#define RT5668_ADC_OSR_64 (0x1)
#define RT5668_ADC_OSR_32 (0x2)
#define RT5663_I2S_PD1_MASK (0x7 << 12)
#define RT5663_I2S_PD1_SHIFT 12
#define RT5663_M_I2S_DIV_MASK (0x7 << 8)
#define RT5663_M_I2S_DIV_SHIFT 8
#define RT5663_CLK_SRC_MASK (0x3 << 4)
#define RT5663_CLK_SRC_MCLK (0x0 << 4)
#define RT5663_CLK_SRC_PLL_OUT (0x1 << 4)
#define RT5663_CLK_SRC_DIV (0x2 << 4)
#define RT5663_CLK_SRC_RC (0x3 << 4)
#define RT5663_DAC_OSR_MASK (0x3 << 2)
#define RT5663_DAC_OSR_SHIFT 2
#define RT5663_DAC_OSR_128 (0x0 << 2)
#define RT5663_DAC_OSR_64 (0x1 << 2)
#define RT5663_DAC_OSR_32 (0x2 << 2)
#define RT5663_ADC_OSR_MASK (0x3)
#define RT5663_ADC_OSR_SHIFT 0
#define RT5663_ADC_OSR_128 (0x0)
#define RT5663_ADC_OSR_64 (0x1)
#define RT5663_ADC_OSR_32 (0x2)
/* TDM1 control 1 (0x0078) */
#define RT5668_TDM_MODE_MASK (0x1 << 15)
#define RT5668_TDM_MODE_SHIFT 15
#define RT5668_TDM_MODE_I2S (0x0 << 15)
#define RT5668_TDM_MODE_TDM (0x1 << 15)
#define RT5668_TDM_IN_CH_MASK (0x3 << 10)
#define RT5668_TDM_IN_CH_SHIFT 10
#define RT5668_TDM_IN_CH_2 (0x0 << 10)
#define RT5668_TDM_IN_CH_4 (0x1 << 10)
#define RT5668_TDM_IN_CH_6 (0x2 << 10)
#define RT5668_TDM_IN_CH_8 (0x3 << 10)
#define RT5668_TDM_OUT_CH_MASK (0x3 << 8)
#define RT5668_TDM_OUT_CH_SHIFT 8
#define RT5668_TDM_OUT_CH_2 (0x0 << 8)
#define RT5668_TDM_OUT_CH_4 (0x1 << 8)
#define RT5668_TDM_OUT_CH_6 (0x2 << 8)
#define RT5668_TDM_OUT_CH_8 (0x3 << 8)
#define RT5668_TDM_IN_LEN_MASK (0x3 << 6)
#define RT5668_TDM_IN_LEN_SHIFT 6
#define RT5668_TDM_IN_LEN_16 (0x0 << 6)
#define RT5668_TDM_IN_LEN_20 (0x1 << 6)
#define RT5668_TDM_IN_LEN_24 (0x2 << 6)
#define RT5668_TDM_IN_LEN_32 (0x3 << 6)
#define RT5668_TDM_OUT_LEN_MASK (0x3 << 4)
#define RT5668_TDM_OUT_LEN_SHIFT 4
#define RT5668_TDM_OUT_LEN_16 (0x0 << 4)
#define RT5668_TDM_OUT_LEN_20 (0x1 << 4)
#define RT5668_TDM_OUT_LEN_24 (0x2 << 4)
#define RT5668_TDM_OUT_LEN_32 (0x3 << 4)
#define RT5663_TDM_MODE_MASK (0x1 << 15)
#define RT5663_TDM_MODE_SHIFT 15
#define RT5663_TDM_MODE_I2S (0x0 << 15)
#define RT5663_TDM_MODE_TDM (0x1 << 15)
#define RT5663_TDM_IN_CH_MASK (0x3 << 10)
#define RT5663_TDM_IN_CH_SHIFT 10
#define RT5663_TDM_IN_CH_2 (0x0 << 10)
#define RT5663_TDM_IN_CH_4 (0x1 << 10)
#define RT5663_TDM_IN_CH_6 (0x2 << 10)
#define RT5663_TDM_IN_CH_8 (0x3 << 10)
#define RT5663_TDM_OUT_CH_MASK (0x3 << 8)
#define RT5663_TDM_OUT_CH_SHIFT 8
#define RT5663_TDM_OUT_CH_2 (0x0 << 8)
#define RT5663_TDM_OUT_CH_4 (0x1 << 8)
#define RT5663_TDM_OUT_CH_6 (0x2 << 8)
#define RT5663_TDM_OUT_CH_8 (0x3 << 8)
#define RT5663_TDM_IN_LEN_MASK (0x3 << 6)
#define RT5663_TDM_IN_LEN_SHIFT 6
#define RT5663_TDM_IN_LEN_16 (0x0 << 6)
#define RT5663_TDM_IN_LEN_20 (0x1 << 6)
#define RT5663_TDM_IN_LEN_24 (0x2 << 6)
#define RT5663_TDM_IN_LEN_32 (0x3 << 6)
#define RT5663_TDM_OUT_LEN_MASK (0x3 << 4)
#define RT5663_TDM_OUT_LEN_SHIFT 4
#define RT5663_TDM_OUT_LEN_16 (0x0 << 4)
#define RT5663_TDM_OUT_LEN_20 (0x1 << 4)
#define RT5663_TDM_OUT_LEN_24 (0x2 << 4)
#define RT5663_TDM_OUT_LEN_32 (0x3 << 4)
/* Global Clock Control (0x0080) */
#define RT5668_SCLK_SRC_MASK (0x3 << 14)
#define RT5668_SCLK_SRC_SHIFT 14
#define RT5668_SCLK_SRC_MCLK (0x0 << 14)
#define RT5668_SCLK_SRC_PLL1 (0x1 << 14)
#define RT5668_SCLK_SRC_RCCLK (0x2 << 14)
#define RT5668_PLL1_SRC_MASK (0x7 << 8)
#define RT5668_PLL1_SRC_SHIFT 8
#define RT5668_PLL1_SRC_MCLK (0x0 << 8)
#define RT5668_PLL1_SRC_BCLK1 (0x1 << 8)
#define RT5668_PLL1_PD_MASK (0x1 << 4)
#define RT5668_PLL1_PD_SHIFT 4
#define RT5668_PLL_INP_MAX 40000000
#define RT5668_PLL_INP_MIN 256000
#define RT5663_SCLK_SRC_MASK (0x3 << 14)
#define RT5663_SCLK_SRC_SHIFT 14
#define RT5663_SCLK_SRC_MCLK (0x0 << 14)
#define RT5663_SCLK_SRC_PLL1 (0x1 << 14)
#define RT5663_SCLK_SRC_RCCLK (0x2 << 14)
#define RT5663_PLL1_SRC_MASK (0x7 << 11)
#define RT5663_PLL1_SRC_SHIFT 11
#define RT5663_PLL1_SRC_MCLK (0x0 << 11)
#define RT5663_PLL1_SRC_BCLK1 (0x1 << 11)
#define RT5663_V2_PLL1_SRC_MASK (0x7 << 8)
#define RT5663_V2_PLL1_SRC_SHIFT 8
#define RT5663_V2_PLL1_SRC_MCLK (0x0 << 8)
#define RT5663_V2_PLL1_SRC_BCLK1 (0x1 << 8)
#define RT5663_PLL1_PD_MASK (0x1 << 4)
#define RT5663_PLL1_PD_SHIFT 4
#define RT5663_PLL_INP_MAX 40000000
#define RT5663_PLL_INP_MIN 256000
/* PLL M/N/K Code Control 1 (0x0081) */
#define RT5668_PLL_N_MAX 0x001ff
#define RT5668_PLL_N_MASK (RT5668_PLL_N_MAX << 7)
#define RT5668_PLL_N_SHIFT 7
#define RT5668_PLL_K_MAX 0x001f
#define RT5668_PLL_K_MASK (RT5668_PLL_K_MAX)
#define RT5668_PLL_K_SHIFT 0
#define RT5663_PLL_N_MAX 0x001ff
#define RT5663_PLL_N_MASK (RT5663_PLL_N_MAX << 7)
#define RT5663_PLL_N_SHIFT 7
#define RT5663_PLL_K_MAX 0x001f
#define RT5663_PLL_K_MASK (RT5663_PLL_K_MAX)
#define RT5663_PLL_K_SHIFT 0
/* PLL M/N/K Code Control 2 (0x0082) */
#define RT5668_PLL_M_MAX 0x00f
#define RT5668_PLL_M_MASK (RT5668_PLL_M_MAX << 12)
#define RT5668_PLL_M_SHIFT 12
#define RT5668_PLL_M_BP (0x1 << 11)
#define RT5668_PLL_M_BP_SHIFT 11
#define RT5663_PLL_M_MAX 0x00f
#define RT5663_PLL_M_MASK (RT5663_PLL_M_MAX << 12)
#define RT5663_PLL_M_SHIFT 12
#define RT5663_PLL_M_BP (0x1 << 11)
#define RT5663_PLL_M_BP_SHIFT 11
/* PLL tracking mode 1 (0x0083) */
#define RT5668_I2S1_ASRC_MASK (0x1 << 13)
#define RT5668_I2S1_ASRC_SHIFT 13
#define RT5668_DAC_STO1_ASRC_MASK (0x1 << 12)
#define RT5668_DAC_STO1_ASRC_SHIFT 12
#define RT5668_ADC_STO1_ASRC_MASK (0x1 << 4)
#define RT5668_ADC_STO1_ASRC_SHIFT 4
#define RT5663_V2_I2S1_ASRC_MASK (0x1 << 13)
#define RT5663_V2_I2S1_ASRC_SHIFT 13
#define RT5663_V2_DAC_STO1_ASRC_MASK (0x1 << 12)
#define RT5663_V2_DAC_STO1_ASRC_SHIFT 12
#define RT5663_V2_ADC_STO1_ASRC_MASK (0x1 << 4)
#define RT5663_V2_ADC_STO1_ASRC_SHIFT 4
/* PLL tracking mode 2 (0x0084)*/
#define RT5668_DA_STO1_TRACK_MASK (0x7 << 12)
#define RT5668_DA_STO1_TRACK_SHIFT 12
#define RT5668_DA_STO1_TRACK_SYSCLK (0x0 << 12)
#define RT5668_DA_STO1_TRACK_I2S1 (0x1 << 12)
#define RT5663_DA_STO1_TRACK_MASK (0x7 << 12)
#define RT5663_DA_STO1_TRACK_SHIFT 12
#define RT5663_DA_STO1_TRACK_SYSCLK (0x0 << 12)
#define RT5663_DA_STO1_TRACK_I2S1 (0x1 << 12)
/* PLL tracking mode 3 (0x0085)*/
#define RT5668_AD_STO1_TRACK_MASK (0x7 << 12)
#define RT5668_AD_STO1_TRACK_SHIFT 12
#define RT5668_AD_STO1_TRACK_SYSCLK (0x0 << 12)
#define RT5668_AD_STO1_TRACK_I2S1 (0x1 << 12)
#define RT5663_V2_AD_STO1_TRACK_MASK (0x7 << 12)
#define RT5663_V2_AD_STO1_TRACK_SHIFT 12
#define RT5663_V2_AD_STO1_TRACK_SYSCLK (0x0 << 12)
#define RT5663_V2_AD_STO1_TRACK_I2S1 (0x1 << 12)
/* HPOUT Charge pump control 1 (0x0091) */
#define RT5668_OSW_HP_L_MASK (0x1 << 11)
#define RT5668_OSW_HP_L_SHIFT 11
#define RT5668_OSW_HP_L_EN (0x1 << 11)
#define RT5668_OSW_HP_L_DIS (0x0 << 11)
#define RT5668_OSW_HP_R_MASK (0x1 << 10)
#define RT5668_OSW_HP_R_SHIFT 10
#define RT5668_OSW_HP_R_EN (0x1 << 10)
#define RT5668_OSW_HP_R_DIS (0x0 << 10)
#define RT5668_SEL_PM_HP_MASK (0x3 << 8)
#define RT5668_SEL_PM_HP_SHIFT 8
#define RT5668_SEL_PM_HP_0_6 (0x0 << 8)
#define RT5668_SEL_PM_HP_0_9 (0x1 << 8)
#define RT5668_SEL_PM_HP_1_8 (0x2 << 8)
#define RT5668_SEL_PM_HP_HIGH (0x3 << 8)
#define RT5668_OVCD_HP_MASK (0x1 << 2)
#define RT5668_OVCD_HP_SHIFT 2
#define RT5668_OVCD_HP_EN (0x1 << 2)
#define RT5668_OVCD_HP_DIS (0x0 << 2)
#define RT5663_OSW_HP_L_MASK (0x1 << 11)
#define RT5663_OSW_HP_L_SHIFT 11
#define RT5663_OSW_HP_L_EN (0x1 << 11)
#define RT5663_OSW_HP_L_DIS (0x0 << 11)
#define RT5663_OSW_HP_R_MASK (0x1 << 10)
#define RT5663_OSW_HP_R_SHIFT 10
#define RT5663_OSW_HP_R_EN (0x1 << 10)
#define RT5663_OSW_HP_R_DIS (0x0 << 10)
#define RT5663_SEL_PM_HP_MASK (0x3 << 8)
#define RT5663_SEL_PM_HP_SHIFT 8
#define RT5663_SEL_PM_HP_0_6 (0x0 << 8)
#define RT5663_SEL_PM_HP_0_9 (0x1 << 8)
#define RT5663_SEL_PM_HP_1_8 (0x2 << 8)
#define RT5663_SEL_PM_HP_HIGH (0x3 << 8)
#define RT5663_OVCD_HP_MASK (0x1 << 2)
#define RT5663_OVCD_HP_SHIFT 2
#define RT5663_OVCD_HP_EN (0x1 << 2)
#define RT5663_OVCD_HP_DIS (0x0 << 2)
/* RC Clock Control (0x0094) */
#define RT5668_DIG_25M_CLK_MASK (0x1 << 9)
#define RT5668_DIG_25M_CLK_SHIFT 9
#define RT5668_DIG_25M_CLK_DIS (0x0 << 9)
#define RT5668_DIG_25M_CLK_EN (0x1 << 9)
#define RT5668_DIG_1M_CLK_MASK (0x1 << 8)
#define RT5668_DIG_1M_CLK_SHIFT 8
#define RT5668_DIG_1M_CLK_DIS (0x0 << 8)
#define RT5668_DIG_1M_CLK_EN (0x1 << 8)
#define RT5663_DIG_25M_CLK_MASK (0x1 << 9)
#define RT5663_DIG_25M_CLK_SHIFT 9
#define RT5663_DIG_25M_CLK_DIS (0x0 << 9)
#define RT5663_DIG_25M_CLK_EN (0x1 << 9)
#define RT5663_DIG_1M_CLK_MASK (0x1 << 8)
#define RT5663_DIG_1M_CLK_SHIFT 8
#define RT5663_DIG_1M_CLK_DIS (0x0 << 8)
#define RT5663_DIG_1M_CLK_EN (0x1 << 8)
/* Auto Turn On 1M RC CLK (0x009f) */
#define RT5668_IRQ_POW_SAV_MASK (0x1 << 15)
#define RT5668_IRQ_POW_SAV_SHIFT 15
#define RT5668_IRQ_POW_SAV_DIS (0x0 << 15)
#define RT5668_IRQ_POW_SAV_EN (0x1 << 15)
#define RT5668_IRQ_POW_SAV_JD1_MASK (0x1 << 14)
#define RT5668_IRQ_POW_SAV_JD1_SHIFT 14
#define RT5668_IRQ_POW_SAV_JD1_DIS (0x0 << 14)
#define RT5668_IRQ_POW_SAV_JD1_EN (0x1 << 14)
#define RT5663_IRQ_POW_SAV_MASK (0x1 << 15)
#define RT5663_IRQ_POW_SAV_SHIFT 15
#define RT5663_IRQ_POW_SAV_DIS (0x0 << 15)
#define RT5663_IRQ_POW_SAV_EN (0x1 << 15)
#define RT5663_IRQ_POW_SAV_JD1_MASK (0x1 << 14)
#define RT5663_IRQ_POW_SAV_JD1_SHIFT 14
#define RT5663_IRQ_POW_SAV_JD1_DIS (0x0 << 14)
#define RT5663_IRQ_POW_SAV_JD1_EN (0x1 << 14)
/* IRQ Control 1 (0x00b6) */
#define RT5668_EN_CB_JD_MASK (0x1 << 3)
#define RT5668_EN_CB_JD_SHIFT 3
#define RT5668_EN_CB_JD_EN (0x1 << 3)
#define RT5668_EN_CB_JD_DIS (0x0 << 3)
#define RT5663_EN_CB_JD_MASK (0x1 << 3)
#define RT5663_EN_CB_JD_SHIFT 3
#define RT5663_EN_CB_JD_EN (0x1 << 3)
#define RT5663_EN_CB_JD_DIS (0x0 << 3)
/* IRQ Control 3 (0x00b8) */
#define RT5668_EN_IRQ_INLINE_MASK (0x1 << 6)
#define RT5668_EN_IRQ_INLINE_SHIFT 6
#define RT5668_EN_IRQ_INLINE_BYP (0x0 << 6)
#define RT5668_EN_IRQ_INLINE_NOR (0x1 << 6)
#define RT5663_V2_EN_IRQ_INLINE_MASK (0x1 << 6)
#define RT5663_V2_EN_IRQ_INLINE_SHIFT 6
#define RT5663_V2_EN_IRQ_INLINE_BYP (0x0 << 6)
#define RT5663_V2_EN_IRQ_INLINE_NOR (0x1 << 6)
/* GPIO Control 1 (0x00c0) */
#define RT5668_GP1_PIN_MASK (0x1 << 15)
#define RT5668_GP1_PIN_SHIFT 15
#define RT5668_GP1_PIN_GPIO1 (0x0 << 15)
#define RT5668_GP1_PIN_IRQ (0x1 << 15)
#define RT5663_GP1_PIN_MASK (0x1 << 15)
#define RT5663_GP1_PIN_SHIFT 15
#define RT5663_GP1_PIN_GPIO1 (0x0 << 15)
#define RT5663_GP1_PIN_IRQ (0x1 << 15)
/* GPIO Control 2 (0x00c1) */
#define RT5668_GP4_PIN_CONF_MASK (0x1 << 5)
#define RT5668_GP4_PIN_CONF_SHIFT 5
#define RT5668_GP4_PIN_CONF_INPUT (0x0 << 5)
#define RT5668_GP4_PIN_CONF_OUTPUT (0x1 << 5)
#define RT5663_GP4_PIN_CONF_MASK (0x1 << 5)
#define RT5663_GP4_PIN_CONF_SHIFT 5
#define RT5663_GP4_PIN_CONF_INPUT (0x0 << 5)
#define RT5663_GP4_PIN_CONF_OUTPUT (0x1 << 5)
/* GPIO Control 2 (0x00c2) */
#define RT5668_GP8_PIN_CONF_MASK (0x1 << 13)
#define RT5668_GP8_PIN_CONF_SHIFT 13
#define RT5668_GP8_PIN_CONF_INPUT (0x0 << 13)
#define RT5668_GP8_PIN_CONF_OUTPUT (0x1 << 13)
#define RT5663_GP8_PIN_CONF_MASK (0x1 << 13)
#define RT5663_GP8_PIN_CONF_SHIFT 13
#define RT5663_GP8_PIN_CONF_INPUT (0x0 << 13)
#define RT5663_GP8_PIN_CONF_OUTPUT (0x1 << 13)
/* 4 Buttons Inline Command Function 1 (0x00df) */
#define RT5668_4BTN_CLK_DEB_MASK (0x3 << 2)
#define RT5668_4BTN_CLK_DEB_SHIFT 2
#define RT5668_4BTN_CLK_DEB_8MS (0x0 << 2)
#define RT5668_4BTN_CLK_DEB_16MS (0x1 << 2)
#define RT5668_4BTN_CLK_DEB_32MS (0x2 << 2)
#define RT5668_4BTN_CLK_DEB_65MS (0x3 << 2)
#define RT5663_4BTN_CLK_DEB_MASK (0x3 << 2)
#define RT5663_4BTN_CLK_DEB_SHIFT 2
#define RT5663_4BTN_CLK_DEB_8MS (0x0 << 2)
#define RT5663_4BTN_CLK_DEB_16MS (0x1 << 2)
#define RT5663_4BTN_CLK_DEB_32MS (0x2 << 2)
#define RT5663_4BTN_CLK_DEB_65MS (0x3 << 2)
/* Inline Command Function 6 (0x00e0) */
#define RT5668_EN_4BTN_INL_MASK (0x1 << 15)
#define RT5668_EN_4BTN_INL_SHIFT 15
#define RT5668_EN_4BTN_INL_DIS (0x0 << 15)
#define RT5668_EN_4BTN_INL_EN (0x1 << 15)
#define RT5668_RESET_4BTN_INL_MASK (0x1 << 14)
#define RT5668_RESET_4BTN_INL_SHIFT 14
#define RT5668_RESET_4BTN_INL_RESET (0x0 << 14)
#define RT5668_RESET_4BTN_INL_NOR (0x1 << 14)
#define RT5663_EN_4BTN_INL_MASK (0x1 << 15)
#define RT5663_EN_4BTN_INL_SHIFT 15
#define RT5663_EN_4BTN_INL_DIS (0x0 << 15)
#define RT5663_EN_4BTN_INL_EN (0x1 << 15)
#define RT5663_RESET_4BTN_INL_MASK (0x1 << 14)
#define RT5663_RESET_4BTN_INL_SHIFT 14
#define RT5663_RESET_4BTN_INL_RESET (0x0 << 14)
#define RT5663_RESET_4BTN_INL_NOR (0x1 << 14)
/* Digital Misc Control (0x00fa) */
#define RT5668_DIG_GATE_CTRL_MASK 0x1
#define RT5668_DIG_GATE_CTRL_SHIFT (0)
#define RT5668_DIG_GATE_CTRL_DIS 0x0
#define RT5668_DIG_GATE_CTRL_EN 0x1
#define RT5663_DIG_GATE_CTRL_MASK 0x1
#define RT5663_DIG_GATE_CTRL_SHIFT (0)
#define RT5663_DIG_GATE_CTRL_DIS 0x0
#define RT5663_DIG_GATE_CTRL_EN 0x1
/* Chopper and Clock control for DAC L (0x013a)*/
#define RT5668_CKXEN_DAC1_MASK (0x1 << 13)
#define RT5668_CKXEN_DAC1_SHIFT 13
#define RT5668_CKGEN_DAC1_MASK (0x1 << 12)
#define RT5668_CKGEN_DAC1_SHIFT 12
#define RT5663_CKXEN_DAC1_MASK (0x1 << 13)
#define RT5663_CKXEN_DAC1_SHIFT 13
#define RT5663_CKGEN_DAC1_MASK (0x1 << 12)
#define RT5663_CKGEN_DAC1_SHIFT 12
/* Chopper and Clock control for ADC (0x013b)*/
#define RT5668_CKXEN_ADCC_MASK (0x1 << 13)
#define RT5668_CKXEN_ADCC_SHIFT 13
#define RT5668_CKGEN_ADCC_MASK (0x1 << 12)
#define RT5668_CKGEN_ADCC_SHIFT 12
#define RT5663_CKXEN_ADCC_MASK (0x1 << 13)
#define RT5663_CKXEN_ADCC_SHIFT 13
#define RT5663_CKGEN_ADCC_MASK (0x1 << 12)
#define RT5663_CKGEN_ADCC_SHIFT 12
/* HP Behavior Logic Control 2 (0x01db) */
#define RT5668_HP_SIG_SRC1_MASK (0x3)
#define RT5668_HP_SIG_SRC1_SHIFT 0
#define RT5668_HP_SIG_SRC1_HP_DC (0x0)
#define RT5668_HP_SIG_SRC1_HP_CALIB (0x1)
#define RT5668_HP_SIG_SRC1_REG (0x2)
#define RT5668_HP_SIG_SRC1_SILENCE (0x3)
#define RT5663_HP_SIG_SRC1_MASK (0x3)
#define RT5663_HP_SIG_SRC1_SHIFT 0
#define RT5663_HP_SIG_SRC1_HP_DC (0x0)
#define RT5663_HP_SIG_SRC1_HP_CALIB (0x1)
#define RT5663_HP_SIG_SRC1_REG (0x2)
#define RT5663_HP_SIG_SRC1_SILENCE (0x3)
/* RT5663 specific register */
#define RT5663_HP_OUT_EN 0x0002
......@@ -707,6 +704,10 @@
#define RT5663_TDM_3 0x0079
#define RT5663_TDM_4 0x007a
#define RT5663_TDM_5 0x007b
#define RT5663_TDM_6 0x007c
#define RT5663_TDM_7 0x007d
#define RT5663_TDM_8 0x007e
#define RT5663_TDM_9 0x007f
#define RT5663_GLB_CLK 0x0080
#define RT5663_PLL_1 0x0081
#define RT5663_PLL_2 0x0082
......@@ -739,7 +740,7 @@
#define RT5663_INT_ST_2 0x00bf
#define RT5663_GPIO_1 0x00c0
#define RT5663_GPIO_2 0x00c1
#define RT5663_GPIO_STA 0x00c5
#define RT5663_GPIO_STA1 0x00c5
#define RT5663_SIN_GEN_1 0x00cb
#define RT5663_SIN_GEN_2 0x00cc
#define RT5663_SIN_GEN_3 0x00cd
......@@ -800,6 +801,8 @@
#define RT5663_TEST_MODE_1 0x0144
#define RT5663_TEST_MODE_2 0x0145
#define RT5663_TEST_MODE_3 0x0146
#define RT5663_TEST_MODE_4 0x0147
#define RT5663_TEST_MODE_5 0x0148
#define RT5663_STO_DRE_1 0x0160
#define RT5663_STO_DRE_2 0x0161
#define RT5663_STO_DRE_3 0x0162
......@@ -921,19 +924,19 @@
#define RT5663_ADC_EQ_POST_VOL_L 0x03f2
#define RT5663_ADC_EQ_POST_VOL_R 0x03f3
/* RT5663: RECMIX Control (0x0010) */
/* RECMIX Control (0x0010) */
#define RT5663_RECMIX1_BST1_MASK (0x1)
#define RT5663_RECMIX1_BST1_SHIFT 0
#define RT5663_RECMIX1_BST1_ON (0x0)
#define RT5663_RECMIX1_BST1_OFF (0x1)
/* RT5663: Bypass Stereo1 DAC Mixer Control (0x002d) */
/* Bypass Stereo1 DAC Mixer Control (0x002d) */
#define RT5663_DACL1_SRC_MASK (0x1 << 3)
#define RT5663_DACL1_SRC_SHIFT 3
#define RT5663_DACR1_SRC_MASK (0x1 << 2)
#define RT5663_DACR1_SRC_SHIFT 2
/* RT5663: TDM control 2 (0x0078) */
/* TDM control 2 (0x0078) */
#define RT5663_DATA_SWAP_ADCDAT1_MASK (0x3 << 14)
#define RT5663_DATA_SWAP_ADCDAT1_SHIFT 14
#define RT5663_DATA_SWAP_ADCDAT1_LR (0x0 << 14)
......@@ -941,7 +944,7 @@
#define RT5663_DATA_SWAP_ADCDAT1_LL (0x2 << 14)
#define RT5663_DATA_SWAP_ADCDAT1_RR (0x3 << 14)
/* RT5663: TDM control 5 (0x007b) */
/* TDM control 5 (0x007b) */
#define RT5663_TDM_LENGTN_MASK (0x3)
#define RT5663_TDM_LENGTN_SHIFT 0
#define RT5663_TDM_LENGTN_16 (0x0)
......@@ -949,17 +952,6 @@
#define RT5663_TDM_LENGTN_24 (0x2)
#define RT5663_TDM_LENGTN_32 (0x3)
/* RT5663: Global Clock Control (0x0080) */
#define RT5663_SCLK_SRC_MASK (0x3 << 14)
#define RT5663_SCLK_SRC_SHIFT 14
#define RT5663_SCLK_SRC_MCLK (0x0 << 14)
#define RT5663_SCLK_SRC_PLL1 (0x1 << 14)
#define RT5663_SCLK_SRC_RCCLK (0x2 << 14)
#define RT5663_PLL1_SRC_MASK (0x7 << 11)
#define RT5663_PLL1_SRC_SHIFT 11
#define RT5663_PLL1_SRC_MCLK (0x0 << 11)
#define RT5663_PLL1_SRC_BCLK1 (0x1 << 11)
/* PLL tracking mode 1 (0x0083) */
#define RT5663_I2S1_ASRC_MASK (0x1 << 11)
#define RT5663_I2S1_ASRC_SHIFT 11
......@@ -978,31 +970,31 @@
#define RT5663_AD_STO1_TRACK_SYSCLK (0x0)
#define RT5663_AD_STO1_TRACK_I2S1 (0x1)
/* RT5663: HPOUT Charge pump control 1 (0x0091) */
/* HPOUT Charge pump control 1 (0x0091) */
#define RT5663_SI_HP_MASK (0x1 << 12)
#define RT5663_SI_HP_SHIFT 12
#define RT5663_SI_HP_EN (0x1 << 12)
#define RT5663_SI_HP_DIS (0x0 << 12)
/* RT5663: GPIO Control 2 (0x00b6) */
/* GPIO Control 2 (0x00b6) */
#define RT5663_GP1_PIN_CONF_MASK (0x1 << 2)
#define RT5663_GP1_PIN_CONF_SHIFT 2
#define RT5663_GP1_PIN_CONF_OUTPUT (0x1 << 2)
#define RT5663_GP1_PIN_CONF_INPUT (0x0 << 2)
/* RT5663: GPIO Control 2 (0x00b7) */
/* GPIO Control 2 (0x00b7) */
#define RT5663_EN_IRQ_INLINE_MASK (0x1 << 3)
#define RT5663_EN_IRQ_INLINE_SHIFT 3
#define RT5663_EN_IRQ_INLINE_NOR (0x1 << 3)
#define RT5663_EN_IRQ_INLINE_BYP (0x0 << 3)
/* RT5663: GPIO Control 1 (0x00c0) */
/* GPIO Control 1 (0x00c0) */
#define RT5663_GPIO1_TYPE_MASK (0x1 << 15)
#define RT5663_GPIO1_TYPE_SHIFT 15
#define RT5663_GPIO1_TYPE_EN (0x1 << 15)
#define RT5663_GPIO1_TYPE_DIS (0x0 << 15)
/* RT5663: IRQ Control 1 (0x00c1) */
/* IRQ Control 1 (0x00c1) */
#define RT5663_EN_IRQ_JD1_MASK (0x1 << 6)
#define RT5663_EN_IRQ_JD1_SHIFT 6
#define RT5663_EN_IRQ_JD1_EN (0x1 << 6)
......@@ -1012,13 +1004,13 @@
#define RT5663_SEL_GPIO1_EN (0x1 << 2)
#define RT5663_SEL_GPIO1_DIS (0x0 << 2)
/* RT5663: Inline Command Function 2 (0x00dc) */
/* Inline Command Function 2 (0x00dc) */
#define RT5663_PWR_MIC_DET_MASK (0x1)
#define RT5663_PWR_MIC_DET_SHIFT 0
#define RT5663_PWR_MIC_DET_ON (0x1)
#define RT5663_PWR_MIC_DET_OFF (0x0)
/* RT5663: Embeeded Jack and Type Detection Control 1 (0x00e6)*/
/* Embeeded Jack and Type Detection Control 1 (0x00e6)*/
#define RT5663_CBJ_DET_MASK (0x1 << 15)
#define RT5663_CBJ_DET_SHIFT 15
#define RT5663_CBJ_DET_DIS (0x0 << 15)
......@@ -1032,17 +1024,17 @@
#define RT5663_POL_EXT_JD_EN (0x1 << 10)
#define RT5663_POL_EXT_JD_DIS (0x0 << 10)
/* RT5663: DACREF LDO Control (0x0112)*/
/* DACREF LDO Control (0x0112)*/
#define RT5663_PWR_LDO_DACREFL_MASK (0x1 << 9)
#define RT5663_PWR_LDO_DACREFL_SHIFT 9
#define RT5663_PWR_LDO_DACREFR_MASK (0x1 << 1)
#define RT5663_PWR_LDO_DACREFR_SHIFT 1
/* RT5663: Stereo Dynamic Range Enhancement Control 9 (0x0168, 0x0169)*/
/* Stereo Dynamic Range Enhancement Control 9 (0x0168, 0x0169)*/
#define RT5663_DRE_GAIN_HP_MASK (0x1f)
#define RT5663_DRE_GAIN_HP_SHIFT 0
/* RT5663: Combo Jack Control (0x0250) */
/* Combo Jack Control (0x0250) */
#define RT5663_INBUF_CBJ_BST1_MASK (0x1 << 11)
#define RT5663_INBUF_CBJ_BST1_SHIFT 11
#define RT5663_INBUF_CBJ_BST1_ON (0x1 << 11)
......@@ -1052,11 +1044,11 @@
#define RT5663_CBJ_SENSE_BST1_L (0x1 << 10)
#define RT5663_CBJ_SENSE_BST1_R (0x0 << 10)
/* RT5663: Combo Jack Control (0x0251) */
/* Combo Jack Control (0x0251) */
#define RT5663_GAIN_BST1_MASK (0xf)
#define RT5663_GAIN_BST1_SHIFT 0
/* RT5663: Dummy register 1 (0x02fa) */
/* Dummy register 1 (0x02fa) */
#define RT5663_EMB_CLK_MASK (0x1 << 9)
#define RT5663_EMB_CLK_SHIFT 9
#define RT5663_EMB_CLK_EN (0x1 << 9)
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7