Commit 73c4b0f8 authored by Hawking Zhang's avatar Hawking Zhang Committed by Alex Deucher

drm/amdgpu: drop temp programming for pagefault handling

Was introduced as workaround. not needed anymore
Signed-off-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarJack Gui <Jack.Gui@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ff742e0c
...@@ -417,34 +417,12 @@ static void gfxhub_v3_0_set_fault_enable_default(struct amdgpu_device *adev, ...@@ -417,34 +417,12 @@ static void gfxhub_v3_0_set_fault_enable_default(struct amdgpu_device *adev,
tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1); tmp = REG_SET_FIELD(tmp, CP_DEBUG, CPG_UTCL1_ERROR_HALT_DISABLE, 1);
WREG32_SOC15(GC, 0, regCP_DEBUG, tmp); WREG32_SOC15(GC, 0, regCP_DEBUG, tmp);
/**
* Set GRBM_GFX_INDEX in broad cast mode
* before programming GL1C_UTCL0_CNTL1 and SQG_CONFIG
*/
WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, regGRBM_GFX_INDEX_DEFAULT);
/**
* Retry respond mode: RETRY
* Error (no retry) respond mode: SUCCESS
*/
tmp = RREG32_SOC15(GC, 0, regGL1C_UTCL0_CNTL1);
tmp = REG_SET_FIELD(tmp, GL1C_UTCL0_CNTL1, RESP_MODE, 0);
tmp = REG_SET_FIELD(tmp, GL1C_UTCL0_CNTL1, RESP_FAULT_MODE, 0x2);
WREG32_SOC15(GC, 0, regGL1C_UTCL0_CNTL1, tmp);
/* These registers are not accessible to VF-SRIOV. /* These registers are not accessible to VF-SRIOV.
* The PF will program them instead. * The PF will program them instead.
*/ */
if (amdgpu_sriov_vf(adev)) if (amdgpu_sriov_vf(adev))
return; return;
/* Disable SQ XNACK interrupt for all VMIDs */
tmp = RREG32_SOC15(GC, 0, regSQG_CONFIG);
tmp = REG_SET_FIELD(tmp, SQG_CONFIG, XNACK_INTR_MASK,
SQG_CONFIG__XNACK_INTR_MASK_MASK >>
SQG_CONFIG__XNACK_INTR_MASK__SHIFT);
WREG32_SOC15(GC, 0, regSQG_CONFIG, tmp);
tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL); tmp = RREG32_SOC15(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL);
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL, tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
......
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